AD AD1819BJST

a
AC’97 SoundPort® Codec
AD1819B
AC’97 FEATURES
Fully Compliant AC’97 Analog I/O Component
48-Terminal LQFP Package
Multibit ⌺⌬ Converter Architecture for Improved
S/N Ratio >90 dB
16-Bit Stereo Full-Duplex Codec
Four Analog Line-Level Stereo Inputs for Connection
from LINE, CD, VIDEO, and AUX
Two Analog Line-Level Mono Inputs for Speakerphone
and PC BEEP
Mono MIC Input Switchable from Two External
Sources
High Quality CD Input with Ground Sense
Stereo Line Level Output
Mono Output for Speakerphone
Power Management Support
ENHANCED FEATURES
Support for Multiple Codec Communications
DSP 16-Bit Serial Port Format
Variable 7 kHz to 48 kHz Sampling Rate with 1 Hz
Resolution
Supports Modem Sample Rates and Filtering
Phat™ Stereo 3D Stereo Enhancement
VHDL and Verilog Models of Serial Port Available
FUNCTIONAL BLOCK DIAGRAM
CS0 CS1 CHAIN_IN CHAIN_CLK
AD1819B
MIC1
MIC2
MASTER/SLAVE
SYNCHRONIZER
0dB/
20dB
LINE_IN
SELECTOR
AUX
CD
VIDEO
PGA
16-BIT
SD A/D
CONVERTER
PGA
16-BIT
SD A/D
CONVERTER
RESET
PHONE_IN
S
G
A
M
G
A
M
G
A
M
G
A
M
G
A
M
SAMPLE
RATE
GENERATORS
G
A
M
AC LINK
SYNC
BIT_CLK
SDATA_OUT
LINE_OUT_L
MV
MONO_OUT
MV
LINE_OUT_R
MV
S
S
PHAT
STEREO
S
S
S
S
S
G
A
M
16-BIT
SD D/A
CONVERTER
G
A
M
16-BIT
SD D/A
CONVERTER
SDATA_IN
S
S
S
PHAT
STEREO
A
M
PC_BEEP
S
S
S
S
G = GAIN
A = ATTENUATE
M = MUTE
MV = MASTER VOLUME
S
OSCILLATORS
XTALO
XTALI
SoundPort is a registered trademark of Analog Devices, Inc.
Phat is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD1819B
PRODUCT OVERVIEW
Each channel of the ADC is independent, and can process
left and right channel data at different sample rates. All programmed sample rates from 7 kHz to 48 kHz have a resolution
of 1 Hz. The AD1819B also supports irrational V.34 sample
rates.
The AD1819B SoundPort Codec is designed to meet all requirements of the Audio Codec ’97, Component Specification, Revision
1.03, © 1996, Intel Corporation, found at www.Intel.com. In
addition, the AD1819B supports multiple codec configurations
(up to three per AC-Link), a DSP serial mode, variable sample
rates, modem sample rates and filtering, and built-in Phat Stereo 3D enhancement.
Sample Rates and D2S
The AD1819B default mode sets the codec to operate at 48 kHz
sample rates. The converter pairs may process left and right
channel data at different sample rates. The AD1819B sample
rate generator allows the codec to instantaneously change and
process sample rates from 7 kHz to 48 kHz with a resolution of
1 Hz. The in-band integrated noise and distortion artifacts introduced by rate conversions are below –90 dB. The AD1819B
uses a 4-bit D/A structure and Data Directed Scrambling (D2S)
to enhance noise immunity on motherboards and in PC enclosures, and to suppress idle tones below the device’s quantization
noise floor. The D2S process pushes noise and distortion artifacts caused by errors in the multibit D/A conversion process to
frequencies beyond the audible range of the human ear and then
filters them.
The AD1819B is an analog front end for high performance PC
audio, modem, or DSP applications. The AC’97 architecture
defines a 2-chip audio solution comprising a digital audio controller, plus a high quality analog component that includes
Digital-to-Analog Converters (DACs), Analog-to-Digital Converters (ADCs) mixer and I/O.
The main architectural features of the AD1819B are the high
quality analog mixer section, two channels of Σ∆ ADC conversion, two channels of Σ∆ DAC conversion and Data Direct
Scrambling (D2S) rate generators. The AD1819B’s left channel
ADC and DAC are compatible for modem applications supporting irrational sample rates and modem filtering requirements.
Digital-to-Analog Signal Path
FUNCTIONAL DESCRIPTION
The analog output of the DAC may be gained or attenuated
from +12 dB to –34.5 dB in 1.5 dB steps, and summed with any
of the analog input signals. The summed analog signal enters
the Master Volume stage where each channel of the mixer output may be attenuated from 0 dB to –46.5 dB in 1.5 dB steps or
muted.
This section overviews the functionality of the AD1819B and is
intended as a general introduction to the capabilities of the
device. Detailed reference information may be found in the
descriptions of the Indexed Control Registers.
Analog Inputs
The codec contains a stereo pair of Σ∆ ADCs. Inputs to the
ADC may be selected from the following analog signals: telephony (PHONE_IN), mono microphone (MIC1 or MIC2),
stereo line (LINE_IN), auxiliary line input (AUX), stereo CD
ROM (CD), stereo audio from a video source (VIDEO) and
post-mixed stereo or mono line output (LINE_OUT).
Host-Based Echo Cancellation Support
Analog Mixing
Telephony Modem Support
PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD and
VIDEO can be mixed in the analog domain with the stereo
output from the DACs. Each channel of the stereo analog inputs may be independently gained or attenuated from +12 dB
to –34.5 dB in 1.5 dB steps. The summing path for the mono
inputs (PHONE_IN, MIC1, and MIC2 to LINE_OUT) duplicates mono channel data on both the left and right LINE_OUT.
Additionally, the PC attention signal (PC_BEEP) may be
mixed with the line output. A switch allows the output of the
DACs to bypass the Phat Stereo 3D enhancement.
The AD1819B contains a V.34-capable analog front end for
supporting host-based and data pump modems. The modem
DAC typical dynamic range is 90 dB over a 4.2 kHz analog
output passband where FS = 12.8 kHz. The left channel of the
ADC and DAC may be used to convert modem data at the same
sample rate in the range between 7 kHz and 48 kHz. All programmed sample rates have a resolution of 1 Hz. The AD1819B
supports irrational V.34 sample rates with 8/7 and 10/7 selectable sample rate multiplier coefficients.
Analog-to-Digital Signal Path
The voltage reference (VREF) of the AD1819B remains active
while RESET is asserted. This eliminates the audible artifacts
associated with the RESET LO to HI transitions that can
occur during a Windows boot (power-up) or Windows warm
restart (reset).
The AD1819B supports time correlated I/O data format by
presenting mic data on the left channel of the ADC and the
mono summation of left and right output on the right channel.
The ADC is splittable; left and right ADC data can be sampled
at different rates.
Differences Between the AD1819A and AD1819B
The selector sends left and right channel signals to the programmable gain amplifier (PGA). The PGA following the selector
allows independent gain for each channel entering the ADC
from 0 dB to +22.5 dB in 1.5 dB steps.
–2–
REV. 0
SPECIFICATIONS
AD1819B
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature
Digital Supply (VDD)
Analog Supply (VCC)
Sample Rate (FS)
Input Signal
Analog Output Passband
VIH (AC-Link)
VIL (AC-Link)
VIH (CS0, CS1, CHAIN_IN)
VIL (CHAIN_CLK)
25
5.0
5.0
48
1008
20 Hz to 20 kHz
2.0
0.8
4.0
1.0
°C
V
V
kHz
Hz
DAC Test Conditions
Calibrated
0 dB Attenuation
Input 0 dB
10 kΩ Output Load
Mute Off
V
V
V
V
ADC Test Conditions
Calibrated
0 dB Gain
Input –3 dB Relative to Full Scale
Line Input Selected
ANALOG INPUT
Parameter
Min
Input Voltage (RMS Values Assume Sine Wave Input)
LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP
Typ
Max
1
2.83
0.1
0.283
1
2.83
MIC1, MIC2 with +20 dB Gain (M20 = 1)
MIC1, MIC2 with 0 dB Gain (M20 = 0)
Input Impedance*
Input Capacitance*
Units
V rms
V p-p
V rms
V p-p
V rms
V p-p
kΩ
pF
10
15
PROGRAMMABLE GAIN AMPLIFIER—ADC
Parameter
Min
Step Size (0 dB to 22.5 dB)
PGA Gain Range Span
Typ
Max
1.5
22.5
Units
dB
dB
ANALOG MIXER— INPUT GAIN/AMPLIFIERS/ATTENUATORS
Parameter
Min
Dynamic Range (–60 dB Input THD+N, Referenced to Full Scale, A-Weighted)
CD to LINE_OUT
90
Other to LINE_OUT*
Step Size (+12 dB to –34.5 dB): (All Steps Tested)
MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC
Input Gain/Attenuation Range
MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC
Step Size␣ (0 dB to –45 dB): (All Steps Tested)
PC_BEEP
Input Gain/Attenuation Range: PC_BEEP
Typ
Max
Units
90
dB
dB
1.5
dB
46.5
dB
3.0
45
dB
dB
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Parameter
Min
Passband
Passband Ripple
Transition Band
Stopband
Stopband Rejection
Group Delay
Group Delay Variation Over Passband
0
0.4 × FS
0.6 × FS
–74
Max
Units
0.4 × FS
± 0.09
0.6 × FS
Hz
dB
Hz
Hz
dB
sec
µs
∞
12/FS
0.0
*Guaranteed, not tested.
Specifications subject to change without notice.
REV. 0
Typ
–3–
AD1819B–SPECIFICATIONS
ANALOG-TO-DIGITAL CONVERTERS
Parameter
Min
Resolution
Total Harmonic Distortion (THD)
Typ
Max
Units
0.02
–74
Bits
%
dB
16
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,
A-Weighted)
Signal-to-Intermodulation Distortion* (CCIF Method)
ADC Crosstalk*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line to Other
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error
84
87
85
dB
dB
–100
–90
–90
–85
± 10
± 0.5
±5
dB
dB
%
dB
mV
Typ
Max
Units
0.02
–74
Bits
%
dB
DIGITAL-TO-ANALOG CONVERTERS
Parameter
Min
Resolution
Total Harmonic Distortion (THD) LINE_OUT
16
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale,
A-Weighted)
Signal-to-Intermodulation Distortion* (CCIF Method)
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk* (Input L, Zero R, Measure LINE_OUT_R; Input R,
Zero L, Measure LINE_OUT_L)
Total Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)*
85
90
85
± 10
± 0.5
–80
–40
dB
dB
%
dB
dB
dB
dB
MASTER VOLUME
Parameter
Min
Step Size (0 dB to –46.5 dB)
LINE_OUT_L, LINE_OUT_R, MONO_OUT
Output Attenuation Range Span
Mute Attenuation of 0 dB Fundamental*
Typ
Max
Units
75
dB
dB
dB
Max
Units
1.5
46.5
ANALOG OUTPUT
Parameter
Min
Full-Scale Output Voltage
Typ
1
2.83
Output Impedance*
External Load Impedance
Output Capacitance*
External Load Capacitance
VREF
VREF Current Drive
VREFOUT
VREFOUT Current Drive
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)*
800
10
15
2.00
2.25
100
2.50
100
2.25
±5
5
V rms
V p-p
Ω
kΩ
pF
pF
V
µA
V
mA
mV
*Guaranteed, not tested.
Specifications subject to change without notice.
–4–
REV. 0
AD1819B
STATIC DIGITAL SPECIFICATIONS
Parameter
Min
High-Level Input Voltage (VIH): Digital Inputs
Low-Level Input Voltage (VIL)
High-Level Output Voltage (VOH), IOH = 2 mA
Low-Level Output Voltage (VOL), IOL = 2 mA
Input Leakage Current
Output Leakage Current
0.4 × DVDD
Typ
Max
0.2 × DVDD
0.5 × DVDD
0.2 × DVDD
10
10
–10
–10
Units
V
V
V
V
µA
µA
POWER SUPPLY
Parameter
Min
Power Supply Range—Analog
Power Supply Range—Digital
Power Supply Current
Power Dissipation
Analog Supply Current
Digital Supply Current
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
4.5
4.5
Typ
Max
Units
5.5
5.5
120
600
60
60
V
V
mA
mW
mA
mA
–40
dB
CLOCK SPECIFICATIONS*
Parameter
Min
Typ
Max
Units
Input Clock Frequency
Recommended Clock Duty Cycle
40
24.576
50
60
MHz
%
Min
Typ
Max
Units
POWER-DOWN STATES
Parameter
Set Bits
ADCs and Input Mux Power-Down
DACs Power-Down
Analog Mixer Power-Down (VREF and VREFOUT On)
Analog Mixer Power-Down (VREF and VREFOUT Off)
Digital Interface Power-Down*
Internal Clocks Disabled*
ADC and DAC Power-Down
VREF Standby Mode*
Total Power-Down
PR0
PR1
PR1, PR2
PR0, PR1, PR3
PR4
PR0, PR1, PR4, PR5
PR0, PR1
PR0, PR1, PR2, PR4, PR5
PR0, PR1, PR2, PR3,
PR4, PR5
RESET (Low)
*Guaranteed, not tested.
Specifications subject to change without notice.
REV. 0
–5–
110
100
54
47
120
85
85
55
mA
mA
mA
mA
mA
mA
mA
mA
220
250
µA
µA
AD1819B
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to
SYNC, SDATA_OUT)
Rising Edge of RESET to HI-Z Delay
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
1.0
162.8
0.0814
Typ
Max
1.0
µs
ns
µs
µs
ns
MHz
ns
ps
ns
ns
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
25
ns
ns
1.3
19.5
162.8
12.288
81.4
tCLK_PERIOD
32.56
32.56
tCLK_HIGH
tCLK_LOW
tSYNC_PERIOD
tSETUP
tHOLD
tRISE CLK
tFALL CLK
tRISE SYNC
tFALL SYNC
tRISE DIN
tFALL DIN
tRISE DOUT
tFALL DOUT
tS2_PDOWN
40.7
40.7
48.0
20.8
750
48.84
48.84
15.0
15.0
4
4
4
4
4
4
4
4
15
tSETUP2RST
tOFF
Units
*Output Jitter is directly dependent on crystal input jitter.
tRST_LOW
tRST2CLK
RESET
BIT_CLK
Figure 1. Cold Reset
tRST2CLK
tSYNC_HIGH
SYNC
BIT_CLK
Figure 2. Warm Reset
tCLK_LOW
BIT_CLK
tCLK_HIGH
tCLK_PERIOD
tSYNC_LOW
SYNC
tSYNC_HIGH
tSYNC_PERIOD
Figure 3. Clock Timing
–6–
REV. 0
AD1819B
tSETUP
SYNC
SLOT 1
SLOT 2
WRITE
TO 0x26
DATA
PR4
BIT_CLK
BIT_CLK
SYNC
SDATA_OUT
SDATA_OUT
DON’T
CARE
tHOLD
tS2_PDOWN
Figure 4. Data Setup and Hold
SDATA_IN
NOTE: BIT_CLK NOT TO SCALE
Figure 6. AC-Link, Link Low Power Mode Timing
BIT_CLK
tRISECLK
tFALLCLK
RESET
SYNC
tRISESYNC
tFALLSYNC
SDATA_OUT
tSETUP2RST
SDATA_IN
SDATA_IN, BIT_CLK
tRISEDIN
HI-Z
tFALLDIN
tOFF
Figure 7. ATE Test Mode
SDATA_OUT
tRISEDOUT
tFALLDOUT
Figure 5. Signal Rise and Fall Time
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
Parameter
Power Supplies
␣ ␣ Analog (AVDD)
␣ ␣ Digital (DVDD)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
Min
Max
Units
Model
–0.3
–0.3
–0.3
–0.3
–40
–65
6.0
6.0
± 10.0
AVDD + 0.3
DVDD + 0.3
+85
+150
V
V
mA
V
V
°C
°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Temperature
Range
Package
Option*
AD1819BJST –40°C to +85°C 48-Terminal LQFP ST-48
*ST = Thin Quad Flatpack.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
TAMB = TCASE – (P D × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
Package
␪JA
␪JC
␪CA
LQFP
76.2°C/W
17°C/W
59.2°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1819B features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
Package
Description
–7–
WARNING!
ESD SENSITIVE DEVICE
AD1819B
PIN CONFIGURATION
MONO_OUT
NC
AVDD2
AVSS2
NC
NC
NC
NC
CS0
CS1
CHAIN_CLK
CHAIN_IN
48-Terminal LQFP
(ST-48)
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 1
XTL_IN 2
PIN 1
IDENTIFIER
36
LINE_OUT_R
35
LINE_OUT_L
CX3D
XTL_OUT 3
34
DVSS1 4
33
SDATA_OUT 5
32
AD1819B
BIT_CLK 6
DVSS2 7
31
TOP VIEW
(Not to Scale)
SDATA_IN 8
DVDD2 9
RX3D
FILT_L
30
FILT_R
AFILT2
29
AFILT1
28
VREFOUT
27 VREF
SYNC 10
RESET 11
PC_BEEP 12
26
AVSS1
25
AVDD1
LINE_IN_R
MIC2
LINE_IN_L
MIC1
CD_R
CD_GND
VIDEO_R
CD_L
VIDEO_L
PHONE_IN
AUX_L
AUX_R
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Digital I/O
Pin Name
LQFP
I/O
Description
XTL_IN
XTL_OUT
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
2
3
5
6
8
10
11
I
O
I
O/I*
O
I
I
24.576 MHz Crystal or Clock Input
24.576 MHz Crystal Output
Serial Data Output. Serial, Time Division Multiplexed, AD1819B Input Stream
Bit Clock Input, 12.288 MHz Serial Data Clock. Daisy Chain Output Clock
Serial Data Input. Serial, Time Division Multiplexed, AD1819B Output Stream
48 kHz Fixed Rate Sample Sync Clock
Reset. AC-Link Master Hardware Reset
*Input if the AD1819B is configured as Slave 1 or Slave 2.
Daisy Chain Connections
Pin Name
LQFP
I/O
Description
CS0
CS1
CHAIN_IN
CHAIN_CLK
45
46
47
48
I
I
I
I/O*
Daisy Chain Codec Select
Daisy Chain Codec Select
Daisy Chain Data Input
24.576 MHz Buffered Clock Input/Output
*Output when configured as Master. Input when configured as Slave 1 or Slave 2.
–8–
REV. 0
AD1819B
Analog I/O
These signals connect the AD1819B component to analog sources and sinks, including microphones and speakers.
Pin Name
LQFP
I/O
Description
PC_BEEP
PHONE_IN
AUX_L
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_GND
CD_R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
LINE_OUT_L
LINE_OUT_R
MONO_OUT
12
13
14
15
16
17
18
19
20
21
22
23
24
35
36
37
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
PC Beep. PC Speaker Beep Pass-Through
Phone. From Telephony Subsystem Speakerphone or Handset
Auxiliary Input Left Channel
Auxiliary Input Right Channel
Video Audio Left Channel
Video Audio Right Channel
CD Audio Left Channel
CD Audio Analog Ground Sense for Differential CD Input
CD Audio Right Channel
Microphone 1. Desktop Microphone Input
Microphone 2. Second Microphone Input
Line In Left Channel
Line In Right Channel
Line Out Left Channel
Line Out Right Channel
Monaural Output to Telephony Subsystem Speakerphone
Pin Name
LQFP
I/O
Description
VREF
VREFOUT
AFILT1
AFILT2
FILT_R
FILT_L
RX3D
CX3D
27
28
29
30
31
32
33
34
O
O
O
O
O
O
O
I
Voltage Reference Filter
Voltage Reference Output 5 mA Drive (Intended for Mic Bias)
Antialiasing Filter Capacitor—ADC Right Channel
Antialiasing Filter Capacitor—ADC Left Channel
AC-Coupling Filter Capacitor—ADC Right Channel
AC-Coupling Filter Capacitor—ADC Left Channel
3D Phat Stereo Enhancement—Capacitor
3D Phat Stereo Enhancement—Capacitor
Filter/Reference
Power and Ground Signals
Pin Name
LQFP
I/O
Description
DVDD1
DVSS1
DVSS2
DVDD2
AVDD1
AVSS1
AVDD2
AVSS2
1
4
7
9
25
26
38
42
I
I
I
I
I
I
I
I
Digital VDD—5.0 V
Digital GND
Digital GND
Digital VDD—5.0 V
Analog VDD—5.0 V
Analog GND
Analog VDD—5.0 V
Analog GND
Pin Name
LQFP
I/O
Description
NC
NC
NC
NC
NC
39
40
41
43
44
No Connects
REV. 0
No Connect
No Connect
No Connect
No Connect
No Connect
–9–
AD1819B
MIC1
0dB/20dB
M20 0x0E
MS
MIC2
LS/RS (0)
0x20
AUX
S
E
LS (1)
L
RS (1)
E
C
LS (2)
T
RS (2)
O
GM 0x1C
LS/RS
(7) R
RIM
LSIM(5)
CD
VIDEO
PHONE_IN
STEREO MIX (L)
MONO MIX
GM 0X1C
LIM
IM
16-BIT
SD ADC
GM 0X1C
RIM
IM
16-BIT
SD ADC
0X74
LS (4)
RS (4)
GM 0x1C
LSLIM
(3)
RSIM(3)
LINE_IN
LS/RS (6)
STEREO MIX (R)
RESET
RS (5)
0x1A
SYNC
GA 0x0C
GA 0x0E GA 0x10
PHV
MCV
LLV
RLA
GA 0x16
LAV
RAV
GA 0x12
GA 0x14
LCV
RCV
LVV
RVV
SR0 0x78
SR1 0x7A
LPBK
0x20
M 0x0C
PHM
LINE_OUT_L
MONO_OUT
M 0x02
A 0x02
MM
LMV
M 0x06
A 0x06
0
MMM
MMV
1
M 0x02
A 0x02
MM
RMV
LINE_OUT_R
S
S
3D 0x22
DP
M 0x0E
M 0x10
M 0x16
M 0x12
M 0x14
MCM
LM
AM
CM
VM
S
S
S
S
GAM 0x18
LOV
OM
S
MIX 0x20
S
3D 0x22
DP
BIT_CLK
SDATA_OUT
SDATA_IN
16-BIT
SD DAC
0x20
POP
S
S
AC LINK
S
S
S
S
S
S
GAM 0x18
ROV
OM
16-BIT
SD DAC
GA 0x0A
PCV
M 0x0A
PC_BEEP
G = GAIN
A = ATTENUATE
M = MUTE
MV = MASTER VOLUME
PCM
AD1819B
OSCILLATORS
XTL_OUT
XTL_IN
Figure 8. Block Diagram Register Map
–10–
REV. 0
AD1819B
Indexed Control Registers
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
00h
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0400h
02h
Master Volume
MM
X
LMV5
LMV4
LMV3
LMV2
LMV1
LMV0
X
X
RMV5
RMV4
RMV3
RMV2
RMV1
RMV0
8000h
04h
Reser ved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
06 h
Master Volume Mono
MMM
X
X
X
X
X
X
X
X
X
MMV5
MMV4
MMV2
MMV2
MMV1
MMV0
8000h
08h
Reser ved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0Ah
PC Beep Volume
PCM
X
X
X
X
X
X
X
X
X
X
PCV3
PCV2
PCV1
PCV0
X
8000h
0Ch
Phone Volume
PHM
X
X
X
X
X
X
X
X
X
X
PHV4
PHV3
PHV2
PHV1
PHV0
8008h
0Eh
Mic Volume
MCM
X
X
X
X
X
X
X
X
M20
X
MCV4
MCV3
MCV2
MCV1
MCV0
8008h
10h
Line In Volume
LM
X
X
LLV4
LLV3
LLV2
LLV1
LLV0
X
X
X
RLV4
RLV3
RLV2
RLV1
RLV0
8808h
12h
CD Volume
CVM
X
X
LCV4
LCV3
LCV2
LCV1
LCV0
X
X
X
RCV4
RCV3
RCV2
RCV1
RCV0
8808h
14h
Video Volume
VM
X
X
LVV4
LVV3
LVV2
LVV1
LVV0
X
X
X
RVV4
RVV3
RVV2
RVV1
RVV0
8808h
16h
Aux Volume
AM
X
X
LAV4
LAV3
LAV2
LAV1
LAV0
X
X
X
RAV4
RAV3
RAV2
RAV1
RAV0
8808h
18h
PCM Out Vol
OM
X
X
LOV4
LOV3
LOV2
LOV1
LOV0
X
X
X
ROV4
ROV3
ROV2
ROV1
ROV0
8808h
1Ah
Record Select
X
X
X
X
X
LS2
LS1
LS0
X
X
X
X
X
RS2
RS1
RS0
0000h
1Ch
Record Gain
IM
X
X
X
LIM3
LIM2
LIM1
LIM0
X
X
X
X
RIM3
RIM2
RIM1
RIM0
8000h
1Eh
Reser ved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
20h
General Purpose
POP
X
3D
X
X
X
MIX
MS
LPBK
X
X
X
X
X
X
X
0000h
22h
3D Control
X
X
X
X
X
X
X
X
X
X
X
X
DP3
DP2
DP1
DP0
0000h
24h
Reser ved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
26h
Power-Down Contr/Stat
X
X
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
DAC
ADC
0000h
28h
Reser ved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
72h
Reser ved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
74 h
Serial Configuration
SLOT
16
REGM
2
REGM
1
REGM
0
DRQE
N
DLRQ
2
DLRQ
1
DLRQ
0
X
X
X
X
X
DRRQ
2
DRRQ
1
DRRQ
0
7000h
SRX1
0D7
SRX8
D7
X
X
DRSR
X
ARSR
0000h
76h
Misc Control Bits
DACZ
X
X
X
X
DLSR
X
ALSR
MOD
EN
78h
Sample Rate 0
SR015
SR014
SR013
SR012
SR011
SR010
SR09
SR08
SR07
SR06
SR05
SR04
SR03
SR02
SR01
SR00
BB80h
7Ah
Sample Rate 1
SR115
SR114
SR113
SR112
SR111
SR110
SR19
SR18
SR17
SR16
SR15
SR14
SR13
SR12
SR11
SR10
BB80h
7Ch
Vendor ID1
F7
F6
F5
F4
F3
F2
F1
F0
S7
S6
S5
S4
S3
S2
S1
S0
4144h
7Eh
Vendor ID2
T7
T6
T5
T4
T3
T2
T1
T0
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
5303h
NOTES
1. All registers not shown and bits containing an X are reserved.
2. Odd register addresses are aliased to the next lower even address.
3. Reserved registers should not be written.
4. Zeros should be written to reserved bits.
REV. 0
–11–
AD1819B
Reset (Index 00h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
00h
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0400h
Note: Writing any value to this register performs a register reset, which cause all registers to revert to their default values (except
74h, which controls the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D
Stereo Enhancement.
ID [9:0]
Identify Capability. The ID field decodes the capabilities of AD1819B on the following:
Bit
Function
AD1819B*
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
Dedicated Mic PCM in Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
0
0
0
0
0
0
0
0
0
0
*The AD1819B contains none of the optional features identified by these bits.
SE [4:0]
Stereo Enhancement. The 3D stereo enhancement field identifies the Analog Devices 3D Phat Stereo enhancement.
Master Volume (Index 02h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
02h
Master Volume
MM
X
LMV5
LMV4
LMV3
LMV2
LMV1
LMV0
X
X
RMV5
RMV4
RMV3
RMV2
RMV1
RMV0
Default
8000h
RMV [4:0]
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of –46.5 dB.
RMV5
Right Master Volume Maximum Attenuation. Forces RMV [4:0] to all “1s,” –46.5 dB.
LMV [4:0]
Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of –46.5 dB.
LMV5
Left Master Volume Maximum Attenuation. Forces LMV [4:0] to all “1s,” –46.5 dB.
MM
Master Volume Mute. When this bit is set to “1,” the left and right channels are muted.
MM
xMV5 . . . xMV0
Function
0
0
0
1
00 0000
01 1111
1x xxxx
xx xxxx
0 dB Attenuation
–46.5 dB Attenuation
–46.5 dB Attenuation
∞ dB Attenuation
Master Volume Mono (Index 06h)
Reg
Num
Name
06h
Master Volume Mono
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MMM
X
X
X
X
X
X
X
X
X
MMV5
MMV4
MMV3
MMV2
MMV1
MMV0
Default
8000h
MMV [4:0]
Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of –46.5 dB.
MMV5
Mono Master Volume Maximum Attenuation –46.5 dB.
MMM
Mono Master Volume Mute. When this bit is set to “1,” the mono channel is muted.
–12–
REV. 0
AD1819B
MMM
MMV5 . . . MMV0
Function
0
0
0
1
00 0000
01 1111
1x xxxx
xx xxxx
0 dB Attenuation
–46.5 dB Attenuation
–46.5 dB Attenuation
∞ dB Attenuation
PC Beep (Index 0Ah)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0Ah
PC Beep Volume
PCM
X
X
X
X
X
X
X
X
X
X
PCV3
PCV2
PCV1
PCV0
X
Default
8000h
PCV [3:0]
PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output
from 0 dB to a maximum attenuation of –45 dB. The PC Beep is routed to the Left and Right Line outputs even
when AD1819B is in a RESET State. This is so that Power-On Self Test (POST) codes can be heard by the user
in case of a hardware problem with the PC.
PCM
PC Beep Mute. When this bit is set to “1,” the channel is muted.
PCM
PCV3 . . . PCV0
Function
0
0
1
0000
1111
xxxx
0 dB Attenuation
–45 dB Attenuation
–∞ dB Attenuation
Phone Volume (Index 0Ch)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0Ch
Phone Volume
PHM
X
X
X
X
X
X
X
X
X
X
PHV4
PHV3
PHV2
PHV1
PHV0
Default
8008h
PHV [4:0]
Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
PHM
Phone Mute. When this bit is set to “1,” the channel is muted.
Mic Volume (Index 0Eh)
Reg
Num
Name
0Eh
Mic Volume
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MCM
X
X
X
X
X
X
X
X
M20
X
MCV4
MCV3
MCV2
MCV1
MCV0
Default
8008h
MCV [4:0]
Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
M20
Microphone +20 dB Gain Block
0 = Disabled; Gain = 0 dB.
1 = Enabled; Gain = +20 dB.
MCM
Mic Mute. When this bit is set to “1,” the channel is muted.
Line In Volume (Index 10h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
10h
LINE_IN Volume
LM
X
X
LLV4
LLV3
LLV2
LLV1
LLV0
X
X
X
RLV4
RLV3
RLV2
RLV1
RLV0
Default
8808h
RLV [4:0]
Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LLV [4:0]
Left Line In Volume. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LM
Line In Mute. When this bit is set to “1,” the channel is muted.
REV. 0
–13–
AD1819B
CD Volume (Index 12h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
12h
CD Volume
CVM
X
X
LCV4
LCV3
LCV2
LCV1
LCV0
X
X
X
RCV4
RCV3
RCV2
RCV1
RCV0
RCV [4:0]
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LCV [4:0]
Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
CVM
CD Volume Mute. When this bit is set to “1,” the channel is muted.
Default
8808h
Video Volume (Index 14h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
14h
Video Volume
VM
X
X
LVV4
LVV3
LVV2
LVV1
LVV0
X
X
X
RVV4
RVV3
RVV2
RVV1
RVV0
Default
RVV [4:0]
Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LVV [4:0]
Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
VM
Video Mute. When this bit is set to “1,” the channel is muted.
8808h
Aux Volume (Index 16h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16h
Aux Volume
AM
X
X
LAV4
LAV3
LAV2
LAV1
LAV0
X
X
X
RAV4
RAV3
RAV2
RAV1
RAV0
8808h
Default
RAV [4:0]
Right Aux Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LAV [4:0]
Left Aux Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
AM
Aux Mute. When this bit is set to “1,” the channel is muted.
Default
PCM Out Volume (Index 18h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
18h
PCM Out Volume
OM
X
X
LOV4
LOV3
LOV2
LOV1
LOV0
X
X
X
ROV4
ROV3
ROV2
ROV1
ROV0
8808h
ROV [4:0]
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LOV [4:0]
Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
OM
PCM Out Volume Mute. When this bit is set to “1,” the channel is muted.
Volume Table (Index 0Ch to 18h)
Mute
x4 . . . x0
Function
0
0
0
1
00000
01000
11111
xxxxx
+12 dB Gain
0 dB Gain
–34.5 dB Gain
–∞ dB Gain
–14–
REV. 0
AD1819B
Record Select Control (Index 1Ah)
Reg
Num
Name
1Ah
Record Select
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
X
X
X
X
X
LS2
LS1
LS0
X
X
X
X
X
RS2
RS1
RS0
0000h
RS [2:0]
Right Record Select.
LS [2:0]
Left Record Select.
Used to select the record source independently for right and left. See table for legend.
The default value is 0000h, which corresponds to Mic in.
RS2 . . . RS0
Right Record Source
0
1
2
3
4
5
6
7
MIC
CD_R
VIDEO_R
AUX_R
LINE_IN_R
Stereo Mix (R)
Mono Mix
PHONE_IN
LS2 . . . LS0
Left Record Source
0
1
2
3
4
5
6
7
MIC
CD_L
VIDEO_L
AUX_L
LINE_IN_L
Stereo Mix (L)
Mono Mix
PHONE_IN
Record Gain (Index 1Ch)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1Ch
Record Gain
IM
X
X
X
LIM3
LIM2
LIM1
LIM0
X
X
X
X
RIM3
RIM2
RIM1
RIM0
Default
8000h
RIM [3:0]
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB.
LIM [3:0]
Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB.
IM
Input Mute. 0 = Unmuted, 1 = Muted or –∞ dB gain.
IM
xIM3 . . . xIM0
Function
0
0
1
1111
0000
xxxxx
+22.5 dB Gain
0 dB Gain
– ∞ dB Gain
General Purpose (Index 20h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
20h
General Purpose
POP
X
3D
X
X
X
MIX
MS
LPBK
X
X
X
X
X
X
X
LPBK
Loopback Control. ADC/DAC digital loopback mode.
MS
MIC Select.
0 = MIC1.
1 = MIC2.
REV. 0
–15–
Default
0000h
AD1819B
MIX
Mono Output Select.
0 = Mix.
1 = Mic.
3D
Phat Stereo Enhancement.
0 = Phat Stereo is off.
1 = Phat Stereo is on.
POP
PCM Output Path. The POP bit controls the optional PCM out 3D bypass path (the pre- and post3D PCM outpaths are mutually exclusive).
0 = Pre-3D.
1 = Post-3D.
The register should be read before writing to generate a mask for only the bit(s) that need to be changed. The
default value is 0000h.
3D Control (Index 22h)
Reg
Num
Name
22h*
3D Control
DP [2:0]
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
X
X
X
X
X
X
X
X
X
X
X
X
DP3
DP2
DP1
DP0
0000h
Default
Depth Control. Sets 3D “Depth” Phat Stereo enhancement according to table below.
DP3 . . . DP0
0
1
14
15
Depth
0%
6.67%
93.33%
100%
Power-Down Control/Status (Index 26h)
Reg
Num
Name
26h
Power-Down Cntrl/Stat
ADC
DAC
ANL
REF
PR [5:0]
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
PR 5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
DAC
ADC
0000h
Ready Bits: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1819B subsections. If the bit is a one then that subsection is “ready.” Ready is defined as
the subsection able to perform in its nominal state.
ADC section ready to transmit data.
DAC section ready to accept data.
Analog gainuators, attenuators, and mixers ready.
Voltage References, VREF and V REFOUT up to nominal level.
Power-Down Bits. Bits 0 and 1 are to be used individually rather than in combination with each other. The last bit
PR3 can be used in combination with PR2 or by itself.
Power-Down State
Set Bits
ADCs and Input Mux Power-Down
DACs Power-Down
Analog Mixer Power-Down (VREF and VREFOUT On)
Analog Mixer Power-Down (VREF and VREFOUT Off)
AC-Link Interface Power-Down
Internal Clocks Disabled
ADC and DAC Power-Down
VREF Standby Mode
Total Power-Down
PR0
PR1
PR1, PR2
PR0, PR1, PR3
PR4
PR0, PR1, PR4, PR5
PR0, PR1
PR0, PR1, PR2, PR4, PR5
PR0, PR1, PR2, PR3, PR4, PR5
–16–
REV. 0
AD1819B
Serial Configuration (Index 74h)
Reg
Num
74h
Name
Serial Configuration
D15
D14
D13
D12
D11
D10
D9
D8
SLOT
16
REGM
2
REGM
1
REGM
0
DRQE
N
DLRQ
2
DLRQ
1
DLRQ
0
D7
X
D6
X
D5
D4
X
X
D3
D2
D1
X
DRRQ
2
DRRQ
1
D0
Default
DRRQ
7000h
0
DRRQ0
Master AC’97 Codec DAC Right Request.
DRRQ1
Slave 1 Codec DAC Right Request.
DRRQ2
Slave 2 Codec DAC Right Request.
DLRQ0
Master AC’97 Codec DAC Left Request.
DLRQ1
Slave 1 Codec DAC Left Request.
DLRQ2
Slave 2 Codec DAC Left Request.
DRQEN
Fills idle status slots with DAC request reads, and stuffs DAC requests into LSB of output address slot. (AC-Link
Slot 1.)
REGM0
Master Codec Register Mask.
REGM1
Slave 1 Codec Register Mask.
REGM2
Slave 2 Codec Register Mask.
SLOT16
Enable 16-Bit Slots.
If your system uses only a single AD1819B, you can ignore the register mask and the slave 1/slave 2 request bits. If
you write to this register, write ones to all of the register mask bits. The request bits are read-only.
The codec asserts each request bit when the corresponding DAC channel can accept data in the next frame. These
bits are snapshots of the codec state taken when the current frame began (effectively, on the rising edge of SYNC),
but they also take notice of DAC samples sent in the current frame.
If you set the DRQEN bit, the AD1819B will fill all otherwise unused AC-Link status address and data slots with
the contents of register 74h. That makes it somewhat simpler to access the information, because you don’t need to
continually issue AC-Link read commands to get the register contents.
Also, the DAC requests are reflected in Slot 1, Bits (11 . . . 6). These bits are active Lo.
SLOT16 makes all AC-Link slots 16 bits in length, formatted into 16 slots.
Miscellaneous Control Bits (Index 76h)
Reg
Num
76h
Name
D15
Misc Control Bits
DACZ
D14
X
D13
X
D12
X
D11
X
D10
DLSR
D9
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALSR
MOD
EN
SRX10
D7
SRX8
D7
X
X
DRSR
X
ARSR
Default
0000h
ARSR
ADC Right Sample Generator Select. Connects right ADC channel to SR0 or SR1.
0 = SR0 Selected.
1 = SR1 Selected.
DRSR
DAC Right Sample Generator Select. Connects right DAC channel to SR0 or SR1.
0 = SR0 Selected.
1 = SR1 Selected.
SRX8D7
Multiply SR1 Rate by 8/7.
SRX10D7
Multiply SR1 Rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set.
MODEN
Modem Filter Enable (left channel only). Change only when DACs are powered down.
ALSR
ADC Left Sample Generator Select. Connects left ADC channel to SR0 or SR1.
0 = SR0 Selected.
1 = SR1 Selected.
DLSR
DAC Left Sample Generator Select. Connects left DAC channel to SR0 or SR1.
0 = SR0 Selected.
1 = SR1 Selected.
DACZ
Zero-Fill (vs. repeat sample) if DAC is starved.
REV. 0
–17–
AD1819B
Sample Rate 0 (Index 78h)
Reg
Num
Name
78h
Sample Rate 0
SR0 [15:0]
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
SR015
SR014
SR013
SR012
SR011
SR010
SR09
SR08
SR07
SR06
SR05
SR04
SR03
SR02
SR01
SR00
BB80h
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Sample Rate 1 (Index 7Ah)
Reg
Num
Name
7Ah
Sample Rate 1
SR1 [15:0]
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
SR115
SR114
SR113
SR112
SR111
SR110
SR19
SR18
SR17
SR16
SR15
SR14
SR13
SR12
SR11
SR10
BB80h
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hz increments. The sample rate may be multiplied by 8/7 or 10/7 by setting Bits D6 and D5 in Register 76h.
Vendor ID (Index 7Ch–7Eh)
Reg
Num
Name
7Ch
Vendor ID1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
F7
F6
F5
F4
F3
F2
F1
F0
S7
S6
S5
S4
S3
S2
S1
S0
4144h
Default
S [7:0]
This register is ASCII encoded to “A.”
F [7:0]
This register is ASCII encoded to “D.”
Reg
Num
Name
7Eh
Vendor ID2
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
T7
T6
T5
T4
T3
T2
T1
T0
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
T [7:0]
This register is ASCII encoded to “S.”
REV [7:0]
Revision Register field contains the revision number.
5303h
These bits are read-only and should be verified before accessing vendor-defined features.
DIGITAL INTERFACE
AD1819B AC-Link Digital Serial Interface Protocol
The AD1819B incorporates an AC'97 5-pin digital serial interface that links it to a digital controller. AC-Link is a bidirectional, fixed
rate, serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employing a
time division multiplexed (TDM) scheme. The AC-Link architecture divides each audio frame into 12 outgoing and 12 incoming
data streams, up to 20-bit sample resolution. The AD1819B uses 16-bit samples. The data streams include:
AC ’97 Protocol
• TAG
1 Input and Output
• Control
Control Register Write Port
2 Output Slots
• Status
Control Register Read Port
2 Input Slots
• PCM Playback
2-Channel Composite PCM Output Stream
2 Output Slots
• PCM Record Data
2-Channel Composite PCM Input Stream
2 Input Slots
Synchronization of all AC-Link data transactions is signaled by the AC’97 controller. The AD1819B drives the serial bit clock onto
AC-Link, which the AC’97 controller then qualifies with a synchronization signal to construct audio frames.
SYNC, which is fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK) by 256. The BIT_CLK is fixed at
12.288 MHz. AC-Link serial data is updated on each rising edge of BIT_CLK. The receiver of AC-Link data, the AD1819B for outgoing data and the AC’97 controller for incoming data, samples each serial bit on the falling edge of BIT_CLK. SYNC must remain
high for a minimum of 1 BIT_CLK up to a maximum duration of 16 BIT_CLKs at the beginning of each audio frame. The first 16
bits of the audio frame is defined as the “Tag Phase.” The remainder of the audio frame is the “Data Phase.” The AD1819B uses
SYNC to define the beginning of the audio frame.
–18–
REV. 0
AD1819B
The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time
slot within the current audio frame. A “1” in a given bit position of Slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is “tagged” invalid, it is the responsibility of the
source of the data, (AD1819B for the input stream, AC’97 controller for the output stream), to stuff all bit positions with 0s during
that slot’s active time. The AD1819B stuffs all invalid slots with zeros and ignores invalid input slots.
Additionally, for power savings, all clock, sync, and data signals can be halted.
For multiple codec operations, the AD1819B supports an enhanced mode for communicating with up to two additional codecs. The
Slave 1 AD1819B codec uses Slots 5 and 6, while Slave 2 uses Slots 7 and 8 as shown in the following diagram.
ENHANCED MODE
1
SLOT # ....
2
3
4
5
6
7
8
9
CMD
DATA
PCM
LEFT
PCM
RIGHT
PCM
LEFT
PCM
RIGHT
PCM
LEFT
PCM
RIGHT
PCM
LEFT
PCM
RIGHT
PCM
LEFT
PCM
RIGHT
PCM
LEFT
PCM
RIGHT
10
11
12
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
SYNC
OUTGOING STREAMS
TAG
INCOMING STREAMS
TAG
CMD
ADR
STATUS STATUS
ADR
DATA
SLAVE 2
SLAVE 1
TAG
PHASE
DATA PHASE
Figure 9. Standard Bidirectional Audio Frame
AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting AD1819B’s DAC
inputs and control registers. As briefly mentioned earlier, each audio output frame supports up to twelve 20-bit outgoing data time
slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure.
Within Slot 0 the first bit is a global bit (SDATA_OUT Slot 0, Bit 15), which flags the validity for the entire audio frame. If the
“Valid Frame” bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12-bit
positions sampled by AC’97 indicate which of the corresponding 12 time slots contain valid data. In this way input DAC data
streams of differing sample rates can be transmitted across the AC-Link at its fixed 48 kHz audio frame rate. The following diagram
illustrates the time-slot-based AC-Link protocol.
TAG PHASE
DATA PHASE
20.8ms (48kHz)
12.2888MHz
SYNC
81.4ns
BIT_CLK
SDATA_IN
CODEC
READY SLOT(1) SLOT(2)
END OF PREVIOUS
AUDIO FRAME
SLOT(12)
“0”
“0”
“0”
TIME SLOT “VALID”
BITS
(1) = TIME SLOT CONTAINS VALID PCM DATA
19
0
SLOT 1
19
0
SLOT 2
19
0
SLOT 3
19
0
SLOT 12
Figure 10. AC-Link Audio Output Frame
A new audio output frame begins with a low-to-high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On
the immediately following falling edge of BIT_CLK, the AD1819B samples the assertion of SYNC. This falling edge marks the time
when both sides of AC-Link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC’97 controller
transitions SDATA_OUT into the first bit position of Slot 0 (Valid Frame Bit). Each new bit position is presented to AC-Link on a
rising edge of BIT_CLK, and subsequently sampled by AD1819B on the following falling edge of BIT_CLK. This sequence ensures
that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
REV. 0
–19–
AD1819B
AD1819A SAMPLES SYNC ASSERTION HERE
SYNC
AC’97 CONTROLLER SAMPLES
FIRST SDATA_OUT BIT OF FRAME HERE
BIT_CLK
VALID
FRAME
SDATA_OUT
SLOT (1) SLOT (2)
END OF PREVIOUS
AUDIO FRAME
Figure 11. Start of an Audio Output Frame
SDATA_OUT’s composite stream is MSB justified (MSB first) with all nonvalid slots’ bit positions stuffed with 0s by the
AC’97 controller. The AD1819B ignores invalid slots.
In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC’97 controller always stuffs all trailing
nonvalid bit positions of the 20-bit slot with 0s. The AD1819B ignores unused bits.
As an example, consider an 8-bit sample stream being played out to one of the AD1819B’s DACs. The first 8-bit positions are presented to the DAC (MSB justified), followed by the next 12 bit positions, which are stuffed with 0s by the AC’97 controller.
When mono audio sample streams are output from the AC’97 controller, it is necessary that BOTH left and right stream time slots
be filled with the same data.
Slot 1: Command Address Port
The command port is used to control features and request status (see Audio Input Frame Slots l and 2) for AD1819B functions
including, but not limited to, mixer settings and power management (refer to the control register section of this specification).
The control interface architecture supports up to sixty-four 16-bit read/write registers, addressable on even byte boundaries. Only the
even registers (00h, 02h, etc.) are valid, odd register (01h, 03h, etc.) accesses are discouraged (defaulting to the preceding even byte
boundary—i.e., a read to 01h will return the 16-bit contents of 00h). Note that shadowing of the control register file on the AC’97
controller is an option left open to the implementation of the AC’97 controller. The AD1819B’s control register file is readable as
well as writable.
Audio output frame Slot 1 communicates control register address, and write/read command information to AD1819B.
Command Address Port Bit Assignments:
Bit (19)
Read/Write Command
(1 = Read, 0 = Write)
Bit (18:12)
Control Register Index
(64 16-Bit Locations, Addressed On Even Byte Boundaries)
Bit (11:0)
Reserved
(Stuffed with 0s)
The first bit (MSB) sampled by the AD1819B indicates whether the current control transaction is a read or a write operation. The
following 7-bit positions communicate the targeted control register address. The trailing 12-bit positions within the slot are reserved.
Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a
write cycle (as indicated by Slot 1, Bit 19).
Bit (19:4)
Control Register Write Data
(Stuffed with 0s If Current Operation Is Not a Write)
Bit (3:0)
Reserved
(Stuffed with 0s)
If the current command port operation is not a write, the entire slot time should be stuffed with 0s by the AC’97 controller.
Slot 3: PCM Playback Left Channel
Audio output frame Slot 3 is the composite digital audio left playback stream. In a typical “Games Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC’97 controller or host processor) with music synthesis
output samples. If a sample stream of resolution less than 20 bits is transferred, the AC’97 controller should stuff all trailing
nonvalid bit positions within this time slot with 0s.
Slot 4: PCM Playback Right Channel
Audio output frame Slot 4 is the composite digital audio right playback stream. In a typical “Games Compatible” PC this slot is
composed of standard PCM (.wav) output samples digitally mixed (on the AC’97 controller or host processor) with music synthesis
output samples. If a sample stream of resolution less than 20 bits is transferred, the AC’97 controller should stuff all trailing nonvalid bit
positions within this time slot with 0s.
–20–
REV. 0
AD1819B
Slot 5–Slot 8: Multicodec Communication
• Slot 5 Slave 1 PCM Playback Left Channel
• Slot 6 Slave 1 PCM Playback Right Channel
• Slot 7 Slave 2 PCM Playback Left Channel
• Slot 8 Slave 2 PCM Playback Right Channel
Slot 6–Slot 12: Reserved
Audio output frame Slot 6 to Slot 12 are reserved for future use and should always be stuffed with 0s by the digital controller.
AC-Link Audio Input Frame (SDATA_IN)
The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC’97 controller. As
is the case for audio output frame, each AC-Link audio input frame consists of twelve 20-bit time slots. Slot 0 is a special reserved
time slot containing 16 bits used for AC-Link protocol infrastructure.
Within Slot 0 the first bit is a global bit (SDATA_IN Slot 0, Bit 15) which flags whether or not AD1819B is in the “Codec Ready”
state. If the “Codec Ready” bit is a 0, this indicates that AD1819B is not ready for normal operation. This condition is normal following the deassertion of power-on reset, for example, while AD1819B’s voltage references settle. When the AC-Link “Codec Ready”
indicator bit is a 1, it indicates that the AC-Link and AD1819B control and status registers are in a fully operational state and all
subsections are ready.
Prior to any attempts at putting AD1819B into operation the AC’97 controller should poll the first bit in the audio input frame
(SDATA_IN Slot 0, Bit 15) for an indication that the AD1819B has asserted “Codec Ready.” Once the AD1819B is sampled, “Codec
Ready” is asserted the next 12-bit positions sampled by the AC’97 controller indicate which of the corresponding 12 time slots are
assigned to input data streams and that they contain valid data. The following diagram illustrates the time-slot-based AC-Link protocol.
TAG PHASE
DATA PHASE
20.8ms (48kHz)
SYNC
12.288MHz
81.4ns
BIT_CLK
SDATA_IN
CODEC
READY
END OF PREVIOUS
AUDIO FRAME
SLOT(1) SLOT(2)
SLOT(12)
“0”
“0”
19
“0”
0
SLOT 1
TIME SLOT “VALID”
BITS
(1) = TIME SLOT CONTAINS VALID PCM DATA
19
0
SLOT 2
19
0
SLOT 3
19
0
SLOT 12
Figure 12. AC-Link Audio Input Frame
A new audio input frame begins with a low-to-high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On
the immediately following falling edge of BIT_CLK, the AD1819B samples the assertion of SYNC. This falling edge marks the time
when both sides of AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AD1819B transitions
SDATA_IN into the first bit position of Slot 0 (“Codec Ready” bit). Each new bit position is presented to AC-Link on a rising edge of
BIT_CLK, and subsequently sampled by the AC’97 controller on the following falling edge of BIT_CLK. This sequence ensures that
data transitions, and subsequent sample points for both incoming and outgoing data streams, are time aligned.
AD1819A SAMPLES SYNC ASSERTION HERE
SYNC
AC’97 CONTROLLER SAMPLES
FIRST SDATA_IN BIT OF FRAME HERE
BIT_CLK
CODEC
READY
SDATA_IN
SLOT (1) SLOT (2)
END OF PREVIOUS
AUDIO FRAME
Figure 13. Start of an Audio Input Frame
SDATA_IN’s composite stream is MSB justified (MSB first) with all nonvalid bit positions (for assigned and/or unassigned time
slots) stuffed with 0s by AD1819B.
Slot 0: Tag Phase SDATA_IN
The AD1819B is capable of sampling data from 7 kHz to 48 kHz with a resolution of 1 kHz. To enable a sample rate other than the
default 48 kHz, set the DRQEN bit (Register 74h Bit 11). This allows DAC request bits (these are low active) to be output on the
SDATA_IN stream. The digital controller should monitor the ADC valid bits to determine when the codec has valid data ready to
send.
REV. 0
–21–
AD1819B
TAG Phase Bit Assignments:
Bit (15)
Bit (14)
Bit (13)
Bit (12)
Bit (11)
Bit (10)
Bit (9)
Bit (8)
Bit (7)
Bit (6:0)
Codec Ready
Slot 1 Valid
Slot 2 Valid
Slot 3 Valid/ADC Left Data Is Valid on Slot 3
Slot 4 Valid/ADC Right Data Is Valid on Slot 4
Slot 5 Valid/ADC Left Data Slave 1 Valid on Slot 5
Slot 6 Valid/ADC Right Data Slave 1 Valid on Slot 6
Slot 7 Valid/ADC Left Data Slave 2 Valid on Slot 7
Slot 8 Valid/ADC Right Data Slave 2 Valid on Slot 8
Not Used
Slot 1: Status Address Port
The status port is used to monitor status for AD1819B functions including, but not limited to, mixer settings and power
management.
Audio input frame Slot 1’s stream echoes the control register index, for historical reference, for the data to be returned in Slot 2
(assuming that Slots 1 and 2 had been tagged “valid” by the AD1819B during Slot 0).
Status Address Port Bit Assignments:
Bit (19)
Bit (18:12)
Bit (11)
Bit (10)
Bit (9)
Bit (8)
Bit (7)
Bit (6)
Bit (5:0)
RESERVED
Control Register Index
DAC Request Slot 3
DAC Request Slot 4
DAC Request Slot 5
DAC Request Slot 6
DAC Request Slot 7
DAC Request Slot 8
RESERVED
(Stuffed with 0)
(Echo of Register Index for Which Data Is Being Returned)
(0 = Request, 1 = No Request)
(0 = Request, 1 = No Request)
(0 = Request, 1 = No Request); Slave 1
(0 = Request, 1 = No Request); Slave 1
(0 = Request, 1 = No Request); Slave 2
(0 = Request, 1 = No Request); Slave 2
(Stuffed with 0s)
The first bit (MSB) generated by the AD1819B is always stuffed with a 0. The following 7-bit positions communicate the associated
control register address, and the trailing 12-bit positions are stuffed with 0s by the AD1819B.
Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
Bit (19:4)
Control Register Read Data
(Stuffed with 0s If Tagged “Invalid” by AD1819B)
Bit (3:0)
RESERVED
(Stuffed with 0s)
If Slot 2 is tagged “invalid” by the AD1819B, the entire slot will be stuffed with 0s by the AD1819B.
Slot 3: PCM Record Left Channel
Audio input frame Slot 3 is the left channel output of the AD1819B’s input MUX, post-ADC.
AD1819B transmits its ADC output data (MSB first), and stuffs the trailing nonvalid bit positions with 0s to fill out its 20-bit time slot.
Slot 4: PCM Record Right Channel
Audio input frame Slot 4 is the right channel output of the AD1819B’s input MUX, post-ADC.
AD1819B transmits its ADC output data (MSB first), and stuffs the trailing nonvalid bit positions with 0s to fill out its 20-bit time slot.
Slot 5–Slot 8: Multicodec Communication
• Slot 5 Slave 1 PCM Record Left Channel
• Slot 6 Slave 1 PCM Record Right Channel
• Slot 7 Slave 2 PCM Record Left Channel
• Slot 8 Slave 2 PCM Record Right Channel
Slot 9–Slot 12: Reserved
Audio input frame Slots 9–12 are reserved for future use and are always stuffed with 0s by the AD1819B.
AC-Link Low Power Mode
The AC-Link signals can be placed in a low power mode. When the AD1819B’s Power-Down Register (26h) is programmed to the
appropriate value, both BIT_CLK and SDATA_IN will be brought to a logic low voltage level.
–22–
REV. 0
AD1819B
SYNC
BIT_CLK
SDATA_OUT
SLOT 12
PREVIOUS
FRAME
TAG
SDATA_IN
SLOT 12
PREVIOUS
FRAME
TAG
WRITE TO
0x26
DATA
PR4
NOTE:
BIT_CLK NOT TO SCALE
Figure 14. AC-Link Power-Down Timing
BIT_CLK and SDATA_IN are transitioned low immediately following the decode of the write to the Power-Down Register (26h)
with PR4. When the AC’97 controller driver is at the point where it is ready to program the AC-Link into its low power mode, Slots
(1 and 2) must be the only valid stream in the audio output frame.
The AC’97 controller should also drive SYNC and SDATA_OUT low after programming AD1819B to this low power “halted” mode.
Once AD1819B has been instructed to halt BIT_CLK, a special “wake-up” protocol must be used to bring the AC-Link to the active
mode, since normal audio output and input frames can not be communicated in the absence of BIT_CLK.
Waking up the AC-Link
There are two methods for bringing the AC-Link out of a low power, halted mode. Regardless of the method, it is the AC’97
controller that performs the wake-up task.
AC-Link protocol provides for a “Cold AC’97 Reset,” and a “Warm AC’97 Reset.” The current power-down state would
ultimately dictate which form of AC’97 reset is appropriate. Unless a “cold” or “register” reset (a write to the Reset Register) is
performed, wherein the AD1819B registers are initialized to their default values, registers are required to keep state during all powerdown modes. The Serial Configuration Register (0x74) maintains state during a register reset.
Once powered down, reactivation of the AC-Link via reassertion of the SYNC signal may be immediate. When the AD1819B powers
up, it indicates readiness via the Codec Ready Bit (Input Slot 0, Bit 15).
Cold AC’97 Reset
A cold reset is achieved by asserting RESET for at least the minimum specified time. SYNC and SDATA_IN should be held low during
the rising edge of RESET. By driving RESET, BIT_CLK and SDATA_IN will be activated, and all AD1819B control registers will be
initialized to their default power-on reset values.
RESET is an asynchronous AD1819B input.
Warm AC’97 Reset
A warm AC’97 reset will reactivate the AC-Link without altering the current AD1819B register values. A warm reset is signaled
by driving SYNC high for a minimum of 1 µs in the absence of BIT_CLK.
Within normal audio frames SYNC is a synchronous AD1819B input. In the absence of BIT_CLK, however, SYNC is treated as an
asynchronous input used in the generation of a warm reset to the AD1819B.
REV. 0
–23–
AD1819B
MULTIPLE CODE CONFIGURATION
Setting Up Multiple Codecs
The AD1819B may be used with up to two additional AD1819
or AD1819B codecs. In order to configure the codecs as Master, Slave 1 or Slave 2, refer to the following table.
CS1
CS0
Configuration
0
0
1
1
0
1
0
1
Slave 1 Codec
Slave 2 Codec
Master Codec
AC’97 Mode Codec
0 = Ground; 1 = V DD.
The XTAL_IN pin on the Slave Codecs “must” be tied to
ground and the CHAIN_IN pin “must” be tied to ground on
the last codec Slave 1 (on a 2-codec design) or Slave 2 (on a
3-codec design). See Figures 15, 16 and 17.
Configure the Codec Resources
Programing REGM (2:0) bits in the Serial Configuration Register (74h) allows the digital controller read write access to all the
internal registers on each codec according to the following table.
REGM2 REGM1
REGM0
Read
Write
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
x
Master
Slave 1
Master
Slave 2
Master
Slave 1
Master
x
Master
Slave 1
Master, Slave 1
Slave 2
Master, Slave 2
Slave 1, Slave 2
Master, Slave 1, Slave 2
–24–
0
0
1
1
0
0
1
1
REV. 0
AD1819B
APPLICATIONS CIRCUITS
The AD1819B has been designed to require a minimum amount
of external circuitry. The recommended applications circuits are
shown in Figures 15–18. Reference designs for the AD1819B
are available and may be obtained by contacting your local
Analog Devices’ sales representative or authorized distributor.
Example shell programs for establishing a communications path
between the AD1819B and an ADSP-21xx DSP are also available.
+5AVDD
+5AVDD
10mF TANT
100nF
1.37kV
+5DVDD
+5DVDD
10mF TANT
10mF TANT
10mF TANT
100nF
100nF
100nF
100nF
AVDD2 AVSS2
AVDD1 AVSS
DVSS1 DVDD1
DVSS2 DVDD2
PC_BEEP
4.99kV
100nF
1mF
LINE_IN_R
1mF
LINE_IN_L
RESET
1mF
1mF
MIC1
SDATA_OUT
MIC2
SDATA_IN
1mF
CD_R
BIT_CLK
1mF
CD_L
1mF
AD1819B
CD_GND
DVDD
1mF
VIDEO_L
1mF
CS0
VIDEO_R
CS1
1mF
1mF
AUX_L
CHAIN_IN 47
AUX_R
CHAIN_CLK 48
1mF
PHONE_IN
1mF
7
MONO_OUT
1mF
36
1mF
LINE_OUT_R
LINE_OUT_L
47kV 47kV
47kV
AFILT1 AFILT2
FILT_L
FILT_R
CX3D
RX3D
VREFOUT
VREF
34
33
28
27
XTAL_IN
100nF
270pF
NP0
270pF
NP0
1mF
47nF
100nF
600Z
10mF
TANT
22pF
NP0
22pF
NP0
DIGITAL GROUND
Figure 15. Recommended One Codec Application Circuit
–25–
XTAL_OUT
24.576MHz
2.25VDC
1mF
ANALOG GROUND
REV. 0
DIGITAL
CONTROLLER
SYNC
AD1819B
RESET
RESET
DR0
SYNC
SYNC
RFS0
BIT_CLK
BIT_CLK
MASTER
DT0
SDATA_IN
SDATA_IN
AD1819B
FL0
SDATA_OUT
SDATA_OUT
SCLK0
CS0
CS1
DIGITAL
CONTROLLER
(ADSP-2181)
SPORT0
DVDD
CHAIN_IN
CHAIN_CLK
XTAL_OUT
XTAL_IN
24.576MHz
22pF
NP0
22pF
NP0
RESET
SDATA_OUT
SDATA_IN
SYNC
AD1819B
BIT_CLK
SLAVE 1
CS0
CS1
CHAIN_IN
CHAIN_CLK
XTAL_IN
XTAL_OUT
RESET
SDATA_OUT
SDATA_IN
SYNC
AD1819B
SLAVE 2
BIT_CLK
CS0
DVDD
CS1
CHAIN_IN
CHAIN_CLK
XTAL_IN
XTAL_OUT
Figure 16. Three Codec System Example
–26–
REV. 0
AD1819B
RESET
RESET
DR0
SYNC
SYNC
RFS0
BIT_CLK
BIT_CLK
MASTER
DT0
SDATA_IN
SDATA_IN
AD1819B
FL0
SDATA_OUT
SDATA_OUT
SCLK0
CS0
SPORT0
CS1
DVDD
CHAIN_IN
CHAIN_CLK
XTAL_IN
XTAL_OUT
24.576MHz
22pF
NP0
22pF
NP0
RESET
SDATA_OUT
SDATA_IN
SYNC
AD1819B
SLAVE 1
BIT_CLK
CS0
CS1
CHAIN_IN
CHAIN_CLK
XTAL_IN
XTAL_OUT
Figure 17. Two Codec System Example
AD1819B
2.21kV*
VREFOUT
FB
MIC
INPUT
100nF
100V
MIC1**
100pF
10nF*
NC
. 10mV RMS
(mean)
200Hz < FREQUENCY RESPONSE < 5kHz @ –3dB
NOTES:
*MAY NEED TO OPTIMIZE TO SUIT MICROPHONE
**SELECT MIC1 AND MAX GAIN 20dB +12dB for 10mV
RMS MICROPHONE OUTPUT.
Figure 18. Microphone Input
REV. 0
–27–
MIC2
DIGITAL
CONTROLLER
(ADSP-2181)
AD1819B
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Terminal LQFP
(ST-48)
0.063 (1.60) MAX
0.276 (7.0) BSC
37
36
48
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0° – 7°
0° MIN
0.007 (0.18)
0.004 (0.09)
12
13
0.0197 (0.5)
BSC
25
24
0.011 (0.27)
0.006 (0.17)
PRINTED IN U.S.A.
0.006 (0.15)
0.002 (0.05)
C3681–2–10/99
0.276 (7.0) BSC
0.354 (9.00) BSC
0.030 (0.75)
0.018 (0.45)
0.354 (9.00) BSC
0.030 (1.45)
(0.75)
0.057
0.018 (1.35)
(0.45)
0.053
–28–
REV. 0