www.fairchildsemi.com FSDM07652R Green Mode Fairchild Power Switch (FPSTM) Features • Internal Avalanche Rugged Sense FET • Advanced Burst-Mode operation consumes under 1 W at 240VAC & 0.5W load • Precision Fixed Operating Frequency (66kHz) • Internal Start-up Circuit • Pulse by Pulse Current Limiting • Abnormal Over Current Protection (AOCP) • Over Voltage Protection (OVP) • Over Load Protection (OLP) • Internal Thermal Shutdown Function (TSD) • Auto-Restart Mode • Under Voltage Lock Out (UVLO) with hysteresis • Low Operating Current (2.5mA) • Built-in Soft Start Application • SMPS for LCD monitor and STB • Adaptor Description The FSDM07652R is an integrated Pulse Width Modulator (PWM) and Sense FET specifically designed for high performance offline Switch Mode Power Supplies (SMPS) with minimal external components. This device is an integrated high voltage power switching regulator which combine an avalanche rugged Sense FET with a current mode PWM control block. The PWM controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (LEB), optimized gate driver, internal soft start, temperature compensated precise current sources for a loop compensation and self protection circuitry. Compared with discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. This device is a basic platform well suited for cost effective designs of flyback converters. OUTPUT POWER TABLE 230VAC ±15%(3) PRODUCT Adapter(1) Open Frame(2) 85-265VAC Adapter(1) Open Frame(2) FSDM0565R 60W 70W 50W 60W FSDM07652R 70W 80W 60W 70W Table 1. Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2. Maximum practical continuous power in an open frame design at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. Typical Circuit AC IN DC OUT Vstr Drain PWM Vfb Vcc Source Figure 1. Typical Flyback Application Rev.1.0.6 ©2005 Fairchild Semiconductor Corporation FSDM07652R Internal Block Diagram Vcc Drain 1 Vstr 6 3 N.C 5 Istart 0.5/0.7V + Vref 8V/12V Vcc Vcc good Internal Bias Switching disable Vref OSC Idelay Vfb IFB S Q R Q PWM 4 2.5R Soft start Gate driver R LEB V SD Vcc 2 GND S Q R Q Vovp TSD Vcc good AOCP Figure 2. Functional Block Diagram of FSDM07652R 2 Vocp FSDM07652R Pin Definitions Pin Number Pin Name Pin Function Description 1 Drain This pin is the high voltage power Sense FET drain. It is designed to drive the transformer directly. 2 GND This pin is the control ground and the Sense FET source. Vcc This pin is the positive supply voltage input. During start up, the power is supplied by an internal high voltage current source that is connected to the Vstr pin. When Vcc reaches 12V, the internal high voltage current source is disabled and the power is supplied from the auxiliary transformer winding. 4 Vfb This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 6.0V, the over load protection is activated resulting in shutdown of the FPSTM. 5 N.C - Vstr This pin is connected directly to the high voltage DC link. At startup, the internal high voltage current source supplies internal bias and charges the external capacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal current source is disabled. 3 6 Pin Configuration TO-220F-6L 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain Figure 3. Pin Configuration (Top View) 3 FSDM07652R Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Parameter Drain-source voltage Vstr Max Voltage Pulsed Drain current (Tc=25°C) (1) Continuous Drain Current(Tc=25°C) Continuous Drain Current(Tc=100°C) Symbol Value Unit VDSS 650 V VSTR 650 V IDM 15 ADC 3.8 A 2.4 A ID Single pulsed avalanche energy (2) EAS 370 mJ Single pulsed avalanche current (3) IAS - A VCC 20 V Supply voltage VFB -0.3 to VCC V PD(Watt H/S) 45 W Operating junction temperature Tj Internally limited °C Operating ambient temperature TA -25 to +85 °C TSTG -55 to +150 °C ESD Capability, HBM Model (All pins excepts for Vstr and Vfb) - 2.0 (GND-Vstr/Vfb=1.5kV) kV ESD Capability, Machine Model (All pins excepts for Vstr and Vfb) - 300 (GND-Vstr/Vfb=225V) V Symbol Value Unit θJA θJC(2) 49.90 °C/W 2.78 °C/W Input voltage range Total power dissipation(Tc=25°C) Storage temperature range Notes: 1. Repetitive rating: Pulse width limited by maximum junction temperature 2. L=14mH, starting Tj=25°C 3. L=13uH, starting Tj=25°C Thermal Impedance Parameter Junction-to-Ambient Thermal Junction-to-Case Thermal Notes: 1. Free standing with no heat-sink under natural convection. 2. Infinite cooling condition - Refer to the SEMI G30-88. 4 (1) FSDM07652R Electrical Characteristics (Ta = 25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit BVDSS VGS = 0V, ID = 250µA 650 - - V VDS = 650V, VGS = 0V - - 50 µA IDSS VDS= 520V VGS = 0V, TC = 125°C - - 200 µA RDS(ON) VGS = 10V, ID = 2.5A - 1.4 1.6 Ω Output capacitance COSS VGS = 0V, VDS = 25V, f = 1MHz - 100 - pF Turn on delay time TD(ON) - 22 - - 60 - - 115 - - 65 - VFB = 3V 60 66 72 kHz 13V ≤ Vcc ≤ 18V 0 1 3 % -25°C ≤ Ta ≤ 85°C 0 ±5 ±10 % Sense FET SECTION Drain source breakdown voltage Zero gate voltage drain current Static drain source on resistance (1) Rise time Turn off delay time Fall time TR TD(OFF) VDD= 325V, ID= 5A (MOSFET switching time is essentially independent of operating temperature) TF ns CONTROL SECTION Initial frequency FOSC Voltage stability FSTABLE Temperature stability (2) ∆FOSC Maximum duty cycle DMAX - 75 80 85 % Minimum duty cycle DMIN - - - 0 % Start threshold voltage VSTART VFB=GND 11 12 13 V Stop threshold voltage VSTOP VFB=GND 7 8 9 V Feedback source current IFB VFB=GND 0.7 0.9 1.1 mA Soft-start time TS VFB=3 - 10 15 ms - 250 - ns Leading Edge Blanking time - TLEB BURST MODE SECTION VBURH Vcc=14V - 0.7 - V VBURL Vcc=14V - 0.5 - V Peak current limit (4) IOVER VFB=5V, VCC=14V 2.2 2.5 2.8 A Over voltage protection VOVP - 18 19 20 V Abnormal Over current protection current (3) IAOCP - 5.54 6.15 6.77 A Thermal shutdown temperature (2) TSD 130 145 160 °C Shutdown feedback voltage VSD 5.5 6.0 6.5 V Burst Mode Voltages (2) PROTECTION SECTION VFB ≥ 5.5V 5 FSDM07652R Shutdown delay current IDELAY VFB=5V 2.8 3.5 4.2 µA - 2.5 5 mA TOTAL DEVICE SECTION Operating supply current (5) IOP VFB=GND, VCC=14V IOP(MIN) VFB=GND, VCC=10V IOP(MAX) VFB=GND, VCC=18V Notes: 1. Pulse test : Pulse width ≤ 300µS, duty ≤ 2% 2. These parameters, although guaranteed at the design, are not tested in mass production. 3. These parameters, although guaranteed, are tested in EDS(wafer test) process. 4. These parameters indicate the inductor current. 5. This parameter is the current flowing into the control IC. 6 FSDM07652R Comparison Between FS6M07652RTC and FSDM07652R Function FS6M07652RTC Soft-Start Adjustable soft-start time using an external capacitor Burst Mode Operation FSDM07652R FSDM07652R Advantages Internal soft-start with • Gradually increasing current limit typically 10ms (fixed) during soft-start further reduces peak current and voltage component stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot • Built into controller • Built into controller • Improve light load efficiency • Output voltage fixed • Reduces no-load consumption • Output voltage drops to around half 7 FSDM07652R Typical Performance Characteristics 1.2 1.2 1.0 1.0 Start Thershold Voltage (Normalized to 25℃) Operating Current (Normalized to 25℃) (These Characteristic Graphs are Normalized at Ta= 25°C) 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0.0 0.0 -50 -25 0 25 50 75 100 -50 125 1.2 1.2 1.0 1.0 0.8 0.6 0.4 25 50 75 100 125 0.8 0.6 0.4 0.2 0.2 0.0 0.0 -50 -25 0 25 50 75 100 125 -50 Junction Temperature(℃) -25 0 25 50 75 100 125 Junction Temperature(℃) Stop Threshold Voltage vs. Temp Operating Freqency vs. Temp 1.2 1.2 1.0 FB Source Current (Normalized to 25℃) 1.0 Maximum Duty Cycle (Normalized to 25℃) 0 Start Threshold Voltage vs. Temp Initial Frequency (Normalized to 25℃) Stop Threshold Voltage (Normalized to 25℃) Operating Current vs. Temp 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 Junction Temperature(℃) Maximum Duty vs. Temp 8 -25 Junction Temperature(℃) Junction Temperature(℃) 125 0.0 -50 -25 0 25 50 75 100 Junction Temperature(℃) Feedback Source Current vs. Temp 125 FSDM07652R Typical Performance Characteristics (Continued) 1.2 1.2 1.0 1.0 Shutdown Delay Current (Normalized to 25℃) Shutdown FB Voltage (Normalized to 25℃) (These Characteristic Graphs are Normalized at Ta= 25°C) 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 0.8 0.6 0.4 0.2 0.0 125 -50 -25 Junction Temperature(℃) ShutDown Feedback Voltage vs. Temp 25 50 75 100 125 ShutDown Delay Current vs. Temp 1.2 1.2 Burst Mode Enable Voltage (Normalized to 25℃) 1.0 Over Voltage Protection (Normalized to 25℃) 0 Junction Temperature(℃) 0.8 0.6 0.4 0.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 0.0 125 -50 Junction Temperature(℃) -25 0 25 50 75 100 125 Junction Temperature(℃) Burst Mode Enable Voltage vs. Temp 1.2 1.2 1.0 1.0 Over Current Limit (Normalized to 25℃) Burst Mode Disable Voltage (Normalized to 25℃) Over Voltage Protection vs. Temp 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0.0 0.0 -50 -25 0 25 50 75 100 125 Junction Temperature(℃) Burst Mode Disable Voltage vs. Temp -50 -25 0 25 50 75 100 125 Junction Temperature(℃) Current Limit vs. Temp 9 FSDM07652R Typical Performance Characteristics (Continued) (These Characteristic Graphs are Normalized at Ta= 25°C) 1.2 Soft Start Time (Normalized to 25℃) 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 Junction Temperature(℃) Soft Start Time vs. Temp 10 100 125 FSDM07652R Functional Description 1. Startup : In previous generations of Fairchild Power Switches (FPSTM) the Vcc pin had an external start-up resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source. At startup, an internal high voltage current source supplies the internal bias and charges the external capacitor (Cvcc) that is connected to the Vcc pin as illustrated in figure 4. When Vcc reaches 12V, the FPSTM begins switching and the internal high voltage current source is disabled. Then, the FPSTM continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless Vcc goes below the stop voltage of 8V. VDC CVcc Vcc 3 6 2.1 Pulse-by-pulse current limit: Because current mode control is employed, the peak current through the Sense FET is limited by the inverting input of PWM comparator (Vfb*) as shown in figure 5. Assuming that the 0.9mA current source flows only through the internal resistor (2.5R +R= 2.8 kΩ), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (Vfb) exceeds 2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping Vfb*. Therefore, the peak value of the current through the Sense FET is limited. 2.2 Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPSTM employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on. Vstr Vcc Istart Vref 8V/12V Vref Idelay Vcc good Vfb Vo 4 H11A817A Figure 4. Internal startup circuit SenseFET OSC D1 CB Internal Bias IFB D2 2.5R + Vfb* KA431 Gate driver R - VSD OLP Rsense Figure 5. Pulse width modulation (PWM) circuit 2. Feedback Control : FSDM07652R employs current mode control, as shown in figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. 3. Protection Circuit : The FSDM07652R has several self protective functions such as over load protection (OLP), abnormal over current protection (AOCP), over voltage protection (OVP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC without external components, the reliability can be improved without increasing cost. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage, 8V, the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage,12V, the FPSTM resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see figure 6). 11 FSDM07652R Vds Power on Fault occurs VFB Fault removed Over load protection 6.0V 2.5V Vcc T 12= Cfb*(6.0-2.5)/Idelay T1 12V t Figure 7. Over load protection 8V Fault situation Normal operation Figure 6. Auto restart operation 3.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is in the normal operation, the over load protection circuit can be activated during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the Sense FET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked and the 3.5uA current source starts to charge CB slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 6V, when the switching operation is terminated as shown in figure 7. The delay time for shutdown is the time required to charge CB from 2.5V to 6.0V with 3.5uA. In general, a 10 ~ 50 ms delay time is typical for most applications. 2.5R OSC PWM R S Q R Q Gate driver LEB Rsense 2 AOCP - Normal operation 3.2 Abnormal Over Current Protection (AOCP) : Even though the FPSTM has OLP (Over Load Protection) and current mode PWM feedback, these are not enough to protect the FPSTM when a secondary side diode short or a transformer pin short occurs. The FPSTM has an internal AOCP (Abnormal Over Current Protection) circuit as shown in figure 8. When the gate turn-on signal is applied to the power Sense FET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is then compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level for longer than 300ns, the reset signal is applied to the latch, resulting in the shutdown of SMPS. + t 12 T2 Vaocp GND Figure 8. AOCP block 3.3 Over voltage Protection (OVP) : If the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, Vfb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because more energy than required is provided to the output, the FSDM07652R output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FPSTM uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, an OVP circuit is activated resulting in the termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be designed to be below 19V. Vo Voset VFB 0.7V 0.5V Ids 3.4 Thermal Shutdown (TSD) : The Sense FET and the control IC are built in one package. This makes it easy for the control IC to detect the heat generation from the Sense FET. When the temperature exceeds approximately 150°C, the thermal shutdown is activated. 4. Soft Start : The FPSTM has an internal soft start circuit that increases PWM comparator inverting input voltage together with the Sense FET current slowly after it starts up. The typical soft start time is 10msec, The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. Vds time Switching disabled T1 T2 T3 Switching disabled T4 Figure 9. Waveforms of burst operation 5. Burst operation : In order to minimize power dissipation in standby mode, the FPSTM enters burst mode operation. As the load decreases, the feedback voltage decreases. As shown in figure 9, the device automatically enters burst mode when the feedback voltage drops below VBURL(500mV). At this point switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBURH(700mV) switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in Standby mode. 13 FSDM07652R Typical application circuit Application Output power LCD Monitor 40W Input voltage Output voltage (Max current) Universal input 5V (2.0A) (85-265Vac) 12V (2.5A) Features • • • • • • High efficiency (>81% at 85Vac input) Low zero load power consumption (<300mW at 240Vac input) Low standby mode power consumption (<800mW at 240Vac input and 0.3W load) Low component count Enhanced system reliability through various protection functions Internal soft-start (10ms) Key Design Notes • Resistors R102 and R105 are employed to prevent start-up at low input voltage. After startup, there is no power loss in these resistors since the startup pin is internally disconnected after startup. • The delay time for over load protection is designed to be about 50ms with C106 of 47nF. If a faster triggering of OLP is required, C106 can be reduced to 10nF. • Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zener diode fails and remains short, which causes the fuse (F1) blown and prevents explosion of the opto-coupler (IC301). This zener diode also increases the immunity against line surge. 1. Schematic D202 T1 EER3016 MBRF10100 C103 100uF 400V R105 40kΩ Ω BD101 2 2KBP06M3N257 1 2 D101 UF 4007 8 3 Vstr Drain 1 5 D201 MBRF1045 NC 4 C102 220nF 275VAC 4 ZD102 10V C106 47nF 50V C202 1000uF 25V C201 1000uF 25V IC1 FSDM07652R 6 3 C104 2.2nF 1kV R103 56kΩ Ω 2W 12V, 2.5A 10 1 R102 30kΩ Ω L201 Vcc 3 Vfb GND 2 ZD101 22V C105 D102 22uF TVR10G 50V R104 5Ω Ω 4 L202 5V, 2A 7 C204 1000uF 10V C203 1000uF 10V 6 5 C301 4.7nF LF101 23mH R201 1kΩ Ω R101 560kΩ Ω 1W RT1 5D-9 14 C101 220nF 275VAC R202 1.2kΩ Ω F1 FUSE 250V 2A IC301 H11A817A IC201 KA431 R204 5.6kΩ Ω R203 12kΩ Ω C205 47nF R205 5.6kΩ Ω FSDM07652R 2. Transformer Schematic Diagram EER3016 Np/2 Np/2 1 10 N 12V 2 9 3 8 4 7 N 5V Na 5 6 3.Winding Specification No Na Pin (s→f) 4→5 Wire 0.2φ ×1 Turns Winding Method 8 Center Winding 18 Solenoid Winding 7 Center Winding 3 Center Winding 18 Solenoid Winding Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 2→1 0.4φ × 1 Insulation: Polyester Tape t = 0.050mm, 2Layers N12v 10 → 8 0.3φ × 3 Insulation: Polyester Tape t = 0.050mm, 2Layers N5v 7→6 0.3φ × 3 Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 3→2 0.4φ × 1 Outer Insulation: Polyester Tape t = 0.050mm, 2Layers 4.Electrical Characteristics Pin Specification Remarks Inductance 1-3 520uH ± 10% 100kHz, 1V Leakage Inductance 1-3 10uH Max 2nd all short 5. Core & Bobbin Core : EER 3016 Bobbin : EER3016 Ae(mm2) : 96 15 FSDM07652R 6.Demo Circuit Part List Part Value Note Fuse F101 Part Value Note C301 4.7nF Polyester Film Cap. 2A/250V NTC RT101 Inductor 5D-9 Resistor L201 5uH Wire 1.2mm L202 5uH Wire 1.2mm R101 560K 1W R102 30K 1/4W R103 56K 2W R104 5 1/4W R105 40K 1/4W D101 UF4007 R201 1K 1/4W D102 TVR10G R202 1.2K 1/4W D201 MBRF1045 R203 12K 1/4W D202 MBRF10100 R204 5.6K 1/4W ZD101 Zener Diode 22V R205 5.6K 1/4W ZD102 Zener Diode 10V Diode Bridge Diode BD101 2KBP06M 3N257 Bridge Diode Capacitor 16 C101 220nF/275VAC Box Capacitor C102 220nF/275VAC Box Capacitor C103 100uF/400V Electrolytic Capacitor C104 2.2nF/1kV Ceramic Capacitor IC101 FSDM07652R FPSTM(7A,650V) C105 22uF/50V Electrolytic Capacitor IC201 KA431(TL431) Voltage reference C106 47nF/50V Ceramic Capacitor IC301 H11A817A Opto-coupler C201 1000uF/25V Electrolytic Capacitor C202 1000uF/25V Electrolytic Capacitor C203 1000uF/10V Electrolytic Capacitor C204 1000uF/10V Electrolytic Capacitor C205 47nF/50V Ceramic Capacitor Line Filter LF101 23mH Wire 0.4mm IC FSDM07652R 7. Layout Figure 10. Layout Considerations for FSDM07652R Figure 11. Layout Considerations for FSDM07652R 17 FSDM07652R Package Dimensions TO-220F-6L(Forming) 18 FSDM07652R Ordering Information Product Number FSDM07652RWDTU Package Marking Code BVdss Rds(on)Max. TO-220F-6L(Forming) DM07652R 650V 1.6 Ω WDTU : Forming Type 19 FSDM07652R DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 1/12/05 0.0m 001 2005 Fairchild Semiconductor Corporation