5V/3.3V 2.5Gbps LIMITING POST AMPLIFIER WITH SIGNAL DETECT DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ 3.3V and 5V power supply options Up to 2.5Gbps operation Low noise Chatter-fee signal detect (SD) generation Open collector TTL signal detect (SD) output TTL EN input Differential PECL inputs for data Single power supply Designed for use with Micrel-Synergy laser diode driver and controller ■ Available in a tiny (3mm) 10-pin MSOP The SY88943V limiting post amplifier with its high gain and wide bandwidth is ideal for use as a post amplifier in fiber-optic receivers with data rates up to 2.5Gbps. Signals as small as 5mVp-p can be amplified to drive devices with PECL inputs. The SY88943V generates a chatter-free Signal Detect (SD) open collector TTL output. The SY88943V incorporates a programmable level detect function to identify when the input signal has been lost. The SD output will change from logic “HIGH” to logic “LOW” when input signal is smaller than the swing set by SDLVL. This information can be fed back to the EN input of the device to maintain stability under loss of signal condition. Using SDLVL pin, the sensitivity of the level detection can be adjusted. The SDLVL voltage can be set by connecting a resistor divider between VCC and VREF as shown in Figure 3. Figure 4, 5, 6, and 7 show the relationship between input level sensitivity and the voltage set on SDLVL. The SD output is a TTL open collector output that requires a pull-up resistor for proper operation, Figure 1. PIN CONFIGURATION EN 1 10 VCC DIN 2 /DIN 3 VREF 4 SDLVL 5 SY88943V VCC 9 DOUT MSOP K10-1 SY88943V 8 /DOUT SD 7 SD 4.7kΩ to 10kΩ 6 GND Figure 1. SD Output with Desired Rise Time BLOCK DIAGRAM APPLICATIONS ■ ■ ■ ■ ■ ■ 1.25Gbps and 2.5Gbps ethernet 531Mbps, 1062Mbps and 2.12Gbps Fibre Channel 622Mbps SONET Gigabit interface converter 2.5Gbps SDH/SONET 2.5Gbps proprietary links DIN /DIN DOUT Limiting Amplifer ECL Buffer /DOUT Enable VREF EN VCC GND Level Detect SD SDLVL Rev.: B 1 Amendment: /0 Issue Date: August 2000 Micrel SY88943V PIN NAMES GENERAL DESCRIPTION Pin Type DIN Data Input Data Input /DIN Data Input Inverting Data Input SDLVL Input SD Level Set EN TTL Input Output Enable (Active High) SD TTL Output (Open Collector) Signal Detect GND Ground Ground /DOUT PECL Output Inverting Data Output DOUT PECL Output Data Output VCC Power Supply Positive Power Supply VREF Output Reference Voltage Output for SD Level Set (see Fig. 3) General The SY88943V is an integrated limiting amplifier intended for high-frequency fiber-optic applications. The circuit connects to typical transimpedance amplifiers found within a fiber-optics link. The linear signal output from a transimpedance amplifier can contain significant amounts of noise, and may vary in amplitude over time. The SY88943V limiting amplifier quantizes the signal and outputs a voltage-limited waveform. The EN pin allows the user to disable the output signal without removing the input signal. Function ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit VCC Power Supply Voltage 0 to +7.0 V DIN, /DIN Input Voltage 0 to VCC V DOUT, /DOUT Output Voltage (with 50Ω load) VCC –2.5 to VCC +0.3 V EN Input Voltage 0 to VCC V SDLVL Input Voltage 0 to VCC V VREF Output Voltage VCC –2.0 to VCC V TA Operating Temperature Range –40 to +85 °C Tstore Storage Temperature Range –55 to +125 °C NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. 2 Micrel SY88943V DC ELECTRICAL CHARACTERISTICS VCC = +5V ±10%, RLOAD = 50Ω to VCC –2V TA = –40°C Symbol Parameter ICC Power Supply Current(1) IIL EN Input LOW Current TA = 0°C TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Typ. Max. Min. Max. Unit — — 40 40 — — 40 40 — — 33 28 40 40 — — 45 45 mA –0.3(6) — –0.3(6) — –0.3(6) — — –0.3(6) — mA — — 20(4) 100(5) — — — — 20(4) 100(5) — — 20(4) 100(5) µA 5V 3.3V IIH EN Input HIGH Current — — 20(4) 100(5) VCMR Common Mode Range GND +2.0 VCC GND +2.0 VCC GND +2.0 — VCC GND +2.0 VCC V Voffset Differential Output Offset — ±100 — ±100 — ±17 ±100 — ±100 mV SDLVL SDLVL Level VREF VCC VREF VCC VREF — VCC VREF VCC V — 0.5 — 0.5 — — 0.5 — 0.5 V — 100 — 100 — — 100 — 100 µA VOL SD Output Low Level(2) Leakage(3) IOH SD Output VOH DOUT and /DOUT HIGH Output VCC -1085 VCC -880 VCC -1025 VCC -880 VCC -1025 VCC -955 VCC -880 VCC -1025 VCC -880 mV VOL DOUT and /DOUT LOW Output VCC -1830 VCC -1555 VCC -1810 VCC -1620 VCC -1810 VCC -1705 VCC -1620 VCC -1810 VCC- 1620 mV VREF Reference Supply VCC -1.38 VCC -1.26 VCC -1.38 VCC -1.26 VCC -1.38 VCC -1.32 VCC -1.26 VCC -1.38 VCC -1.26 V IREF VREF Output Current –0.8 0.5 –0.8 0.5 –0.8 — 0.5 –0.8 0.5 mA VIH EN Input HIGH Voltage 2.0 — 2.0 — 2.0 — — 2.0 — V VIL EN Input LOW Voltage — 0.8 — 0.8 — — 0.8 — 0.8 V NOTES: 1. No output load 2. IOL = + 2mA 3. VOH = 5.5V 4. VIN = 2.7V 5. VIN = VCC 6. VIN = 0.5V AC ELECTRICAL CHARACTERISTICS VCC = +5V ±10%, RLOAD = 50Ω to VCC –2V TA = –40°C Symbol Parameter TA = 0°C TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Typ. Max. Min. Max. Unit PSRR Power Supply(1) Rejection Ratio — — — — — 35 — — — dB VID Input Voltage Range 5 1800 5 1800 5 — 1800 5 VOD Differential Output Voltage Swing(2) — — — — — — — — — — 700 300 — — — — — — mV mV tONL SD Release Time(3) Minimum Input — 0.5 — 0.5 — 0.2 0.5 — 0.5 µs tONH SD Release Time(4) Maximum Input — 0.5 — 0.5 — 0.2 0.5 — 0.5 µs tOFFL SD Assert Time(3) — 0.5 — 0.5 — 0.1 0.5 — 0.5 µs VSR SD Sensitivity Range 5 50 5 50 5 — 50 5 50 MVp-p 223-1 pattern HYS SD Hysteresis 2 8 2 8 2 4.6 8 2 8 dB 223-1 pattern tr, tf Output Rise/Fall Time — — 175 — — — 175 — — — 150 trin,tfin 175 — — — 175 — ps VID > 100mVp-p VID < 100mVp-p NOTES: 1. Input referred noise = RMS output noise/low frequency gain. 2. Input is a 622MHz square wave. Conditions Input referred, 55MHz 1800 mVp-p VID = 15mVp-p VID = 5mVp-p 3. Input is a 200MHz square wave, tr < 300ps, 8mVp-p. 4. Input is a 200MHz square wave, tr < 300ps, 1.8Vp-p. 3 Micrel SY88943V DESIGN PROCEDURE Output Termination The SY88943V outputs must be terminated with a 50Ω load to VCC –2V (or Thevenin equivalent). The SY88943V ground pin should be connected to the circuit board ground. Use multiple PCB vias close to the part to connect to ground. Avoid long, inductive runs which can degrade performance. Layout and PCB Design Since the SY88943V is a high-frequency component, performance can be largely determined by the board layout and design. A common problem with high-gain amplifiers is the feedback from the large swing outputs to the input via the power supply. VCC 0.1µF DIN+ R1 0.1µF 50Ω DIN– SDLVL 50Ω R2 VREF VREF 0.1µF Figure 2. Differential Input Configuration Figure 3. SDLVL Circuit NOTES: R2 × 1.32V SDLVL = VCC -1.32V + R1 + R2 R1 + R2 ≥ 2.6kΩ PRODUCT ORDERING CODE Ordering Code 4 Package Type Operating Range SY88943VKC K10-1 Commercial SY88943VKCTR K10-1 Commercial Micrel SY88943V PERFORMANCE CURVE SD Assert and Deassert Levels vs SD SD Assert and Deassert Levels vs SDLVL LVL 100 3.3V TA = 25°C 2.5Gbps Pattern 223-1 90 80 70 60 50 INPUT LEVEL (mVp-p) INPUT LEVEL (mVp-p) 100 40 30 20 10 0 0 70 60 50 40 30 20 10 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 SDLVL = VCC– V (V) 5.0V TA = 25°C 2.5Gbps Pattern 223-1 90 80 0 Figure 4. Figure 5. SD Assert and Deassert Levels vs SD SD Assert and Deassert Levels vs SDLVL LVL 100 3.3V TA = 25°C 2.5Gbps Pattern 27-1 90 80 70 60 50 INPUT LEVEL (mVp-p) INPUT LEVEL (mVp-p) 100 40 30 20 10 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 SDLVL = VCC– V (V) 0 70 60 50 40 30 20 10 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 SDLVL = VCC– V (V) Figure 6. 5.0V TA = 25°C 2.5Gbps Pattern 27-1 90 80 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 SDLVL = VCC– V (V) Figure 7. 5 Micrel SY88943V 10 LEAD MSOP (K10-1) Rev. 00 6 Micrel SY88943V 7 Micrel SY88943V MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 8