AD AD9739A

14-Bit, 2.5 GSPS,
RF Digital-to-Analog Converter
AD9739A
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix mode
Industry leading single/multicarrier IF or RF synthesis
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Pin-compatible with the AD9739
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.1 W at 2.5 GSPS
The AD9739A is manufactured on a 0.18 μm CMOS process
and operates from 1.8 V and 3.3 V supplies. It is supplied in a
160-ball chip scale ball grid array for reduced package
parasitics.
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
AD9739A
SDIO
SDO
CS
SCLK
1.2V
SPI
DAC BIAS
APPLICATIONS
The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface
simplifies the digital interface with existing FGPA/ASIC
technology. On-chip controllers are used to manage external
and internal clock domain variations over temperature to
ensure reliable data transfer from the host to the DAC core. A
serial peripheral interface (SPI) is used for device configuration
as well as readback of status registers.
DCO
DATA
LATCH
LVDS DDR
RECEIVER
4-TO-1
DATA ASSEMBLER
GENERAL DESCRIPTION
LVDS DDR
RECEIVER
DB1[13:0]
DCI
DATA
CONTROLLER
DB0[13:0]
I120
Broadband communications systems
DOCSIS CMTS systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
The AD9739A is a 14-bit, 2.5 GSPS high performance RF DAC
capable of synthesizing wideband signals from dc up to 3 GHz.
The AD9739A is pin and functionally compatible with the AD9739
with the exception that the AD9739A does not support
synchronization and is specified to operate between 1.6 GSPS
and 2.5 GSPS. By elimination of the synchronization circuitry,
some nonideal artifacts such as images and discrete clock spurs
remain stationary on the AD9739A between power-up cycles,
thus allowing for possible system calibration. AC linearity and
noise performance remain the same between the AD9739 and
AD9739A.
VREF
CLK DISTRIBUTION
(DIV-BY-4)
TxDAC
CORE
IOUTN
IOUTP
DLL
(MU CONTROLLER)
DACCLK
09616-001
FEATURES
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mixmode operation.
A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
On-chip controllers manage external and internal clock
domain skews.
Programmable differential current output with a 8.66 mA
to 31.66 mA range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD9739A
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 64- and 128-Carrier DOCSIS Performance
(Normal Mode)........................................................................... 21 General Description ......................................................................... 1 Terminology .................................................................................... 22 Functional Block Diagram .............................................................. 1 Serial Port Interface (SPI) Register .............................................. 23 Product Highlights ........................................................................... 1 SPI Register Map Description .................................................. 23 Revision History ............................................................................... 2 SPI Operation ............................................................................. 23 Specifications..................................................................................... 3 SPI Register Map ........................................................................ 25 DC Specifications ......................................................................... 3 Theory of Operation ...................................................................... 28 LVDS Digital Specifications ........................................................ 4 LVDS Data Port Interface.......................................................... 29 Serial Port Specifications ............................................................. 5 Mu Controller ............................................................................. 32 AC Specifications.......................................................................... 6 Interrupt Requests...................................................................... 33 Absolute Maximum Ratings............................................................ 7 Analog Interface Considerations.................................................. 35 Thermal Resistance ...................................................................... 7 Analog Modes of Operation ..................................................... 35 ESD Caution.................................................................................. 7 Clock Input Considerations...................................................... 36 Pin Configurations and Function Descriptions ........................... 8 Voltage Reference ....................................................................... 37 Typical Performance Characteristics ........................................... 11 Analog Outputs .......................................................................... 37 AC (Normal Mode).................................................................... 11 Nonideal Spectral Artifacts....................................................... 39 AC (Mix Mode) .......................................................................... 14 Lab Evaluation of the AD9739A .............................................. 40 One-Carrier DOCSIS Performance (Normal Mode) ............ 16 Recommended Start-Up Sequence .......................................... 41 Four-Carrier DOCSIS Performance (Normal Mode) ........... 17 Outline Dimensions ....................................................................... 43 Eight-Carrier DOCSIS Performance (Normal Mode) .......... 18 Ordering Guide .......................................................................... 43 16-Carrier DOCSIS Performance (Normal Mode) ............... 19 32-Carrier DOCSIS Performance (Normal Mode) ............... 20 REVISION HISTORY
1/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
AD9739A
SPECIFICATIONS
DC SPECIFICATIONS
VDDA = VDD33 = 3.3 V ± 6%, VDDC = VDD = 1.8 V ± 6%, IOUTFS = 20 mA.
Table 1.
Parameter
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current
Output Compliance Range
Common-Mode Output Resistance
Differential Output Resistance
Output Capacitance
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Clock Rate
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
VDDA
VDDC
DIGITAL SUPPLY VOLTAGES
VDD33
VDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS
IVDDA
IVDDC
IVDD33
IVDD
Power Dissipation
Sleep Mode, IVDDA
Power-Down Mode (All Power-Down Bits Set in Register 0x01 and
Register 0x02)
IVDDA
IVDDC
IVDD33
IVDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS
IVDDA
IVDDC
IVDD33
IVDD
Power Dissipation
Min
Typ
14
Max
±2.5
±2.0
8.66
−1.0
5.5
20.2
LSB
LSB
31.66
+1.0
10
70
1
1.2
1.6
900
1.6
Unit
Bits
2.0
2.5
60
20
%
mA
V
MΩ
Ω
pF
V
mV
GHz
ppm/°C
ppm/°C
1.15
1.2
5
1.25
V
kΩ
3.1
1.70
3.3
1.8
3.5
1.90
V
V
3.10
1.70
3.3
1.8
3.5
1.90
V
V
37
158
14.5
173
0.770
2.5
38
167
16
183
mA
mA
mA
mA
W
mA
Rev. 0 | Page 3 of 44
2.75
0.02
6
0.6
0.1
mA
mA
mA
mA
37
223
14.5
215
0.960
mA
mA
mA
mA
W
AD9739A
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V ± 6%, VDDC = VDD = 1.8 V ± 6%, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE
Standard 1596.3-1996 reduced range link, unless otherwise noted.
Table 2.
Parameter
LVDS DATA INPUTS (DB0[13:0], DB1[13:0]) 1
Input Common-Mode Voltage Range, VCOM
Logic High Differential Input Threshold, VIH_DTH
Logic Low Differential Input Threshold, VIL_DTH
Receiver Differential Input Impedance, RIN
Input Capacitance
LVDS Input Rate
LVDS Minimum Data Valid Period (tMDE) (See Figure 76)
LVDS CLOCK INPUT (DCI) 2
Input Common-Mode Voltage Range, VCOM
Logic High Differential Input Threshold, VIH_DTH
Logic Low Differential Input Threshold, VIL_DTH
Receiver Differential Input Impedance, RIN
Input Capacitance
Maximum Clock Rate
LVDS CLOCK OUTPUT (DCO) 3
Output Voltage High (DCO_P or DCO_N)
Output Voltage Low (DCO_P or DCO_N)
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, Single-Ended, RO
RO Single-Ended Mismatch
Maximum Clock Rate
Min
Typ
825
175
−175
80
400
−400
Max
Unit
1575
mV
mV
mV
Ω
pF
MSPS
ps
120
1.2
1250
344
825
175
−175
80
1575
400
−400
120
1.2
625
1375
1025
150
1150
80
625
1
DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.
DCI_P and DCI_N pins.
3
DCO_P and DCO_N pins with 100 Ω differential termination.
2
Rev. 0 | Page 4 of 44
200
100
250
1250
120
10
mV
mV
mV
Ω
pF
MHz
mV
mV
mV
mV
Ω
%
MHz
AD9739A
SERIAL PORT SPECIFICATIONS
VDDA = VDD33 = 3.3 V ± 6%, VDDC = VDD = 1.8 V ± 6%.
Table 3.
Parameter
WRITE OPERATION (See Figure 71)
SCLK Clock Rate, fSCLK, 1/tSCLK
SCLK Clock High, tHI
SCLK Clock Low, tLOW
SDIO to SCLK Setup Time, tDS
SCLK to SDIO Hold Time, tDH
CS to SCLK Setup Time, tS
SCLK to CS Hold Time, tH
Min
Typ
Max
Unit
20
MHz
ns
ns
ns
ns
ns
ns
20
MHz
ns
ns
ns
ns
ns
ns
ns
18
18
2
1
3
2
READ OPERATION (See Figure 72 and Figure 73)
SCLK Clock Rate, fSCLK, 1/tSCLK
SCLK Clock High, tHI
SCLK Clock Low, tLOW
SDIO to SCLK Setup Time, tDS
SCLK to SDIO Hold Time, tDH
CS to SCLK Setup Time, tS
SCLK to SDIO (or SDO) Data Valid Time, tDV
CS to SDIO (or SDO) Output Valid to High-Z, tEZ
18
18
2
1
3
15
2
INPUTS (SDI, SDIO, SCLK, CS)
Voltage in High, VIH
Voltage in Low, VIL
Current in High, IIH
Current in Low, IIL
OUTPUT (SDIO)
Voltage Out High, VOH
Voltage Out Low, VOL
Current Out High, IOH
Current Out Low, IOL
2.0
3.3
0
−10
−10
0.8
+10
+10
2.4
0
3.5
0.4
4
4
Rev. 0 | Page 5 of 44
V
V
μA
μA
V
V
mA
mA
AD9739A
AC SPECIFICATIONS
VDDA = VDD33 = 3.3 V ± 6%, VDDC = VDD = 1.8 V ± 6%, IOUTFS = 20 mA.
Table 4.
Parameter
DYNAMIC PERFORMANCE
Maximum Update Rate (DACCLK Input)
Output Settling Time to 0.1%
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 950 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD), fOUT2 = fOUT1 + 1.25 MHz
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 950 MHz
NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 850 MHz
WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE ADJACENT CHANNEL
fDAC = 2457.6 MSPS fOUT = 350 MHz
fDAC = 2457.6 MSPS, fOUT = 950 MHz
fDAC = 2457.6 MSPS, fOUT = 1700 MHz (Mix Mode)
fDAC = 2457.6 MSPS, fOUT = 2100 MHz (Mix Mode)
Rev. 0 | Page 6 of 44
Min
Typ
Max
Unit
2500
13
MSPS
ns
69.5
58.5
54
60
dBc
dBc
dBc
dBc
94
78
72
68
dBc
dBc
dBc
dBc
−166
−161
−160
−160
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
80/80
78/79
74/74
69/72
dBc
dBc
dBc
dBc
800
AD9739A
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
VDDA
VDD33
VDD
VDDC
VSSA
VSSA
VSS
DACCLK_P,
DACCLK_N
DCI, DCO
LVDS Data Inputs
IOUTP, IOUTN
I120, VREF
IRQ, CS, SCLK, SDO,
SDIO, RESET
Junction
Temperature
Storage Temperature
With
Respect To
VSSA
VSS
VSS
VSSC
VSS
VSSC
VSSC
VSSC
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +1.98 V
−0.3 V to +1.98 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to VDDC + 0.18 V
VSS
VSS
VSSA
VSSA
VSS
−0.3 V to VDD33 + 0.3 V
−0.3 V to VDD33 + 0.3 V
−1.0 V to VDDA + 0.3 V
−0.3 V to VDDA + 0.3 V
−0.3 V to VDD33 + 0.3 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
160-Ball CSP_BGA
1
With no airflow movement.
ESD CAUTION
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 44
θJA
31.2
θJC
7.0
Unit
°C/W1
AD9739A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
3
4
5
6
7
8
9 10 11 12 13 14
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD
09616-002
VSSA, ANALOG SUPPLY GROUND
3
4
5
6
7
8
4
5
6
7
8
9 10 11 12 13 14
VSSC, CLOCK SUPPLY GROUND
Figure 2. Analog Supply Pins (Top View)
2
3
VDDC, 1.8V, CLOCK SUPPLY
VDDA, 3.3V, ANALOG SUPPLY
1
2
09616-004
1
Figure 4. Digital LVDS Clock Supply Pins (Top View)
1
9 10 11 12 13 14
A
A
B
B
C
DACCLK_N C
D
DACCLK_P D
2
3
4
5
6
7
8
9 10 11 12 13 14
E
E
F
F
G
G
H
H
J
K
J
DCO_P/_N
K
DCI_P/_N
DB1[0:13]P L
L
DB0[0:13]P N
N
DB0[0:13]N P
P
DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)
VSS DIGITAL SUPPLY GROUND
VDD33, 3.3V DIGITAL SUPPLY
09616-003
VDD, 1.8V, DIGITAL SUPPLY
Figure 5. Digital LVDS Input, Clock I/O (Top View)
Figure 3. Digital Supply Pins (Top View)
Rev. 0 | Page 8 of 44
09616-005
DB1[0:13]N M
M
2
3
4
5
6
IOUTP
1
IOUTN
AD9739A
7
8
9 10 11 12 13 14
A
B
I120
C
VREF
D
E
RESET
F
IRQ
G
CS
SDIO
H
SCLK
SDO
J
K
L
M
09616-006
N
P
Figure 6. Analog I/O and SPI Control Pins (Top View)
Table 7. AD9739A Pin Function Descriptions
Pin No.
C1, C2, D1, D2, E1, E2, E3, E4
A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,
C5, D4, D5
A10, A11, B10, B11, C10, C11, D10, D11
A12, A13, B12, B13, C12, C13, D12, D13,
A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3,
F4, E11, E12, E13, E14, F11, F12
A14
A7, B7, C7, D7
A8, B8, C8, D8
B14
Mnemonic
VDDC
VSSC
Description
1.8 V Clock Supply Input.
Clock Supply Return.
VDDA
VSSA
VSSA Shield
3.3 V Analog Supply Input.
Analog Supply Return.
Analog Supply Return Shield.
Tie to VSSA at the DAC.
Do not connect to this pin.
DAC Negative Current Output Source.
DAC Positive Current Output Source.
Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ
resistor to generate a 120 μA reference current.
Voltage Reference Input/Output.
Decouple to VSSA with a 1 nF capacitor.
Factory Test Pin. Do not connect to this pin.
Negative/Positive DAC Clock Input (DACCLK).
Interrupt Request Open Drain Output. Active high. Pull up to
VDD33 with a 10 kΩ resistor.
Reset Input. Active high. Tie to VSS if unused.
Serial Port Enable Input.
Serial Port Data Input/Output.
Serial Port Clock Input.
Serial Port Data Output.
3.3 V Digital Supply Input.
1.8 V Digital Supply. Input.
Digital Supply Return.
Differential resistor of 200 Ω exists between J1 and J2. Do not
connect to this pin.
Differential resistor of 100 Ω exists between J1 and J2. Do not
connect to this pin.
Positive/Negative Data Clock Output (DCO).
Positive/Negative Data Clock Input (DCI).
Port 1 Positive/Negative Data Input Bit 0.
Port 1 Positive/Negative Data Input Bit 1.
Port 1 Positive/Negative Data Input Bit 2.
Port 1 Positive/Negative Data Input Bit 3.
NC
IOUTN
IOUTP
I120
C14
VREF
D14
C3, D3
F13
NC
DACCLK_N/DACCLK_P
IRQ
F14
G13
G14
H13
H14
J3, J4, J11, J12
G1, G2, G3, G4, G11, G12
H1, H2, H3, H4, H11, H12, K3, K4, K11, K12
J1, J2
RESET
CS
SDIO
SCLK
SDO
VDD33
VDD
VSS
NC
K1, K2
NC
J13, J14
K13, K14
L1, M1
L2, M2
L3, M3
L4, M4
DCO_P/DCO_N
DCI_P/DCI_N
DB1[0]P/DB1[0]N
DB1[1]P/DB1[1]N
DB1[2]P/DB1[2]N
DB1[3]P/DB1[3]N
Rev. 0 | Page 9 of 44
AD9739A
Pin No.
L5, M5
L6, M6
L7, M7
L8, M8
L9, M9
L10, M10
L11, M11
L12, M12
L13, M13
L14, M14
N1, P1
N2, P2
N3, P3
N4, P4
N5, P5
N6, P6
N7, P7
N8, P8
N9, P9
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
Mnemonic
DB1[4]P/DB1[4]N
DB1[5]P/DB1[5]N
DB1[6]P/DB1[6]N
DB1[7]P/DB1[7]N
DB1[8]P/DB1[8]N
DB1[9]P/DB1[9]N
DB1[10]P/DB1[10]N
DB1[11]P/DB1[11]N
DB1[12]P/DB1[12]N
DB1[13]P/DB1[13]N
DB0[0]P/DB0[0]N
DB0[1]P/DB0[1]N
DB0[2]P/DB0[2]N
DB0[3]P/DB0[3]N
DB0[4]P/DB0[4]N
DB0[5]P/DB0[5]N
DB0[6]P/DB0[6]N
DB0[7]P/DB0[7]N
DB0[8]P/DB0[8]N
DB0[9]P/DB0[9]N
DB0[10]P/DB0[10]N
DB0[11]P/DB0[11]N
DB0[12]P/DB0[12]N
DB0[13]P/DB0[13]N
Description
Port 1 Positive/Negative Data Input Bit 4.
Port 1 Positive/Negative Data Input Bit 5.
Port 1 Positive/Negative Data Input Bit 6.
Port 1 Positive/Negative Data Input Bit 7.
Port 1 Positive/Negative Data Input Bit 8.
Port 1 Positive/Negative Data Input Bit 9.
Port 1 Positive/Negative Data Input Bit 10.
Port 1 Positive/Negative Data Input Bit 11.
Port 1 Positive/Negative Data Input Bit 12.
Port 1 Positive/Negative Data Input Bit 13.
Port 0 Positive/Negative Data Input Bit 0.
Port 0 Positive/Negative Data Input Bit 1.
Port 0 Positive/Negative Data Input Bit 2.
Port 0 Positive/Negative Data Input Bit 3.
Port 0 Positive/Negative Data Input Bit 4.
Port 0 Positive/Negative Data Input Bit 5.
Port 0 Positive/Negative Data Input Bit 6.
Port 0 Positive/Negative Data Input Bit 7.
Port 0 Positive/Negative Data Input Bit 8.
Port 0 Positive/Negative Data Input Bit 9.
Port 0 Positive/Negative Data Input Bit 10.
Port 0 Positive/Negative Data Input Bit 11.
Port 0 Positive/Negative Data Input Bit 12.
Port 0 Positive/Negative Data Input Bit 13.
Rev. 0 | Page 10 of 44
AD9739A
TYPICAL PERFORMANCE CHARACTERISTICS
AC (NORMAL MODE)
STOP 2.4GHz
VBW 10kHz
START 20MHz
Figure 7. Single-Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS
Figure 10. Single-Tone Spectrum at fOUT = 1091 MHz, fDAC = 2.4 GSPS
80
1.2GSPS
75
STOP 2.4GHz
VBW 10kHz
09616-010
START 20MHz
09616-007
10dB/DIV
10dB/DIV
IOUTFS = 20 mA, nominal supplies, 25°C, unless otherwise noted.
100
95
1.6GSPS
1.2GSPS
70
85
65
80
2.0GSPS
75
60
IMD (dBc)
SFDR (dBc)
90
2.4GSPS
55
2.0GSPS
50
1.6GSPS
70
65
2.4GSPS
60
55
45
50
40
45
40
35
100 200 300 400 500 600 700 800 900 1000 1100 1200
fOUT (MHz)
30
0
fOUT (MHz)
Figure 11. IMD vs. fOUT over fDAC
–160
–152
–161
–154
–162
–156
–163
NSD (dBm/Hz)
–150
2.4GSPS
–160
–162
–164
–164
–165
–167
1.2GSPS
–168
–168
–169
–170
0
100 200 300 400 500 600 700 800 900 1000 1100 1200
fOUT (MHz)
2.4GSPS
–166
–166
09616-009
NSD (dBm/Hz)
Figure 8. SFDR vs. fOUT over fDAC
–158
100 200 300 400 500 600 700 800 900 1000 1100 1200
Figure 9. Single-Tone NSD over fOUT
–170
1.2GSPS
0
100 200 300 400 500 600 700 800 900 1000 1100 1200
fOUT (MHz)
Figure 12. Eight-Tone NSD over fOUT
Rev. 0 | Page 11 of 44
09616-012
0
09616-011
35
09616-008
30
AD9739A
fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, 25°C, unless otherwise noted.
110
90
100
80
–6dBFS
–6dBFS
80
IMD (dBc)
SFDR (dBc)
90
–3dBFS
70
60
70
50
–3dBFS
60
0dBFS
0dBFS
50
40
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
30
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
Figure 13. SFDR vs. fOUT over Digital Full Scale
09616-016
0
09616-013
30
40
Figure 16. IMD vs. fOUT over Digital Full Scale
90
90
–6dBFS
80
–6dBFS
80
–3dBFS
SFDR (dB)
70
0dBFS
–3dBFS
50
50
40
40
30
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
30
0dBFS
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
Figure 14. SFDR for Second Harmonic over fOUT vs. Digital Full Scale
Figure 17. SFDR for Third Harmonic over fOUT vs. Digital Full Scale
90
110
100
80
20mA FS
90
30mA FS
10mA FS
70
IMD (dBc)
80
60
20mA FS
50
70
10mA FS
60
30mA FS
50
40
0
100
200
300
400
500
600
700
800
fOUT (MHz)
900
1000
30
0
100
200
300
400
500
600
700
800
fOUT (MHz)
Figure 15. SFDR vs, fOUT over DAC IOUTFS
Figure 18. IMD vs. fOUT over DAC IOUTFS
Rev. 0 | Page 12 of 44
900
1000
09616-018
30
40
09616-015
SFDR (dBc)
60
09616-017
60
09616-014
SFDR (dB)
70
AD9739A
110
90
100
80
90
+85°C
–40°C
60
70
+25°C
60
+25°C
50
+85°C
80
IMD (dBc)
SFDR (dBc)
70
–40°C
50
40
40
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
0
200
300
400
500
600
700
800
900
1000
900
1000
fOUT (MHz)
Figure 19. SFDR vs. fOUT over Temperature
Figure 22. IMD vs. fOUT over Temperature
–150
–150
–152
–152
–154
–154
–156
–156
–158
NSD (dBm/Hz)
–40°C
–160
–162
+85°C
–164
–158
–160
–162
–40°C
–164
–166
–166
+25°C
+85°C
–168
–168
+25°C
–170
–170
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
0
09616-020
0
100
200
300
400
500
600
700
800
fOUT (MHz)
Figure 20. Single-Tone NSD vs. fOUT over Temperature
Figure 23. Eight-Tone NSD vs. fOUT over Temperature
–50
–55
ACLR (dBc)
–60
10dB/DIV
–65
–70
FIRST ADJ CH
–75
–80
FIFTH ADJ CH
–85
SECOND ADJ CH
FREQ
VBW 300kHz
0
(MHz)
3.84
3.84
3.84
3.84
3.84
LOWER
(dBc) (dBm)
–79.90 –94.44
–80.60 –95.14
–80.90 –95.45
–80.62 –95.16
–80.76 –95.30
UPPER
(dBc) (dBm)
–79.03 –93.57
–79.36 –94.40
–80.73 –95.27
–80.97 –95.51
–80.95 –95.49
245.76
491.52
737.28
983.04
1228.80
122.88
368.64
614.40
860.16
1105.90
fOUT (MHz)
REF
RMS RESULTS OFFSET BW
CARRIER POWER (MHz)
5
–14.54dBm/
10
3.84MHz
15
20
25
SPAN 53.84MHz
SWEEP 174.6ms (601pts)
Figure 21. Single-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS
Figure 24. Four-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS
Rev. 0 | Page 13 of 44
09616-108
–90
CENTER 350.27MHz
#RES BW 30kHz
09616-021
NSD (dBm/Hz)
100
09616-022
100
09616-019
0
09616-023
30
30
AD9739A
AC (MIX MODE)
STOP 2.4GHz
SWEEP 28.7s (601pts)
VBW 10kHz
START 20MHz
#RES BW 10kHz
Figure 25. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS
VBW 10kHz
STOP 2.4GHz
SWEEP 28.7s (601pts)
09616-030
START 20MHz
#RES BW 10kHz
09616-026
10dB/DIV
10dB/DIV
fDAC = 2.4 GSPS, IOUTFS = 20 mA, nominal supplies, 25°C, unless otherwise noted.
Figure 28. Single-Tone Spectrum in Mix Mode at fOUT = 1.31 GHz,
fDAC = 2.4 GSPS
80
90
75
85
70
80
65
75
60
70
65
IMD (dBc)
SFDR (dBc)
55
50
45
40
60
55
35
50
30
45
25
35
10
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
30
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
fOUT (MHz)
09616-027
15
fOUT (MHz)
09616-031
40
20
Figure 29. IMD in Mix Mode vs. fOUT at 2.4 GSPS
Figure 26. SFDR in Mix Mode vs. fOUT at 2.4 GSPS
–40
–45
SECOND NYQUIST ZONE
THIRD NYQUIST ZONE
–50
10dB/DIV
ACLR (dBc)
–55
–60
–65
FIRST ADJ CH
–70
SECOND ADJ CH
–75
–80
FIFTH ADJ CH
FREQ
RMS RESULTS OFFSET
CARRIER POWER (MHz)
5
–21.43dBm/
10
3.84MHz
15
20
25
VBW 300kHz
REF
BW
(MHz)
3.84
3.84
3.84
3.84
3.84
–90
1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686
SPAN 53.84MHz
SWEEP 174.6ms (601pts)
LOWER
(dBc) (dBm)
–68.99 –90.43
–72.09 –93.52
–72.86 –94.30
–74.34 –95.77
–74.77 –96.20
UPPER
(dBc) (dBm)
–63.94 –90.37
–71.07 –92.50
–71.34 –92.77
–72.60 –94.03
–73.26 –94.70
fOUT (MHz)
09616-032
CENTER 2.10706MHz
#RES VW 30kHz
Figure 27. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz,
fDAC = 2457.6 MSPS (Second Nyquist Zone)
Figure 30. Single-Carrier WCDMA ACLR vs. fOUT at 2457.6 MSPS
Rev. 0 | Page 14 of 44
09616-025
–85
FREQ
VBW 300kHz
REF
RMS RESULTS OFFSET BW
CARRIER POWER (MHz)
5
–24.4dBm/
10
3.84MHz
15
20
25
(MHz)
3.84
3.84
3.84
3.84
3.84
CENTER 2.81271GHz
#RES BW 30kHz
SPAN 53.84MHz
SWEEP 174.6ms (601pts)
LOWER
(dBc) (dBm)
–64.90 –89.30
–66.27 –90.67
–68.44 –92.84
–70.20 –94.60
–70.85 –95.25
UPPER
(dBc) (dBm)
–63.82 –88.22
–65.70 –90.10
–66.55 –90.95
–68.95 –93.35
–70.45 –94.85
FREQ
CARRIER POWER (MHz)
5
–27.98dBm/
10
3.84MHz
15
20
25
30
REF
RMS RESULTS OFFSET BW
CARRIER POWER (MHz)
5
–25.53dBm/
10
3.84MHz
15
20
25
30
(MHz)
3.84
3.84
3.84
3.84
3.84
3.84
SPAN 63.84MHz
SWEEP 207ms (601pts)
LOWER
(dBc) (dBm)
0.22 –25.31
–66.68 –92.21
–68.01 –93.53
–68.61 –94.14
–68.87 –94.40
–69.21 –94.74
UPPER
(dBc) (dBm)
0.24 –25.29
0.14 –25.38
–66.82 –92.35
–67.83 –93.36
–67.64 –93.17
–68.50 –94.03
09616-034
FREQ
VBW 300kHz
REF
(MHz)
3.84
3.84
3.84
3.84
3.84
3.84
SPAN 63.84MHz
SWEEP 207ms (601pts)
LOWER
(dBc) (dBm)
–0.42 –28.40
–64.32 –92.30
–66.03 –94.01
–66.27 –94.24
–66.82 –94.79
–67.16 –95.13
UPPER
(dBc) (dBm)
–0.10 –28.07
–0.08 –28.06
–65.37 –93.34
–66.06 –94.03
–63.36 –93.34
–66.54 –94.51
Figure 33. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz,
fDAC = 2457.6 MSPS (Third Nyquist Zone)
10dB/DIV
Figure 31. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz,
fDAC = 2457.6 MSPS (Third Nyquist Zone)
CENTER 2.09758GHz
#RES BW 30kHz
VBW 300kHz
RMS RESULTS OFFSET BW
09616-033
CENTER 2.807GHz
#RES BW 30kHz
09616-035
10dB/DIV
10dB/DIV
AD9739A
Figure 32. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz,
fDAC = 2457.6 MSPS (Second Nyquist Zone)
Rev. 0 | Page 15 of 44
AD9739A
ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
fDAC = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.
–80.7dBc
–42
–45
–53
–55
–64
–65
–75
–86
–97
–80.7dBc
–81.2dBc
–10.2dBm
–81.3dBc
–80.7dBc
–80.8dBc
–80.8dBc
–75
–85
–95
–108
3∆1
2∆1
–105
4∆1
5∆1
–119
–115
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
X
200MHz
199.60MHz
400.05MHz
597.65MHz
413.35MHz
(∆)
(∆)
(∆)
(∆)
Y
–11.476dBm
–77.042dB
–76.238dB
–74.526dB
–75.919dB
CENTER 200MHz
#RES BW 30kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–11.475dBm
(∆) –77.042dB
(∆) –76.238dB
(∆) –74.526dB
(∆) –75.919dB
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
–78.5dBc
ACP-IBW
LOWER
dBm
dBc
–59.38 –69.57
–81.23 –91.42
–80.71 –90.90
–80.72 –90.91
–80.73 –90.92
UPPER
dBm
dBc
–60.16 –70.35
–81.26 –91.45
–80.72 –90.91
–80.76 –90.95
–80.78 –90.97
FILTER
OFF
OFF
OFF
OFF
OFF
–77.6dBc
–76.3dBc
–75.1dBc
–10.4dBm
–74.4dBc
–75.6dBc
–76.7dBc
–77.7dBc
–35
1
–45
–53
–55
–64
–65
10dB/DIV
–42
–75
–86
–75
–85
–95
–97
5∆1
2∆1
4∆1
3∆1
–105
6∆1
–115
–119
MKR
1
2
3
4
5
6
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
VBW 2kHz
X
549.60MHz
–485.35MHz (∆)
127.40MHz (∆)
254.70MHz (∆)
63.75MHz (∆)
293.65MHz (∆)
Y
–10.231dBm
–76.444dB
–75.649dB
–70.658dB
–75.836dB
–78.054dB
CENTER 550MHz
#RES BW 30kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–10.231dBm
(∆) –76.425dB
(∆) –75.626dB
(∆) –70.658dB
(∆) –75.824dB
(∆) –78.118dB
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
09616-037
START 50MHz
#RES BW 20kHz
–10.368dBm/6MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
ACP-IBW
LOWER
dBm
dBc
–57.91 –68.28
–75.09 –85.46
–76.29 –86.65
–77.63 –88.00
–78.51 –88.88
UPPER
dBm
dBc
–58.53 –68.90
–74.41 –84.78
–75.55 –85.92
–76.69 –87.06
–77.67 –88.03
FILTER
OFF
OFF
OFF
OFF
OFF
09616-040
–108
–10.190dBm/6MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
Figure 37. Low Band Narrow-Band ACLR
Figure 34. Low Band Wideband ACLR
–31
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
09616-039
MKR
1
2
3
4
5
VBW 2kHz
09616-036
START 50MHz
#RES BW 20kHz
11dB/DIV
–80.7dBc
–35
1
10dB/DIV
11dB/DIV
–31
Figure 38. Mid Band Narrow-Band ACLR
Figure 35. Mid Band Wideband ACLR
–72.6dBc
–31
–71.1dBc
–69.9dBc
–68.7dBc
–12.6dBm
–67.9dBc
–68.6dBc
–70.6dBc
–72.3dBc
–35
–45
–53
–55
–64
–65
10dB/DIV
–75
–86
–97
–75
–85
–95
2∆1
4∆1
–108
3∆1
5∆1
–105
–119
–115
MKR
1
2
3
4
5
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
VBW 2kHz
X
979.00MHz
–484.40MHz
–118.65MHz
–613.60MHz
–365.65MHz
(∆)
(∆)
(∆)
(∆)
Y
–13.703dBm
–65.548dB
–66.990dB
–69.044dB
–72.789dB
CENTER 980MHz
#RES BW 30kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–13.658dBm
–65.548dB
–66.990dB
–69.049dB
–72.789dB
(∆)
(∆)
(∆)
(∆)
CARRIER POWER
09616-038
START 50MHz
#RES BW 20kHz
Figure 36. High Band Wideband ACLR
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
–12.778dBm/6MHz
ACP-IBW
LOWER
dBm
dBc
–60.38 –73.15
–68.67 –81.44
–69.90 –82.68
–71.12 –83.90
–72.61 –85.39
UPPER
dBm
dBc
–59.15 –71.93
–67.94 –80.72
–68.58 –81.35
–70.64 –83.42
–72.35 –85.13
FILTER
OFF
OFF
OFF
OFF
OFF
Figure 39. High Band Narrow-Band ACLR
Rev. 0 | Page 16 of 44
09616-041
11dB/DIV
1
–42
AD9739A
FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.
–37
1
–48
–47
–58
–57
10dB/DIV
–68
–78
–108
6∆1
3∆1
–0.5dBc
–17.6dBm
–73.6dBc
–75.4dBc
–78.1dBc
–79.1dBc
–67
–77
2∆1
–107
4∆1
5∆1
–117
MKR
1
2
3
4
5
6
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
X
217.50MHz
201.10MHz (∆)
417.70MHz (∆)
608.65MHz (∆)
–124.75MHz (∆)
395.85MHz (∆)
Y
–18.065dBm
–72.097dB
–72.882dB
–72.292dB
–76.776dB
–71.133dB
CENTER 210MHz
#RES BW 30kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–18.064dBm
–72.097dB
–72.882dB
–72.292dB
–76.776dB
–71.133dB
(∆)
(∆)
(∆)
(∆)
(∆)
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
–17.556dBm/6MHz
ACP-IBW
LOWER
dBm
dBc
–11.15 –28.70
–0.454 –18.01
–0.065 –17.62
–0.091 –17.65
–53.44 –70.99
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
UPPER
dBm
dBc
–58.78 –76.34
–73.56 –91.12
–75.42 –92.98
–78.08 –95.64
–79.06 –96.62
FILTER
OFF
OFF
OFF
OFF
OFF
Figure 43. Low Band Narrow-Band ACLR (Worst Side)
Figure 40. Low Band Wideband ACLR
–38
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
09616-045
START 50MHz
#RES BW 20kHz
09616-042
–118
–37
1
–48
–47
–58
–57
–68
–67
10dB/DIV
–78
–88
–98
–76.6dBc
–76.4dBc
–75.0dBc
–72.9dBc
–19.5dBm
–0.3dBc
–0.1dBc
–0.1dBc
–50.2dBc
–77
–87
–97
4∆1
–118
2∆1 3∆1
6∆1
–107
5∆1
–117
MKR
1
2
3
4
5
6
MODE TRC SCL
f
1
N
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
X
667.80MHz
–192.20MHz (∆)
–98.15MHz (∆)
–614.00MHz (∆)
–567.45MHz (∆)
–55.40MHz (∆)
Y
–18.760dBm
–69.536dB
–71.601dB
–72.824dB
–75.786dB
–71.997dB
CENTER 650MHz
#RES BW 30kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–18.760dBm
(∆) –69.536dB
(∆) –71.601dB
(∆) –72.833dB
(∆) –75.320dB
(∆) –71.997dB
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
09616-043
START 50MHz
#RES BW 20kHz
Figure 41. Mid Band Wideband ACLR
–19.503dBm/6MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
ACP-IBW
LOWER
dBm
dBc
–61.84 –81.35
–72.95 –92.45
–74.99 –94.49
–76.38 –95.89
–76.59 –96.10
UPPER
dBm
dBc
–11.18 –30.68
–0.294 –19.80
–0.075 –19.58
–0.145 –19.65
–50.21 –69.71
FILTER
OFF
OFF
OFF
OFF
OFF
09616-046
10dB/DIV
–0.1dBc
–97
–98
Figure 44. Mid Band Narrow-Band ACLR (Worst Side)
–38
–37
1
–48
–74.2dBc
–73.0dBc
–70.7dBc
–68.7dBc
–20.7dBm
–0.5dBc
0.1dBc
–0.5dBc
–52.3dBc
–47
–58
–57
10dB/DIV
–68
–78
–88
–67
–77
–87
–98
2∆1
–108
4∆1
3∆1
–97
6∆1
5∆1
–107
–118
START 50MHz
#RES BW 20kHz
MKR
1
2
3
4
5
6
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
VBW 2kHz
X
987.95MHz
–490.50MHz (∆)
–624.45MHz (∆)
–738.45MHz (∆)
–130.46MHz (∆)
–374.60MHz (∆)
Y
–21.040dBm
–60.683dB
–69.390dB
–71.954dB
–66.954dB
–68.889dB
–117
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–21.029dBm
–60.683dB
–69.390dB
–71.847dB
–66.954dB
–68.889dB
(∆)
(∆)
(∆)
(∆)
(∆)
CENTER 970MHz
#RES BW 30kHz
09616-044
10dB/DIV
–0.1dBc
–87
–88
–108
–53.4dBc
Figure 42. High Band Wideband ACLR
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
–20.666dBm/6MHz
ACP-IBW
LOWER
dBm
dBc
–60.65 –81.32
–68.68 –89.34
–70.67 –91.33
–72.96 –93.63
–74.22 –94.89
UPPER
dBm
dBc
–10.77 –31.44
–0.522 –21.19
–0.140 –20.81
–0.511 –21.18
–52.31 –72.98
FILTER
OFF
OFF
OFF
OFF
OFF
Figure 45. High Band Narrow-Band ACLR (Worst Side)
Rev. 0 | Page 17 of 44
09616-047
10dB/DIV
–38
AD9739A
EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.
–37
–38
–47
–58
–57
–68
–67
10dB/DIV
10dB/DIV
1
–48
–78
–88
–98
0dBc
0dBc
0.1dBc
–0.3dBc
–21.9dBm
–70.0dBc
–69.9dBc
–69.7dBc
–70.1dBc
–77
–87
–97
6∆1
–108
–117
START 50MHz
#RES BW 20kHz
MKR
1
2
3
4
5
6
4∆1
2∆1
5∆1
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
X
241.25MHz
198.25MHz (∆)
–135.20MHz (∆)
746.40MHz (∆)
20.60MHz (∆)
371.15MHz (∆)
Y
–23.278dBm
–67.453dB
–72.684dB
–68.278dB
–69.581dB
–66.474dB
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–23.279dBm
–67.448dB
–72.764dB
–68.258dB
–69.581dB
–66.457dB
(∆)
(∆)
(∆)
(∆)
(∆)
CENTER 222MHz
#RES BW 30kHz
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
Figure 46. Low Band Wideband ACLR
–37
–47
–58
–57
–68
–67
10dB/DIV
–78
–88
FILTER
OFF
OFF
OFF
OFF
OFF
0dBc
–0.1dBc
–0.1dBc
–0.3dBc
–22.7dBm
–69.2dBc
–68.6dBc
–69.3dBc
–69.2dBc
–77
–87
–97
–98
6∆1
2∆1
4∆1
5∆1
X
667.80MHz
–171.30MHz (∆)
–98.15MHz (∆)
–614.00MHz (∆)
–567.45MHz (∆)
–55.40MHz (∆)
Y
–23.977dBm
–69.185dB
–68.551dB
–69.923dB
–72.145dB
–65.009dB
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–23.977dBm
(∆) –69.185dB
(∆) –68.551dB
(∆) –69.938dB
(∆) –72.083dB
(∆) –65.009dB
CENTER 622MHz
#RES BW 30kHz
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
Figure 47. Mid Band Wideband ACLR
–37
1
–48
–67
10dB/DIV
–57
–68
–78
–88
–98
START 50MHz
#RES BW 20kHz
MKR
1
2
3
4
5
6
MODE TRC SCL
f
1
N
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
UPPER
dBc
dBc
–61.38 –84.07
–69.17 –91.86
–68.64 –91.33
–69.33 –92.02
–69.18 –91.88
FILTER
OFF
OFF
OFF
OFF
OFF
–67.7dBc
–67.7dBc
–67.3dBc
–67.4dBc
–25.3dBm
–0.5dBc
–0.2dBc
0dBc
0dBc
–77
–87
–97
6∆1
–107
5∆1
3∆1
–117
VBW 2kHz
X
990.80MHz
–481.00MHz (∆)
–633.95MHz (∆)
–734.65MHz (∆)
–128.55MHz (∆)
–378.40MHz (∆)
Y
–25.435dBm
–61.947dB
–67.517dB
–69.583dB
–65.237dB
–64.615dB
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–25.435dBm
(∆) –61.947dB
(∆) –67.532dB
(∆) –69.602dB
(∆) –65.237dB
(∆) –64.615dB
CENTER 950MHz
#RES BW 30kHz
CARRIER POWER
09616-050
4∆1
–118
LOWER
dBc
dBc
–11.01 –33.70
–0.339 –23.03
–0.135 –22.83
–0.089 –22.78
–0.049 –22.74
–47
–58
2∆1
ACP-IBW
Figure 50. Mid Band Narrow-Band ACLR (Worst Side)
–38
–108
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
–22.691dBm/6MHz
09616-052
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
09616-049
MKR
1
2
3
4
5
6
–107
3∆1
–117
START 50MHz
#RES BW 20kHz
10dB/DIV
UPPER
dBm
dBc
–59.41 –81.28
–69.96 –91.83
–69.91 –91.78
–69.74 –91.62
–70.08 –91.95
Figure 48. High Band Wideband ACLR
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
–25.344dBm/6MHz
ACP-IBW
LOWER
dBm
dBc
–60.39 –85.73
–67.44 –92.78
–67.29 –92.63
–67.65 –93.00
–67.65 –93.00
UPPER
dBm
dBc
–10.93 –36.27
–0.487 –25.83
–0.205 –25.55
–0.047 –25.39
0.016 –25.33
FILTER
OFF
OFF
OFF
OFF
OFF
Figure 51. High Band Narrow-Band ACLR (Worst Side)
Rev. 0 | Page 18 of 44
09616-053
10dB/DIV
1
–48
–118
ACP-IBW
LOWER
dBm
dBc
–10.98 –32.85
–0.334 –22.21
–0.087 –21.79
–0.034 –21.91
–0.031 –21.84
Figure 49. Low Band Narrow-Band ACLR (Worst Side)
–38
–108
–21.874dBm/6MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
09616-051
3∆1
09616-048
–118
–107
AD9739A
16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.
–44
–38
1
–67.3dBc
–67.4dBc
–68.5dBc
–24.8dBm
–0.4dBc
–0.1dBc
0dBc
0dBc
–54
–58
–64
–68
–74
10dB/DIV
10dB/DIV
–48
–67.4dBc
–78
–88
–84
–94
–104
–98
6∆1
–108
–124
MKR
1
2
3
4
5
6
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
MODE TRC SCL
f
1
N
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
X
289.70MHz
202.05MHz (∆)
–183.65MHz (∆)
697.95MHz (∆)
18.70MHz (∆)
322.70MHz (∆)
Y
–25.335dBm
–66.838dB
–70.421dB
–65.880dB
–67.033dB
–64.481dB
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–26.335dBm
–66.838dB
–70.312dB
–65.928dB
–66.973dB
–64.451dB
(∆)
(∆)
(∆)
(∆)
(∆)
CENTER 200MHz
#RES BW 30kHz
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
Figure 52. Low Band Wideband ACLR
–44
–68
–74
10dB/DIV
FILTER
OFF
OFF
OFF
OFF
OFF
–66.7dBc
–66.8dBc
–67.1dBc
–67.4dBc
–26.1dBm
–0.5dBc
0.1dBc
0.2dBc
0dBc
–78
–88
–84
–94
–104
–108
4∆1
–124
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
X
690.60MHz
–141.85MHz (∆)
–623.50MHz (∆)
152.65MHz (∆)
Y
–28.317dBm
–64.672dB
–65.202dB
–64.574dB
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–28.317dBm
(∆) –64.672dB
(∆) –65.207dB
(∆) –64.574dB
CENTER 600MHz
#RES BW 30kHz
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
–26.083dBm/6MHz
ACP-IBW
LOWER
UPPER
dBm
dBc
dBm
dBc
–61.77 –87.85 –10.38 –36.49
–67.40 –93.48 –0.494 –26.58
–67.09 –93.18 0.098 –25.98
–66.80 –92.88 0.180 –25.90
–66.67 –92.75 0.021 –26.06
FILTER
OFF
OFF
OFF
OFF
OFF
09616-058
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
09616-055
START 50MHz
#RES BW 20kHz
MKR
1
2
3
4
–114
2∆1
3∆1
Figure 56. Mid Band Narrow-Band ACLR(Worst Side)
Figure 53. Mid Band Wideband ACLR
–44
–38
–48
–64.9dBc
–64.8dBc
–64.6dBc
–65.0dBc
–28.4dBm
–0.5dBc
–0.1dBc
0dBc
0.2dBc
–54
1
–64
–68
–74
10dB/DIV
–58
–78
–88
–84
–94
–104
–98
2∆1 6∆1
–108
–114
5∆1
4∆1
3∆1
–124
–118
MKR
1
2
3
4
5
6
MODE TRC SCL
f
1
N
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
VBW 2kHz
X
989.85MHz
–422.10MHz (∆)
–922.75MHz (∆)
–668.15MHz (∆)
–137.10MHz (∆)
–377.45MHz (∆)
Y
–27.971dBm
–61.110dB
–63.327dB
–65.509dB
–62.779dB
–59.828dB
CENTER 900MHz
#RES BW 30kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–27.960dBm
(∆) –61.110dB
(∆) –63.332dB
(∆) –65.483dB
(∆) –62.779dB
(∆) –59.828dB
CARRIER POWER
09616-056
START 50MHz
#RES BW 20kHz
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
–28.435dBm/6MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
ACP-IBW
LOWER
dBc
dBm
–57.24 –85.68
–65.03 –93.46
–64.64 –93.08
–64.80 –93.24
–64.86 –93.29
UPPER
dBc
dBm
–11.30 –39.73
–0.490 –28.92
–0.119 –28.55
–0.016 –28.45
0.153 –28.28
FILTER
OFF
OFF
OFF
OFF
OFF
Figure 57. High Band Narrow-Band ACLR (Worst Side)
Figure 54. High Band Wideband ACLR
Rev. 0 | Page 19 of 44
09616-059
10dB/DIV
–64
–98
10dB/DIV
ACP-IBW
UPPER
LOWER
dBc
dBm
dBc
dBm
–60.64 –85.46 –11.03 –35.85
–68.49 –93.30 –0.368 –25.19
–67.43 –92.24 0.137 –24.68
–67.32 –92.13 0.010 –24.81
–67.44 –92.26 0.035 –24.78
–54
1
–58
–118
–24.819dBm/6MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
Figure 55. Low Band Narrow-Band ACLR (Worst Side)
–38
–48
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
09616-057
START 50MHz
#RES BW 20kHz
09616-054
–118
–114
4∆1
2∆1
5∆1
3∆1
AD9739A
32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.
1
–44
–54
–72
–64
10dB/DIV
–62
–82
–92
2∆1
–114
–132
–124
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
X
384.70MHz
–283.40MHz (∆)
227.70MHz (∆)
325.55MHz (∆)
STOP 1GHz
SWEEP 24.1s (1001pts)
Y
–29.646dBm
–64.175dB
–59.429dB
–62.750dB
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–29.645dBm
(∆) –64.167dB
(∆) –59.423dB
(∆) –62.750dB
CENTER 200MHz
#RES BW 30kHz
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
Figure 58. Low Band Wideband ACLR
–72
–64
10dB/DIV
–54
–82
–92
–102
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
–29.311dBm/6MHz
ACP-IBW
LOWER
dBm
dBc
–58.76 –88.07
–63.30 –92.61
–63.05 –92.36
–63.21 –92.52
–63.46 –92.78
UPPER
dBm
dBc
–10.78 –40.09
–0.487 –29.80
–0.175 –29.49
–0.151 –29.46
–0.061 –29.37
FILTER
OFF
OFF
OFF
OFF
OFF
–64.7dBc
–64.7dBc
–64.7dBc
–65.3dBc
–29.3dBm
–0.5dBc
–0.1dBc
–0.1dBc
–0.2dBc
–94
–104
4∆1
3∆1
–114
–132
–124
MKR
1
2
3
4
MODE TRC SCL
N
1
f
∆1
1
f (∆)
∆1
1
f (∆)
∆1
1
f (∆)
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
X
685.85MHz
–611.15MHz (∆)
–243.50MHz (∆)
162.15MHz (∆)
Y
–30.335dBm
–63.136dB
–63.860dB
–62.151dB
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–30.335dBm
–63.112dB
–63.860dB
–62.151dB
(∆)
(∆)
(∆)
CENTER 600MHz
#RES BW 30kHz
CARRIER POWER
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
ACP-IBW
LOWER
dBc
dBm
–60.64 –89.90
–65.26 –94.52
–64.73 –93.99
–64.65 –93.91
–64.68 –93.93
UPPER
dBc
dBm
–10.40 –39.65
–0.515 –29.77
–0.178 –29.43
–0.069 –29.32
–0.197 –29.45
FILTER
OFF
OFF
OFF
OFF
OFF
Figure 62. Mid Band Narrow-Band ACLR(Worst Side)
Figure 59. Mid Band Wideband ACLR
–52
–29.255dBm/6MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
09616-064
2∆1
START 50MHz
#RES BW 20kHz
–44
1
–54
–72
–64
10dB/DIV
–62
–82
–92
–62.8dBc
–62.7dBc
–62.8dBc
–63.2dBc
–30.7dBm
–0.4dBc
–0.4dBc
–0.5dBc
–0.4dBc
–74
–84
–94
–102
4∆1
3∆1
–104
2∆1
–122
–114
–132
–124
START 50MHz
#RES BW 20kHz
MKR
1
2
3
4
MODE TRC SCL
f
1
N
f (∆)
1
∆1
f (∆)
1
∆1
f (∆)
1
∆1
VBW 2kHz
X
985.10MHz
–334.70MHz (∆)
–909.45MHz (∆)
–373.65MHz (∆)
Y
–31.616dBm
–59.997dB
–60.458dB
–57.761dB
CENTER 800MHz
#RES BW 30kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION
BAND POWER
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
6MHz
FUNCTION
VALUE
–31.516dBm
(∆) –59.997dB
(∆) –60.535dB
(∆) –57.763dB
CARRIER POWER
09616-062
10dB/DIV
–0.1dBc
–84
–122
–112
–0.2dBc
–74
09616-061
10dB/DIV
–44
–62
–112
–0.2dBc
Figure 61. Low Band Narrow-Band ACLR (Worst Side)
1
–52
–0.5dBc
–84
–122
MKR
1
2
3
4
–29.3dBm
–104
4∆1
VBW 2kHz
–63.3dBc
–94
3∆1
START 50MHz
#RES BW 20kHz
–63.1dBc
Figure 60. High Band Wideband ACLR
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
–30.746dBm/6MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
ACP-IBW
LOWER
dBc
dBm
–60.75 –91.49
–63.18 –93.92
–62.76 –93.50
–62.74 –93.48
–62.84 –93.59
UPPER
dBc
dBm
–10.84 –41.59
–0.437 –31.18
–0.354 –31.10
–0.455 –31.20
–0.410 –31.16
FILTER
OFF
OFF
OFF
OFF
OFF
Figure 63. High Band Narrow-Band ACLR (Worst Side)
Rev. 0 | Page 20 of 44
09616-065
–112
–63.2dBc
09616-063
–102
–63.5dBc
–74
09616-060
10dB/DIV
–52
AD9739A
64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.
–51
1
–62
–61
–72
–71
–82
–81
10dB/DIV
10dB/DIV
–52
–92
–102
0.3dBc
0.2dBc
0.1dBc
–0.3dBc
–32.4dBm
–62.3dBc
–61.5dBc
–61.5dBc
–61.4dBc
–91
–101
3∆1
–111
–122
–121
–132
–131
VBW 2kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
478.75MHz
N
1
1
f
–33.210dBm BAND POWER 6MHz
∆1
2
1
f (∆) 372.10MHz (∆) –58.746dB
BAND POWER 6MHz
∆1
3
1
f (∆) 132.70MHz (∆) –55.165dB
BAND POWER 6MHz
FUNCTION
VALUE
–33.209dBm
–58.804dB
–55.165dB
(∆)
(∆)
CENTER 478MHz
#RES BW 30kHz
CARRIER POWER
09616-066
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
–51
1
–61
–72
–71
–82
–81
10dB/DIV
–62
–92
–102
–121
–131
MODE TRC SCL
f
1
N
f (∆)
1
∆1
f (∆)
1
∆1
VBW 2kHz
X
978.45MHz
–901.85MHz (∆)
–561.75MHz (∆)
Y
–35.872dBm
–58.581dB
–59.214dB
FUNCTION
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
VALUE
–35.873dBm
(∆) –58.625dB
(∆) –59.286dB
1
–82
–92
–102
2∆1
3∆1
–122
–132
VBW 2kHz
X
988.90MHz
–481.95MHz (∆)
–925.60MHz (∆)
Y
–37.954dBm
–55.764dB
–57.007dB
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION
BAND POWER
BAND POWER
BAND POWER
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
VALUE
–37.983dBm
–55.764dB
–56.953dB
(∆)
(∆)
09616-068
10dB/DIV
–72
MODE TRC SCL
f
1
N
f (∆)
1
∆1
f (∆)
1
∆1
–60.6dBc
–61.1dBc
33.6dBm
0.3dBc
0.1dBc
0.2dBc
0.1dBc
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
–33.558dBm/6MHz
INTEG BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
ACP-IBW
LOWER
dBm
dBc
–60.02 –93.58
–61.11 –94.66
–60.57 –94.13
–60.64 –94.20
–60.58 –94.14
UPPER
dBm
dBc
–11.84 –45.04
–0.284 –33.84
–0.099 –33.46
–0.221 –33.34
–0.060 –33.50
FILTER
OFF
OFF
OFF
OFF
OFF
Figure 68. Mid Band Narrow-Band ACLR(Worst Side)
–62
MKR
1
2
3
–60.6dBc
CARRIER POWER
–52
START 50MHz
#RES BW 20kHz
–60.6dBc
CENTER 600MHz
#RES BW 30kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
Figure 65. Mid Band Wideband ACLR
–112
FILTER
OFF
OFF
OFF
OFF
OFF
–91
–132
MKR
1
2
3
UPPER
dBm
dBc
–60.80 –93.21
–62.25 –94.66
–61.47 –93.88
–61.54 –93.95
–61.40 –93.81
–101
–122
START 50MHz
#RES BW 20kHz
ACP-IBW
–111
3∆1
09616-067
10dB/DIV
–52
2∆1
–32.409dBm/6MHz
LOWER
INTEG BW
dBm
dBc
750.0kHz
–10.83 –43.24
5.250MHz –0.267 –32.68
6.000MHz
0.139 –32.27
6.000MHz
0.201 –32.21
6.000MHz
0.308 –32.10
Figure 67. Low Band Narrow-Band ACLR (Worst Side)
Figure 64. Low Band Wideband ACLR
–112
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
Figure 66. 128-Carrier High Band Wideband ACLR
Rev. 0 | Page 21 of 44
09616-070
START 50MHz
#RES BW 20kHz
09616-069
2∆1
–112
AD9739A
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
The maximum deviation of the actual analog output from the
ideal output, determined by a straight line drawn from 0 to full
scale.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Differential Nonlinearity (DNL)
The measure of the variation in analog value, normalized to full
scale, associated with a 1 LSB change in digital input code.
Spurious-Free Dynamic Range
The difference, in decibels (dB), between the rms amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of 0 is called
the offset error. For IOUTP, 0 mA output is expected when the
inputs are all 0s. For IOUTN, 0 mA output is expected when all
inputs are set to 1.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1 minus the output when all inputs are set to 0.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Specified as the maximum change from the ambient (25°C)
value to the value at either TMIN or TMAX. For offset and gain
drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal. It is expressed as
a percentage or in decibels (dB).
Noise Spectral Density (NSD)
NSD is the converter noise power per unit of bandwidth. This is
usually specified in dBm/Hz in the presence of a 0 dBm fullscale signal.
Adjacent Channel Leakage Ratio (ACLR)
The adjacent channel leakage (power) ratio is a ratio, in dBc, of
the measured power within a channel relative to its adjacent
channels.
Modulation Error Ratio (MER)
Modulated signals create a discrete set of output values referred
to as a constellation. Each symbol creates an output signal
corresponding to one point on the constellation. MER is a
measure of the discrepancy between the average output symbol
magnitude and the rms error magnitude of the individual
symbol.
Intermodulation Distortion (IMD)
IMD is the result of two or more signals at different frequencies
mixing together. Many products are created according to the
formula, aF1 ± bF2, where a and b are integer values.
Rev. 0 | Page 22 of 44
AD9739A
SERIAL PORT INTERFACE (SPI) REGISTER
SPI REGISTER MAP DESCRIPTION
SPI OPERATION
The AD9739A contains a set of programmable registers
described in Table 9 that are used to configure and monitor
various internal parameters. Note the following points when
programming the AD9739A SPI registers:
The serial port of the AD9739A shown in Figure 69 has a 3- or
4-wire SPI capability, allowing read/write access to all registers
that configure the device’s internal parameters. It provides a
flexible, synchronous serial communications port, allowing easy
interface to many industry-standard microcontrollers and
microprocessors. The 3.3 V serial I/O is compatible with most
synchronous transfer formats, including the Motorola® SPI and
the Intel® SSR protocols.
•
•
•
•
Registers pertaining to similar functions are grouped
together and assigned adjacent addresses.
Bits that are undefined within a register should be assigned
a 0 when writing to that register.
Registers that are undefined should not be written to.
A hardware or software reset is recommended upon
power-up to place SPI registers in a known state.
A SPI initialization routine is required as part of the boot
process. See Table 12 for an example procedure.
SDO (PIN H14)
SDIO (PIN G14)
AD9739
SCLK (PIN H13)
SPI PORT
CS (PIN G13)
Figure 69. AD9739A SPI Port
Reset
Issuing a hardware or software reset places the AD9739A SPI
registers in a known state. All SPI registers (excluding 0x00) are
set to their default states as described in Table 9 upon issuing a
reset. After issuing a reset, the SPI initialization process need
only write to registers that are required for the boot process as
well as any other register settings that must be modified,
depending on the target application.
Although the AD9739A does feature an internal power-on-reset
(POR), it is still recommended that a software or hardware reset
be implemented shortly after power-up. The internal reset
signal is derived from a logical OR operation from the internal
POR signal, the RESET pin, and the software reset state. A
software reset can be issued via the reset bit (Register 0x00,
Bit 5) by toggling the bit high then low. Note that, because the
MSB/LSB format may still be unknown upon initial power-up
(that is, internal POR is unsuccessful), it is also recommended
that the bit settings for Bits[7:5] be mirrored onto Bits[2:0] for
the instruction cycle that issues a software reset. A hardware
reset can be issued from a host or external supervisory IC by
applying a high pulse with a minimum width of 40 ns to the
RESET pin (that is, Pin F14). RESET should be tied to VSS if
unused.
Table 8. SPI Registers Pertaining to SPI Options
Address (Hex)
0x00
09616-072
•
Bit
7
6
5
Description
Enable 3-wire SPI
Enable SPI LSB first
Software reset
The default 4-wire SPI interface consists of a clock (SCLK),
serial port enable (CS), serial data input (SDIO), and serial data
output (SDO). The inputs to SCLK, CS, and SDIO contain a
Schmitt trigger with a nominal hysteresis of 0.4 V centered
about VDD33/2. The maximum frequency for SCLK is 20 MHz.
The SDO pin is active only during the transmission of data and
remains three-stated at any other time.
A 3-wire SPI interface can be enabled by setting the SDIO_DIR
bit (Register 0x00, Bit 7). This causes the SDIO pin to become
bidirectional such that output data only appears on the SDIO
pin during a read operation. The SDO pin remains three-stated
in a 3-wire SPI interface.
Instruction Header Information
MSB
17
R/W
16
A6
15
A5
14
A4
13
A3
12
A2
11
A1
LSB
10
A0
An 8-bit instruction header must accompany each read and write
operation. The MSB is a R/W indicator bit with logic high
indicating a read operation. The remaining seven bits specify
the address bits to be accessed during the data transfer portion.
The eight data bits immediately follow the instruction header
for both read and write operations. For write operations,
registers change immediately upon writing to the last bit of each
transfer byte. CS can be raised after each sequence of eight bits
(except the last byte) to stall the bus. The serial transfer resumes
when CS is lowered. Stalling on nonbyte boundaries resets the
SPI.
Rev. 0 | Page 23 of 44
AD9739A
initiate a write operation, the read/not-write bit is set low. After
the instruction header is read, the eight data bits pertaining to
the specified register are shifted into the SDIO pin on the rising
edge of the next eight clock cycles.
The AD9739A serial port can support both most significant bit
(MSB) first and least significant bit (LSB) first data formats.
Figure 70 illustrates how the serial port words are formed for
the MSB first and LSB first modes. The bit order is controlled
by the SDIO_DIR bit (Register 0x00, Bit 7). The default value is
0, MSB first. When the LSB first bit is set high, the serial port
interprets both instruction and data bytes LSB first.
INSTRUCTION CYCLE
CS
Figure 72 illustrates the timing for a 3-wire read operation to
the SPI port. After CS goes low, data (SDIO) pertaining to the
instruction header is read on the rising edges of SCLK. A read
operation occurs if the read/not-write indicator is set high.
After the address bits of the instruction header are read, the
eight data bits pertaining to the specified register are shifted out
of the SDIO pin on the falling edges of the next eight clock
cycles.
DATA TRANSFER CYCLE
SCLK
SDATA
R/W N1
N2 A4
A3
A2 A1
A0 D71 D61
Figure 73 illustrates the timing for a 4-wire read operation to
the SPI port. The timing is similar to the 3-wire read operation
with the exception that data appears at the SDO pin only, while
the SDIO pin remains at high impedance throughout the
operation. The SDO pin is an active output only during the data
transfer phase and remains three-stated at all other times.
DATA TRANSFER CYCLE
INSTRUCTION CYCLE
CS
D1N D0N
SCLK
A0
A1
A2 A3
A4 N2 N1 R/W D01 D11
D6N D7N
09616-073
SDATA
Figure 70. SPI Timing, MSB First (Upper) and LSB First (Lower)
Figure 71 illustrates the timing requirements for a write
operation to the SPI port. After the serial port enable (CS)
signal goes low, data (SDIO) pertaining to the instruction
header is read on the rising edges of the clock (SCLK). To
tS 1/fSCLK
CS
tH
tLOW
tHI
tDS
tDH
SDIO
R/W
N1
N0
A0
D6 D1
D7
D0
09616-074
SCLK
Figure 71. SPI Write Operation Timing
tS 1/fSCLK
CS
tLOW
tHI
tDS
tDV
tDH
SDIO
R/W
N1
A2
A1
A0
tEZ
D7
D6
D1
D0
09616-075
SCLK
Figure 72. SPI 3-Wire Read Operation Timing
tS 1/fSCLK
CS
tLOW
tHI
SCLK
SDIO
tEZ
tDH
R/W
N1
A2
A1
A0
tEZ
tDV
D7
SDO
D6
D1
Figure 73. SPI 4-Wire Read Operation Timing
Rev. 0 | Page 24 of 44
D0
09616-076
tDS
AD9739A
SPI REGISTER MAP
Table 9.
Address
(Hex)
Name
Bit
R/W
SPI Port Configuration and Software Reset
0x00
SDIO_DIR
7
R/W
LSB/MSB
6
R/W
Reset
5
R/W
Default
Setting
Comments
0
0
0
0 = 4-wire SPI, 1 = 3-wire SPI.
0 = MSB first, 1 = LSB first.
Software reset is recommended before modification of other SPI registers from
the default setting. Setting the bit to 1 causes all registers (except 0x00) to be set
to the default setting. Setting the bit to 0 corresponds to the inactive state,
allowing the user to modify registers from the default setting.
Power-Down LVDS Interface and TxDAC
0x01
LVDS_DRVR_PD
5
LVDS_RCVR_PD4 4
CLK_RCVR_PD
1
DAC_BIAS_PD
0
Controller Clock Disable
0x02
CLKGEN_PD
3
REC_CNT_CLK
1
R/W
R/W
R/W
R/W
0
0
0
0
Power-down of the LVDS drivers/receivers and TxDAC.
0 = enable, 1 = disable.
R/W
R/W
0
1
MU_CNT_CLK
R/W
1
Internal CLK distribution enable: 0 = enable, 1 = disable.
LVDS receiver and Mu controller clock disable.
0 = disable, 1 = enable.
W
W
W
W
R
0
0
0
0
0
R
R
R
0
0
0
0
Interrupt Request (IRQ) Enable/Status
0x03
MU_LST_EN
3
MU_LCK_EN
2
RCV_LST_EN
1
RCV_LCK_EN
0
0x04
MU_LST_IRQ
3
MU_LCK_IRQ
RCV_LST_IRQ
RCV_LCK_IRQ
2
1
0
TxDAC Full-Scale Current Setting (IOUTFS) and Sleep
0x06
FSC_1
[7:0] R/W 0x00
0x07
FSC_2
[1:0] R/W 0x02
Sleep
7
R/W
TxDAC Quad-Switch Mode of Operation
0x08
DAC-DEC
[1:0] R/W 0x00
DCI Phase Alignment Status
0x0C
DCI_PRE_PH0
DCI_PST_PH0
2
R
0
0
R
0
This register enables the Mu and LVDS Rx controllers to update their
corresponding IRQ status bits in Register 0x04, which defines whether the
controller is locked (LCK) or unlocked (LST).
0 = disable (resets the status bit), 1 = enable.
This register indicates the status of the controllers.
For LCK_IQR bits: 0 = lost locked, 1 = locked.
For LST_IQR bits: 0 = not lost locked, 1 = unlocked.
Note that, if the controller IRQ is serviced, the relevant bits in Register 0x03
should be reset by writing 0, followed by another write of 1 to enable.
Sets the TxDAC IOUTFS current between 8 mA and 31 mA (default = 20 mA).
IOUTFS = 0.0226 × FSC[9:0] + 8.58, where FSC = 0 to 1023.
0 = enable DAC output, 1 = disable DAC output (sleep).
0x00 = normal baseband mode.
0x01 = return-to-zero mode.
0x02 = mix mode.
0 = DCI rising edge is after the PRE delayed version of the Phase 0 sampling
edge.
1 = DCI rising edge is before the PRE delayed version of the Phase 0 sampling
edge.
0 = DCI rising edge is after the POST delayed version of the Phase 0 sampling
edge.
1 = DCI rising edge is before the POST delayed version of the Phase 0 sampling
edge.
Rev. 0 | Page 25 of 44
AD9739A
Address
(Hex)
Name
Bit
R/W
Data Receiver Controller Configuration
0x10
RCVR_FLG_RST
2
W
RCVR_LOOP_ON
1
R/W
Default
Setting
0
1
RCVR_CNT_ENA
0
R/W 0
Data Receiver Controller_Data Sample Delay Value
0x11
SMP_DEL[1:0]
[7:6] R/W 11
0x12
SMP_DEL[9:2]
[7:0]
R/W
0x25
Comments
Data receiver controller flag reset. Write 1 followed by 0 to reset flags.
0 = disable, 1 = enable.
When enabled, the data receiver controller generates an IRQ; it falls out of lock
and automatically begins a search/track routine.
Data receiver controller enable. 0 = disable, 1 = enable.
Controller enabled: the 10-bit value (with a maximum of 332) represents the
start value for the delay line used by the state machine to sample data. Leave at
the default setting of 167, which represents the midpoint of the delay line.
Controller disabled: the value sets the actual value of the delay line.
Data Receiver Controller_DCI Delay Value/Window and Phase Rotation
0x13
DCI_DEL[3:0]
[7:4] R/W 0111
Refer to the DCI_DEL description in Register 0x14.
FINE_DEL_SKEW
[3:0] R/W 0001
A 4-bit value sets the difference (that is, window) for the DCI PRE and POST
sampling clocks. Leave at the default value of 1 for a narrow window.
0x14
DCI_DEL[9:4]
[5:0] R/W 001010 Controller enabled: the 10-bit value (with a maximum of 332) represents the
start value for the delay line used by the state machine to sample the DCI input.
Leave at the default setting of 167, which represents the midpoint of the delay
line.
Controller disabled: the value sets the actual value of the delay line.
Data Receiver Controller_Delay Line Status
0x19
SMP_DEL[1:0]
[1:0] R
00
The actual value of the DCI and data delay lines determined by the data receiver
controller (when enabled) after the state machine completes its search and
0x1A
SMP_DEL[9:2]
[7:0] R
0x00
enters track mode. Note that these values should be equal.
0x1B
DCI_DEL[1:0]
[1:0] R
00
0x1C
DCI_DEL[9:2]
[7:0] R
0x00
Data Receiver Controller Lock/Tracking Status
0x21
RCVR_TRK_ON
3
R
RCVR_LST
1
R
RCVR_LCK
R
0
0 = controller is not locked, 1 = controller is locked.
4
R/W
0
CLKP_OFFSET[3:0]
[3:0]
R/W
0000
DIR_N
4
R/W
0
DIR_P and DIR_N.
0 = VCM at the DACCLK_P input decreases with the offset value.
1 = VCM at the DACCLK_P input increases with the offset value.
CLKx_OFFSET sets the magnitude of the offset for the DACCLK_P and DACCLK_N
inputs. For optimum performance, set to 1111.
CLKN_OFFSET[3:0]
[3:0]
R/W
0000
Mu Controller Configuration and Status
0x24
CMP_BST
5
R/W
0x25
0x26
0 = tracking not established, 1 = tracking established.
0 = controller has not lost lock, 1 = controller has lost lock.
0
CLK Input Common Mode
0x22
DIR_P
0x23
0
0
0
PHS_DET
AUTO_EN
MU_DUTY
AUTO_EN
4
R/W
0
7
R/W
0
Slope
6
R/W
1
Mode[1:0]
[5:4]
R/W
00
Read
3
R/W
0
Phase detector enable and boost bias bits.
Note that both bits should always be set to 1 to enable these functions.
Mu controller duty cycle enable.
Note that this bit should always be set to 1 to enable.
Mu controller phase slope lock. 0 = negative slope, 1 = positive slope. Note that a
setting of 0 is recommended for best ac performance.
Sets the Mu controller mode of operation.
00 = search and track (recommended).
01 = search only.
10 = track.
Set to 1 to read the current value of the Mu delay line in.
Rev. 0 | Page 26 of 44
AD9739A
Address
(Hex)
0x27
0x28
0x29
0x2A
Part ID
0x35
Name
Gain[1:0]
Bit
[2:1]
R/W
R/W
Default
Setting
01
Enable
0
R/W
0
MUDEL[0]
7
R/W
0
SRCH_MODE[1:0]
[6:5]
R/W
0
SET_PHS[4:0]
[4:0]
R/W
0
MUDEL[8:1]
[7:0]
W
0x00
R
0x00
SEARCH_TOL
7
R/W
0
Retry
6
R/W
0
CONTRST
5
R/W
0
Guard[4:0]
5
R/W
01011
MU_LST
1
R
0
MU_LKD
0
R
0
PART_ID
[7:0]
R
0x24
Comments
Sets the Mu controller tracking gain.
Recommended to leave at the default 01 setting.
0 = enable the Mu controller.
1 = disable the Mu controller.
The LSB of the 9-bit MUDEL setting.
Sets the direction in which the Mu controller searches (from its initial MUDEL setting)
for the optimum Mu delay line setting that corresponds to the desired phase/slope
setting (that is, SET_PHS and slope ).
00 = down.
01 = up.
10 = down/up (recommended).
Sets the target phase that the Mu controller locks to with a maximum setting of 16.
A setting of 4 (that is, 00100) is recommended for optimum ac performance.
With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the value
that the Mu delay is set to. Note that the maximum value is 432.
With enable set to 1, this value represents the Mu delay value at which the
controller begins its search. Setting this value to the delay line midpoint of 216 is
recommended.
When read (Bit 3, Register 0x26) is set to 1, the value read back is equal to the
value written into the register when enable = 0 or the value that the Mu
controller locks to when enable = 1.
0 = not exact (can find a phase within two values of the desired phase).
1 = finds the exact phase that is targeted (optimal setting).
0 = stop the search if the correct value is not found,
1 = retry the search if the correct value is not found.
Controls whether the controller resets or continues when it does not find the
desired phase.
0 = continue (optimal setting), 1 = reset.
Sets a guard band from the beginning and end of the mu delay line which the
Mu controller does not enter into unless it does not find a valid phase outside
the guard band (optimal value is Decimal 11 or 0x0B).
0 = Mu controller has not lost lock.
1 = Mu controller has lost lock.
0 = Mu controller is not locked.
1= Mu controller is locked.
Rev. 0 | Page 27 of 44
AD9739A
IRQ
AD9739A
SDIO
SDO
CS
SCLK
1.2V
SPI
DAC BIAS
VREF
CLK DISTRIBUTION
(DIV-BY-4)
TxDAC
CORE
IOUTP
DLL
(MU CONTROLLER)
DACCLK
Figure 74. Functional Block Diagram of the AD9739A
Rev. 0 | Page 28 of 44
IOUTN
09616-077
DCO
DATA
LATCH
DCI
4-TO-1
DATA ASSEMBLER
I120
LVDS DDR
RECEIVER
As mentioned, the host processor provides the AD9739A with a
deinterleaved data stream such that the DB0 and DB1 data
ports receive alternating samples (that is, odd/even data
streams). The AD9739A data assembler is used to reassemble
(that is, multiplex) the odd/even data streams into their original
order before delivery into the TxDAC for signal reconstruction.
The pipeline delay from a sample being latched into the data
port to when it appears at the DAC output is on the order of 78
(±) DACCLK cycles.
RESET
LVDS DDR
RECEIVER
The AD9739A data receiver controller generates an internal
sampling clock for the DDR receiver such that the data instance
sampling is optimized. When enabled and configured properly
for track mode, it ensures proper data recovery between the
host and the AD9739A clock domains. The data receiver
controller has the ability to track several hundreds of ps of drift
between these clock domains, typically caused by supply and
temperature variation.
The following sections discuss the various functional blocks in
more detail as well as their implications when interfacing to
external ICs and circuitry. While a detailed description of the
various controllers (and associated SPI registers used to
configure and monitor) is also included for completeness, the
recommended SPI boot procedure can be used to ensure
reliable operation.
DATA
CONTROLLER
The AD9739A includes two 14-bit LVDS data ports (DB0 and
DB1) to reduce the data interface rate to ½ the TxDAC update
rate. The host processor drives deinterleaved data with offset
binary format onto the DB0 and DB1 ports, along with an
embedded DCI clock that is synchronous with the data.
Because the interface is double data rate (DDR), the DCI clock
is essentially an alternating 0-1 bit pattern with a frequency
equal to ¼ the TxDAC update rate (fDAC). To simplify synchronization with the host processor, the AD9739A passes an
LVDS clock output (DCO) that is also equal to the DCI
frequency.
A SPI interface is used to configure the various functional
blocks as well as monitor their status for debug purposes.
Proper operation of the AD9739A requires that controller
blocks be initialized upon power-up. A simple SPI initialization
routine is used to configure the controller blocks (see Table 11).
An IRQ output signal is available to alert the host should any of
the controllers fall out of lock during normal operation.
DB0[13:0]
The AD9739A is a 14-bit TxDAC with a specified update rate of
1.6 GSPS to 2.5 GSPS. Figure 74 shows a top-level functional
diagram of the AD9739A. A high performance TxDAC core
delivers a signal dependent, differential current (nominal
±10 mA) to a balanced load referenced to ground. The frequency
of the clock signal appearing at the AD9739A differential clock
receiver, DACCLK, sets the TxDAC’s update rate. This clock
signal, which serves as the master clock, is routed directly to the
TxDAC as well as to a clock distribution block that generates all
critical internal and external clocks.
The AD9739A includes a delay lock loop (DLL) circuit
controlled via a Mu controller to optimize the timing hand-off
between the AD9739A digital clock domain and TxDAC core.
Besides ensuring proper data reconstruction, the TxDAC’s ac
performance is also dependent on this critical hand-off between
these clock domains with speeds of up to 2.5 GSPS. Once
properly initialized and configured for track mode, the DLL
maintains optimum timing alignment over temperature, time,
and power supply variation.
DB1[13:0]
THEORY OF OPERATION
AD9739A
LVDS DATA PORT INTERFACE
The AD9739A supports input data rates from 1.6 GSPS to
2.5 GSPS using dual LVDS data ports. The interface is source
synchronous and double data rate (DDR) where the host
provides an embedded data clock input (DCI) at fDAC/4 with its
rising and falling edges aligned with the data transitions. The
data format is offset binary; however, twos complement format
can be realized by reversing the polarity of the MSB differential
trace. As shown in Figure 75, the host feeds the AD9739A with
deinterleaved input data into two 14-bit LVDS data ports (DB0
and DB1) at ½ the DAC clock rate (that is, fDAC/2). The
AD9739A internal data receiver controller then generates a
phase shifted version of DCI to register the input data on both
the rising and falling edges.
HOST
PROCESSOR
14 × 2
LVDS DDR
RECEIVER
ODD DATA
SAMPLES
1×2
DATA
CONTROLLER
fDATA = fDAC /2
DB1[13:0]
LVDS DDR DRIVER
DATA DEINTERLEAVER
14 × 2
DB0[13:0]
EVEN DATA
SAMPLES
LVDS DDR
RECEIVER
AD9739A
DCI
DCO
1×2
fDCO = fDAC /4
DIV-BY-4
fDAC
09616-078
fDCI = fDAC/4
Figure 75. Recommended Digital Interface Between the AD9739A and
Host Processor
As shown in Figure 76, the DCI clocks edges must be coincident
with the data bit transitions with minimum skew, jitter, and
intersymbol interference. To ensure coincident transitions with
the data bits, the DCI signal should be implemented as an
additional data line with an alternating (010101…) bit sequence
from the same output drivers used for the data. Maximizing the
opening of the eye in both the DCI and data signals improves
the reliability of the data port interface. Differential controlled
impedance traces of equal length (that is, delay) should also be
used between the host processor and AD9739A input to limit
bit-to-bit skew.
The maximum allowable skew and jitter out of the host
processor with respect to the DCI clock edge on each LVDS
port is calculated as follows:
MaxSkew + Jitter = Period(ns) − ValidWindow(ps) − Guard
= 800 ps − 344 ps − 100 ps
= 356 ps
where ValidWindow(ps) is represented by tVALID and Guard is
represented by tGUARD in Figure 76.
The minimum specified LVDS valid window is 344 ps, and a
guard band of 100 ps is recommended. Therefore, at the maximum operating frequency of 2.5 GSPS, the maximum allowable
FPGA and PCB bit skew plus jitter is equal to 356 ps.
For synchronous operation, the AD9739A provides a data clock
output, DCO, to the host at the same rate as DCI (that is, fDAC/4)
to maintain the lowest skew variation between these clock
domains. The host processor has a worst case skew between
DCO and DCI that is both implementation and process
dependent. This worst case skew can also vary an additional
30% over temperature and supply corners. The delay line within
the data receiver controller can track a ±1.5 ns skew variation
after initial lock. While it is possible for the host to have an
internal PLL that generates a synchronous fDAC/4 from which the
DCI signal is derived, digital implementations that result in the
shortest propagation delays result in the lowest skew variation.
The data receiver controller is used to ensure proper data handoff between the host and AD9739A internal digital clock
domains. The circuit shown in Figure 77 functions as a delay
lock loop in which a 90o phase shifted version of the DCI clock
input is used to sample the input data into the DDR receiver
registers. This ensures that the sampling instance occurs in the
middle of the data pattern eyes (assuming matched DCI and
DBx[13:0] delays). Note that, because the DCI delay and sample
delay clocks are derived from the DIV-BY-4 circuitry, this 90°
phase relationship holds as long as the delay settings (that is,
DCI_DEL, SMP_DEL) are also matched.
2 × 1/fDAC
DCI
tVALID + tGUARD
tVALID
09616-079
DB0[13:0]
AND DB1[13:0]
max skew
+ jitter
Figure 76. LVDS Data Port Timing Requirements
Rev. 0 | Page 29 of 44
AD9739A
DATA RECEIVER CONTROLLER
DCI
DDR
FF
DCI WINDOW PRE
FINE
DELAY
PRE
DDR
FF
DELAY
DELAY
DCI DELAY
DCI WINDOW POST
0
90
DIV-BY-4
180
270
STATE MACHINE/
TRACKING LOOP
FINE
DELAY
POST
DDR
FF
DCI
DELAY
PATH
FDAC
SAMPLE
DELAY
DCI WINDOW SAMPLE
SAMPLE
DELAY
PATH
FINE
DELAY
DELAY
DELAY
SAMPLE
DBx[13:1]
DDR
FF
DDR
FF
DDR
FF
DDR
FF
DATA TO
CORE
09616-080
ELASTIC FIFO
DCO
Figure 77. Top Level Diagram of the Data Receiver Controller
Once this data has been successively sampled into the first set of
registers, an elastic FIFO is used to transfer the data into the
AD9739A clock domain. To continuously track any phase
variation between the two clock domains, the data receiver
controller should always be enabled and placed into track mode
(Register 0x10, Bit 1 and Bit 0). Tracking mode operates
continuously in the background to track delay variations
between the host and AD9739A clock domains. It does so by
ensuring that the DCI signal is sampled within a very narrow
window defined by two internally generated clocks (that is, PRE
and PST), as shown in Figure 78. Note that proper sampling of
the DCI signal can also be confirmed by monitoring the status
of DCI_PRE_PH0 (Register 0x0C, Bit 2) and DCI_PST_PH0
(Register 0x0C, Bit 0). If the delay settings are correct, the state
of DCI_ PRE_PH0 should be 0, and the state of DCI_PST_PH0
should be 1.
DCI
FINE DELAY
PST
FINE DELAY
PRE
FINE_DEL_SKEW
09616-081
The DIV-BY-4 circuit generates four clock phases that serve as
inputs to the data receiver controller. All of the DDR registers in
the data and DCI paths operate on both clock edges; however,
for clarity purposes, only the phases (that is, 0o and 90o)
corresponding to the positive edge of each path are shown. One
of the DIV-BY-4 phases is used to generate the DCO signal;
therefore, the phase relationship between DCO and clocks fed
into the controller remains fixed. Note that it is this attribute
that allows possible factory calibration of images and clock
spurs attributed to fDAC/4 modulation of the critical DAC clock.
Figure 78. Pre- and Post-Delay Sampling Diagram
The skew or window width (FINE_DEL_SKEW) is set via
Register 0x13, Bits[3:0], with a maximum skew of approximately 300 ps and resolution of 20 ps. It is recommended that
the skew be set to 60 ps (that is, Register 0x13 = 0x72) during
initialization. Note that the skew setting also affects the speed of
the controller loop, with tighter skew settings corresponding to
longer response time.
Data Receiver Controller Initialization Description
The data controller should be initialized and placed into track
mode as the second step in the SPI boot sequence. The
following steps are recommended for the initialization of the
data receiver controller:
1.
2.
3.
4.
Rev. 0 | Page 30 of 44
Set FINE_DEL_SKEW to 2 for a larger DCI sampling
window (Register 0x13 = 0x72). Note that the default
DCI_DEL and SMP_DEL settings of 167 are optimum.
Disable the controller before enabling (that is, Register
0x10 = 0x00).
Enable the Rx controller in two steps: Register 0x10 – 0x02
followed by Register 0x10 = 0x03.
Wait 135 K clock cycles.
AD9739A
Once the controller is enabled during the initial SPI boot
process (see Table 12), the controller enters a search mode
where it seeks to find the closest rising edge of the DCI clock
(relative to a delayed version of an internal fDAC/4 clock) by
simultaneously adjusting the delays in the clocks used to
register the DCI and data inputs. A state machine searches
above and below the initial DCI_DEL value. The state machine
first searches for the first rising edge above the DCI_DEL and
then searches for the first rising edge below the DCI_DEL
value. The state machine selects the closest rising edge and then
enters track mode. It is recommended that the default midpoint
delay setting (that is, Decimal 167) for the DCI_DEL and
SMP_DEL bits be kept to ensure that the selected edge remains
closest to the delay line midpoint, thus providing the greatest
range for tracking timing variations and preventing the
controller from falling out of lock.
The adjustable delay span for these internal clocks (that is, DCI
and sample delay) is nominally 4 ns. The 10-bit delay value is
user programmable from the decimal equivalent code (0 to 334)
with approximately 12 ps/LSB resolution via the DCI_DEL and
SMP_DEL registers (Register 0x13 and Register14). When the
controller is enabled, it overwrites these registers with the delay
value it converges upon. The minimum difference between this
delay value and the minimum/maximum values (that is, 0 and
334) represents the guard band for tracking. Therefore, if the
controller initially converges upon a DCI_DEL and SMP_DEL
value between 80 and 254, the controller has a guard band of at
least 80 code (approximately 1 ns) to track phase variations
between the clock domains.
Upon initialization of the AD9739A, a certain period of time is
required for the data receiver controller to establish a lock of the
DCI clock signal. Note that, due to its dependency on the Mu
controller, the data receiver controller should be enabled only
after the Mu controllers have been enabled and established lock.
All of the internal controllers operate at a submultiple of the
DAC update rate. The number of fDAC clock cycles required to
lock onto the DCI clock is typically 70 k clock cycles but can be
up to 135 k clock cycles. During the SPI initialization process,
the user has the option of polling Register 0x21 (Bit 0, Bit 1, and
Bit 3) to determine if the data receiver controller is locked, has
lost lock, or has entered into track mode before completing the
boot sequence. Alternatively, the appropriate IRQ bit (Register
0x03 and Register 0x04) can be enabled such that an IRQ
output signal is generated upon the controller establishing lock.
power supply rail. To service the interrupt, the host can poll the
RCVR_LCK bit to determine the current state of the controller.
If this bit is cleared, the search/track procedure can be restarted
by setting the RCVR_LOOP_ON bit in Register 0x10, Bit 1.
After waiting the required lock time, the host can poll the
RCVR_LCK bit to see if it has been set. Before leaving the
interrupt routine, the RCVR_FLG_RST bit should be reset by
writing a high followed by a low.
LVDS Driver and Receiver Input
The AD9739A features an LVDS-compatible driver and
receivers. The LVDS driver output used for the DCO signal
includes an equivalent 200 Ω source resistor that limits its
nominal output voltage swing to ±200 mV when driving a
100 Ω load. The DCO output driver can be powered down via
Register 0x1, Bit 5. An equivalent circuit is shown in Figure 79
VDD33
V+
DCO_N
ESD
V–
V–
100Ω 100Ω
VCM
ESD
DCO_P
V+
09616-082
6.
Read back Register 0x21 and confirm that it is equal to
0x05 to ensure that the DLL loop is locked and tracking.
Read back the DCI_DEL value to determine whether the
value falls within a user defined tracking guard band. If it
does not, go back to Step 2.
VSS
Figure 79. Equivalent LVDS Output
VDD33
100Ω
DCI_P
DBx[13:0]P
ESD
ESD
VSS
DCI_N
DBx[13:0]N
09616-083
5.
Figure 80. Equivalent LVDS Input
The LVDS receivers include 100 Ω termination resistors, as
shown in Figure 80. These receivers meet the IEEE-1596.3-1996
reduced swing specification (with the exception of input
hysteresis, which cannot be guaranteed over all process
corners). Figure 81 and Table 10 show an example of nominal
LVDS voltage levels seen at the input of the differential receiver
with resulting common-mode voltage and equivalent logic level.
Note that the AD9739A LVDS inputs do not include fail-safe
capability; hence, any unused input should be biased with an
external circuit or static driver. The LVDS receivers can be
powered-down via Register 0x01, Bit 4.
The data receiver controller can also be configured to generate
an interrupt request (IRQ) upon losing lock. Losing lock can be
caused by disruption of the main DAC clock input or loss of a
Rev. 0 | Page 31 of 44
AD9739A
The Mu controller adjusts the timing relationship between the
digital and analog domains via a tapped digital delay line having
a nominal total delay of 864 ps. The delay value is programmable to a 9-bit resolution (that is, 0 to 432 decimal) via the
MUDEL register, resulting in a nominal resolution of 2 ps/LSB.
Because a time delay maps to a phase offset for a fixed clock
frequency, the control loop essentially compares the phase
relationship between the two clock domains and adjusts the
phase (that is, via a tapped delay line) of the digital clock such
that it is at the desired fixed phase offset (SET_PHS) from the
critical analog clock.
LVDS INPUTS
(NO FAIL-SAFE)
V
V
P
LVDS
RECEIVER
100Ω
P,N
VN
GND
Example
V
P
1.4V
V
1.0V
N
V
P
18
0.4V
16
0V
12
LOGIC BIT
EQUIVALENT
LOGIC 0
09616-084
–0.4V
LOGIC 1
Figure 81. LVDS Data Input Levels
MU PHASE
V
N
Applied Voltages
VP
VN
1.4 V
1.0 V
1.0 V
1.4
1.0 V
0.8 V
0.8 V
1.0 V
14-BIT
DATA
Logic Bit
Binary
Equivalent
1
0
1
0
DAC
CLOCK
IOUTP
IOUTN
PHASE
DETECTOR
MU
DELAY
CONTROLLER
09616-085
MU
DELAY
ANALOG
CIRCUITRY
SEARCH STARTING
LOCATION
2
A delay lock loop (DLL) is used to optimize the timing between
the internal digital and analog domains of the AD9739A such
that data is successfully transferred into the TxDAC core at rates
of up to 2.5 GSPS. As shown in Figure 82, the DAC clock is split
into an analog and a digital path with the critical analog path
leading to the DAC core (for minimum jitter degradation) and
the digital path leading to a programmable delay line. Note that
the output of this delay line serves as the master internal digital
clock from which all other internal and external digital clocks
are derived. The amount of delay added to this path is under the
control of the Mu controller, which optimizes the timing
between these two clock domains and continuously tracks any
variation (once in track mode) to ensure proper data hand-off.
DIGITAL
CIRCUITRY
DESIRED
PHASE
8
4
Resulting
CommonModel
Voltage
VCOM
1.2 V
1.2 V
900 mV
900 mV
MU CONTROLLER
14-BIT
DATA
10
6
Table 10. Example of LVDS Input Levels
Resulting
Differenital
Voltage
VP,N
+0.4 V
−0.4 V
+200 mV
−200 mV
GUARD
BAND
GUARD
BAND
14
0
0
40
80
120
160
200
240
280
320
360
400
440
MU DELAY
09616-086
V
COM
= (V + V )/2
P
N
Figure 83. Typical Mu Phase Characteristic Plot at 2.4 GSPS
Figure 83 maps the typical Mu phase characteristic at 2.4 GSPS
versus the 9-bit digital delay setting (MUDEL). The Mu phase
scaling is such that a value of 16 corresponds to 180 degrees.
The critical keep-out window between the digital and analog
domains occurs at a value of 0 (but can extend out to +2
depending on the clock rate). The target Mu phase (and slope)
is selected to provide optimum ac performance while ensuring
that the Mu controller for any device can establish and maintain
lock. While the Mu phase characteristics can vary among
devices, a slope/phase setting of −4 has been verified to ensure
robust operation and optimum ac performance for 1.6 GSPS to
2.5 GSPS operation.
After the Mu controller completes its search and establishes
lock on the target Mu phase, it attempts to maintain a constant
timing relationship between the two clock domains over the
specified temperature and supply range. If the Mu controller
requests a Mu delay setting that exceeds the tapped delay line
range (that is, <0 or >432), the Mu controller can lose lock,
causing possible system disruption (that is, can generate IRQ or
restart the search). To avoid this scenario, symmetrical guard
bands are recommended at each end of the Mu delay range. The
guard band scaling is such that one LSB of Guard[4:0] corresponds to eight LSBs of MUDEL. The recommended guard band
setting of 11 (that is, Register 0x29 = 0xCB) corresponds to 88
LSBs, thus providing sufficient margin.
Figure 82. Mu Delay Controller Block Diagram
Rev. 0 | Page 32 of 44
AD9739A
Mu Controller Initialization Description
The Mu controller must be initialized and placed into track
mode as a first step in the SPI boot sequence. The following
steps are required for initialization of the Mu controller. Note
that the AD9739A data sheet specifications and characterization
data are based on the following Mu controller settings:
1.
2.
3.
4.
5.
Turn on the phase detector with boost (Register 0x24 =
0x30).
Enable the Mu delay controller duty-cycle correction
circuitry and specify the recommended slope for phase.
(that is, Register 0x25 = 0x80 corresponds to a negative
slope).
Specify search/track mode with a recommended target
phase, SET_PHS, of 4 and an initial MUDEL[8:0] setting
of 216 (Register 0x27 = 0x44 and Register 0x28 = 0x6C).
Set search tolerance to exact and retry if the search fails
its initial attempt. Also, set the guard band to the recommended setting of 11 (Register 0x29 = 0xCB).
Set the Mu controller tracking gain to the recommended
setting and enable the Mu controller state machine
(Register 0x26 = 0x03).
Upon completion of the last step, the Mu controller begins a
search algorithm that starts with an initial delay setting specified
by the MUDEL register (that is, 216, which corresponds to the
midpoint of the delay line). The initial search algorithm works
by sweeping through different Mu delay values in an alternating
manner until the desired phase (that is, a SET_PHS of 4) is
exactly measured. When the desired phase is measured, the
slope of the phase measurement is then calculated and
compared against the specified slope (slope = negative).
If everything matches, the search algorithm is finished. If not,
the search continues in both directions until an exact match can
be found or a programmable guard band is reached in one of
the directions. When the guard band is reached, the search still
continues but only in the opposite direction. If the desired
phase is not found before the guard band is reached in the
second direction, the search changes back to the alternating
mode and continues looking within the guard band. The typical
locking time for the Mu controller is approximately 180 K DAC
cycles (at 2 GSPS ~ 75 μs).
The search fails if the Mu delay controller reaches the endpoints. The Mu controller can be configured to retry (Register
0x29, Bit 6) the search or stop. For applications that have a
microcontroller, the preferred approach is to poll the MU_LKD
status bit (Register 0x2A, Bit 0) after the typical locking time
has expired. This method allows the system controller to check
the status of other system parameters (that is, power supplies
and clock source) before reattempting the search (by writing
0x03 to Register 26). For applications not having polling capability, the Mu controller state machine should be reconfigured
to restart the search in hopes that the systems condition that did
not cause locking on the first attempt has disappeared.
Once the Mu delay value is found that exactly matches the
desired Mu phase setting and slope (that is, 4 with a negative.
slope), the Mu controller goes into track mode. In this mode,
the Mu controller makes slight adjustments to the delay value to
track any variations between the two clock paths due to
temperature, time, and supply variations. Two status bits,
MU_LKD (Register 0x2A, Bit 0) and MU_LST (Register 0x2A,
Bit 1) are available to the user to signal the existing status
control loop. If the current phase is more than four steps away
from the desired phase, the MU_LKD bit is cleared, and the
MU_LST bit is set if the lock acquired was previously set.
Should the phase deviation return to within three steps, the
MU_LKD bit is set again while the MU_LST is cleared. Note
that this sort of event may occur if the main clock input (that is,
DACCLK) is disrupted or the Mu controller exceeds the tapped
delay line range (that is, <0 or >432).
If lock is lost, the Mu controller has the option of remaining in
the tracking loop or resetting and starting the search again via
the CONTRST bit (Register 0x29, Bit 5). Continued tracking is
the preferred state because it is the least disruptive to a system
in which the AD9739A temporarily loses lock. The user can
poll the Mu delay and phase value by first setting the read bit
high (Register 0x26, Bit 3). Once the read bit is set, the
MUDEL[8:0] bits and the SET_PHS[4:0] bits (Register 0x27
and Register 0x28) that the controller is currently using can be
read.
INTERRUPT REQUESTS
The AD9739A can provide the host processor with an interrupt
request output signal (IRQ) that indicates that one or more of
the AD9739A internal controllers have achieved lock or lost
lock. These controllers include the Mu, data receiver, and
synchronization controllers. The host can then poll the IRQ
status register (Register 0x04) to determine which controller has
lost lock. The IRQ output signal is an active high output signal
available on Pin F13. If used, its output should be connected via
a 10 kΩ pull-up resistor to VDD33.
Each IRQ is enabled by setting the enable bits in Register 0x03,
which purposely has the same bit mapping as the IRQ status
bits in Register 0x04. Note that these IRQ status bits are set only
when the controller transitions from a false to true state. Hence,
it is possible for the x_LCK_IRQ and x_LST_IRQ status bits to
be set when a controller temporarily loses lock but is able to
reestablish lock before the IRQ is serviced by the host. In this
case, the host should validate the present status of the suspect
controller by reading back its current status bits, which are
available in Register 0x21 and/or Register 0x2A. Based on the
status of these bits, the host can take appropriate action, if
required, to reestablish lock. To clear an IRQ after servicing, it is
necessary to reset relevant bits in Register 0x03 by writing 0
followed by another write of 1 to reenable. A detailed diagram of
the interrupt circuitry is shown in Figure 84.
Rev. 0 | Page 33 of 44
AD9739A
Table 11. Interrupt Request Registers
D
SPI
DATA
Q
INT(n)
Address (Hex)
0x03
(PIN F13) INT
SOURCE
SPI ISR
READ DATA
SPI WRITE
SPI ADDRESS
IMR
DATA = 1
09616-087
INT
SOURCE
SCLK
0x04
Figure 84. Interrupt Request Circuitry
It is also possible to use the IRQ during the AD9739A initialization phase after power-up to determine when the Mu and
data receiver controllers have achieved lock. For example, before
enabling the Mu controller, the MU_LCK_EN bit can be set and
the IRQ output signal monitored to determine when lock has
been established before continuing in a similar manner with the
data receiver controllers. Note that the relevant LCK bit should
be cleared before continuing to the next controller. After all
controllers are locked, the lost lock enable bits (that is,
x_LST_EN) should be set.
0x21
0x2A
Rev. 0 | Page 34 of 44
Bit
3
2
1
0
3
2
1
0
3
1
0
1
0
Description
MU_LST_EN
MU_LCK_EN
RCV_LST_EN
RCV_LCK_EN
MU_LST_IRQ
MU_LCK_IRQ
RCV_LST_IRQ
RCV_LCK_IRQ
RCVR_TRK_ON
RCVR_LST
RCVR_LCK
MU_LST
MU_LKD
AD9739A
ANALOG INTERFACE CONSIDERATIONS
INPUT
DATA
ANALOG MODES OF OPERATION
VDD
DACCLK_x
CLK
VG1
VG2
VG1
LATCHES V 3
G
DBx[13:0]
V G4
VG2 VG3
IOUTP
09616-088
VG4
IOUTN
Figure 85. AD9739A Quad-Switch Architecture
INPUT
DATA
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D6
D7
D8
D9
D10
DACCLK_x
TWO-SWITCH
DAC OUTPUT
D2
D3
D4
D5
D6
D7
D8
D9
D10
DACCLK_x
D3
–D8
D2
FOUR-SWITCH
DAC OUTPUT
(fS MIX MODE)
D4
–D7
D1
D5
–D9
–D10
–D6
t
–D5 D6
–D1
–D2
D10
–D4
D9
D7
–D3
FOUR-SWITCH
DAC OUTPUT
(RETURN TO D
ZERO MODE) 1
D8
D6
D2
D3
D4
D7
D8
D9
D10
t
D5
09616-090
The AD9739A uses the quad-switch architecture shown in
Figure 85. The quad-switch architecture masks the codedependent glitches that occur in a conventional two-switch
DAC. Figure 86 compares the waveforms for a conventional
DAC and the quad-switch DAC. In the two-switch architecture,
a code-dependent glitch occurs each time the DAC switches to
a different state (that is, D1 to D2). This code-dependent
glitching causes an increased amount of distortion in the DAC.
In quad-switch architecture (no matter what the codes are),
there are always two switches transitioning at each half clock
cycle, thus eliminating the code-dependent glitches. However, a
constant glitch occurs at 2 × DACCLK because half the internal
switches change state on the rising DACCLK edge while the
other half change state on the falling DACCLK edge.
D1
Figure 87. Mix-Mode and RZ DAC Waveforms
Figure 87 shows the DAC waveforms for both the mix mode
and the RZ mode. Note that the disadvantage of the RZ mode
is the 6 dB loss of power to the load because the DAC is only
functioning for ½ the DAC update period. This ability to
change modes provides the user the flexibility to place a carrier
anywhere in the first three Nyquist zones, depending on the
operating mode selected. Switching between the analog modes
reshapes the sinc roll-off inherent at the DAC output. The
maximum amplitude in all three Nyquist zones is impacted by
this sinc roll-off, depending on where the carrier is placed (see
Figure 88). As a practical matter, the usable bandwidth in the
third Nyquist zone becomes limited at higher DAC clock rates
(that is, >2 GSPS) when the output bandwidth of DAC core and
the interface network (that is, balun) contributes to additional
roll-off.
FIRST
NYQUIST ZONE
t
SECOND
NYQUIST ZONE
0
THIRD
NYQUIST ZONE
MIX MODE
–5
RZ MODE
D2
D3
D4
D7
D8
D9
D10
D5
t
–10
Figure 86. Two-Switch and Quad-Switch DAC Waveforms
–15
NORMAL
MODE
–20
Another attribute of the quad-switch architecture is that it also
enables the DAC core to operate in one of the following three
modes: normal mode, mix mode, and return-to-zero (RZ )
mode. The mode is selected via SPI Register 0x08, Bits[1:0] with
normal mode being the default value. In the mix mode, the
output is effectively chopped at the DAC sample rate. This has
the effect of reducing the power of the fundamental signal while
increasing the power of the images centered around the DAC
sample rate, thus improving the output power of these images.
The RZ mode is similar to the analog mix mode, except that the
intermediate data samples are replaced with midscale values.
–25
–30
–35
0FS
Rev. 0 | Page 35 of 44
0.25FS
0.50FS
0.75FS
1.00FS
1.25FS
1.50FS
FREQUENCY (Hz)
Figure 88. Sinc Roll-Off for Each Analog Operating Mode
09616-091
D6
09616-089
FOUR-SWITCH
DAC OUTPUT
(NORMAL MODE) D1
AD9739A
CLOCK INPUT CONSIDERATIONS
VCC
VREF
VT
50Ω
50Ω
AD9739A
50Ω
50Ω
D
Q
D
Q
50Ω
10nF
DACCLK_P
100Ω
DACCLK_N
10nF
10nF
09616-092
10nF
50Ω
ADCLK914
VEE
Figure 89. ADCLK914 Interface to the AD9739A CLK Input
ADF4350
1nF
RFOUTA+
PLL
FREF
VCO
AD9739A
3.9nH
VVCO
DIV-BY-2N
N=0–4
DACCLK_P
100Ω
1nF
DACCLK_N
RFOUTA–
1.8V p-p
RFOUTA+
09616-093
RFOUTA–
Figure 90. ADF4350 Interface to the AD9739A CLK Input
VDDC
The quality of the clock source and its drive strength are
important considerations in maintaining the specified ac
performance. The phase noise and spur characteristics of the
clock source should be selected to meet the target application
requirements. Phase noise and spurs at a given frequency offset
on the clock source are directly translated to the output signal.
It can be shown that the phase noise characteristics of a
reconstructed output sine wave are related to the clock source
by 20 × log10(fOUT/fCLK) when the DAC clock path contribution,
along with thermal and quantization effects, are negligible.
The AD9739A clock receiver provides optimum jitter
performance when driven by a fast slew rate originating from
the LVPECL or CML output drivers. For a low jitter sinusoidal
clock source, the ADCLK914 can be used to square-up the
signal and provide a CML input signal for the AD9739A clock
receiver. Note that all specifications and characterization
presented in the data sheet are with the ADCLK914 driven by a
high quality RF signal generator with the clock receiver biased
at a 800 mV level.
Figure 90 shows a clock source based on the ADF4350 low
phase noise/jitter PLL. The ADF4350 can provide output
frequencies from 140 MHz up to 4.4 GHz with jitter as low as
0.5 ps rms. Each single-ended output can provide a squared-up
output level that can be varied from −4 dBm to +5 dBm
allowing for >2 V p-p output differential swings. The ADF4350
also includes an additional CML buffer that can be used to drive
another AD9739A device.
4-BIT PMOS
IOUT ARRAY
CLKx_OFFSET
DIR_x = 0
ESD
CLKx_OFFSET
DIR_x = 0
4-BIT NMOS
IOUT ARRAY
VSSC
09616-094
DACCLK_P
DACCLK_N
Figure 91. Clock Input and Common-Mode Control
The AD9739A clock receiver features the ability to independently adjust the common-mode level of its inputs over a span
of ±100 mV centered about is mid-supply point (that is,
VDDC/2) as well as an offset for hysteresis purposes. Figure 91
shows the equivalent input circuit of one of the inputs. ESD
diodes are not shown for clarity purposes. It has been found
through characterization that the optimum setting is for both
inputs to be biased at approximately 0.8 V. This can be achieved
by writing a 0x0F (corresponding to a −15) setting to both cross
controller registers (that is, Register 0x22 and Register 0x23).
Rev. 0 | Page 36 of 44
AD9739A
1.10
The following equation relates IOUTFS to the FSC[9:0] register,
which can be set from 0 to 1023.
CLKP
CLKN
1.05
IOUTFS = 22.6 × FSC[9:0]/1000 + 8.7
COMMON MODE (V)
1.00
0.90
Note that a default value of 0x200 generates 20 mA full scale,
which is used for most of the characterization presented in this
data sheet (unless noted otherwise).
0.85
ANALOG OUTPUTS
0.80
Equivalent DAC Output and Transfer Function
0.95
0.70
–15 –13 –11 –9 –7 –5 –3 –1
1
3
5
7
9 11 13 15
OFFSET CODE
09616-095
0.75
Figure 92. Common-Mode Voltage with Respect to
CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N
VOLTAGE REFERENCE
The AD9739A provides complementary current outputs,
IOUTP and IOUTN, that source current into an external
ground reference load. Figure 94 shows an equivalent output
circuit for the DAC. Note that, compared to most current
output DACs of this type, the AD9739A outputs exhibit a slight
offset current (that is, IOUTFS/16), and the peak differential ac
current is slightly below IOUTFS/2 (that is, 15/32 × IOUTFS).
IOUTFS = 8.6 – 31.2mA
The AD9739A output current is set by a combination of
digital control bits and the I120 reference current, as shown
in Figure 93.
17/32 × IOUTFS
IPEAK =
15/32 × IOUTFS
AD9739
FSC[9:0]
VBG
1.2V
DAC
IFULL-SCALE
I120
Figure 94. Equivalent DAC Output Circuit
09616-096
CURRENT
SCALING
Figure 93. Voltage Reference Circuit
The reference current is obtained by forcing the band gap
voltage across an external 10 kΩ resistor from I120 (Pin B14) to
ground. The 1.2 V nominal band gap voltage (VREF) generates
a 120 μA reference current in the 10 kΩ resistor. Note the
following constraints when configuring the voltage reference
circuit:
•
•
•
•
2.2pF
17/32 × IOUTFS
+
10kΩ
VSSA
70Ω
–
I120
1nF
AC
09616-097
VREF
•
(1)
Both the 10 kΩ resistor and 1 nF bypass capacitor are
required for proper operation.
Adjusting the DAC’s output full-scale current, IOUTFS, from
its default setting of 20 mA should be performed digitally.
The AD9739A is not a multiplying DAC. Modulating the
reference current, I120, with an ac signal is not supported.
The band gap voltage appearing at the VREF pin must be
buffered for use with an external circuitry because its
output impedance is approximately 5 kΩ.
An external reference can be used to overdrive the internal
reference by connecting it to the VREF pin.
IOUTFS can be adjusted digitally over 8.7 mA to 31.7 mA by using
FSC[9:0] (Register 0x06 and Register 0x07).
As shown in Figure 94, the DAC output can be modeled as a
pair of dc current sources that source a current of 17/32 × IOUTFS
to each output. A differential ac current source, IPEAK, is used to
model the signal-dependent nature of the DAC output. The
polarity and signal dependency of this ac current source are
related to the digital code by the following equation:
F(Code) = (DACCODE − 8192)/8192
(2)
−1 < F(Code) < 1
(3)
where DACCODE = 0 to 16,383 (decimal).
Because IPEAK can swing ±(15/32) × IOUTFS, the output currents
measured at IOUTP and IOUTN can span from IOUTFS/16 to
IOUTFS. However, because the ac signal-dependent current
component is complementary, the sum of the two outputs is
always constant (that is, IOUTP + IOUTN = (34/32) × IOUTFS).
The code-dependent current measured at the IOUTP (and
IOUTN) output is as follows:
IOUTP = 17/32 × IOUTFS + 15/32 × IOUTFS × F(Code)
(4)
IOUTN = 17/32 × IOUTFS − 15/32 × IOUTFS × F(Code)
(5)
Figure 95 shows the IOUTP vs. DACCODE transfer function
when IOUTFS is set to 19.65 mA.
Rev. 0 | Page 37 of 44
AD9739A
20
If the AD9739A is programmed for IOUTFS = 20 mA, its peak ac
current is 9.375 mA and its peak power delivered to the
equivalent load is 2.2 mW (that is, P = I2R). Because the source
and load resistance seen by the 1:1 balun are equal, this power is
shared equally; therefore, the output load receives 1.1 mW or
0.4 dBm.
18
OUTPUT CURRENT (mA)
16
14
12
10
To calculate the rms power delivered to the load, the following
must be considered:
8
6
•
•
•
4
0
0
4096
8192
12,288
16,384
DAC CODE
09616-098
2
For example, a reconstructed sine wave with no digital backoff
ideally measures −2.6 dBm because it has a peak-to-rms ratio of
3 dB. If a typical balun loss of 0.4 dBm is included, −3 dBm of
actual power can be expected in the region where the DAC’s
sinc response has negligible influence. Increasing the output
power is best accomplished by increasing IOUTFS, although any
degradation in linearity performance must be considered
acceptable for the target application.
Figure 95. Gain Curve for FSC[9:0] = 512, DAC OFFSET = 1.228 mA
Peak DAC Output Power Capability
The maximum peak power capability of a differential current
output DAC is dependent on its peak differential ac current,
IPEAK, and the equivalent load resistance it sees. Because the
AD9739A includes a differential 70 Ω resistance, it is best to use
a doubly terminated external output network similar to what is
shown in Figure 97. In this case, the equivalent load seen by the
DAC’s ac current source is 25 Ω.
RSOURCE
= 50Ω
IOUTFS = 8.6 – 31.2mA
AC
70Ω
180Ω
LOSSLESS
BALUN
1:1
RLOAD
= 50Ω
09616-099
IPEAK =
15/32 × IOUTFS
Peak-to-rms of the digital waveform
Any digital backoff from digital full scale
The DAC’s sinc response and nonideal losses in external
network
Figure 96. Equivalent Circuit for Determining Maximum Peak Power
to a 50 Ω Load
Rev. 0 | Page 38 of 44
AD9739A
The AD9739A is intended to serve high dynamic range
applications that require wide signal reconstruction bandwidth
(that is, DOCSIS CMTS) and/or high IF/RF signal generation.
Optimum ac performance can only be realized if the DAC
output is configured for differential (that is, balanced) operation
with its output common-mode voltage biased to analog ground.
The output network used to interface to the DAC should
provide a near 0 Ω dc bias path to analog ground. Any
imbalance in the output impedance between the IOUTP and
IOUTN pins results in asymmetrical signal swings that degrade
the distortion performance (mostly even order) and noise
performance. Component selection and layout are critical in
realizing the AD9739A’s performance potential.
block. The inductors shown serve as RF chokes (L) that provide
the dc bias path to analog ground. The value of the inductor,
along with the dc blocking capacitors (C), determines the lower
cutoff frequency of the composite pass-band response. An RF
balun should also be considered before the RF differential gain
stage and any filtering to ensure symmetrical common-mode
impedance seen by the DAC output while suppressing any
common mode noise, harmonics, and clock spurs prior to
amplification.
OPTIONAL BALUN AND FILTER
IOUTP
L
70Ω
90Ω
LPF
MINI-CIRCUITS®
TC1-33-75G+
L
09616-100
IOUTN
90Ω
Figure 97. Recommended Balun for Wideband Applications with Upper
Bandwidths of up to 2.2 GHz
Most applications requiring balanced-to-unbalanced conversion
can take advantage of the Ruthroff 1:1 balun configuration
shown in Figure 97. This configuration provides excellent
amplitude/phase balance over a wide frequency range while
providing a 0 Ω dc bias path to each DAC output. Also, its
design provides exceptional bandwidth and can be considered
for applications requiring signal reconstruction of up to 2.2 GHz.
The characterization plots shown in this data sheet are based on
the AD9739A evaluation board, which uses this configuration.
Figure 98 compares the measured frequency response for
normal and mix mode using the AD9739A evaluation board vs.
the ideal frequency response.
For applications operating the AD9739A in mix mode with output
frequencies extending beyond 2.2 GHz, the circuits shown in
Figure 100 should be considered. The circuit in Figure 100 uses
a wideband balun with a configuration similar to the one shown
in Figure 99 to provide a dc bias path for the DAC outputs. The
circuit in Figure 101 takes advantage of ceramic chip baluns to
provide a dc bias path for the DAC outputs while providing
excellent amplitude/phase balance over a narrower RF band.
These low cost, low insertion loss baluns are available for
different popular RF bands and provide excellent amplitude/
phase balance over their specified frequency range.
C
IOUTP
90Ω
L
90Ω
L
MINI-CIRCUITS
TC1-1-462M
70Ω
IOUTN
C
09616-103
90Ω
Figure 100. Recommended Mix-Mode Configuration Offering Extended RF
Bandwidth Using a TC1-1-43A+ Balun
MURATA
JOHANSON TECHNOLOGY
CHIP BALUNS
IDEAL BASEBAND MODE
BASEBAND
–6 TC1-33-75G
IOUTP
MIX MODE
TC1-33-75G
–9
RF DIFF
AMP
Figure 99. Interfacing the DAC Output to the Self-Biased Differential
Gain Stage
70Ω
–3
C
IOUTN
IOUTP
0
C
90Ω
09616-102
Output Stage Configuration
70Ω
180Ω
IDEAL MIX MODE
–15
IOUTN
–18
–21
Figure 101. Lowest Cost and Size Configuration for Narrow RF Band
Operation
–24
–27
NONIDEAL SPECTRAL ARTIFACTS
–30
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
3000
3500
09616-101
–33
–36
09616-104
POWER (dBc)
–12
Figure 98. Measured vs. Ideal Frequency Response for Normal (Baseband)
and Mix-Mode Operation Using a TC1-33-75G Transformer on
the AD9739A EVB
Figure 99 shows an interface that can be considered when
interfacing the DAC output to a self-biased differential gain
The AD9739A output spectrum contains spectral artifacts that
are not part of the original digital input waveform. These nonideal artifacts included harmonics (including alias harmonics),
images, and clock spurs. Figure 102 shows a spectral plot of the
AD9739A within the first Nyquist zone (that is, dc to fDAC/2)
reconstructing a 650 MHz, 0 dBFS sine wave at 2.4 GSPS. Besides
the desired fundamental tone at the −7.8 dBm level, the spectrum
also reveals these nonideal artifacts that also appear as spurs
Rev. 0 | Page 39 of 44
AD9739A
above the measurement noise floor. Because these nonideal
artifacts are also evident in the second and third Nyquist zones
during mix-mode operation, the effects of these artifacts should
also be considered when selecting the DAC clock rate for a
target RF band.
4.
0
FUND AT
–7.6dBm
–10
–20
POWER (dBc)
–30
–40
fDAC /2 –
fDAC /4
fOUT
–50
fDAC /4 –
fOUT
–60
–70
3/4 × fDAC /4 –
fOUT
HD3
5.
HD2
HD5
HD6
HD4
HD9
–80
–100
0
200
400
600
800
FREQUENCY (MHz)
1000
1200
09616-105
–90
Figure 102. Spectral Plot
Note the following important observations pertaining to these
nonideal spectral artifacts:
1.
2.
3.
A full-scale sine wave (that is, single-tone) typically
represents the worst case condition because it is has a
peak-to-rms ratio of 3 dB and is unmodulated. Harmonics
and aliased harmonics of a sine wave are easy to identify
because they also appear as discrete spurs. Significant
characterization of a high speed DAC is performed using
single (or multitone) signals for this reason.
Modulated signals (that is, AM, PM, or FM) do not appear
as spurs but rather as signals whose power spectral density
is spread over a defined bandwidth determined by the
modulation parameters of the signals. Any harmonics from
the DAC spread over a wider bandwidth determined by the
order of the harmonic and bandwidth of the modulated
signal. For this reason, harmonics often appear as slight
bumps in the measurement noise floor and can be difficult to
discern.
Images appear as replicas of the original signal, hence, can
be easier to identify. In the case of the AD9739A, internal
modulation of the sampling clock at intervals related to
fDAC/4 generate image pairs at ¼ × fDAC, ½ × fDAC, and ¾ ×
fDAC. Both upper and lower sideband images associated
with ¼ × fDAC fall within the first Nyquist zone, while only
the lower image of ½ × fDAC and ¾ × fDAC fall back. Note
that the lower images appear frequency inverted. The ratio
between the fundamental and various images (that is, dBc)
remains mostly signal independent because the mechanism
causing these images is related to corruption of the
sampling clock.
6.
The magnitude of these images for a given device is
dependent on several factors including DAC clock rate,
output frequency, and Mu controller phase setting. Because
the image magnitude is repeatable between power-up
cycles (assuming the same conditions), a one-time factory
calibration procedure can be used to improve suppression.
Calibration consists of additional dedicated DSP resources
in the host that can generate a replica of the image with
proper amplitude, phase, and frequency scaling to cancel
the image from the DAC. Because the image magnitude
can vary among devices, each device must be calibrated.
A clock spur appears at fDAC/4 and integer multiples of it.
Similar to images, the spur magnitude is also dependent on
the same factors that cause variations in image levels.
However, unlike images and harmonics, clock spurs always
appear as discrete spurs, albeit their magnitude shows a
slight dependency on the digital waveform and output
frequency. The calibration method is similar to image
calibration; however, only a digital tone of equal amplitude
and opposite phase at fDAC/4 need be generated.
A large clock spur also appears at 2 × fDAC in either normal
or mix-mode operation. This clock spur is due to the quad
switch DAC architecture causing switching events to occur
on both edges of fDAC.
LAB EVALUATION OF THE AD9739A
Figure 103 shows a recommended lab setup that was used to
characterize the AD9739A’s performance. The DPG2 is a dual
port LVDS/CMOS data pattern generator available from Analog
Devices, Inc., with an up to 1.25 GSPS data rate. The DPG2
directly interfaces to the AD9739A evaluation board via Tyco
Z-PACK HM-Zd connectors. A low phase noise/jitter RF source
such as an R&S SMA 100A signal generator is used for the DAC
clock. A +5 V power supply is used to power up the AD9739A
evaluation board, and SMA cabling is used to interface to the
supply, clock source, and spectrum analyzer. A USB 2.0
interface to a host PC is used to communicate to both the
AD9739A evaluation board and the DPG2.
A high dynamic range spectrum analyzer is required to evaluate
the AD9739A reconstructed waveform’s ac performance. This is
especially the case when measuring ACLR performance for
high dynamic range applications such as multicarrier DOCSIS
CMTS applications. Harmonic, SFDR, and IMD measurements
pertaining to unmodulated carriers can benefit by using a
sufficiently high RF attenuation setting because these artifacts
are easy to identify above the spectrum analyzer noise floor.
However, reconstructed waveforms having modulated carrier(s)
often benefit from the use of a high dynamic range RF amplifier
and/or passive filters to measure close-in and wideband ACLR
performance when using spectrum analyzers of limited
dynamic range.
Rev. 0 | Page 40 of 44
AD9739A
ADI PATTERN GENERATOR
DPG2
DCO
USB 2.0
provides more detail on the SPI register write/read operations
required to implement the flow chart steps. Note the following:
LAB
PC
•
LVDS
DATA
AND DCI
•
GPIB
1.6GHz TO
2.5GHz
3dBm
AD9739
EVAL. BOARD
POWER
SUPPLY
+5V
10 MHz
REFIN
10 MHz
REOUT
•
•
AGILENT PSA
E4440A
09616-106
RHODE AND
SCHWARTZ
SMA 100A
•
Figure 103. Lab Test Setup Used to Characterize the AD9739A.
A software reset is optional because the AD9739A has both
an internal POR circuit and a RESET pin.
The Mu controller must be first enabled (and in track
mode) before the data receiver controller is enabled
because the DCO output signal is derived from this
circuitry.
A wait period is related to fDATA periods.
Limit the number of attempts to lock the controllers to
three; locks typically occur on the first attempt.
Hardware or software interrupts can be used to monitor
the status of the controllers.
RECOMMENDED START-UP SEQUENCE
Upon power-up of the AD9739A, a host processor is required
to initialize and configure the AD9739A via its SPI port. Figure 104
shows a flow chart of the sequential steps required, while Table 12
CONFIGURE
SPI PORT
CONFIGURE
MU CONT.
NO
CONFIGURE
RX DATA
CONT.
NO
RECONFIGURE
TXDAC FROM
DEFAULT SETTING
SOFTWARE
RESET
WAIT A
FEW 100µs
WAIT A
FEW 100µs
MU CONT.
LOCKED?
RX DATA
CONT.
LOCKED?
YES
YES
OPTIONAL
Figure 104. Flowchart for Initialization and Configuration of the AD9739A
Rev. 0 | Page 41 of 44
09616-107
SET CLK
INPUT CMV
AD9739A
Table 12. Recommended SPI Initialization
Step
1
Address (Hex)
0x00
Write Value
0x00
2
3
4
5
6
7
8
9
10
11
12
13
14
0x00
0x00
0x22
0x23
0x24
0x25
0x27
0x28
0x29
0x26
0x26
0x20
0x00
0x0F
0x0F
0x30
0x80
0x44
0x6C
0xCB
0x02
0x03
15
16
17
18
19
20
21
22
23
0x2A
0x13
0x10
0x10
0x10
0x72
0x00
0x02
0x03
0x21
0x06
0x07
0x08
0x00
0x02
0x00
Comments
Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto
Bits[2:0] because the MSB/LSB format can be unknown at power-up.
Software reset to default SPI values.
Clear the reset bit.
Set the common-mode voltage of DACCLK_P and DACCLK_N inputs
Configure the Mu controller.
Enable the Mu controller search and track mode.
Wait for 160 K × 1/fDATA cycles.
Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop
is locked. If it is not locked, proceed to Step 10 and repeat. Limit attempts to three
before breaking out of the loop and reporting a Mu lock failure.
Ensure that the AD9739A is fed with DCI clock input from the data source.
Set FINE_DEL_SKEW to 2.
Disable the data Rx controller before enabling it.
Enable the data Rx controller for loop and IRQ.
Enable the data Rx controller for search and track mode.
Wait for 135 K × 1/fDATA cycles.
Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop
is locked and tracking. If it is not locked and tracking, proceed to Step 16 and repeat.
Limit attempts to three before breaking out of the loop and reporting an Rx data lock
failure.
Optional: modify the TxDAC IOUTFS setting (the default is 20 mA).
Optional: modify the TxDAC operation mode (the default is normal mode).
Rev. 0 | Page 42 of 44
AD9739A
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
12.10
12.00 SQ
11.90
14
13
12
11
10
9
8
7
6
5
4
3
BALL A1
INDICATOR
10.40
BSC SQ
TOP VIEW
BOTTOM
VIEW
0.80
REF
DETAIL A
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
0.80 BSC
1.40 MAX
DETAIL A
1.00 MAX
0.85 MIN
0.43 MAX
0.25 MIN
SEATING
PLANE
0.12 MAX
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-205-AE.
012006-0
0.55
0.50
0.45
BALL DIAMETER
Figure 105. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-160-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9739ABBCZ
AD9739ABBCZRL
AD9739A-EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
160- Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
Z = RoHs Compliant Part.
Rev. 0 | Page 43 of 44
Package Option
BC-160-1
BC-160-1
AD9739A
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
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