AMICC A49FL004TX-33

A49FL004
4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory
Preliminary
Document Title
4 Mbit CMOS 3.3 Volt-only Firmware Hub/LPC Flash Memory
Revision History
Rev. No.
0.0
PRELIMINARY
History
Issue Date
Initial issue
September 23, 2005
(September, 2005, Version 0.0)
Remark
Preliminary
AMIC Technology, Corp.
A49FL004
4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory
Preliminary
FEATURES
• Single Power Supply Operation
Low voltage range: 3.0 V - 3.6 V
• Standard Intel Firmware Hub/LPC Interface
Read compatible to Intel® 82802 Firmware
Hub devices
Conforms to Intel LPC Interface Specification
Revision 1.1
• Memory Configuration
512K x 8 (4 Mbit)
• Block Architecture
Uniform 4 KBytes Sectors
Uniform 64 KByte overlay blocks
Support full chip erase for Address/Address
Multiplexed (A/A Mux) mode
• Automatic Erase and Program Operation
Build-in automatic program verification for extended
product endurance
Typical 10 µs/byte programming time
Typical x s sector erase time
Typical y s block erase time
Typical z s chip erase time
• Two Configurable Interfaces
In-System hardware interface: Auto detection of
Firmware Hub (FWH) or Low Pin Count (LPC)
Interface for in-system read and write operations
Address/Address Multiplexed (A/A Mux) Interface for
programming on EPROM Programmers during
manufacturing
• Firmware Hub (FWH)/Low Pin Count (LPC) Mode
33 MHz synchronous operation with PCI bus
5-signal communication interface for in-system read
and write operations
PRELIMINARY
(September, 2005, Version 0.0)
-
Standard SDP Command Set
-
Data Polling and Toggle Bit features
Block Locking Register for all blocks
Register-based read and write protection for
each block
4 ID pins for multiple chips selection
5 GPI pins for General Purpose Input Register
-
TBL pin for hardware write protection to Boot Block
-
WP pin for hardware write protection to whole memory
array except Boot Block
• Address/Address Multiplexed (A/A Mux) Mode
11-pin multiplexed address and 8-pin data I/O interface
Supports fast programming on EPROM programmers
Standard SDP Command Set
Data Polling and Toggle Bit features
• Lower Power Consumption
Typical 12mA active read current
Typical 17mA program/erase current
• High Product Endurance
Guarantee 100,000 program/erase cycles per single
sector (preliminary)
Minimum 20 years data retention
• Compatible Pin-out and Packaging
32-pin (8 mm x 14 mm) TSOP
32-pin PLCC
Optional lead-free (Pb-free) package
• Hardware Data Protection
1
AMIC Technology, Corp.
A49FL004
GENERAL DESCRIPTION
The A49FL004 is a 4 Mbit 3.0 Volt-only Flash Memories used
for BIOS storage in PCs and Notebooks. This device is
designed to use a single low voltage, ranging from 3.0 Volt to
3.6 Volt, power supply to perform in-system or off-system
read, erase and program operations. The device conforms to
Intel® Low Pin Count (LPC) Interface specification revision
1.1 and also is compatible with Intel 82802 Firmware Hub
(FWH) for most PC and Notebook applications. The
A49FL004 supports two configurable interfaces: In-system
hardware interface which can automatic detect the FWH or
LPC memory cycle for in-system read and write operations,
and Address/Address Multiplexed (A/A Mux) interface for fast
manufacturing on EPROM Programmers. This device is
designed to work with both Intel Family chipset and Non-Intel
Family Chipset, it will provide PC and Notebook
manufacturers great flexibility and simplicity for design,
procurement, and material inventory.
The program operation of A49FL004 is executed by issuing
the program command code into command register. The
internal control logic automatically handles the programming
voltage ramp-up and timing. The erase operation of the
device is also executed by issuing the sector, block, or chip
erase command code into command register. The internal
control logic automatically handles the erase voltage rampup and timing. The device offer Data Polling and Toggle Bit
functions in FWH/LPC and A/A Mux modes, the progress or
completion of program and erase operation can be detected
by reading the Data Polling on I/O7 or Toggle Bit on I/O6.
The A49FL004 has a 64 KByte top boot block. The boot
block can be write protected by a hardware method
controlled by the TBL pin or a register-based protection
turned on/off by the Block Locking Registers (FWH or LPC
mode only). The rest of blocks except boot block in the
The memory array of A49FL004 is divided into 128 uniform 4
KByte sectors or 8 uniform 64 KByte blocks (sector group consists of sixteen adjacent sectors). The sector or block
erase feature in the A49FL004 allows user to flexibly erase a
memory area as 4Kbyte or 64 KByte by one single erase
operation without affecting the data in others. The chip erase
feature allows the whole memory to be erased in one single
erase operation. The device can be programmed on a byteby-byte basis after performing the erase operation.
PRELIMINARY
(September, 2005, Version 0.0)
device also can be write protected by WP pin or Block
Locking Registers (FWH or LPC mode only).
The A49FL004 is manufactured on AMIC ‘s advanced
nonvolatile technology. The device is offered in 32-pin TSOP
and PLCC packages with optional environmental friendly
lead-free package.
2
AMIC Technology, Corp.
A49FL004
PIN CONFIGURATIONS
CLK
GPI4
R/C
A10
GPI4
VDD
CLK
NC
NC
VDD
RST
RST
VDD
GPI3
GPI3
A9
NC
GPI2
GPI2
A8
RST
FWH
LPC
A/A Mux
Figure 1: 32-Pin PLCC
5
29
IC
IC
IC
GPI0
GPI0
A6
6
28
GND
GND
GND
WP
WP
A5
7
27
NC
NC
NC
8
26
NC
NC
NC
A/A Mux
30
31
A7
32
GPI1
1
GPI1
2
A/A Mux
3
LPC
4
FWH
LPC
FWH
TBL
TBL
A4
ID3
RES
A3
9
25
VDD
VDD
VDD
ID2
RES
A2
10
24
OE
INIT
INIT
ID1
RES
A1
11
23
WE
LFRAME FWH4
ID0
RES
A0
12
22
NC
NC
NC
FWH0
LAD0
I/O0
13
21
I/O7
RES
RES
15
16
17
18
19
20
I/O2
GND
I/O3
I/O4
I/O5
I/O6
LAD2
GND
LAD3
RES
RES
RES
FWH2
GND
FWH3
RES
RES
RES
14
I/01
LAD1
FWH1
A/A Mux
LPC
FWH
32-pin PLCC
Figure 2: 32-Pin TSOP
FWH
VD
D
NC
NC
GND
IC
GPI4
CLK
VD
D
NC
RST
GPI3
GPI2
GPI1
GPI0
WP
TBL
LPC
VD
D
NC
NC
GND
IC
GPI4
CLK
VD
D
NC
RST
GPI3
GPI2
GPI1
GPI0
WP
TBL
PRELIMINARY
A/A Mux
VD
D
NC
NC
GND
IC
A10
R/C
VD
D
NC
RST
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-lead TSOP ( 8 MM X 14 MM )
(September, 2005, Version 0.0)
Top View
3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A/A Mux
OE
WE
VDD
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
LPC
FWH
INIT
LFRAME
N
C
RES
RES
RES
RES
LAD3
GND
LAD2
LAD1
LAD0
RES
RES
RES
RES
INIT
LFRAME
NC
RES
RES
RES
RES
LAD3
GND
LAD2
LAD1
LAD0
RES
RES
RES
RES
AMIC Technology, Corp.
A49FL004
Figure 3: BLOCK DIAGRAM
TBL
Erase/Program Voltage
Generator
WP
INIT
FWH[3:0] or
LAD[3:0]
FWH4 or LFRAME
CLK
FWH/LPC
Mode
Interface
I/O Buffers
High Voltage Switch
GPI[4:0]
A[10:0]
I/O[7:0]
WE
OE
Control Logic
A/A Mode
Data
Latch
Sense
Amp
Interface
R/C
Address
Latch
IC
RST
PRELIMINARY
(September, 2005, Version 0.0)
4
Y-Decoder
X-decoder
Y - Gating
Memory Array
AMIC Technology, Corp.
A49FL004
Table 1: Pin Description
Interface
Symbol
Type
A[10:0]
IN
X
I/O[7:0]
I/O
X
A/A
FWH
Descriptions
LPC
Addresses Inputs: For inputting the multiplex address in A/A Mux mode. Row
and column address are latched during a read or write cycle controlled by R/ C
pin.
Data Inputs/Outputs: Used for A/A Mux mode only, to input command/data
during write operation and to output data during Read operation. The data pins
float to tri-state when OE is high.
Output Enable: Control the device’s output buffers during a read cycle.
OE
IN
X
WE
IN
X
Write Enable: Active the device for write operation. WE is active low.
X
IC
IN
INIT
IN
ID[3:0]
IN
OE is a active low.
X
X
Interface Configuration Select: This pin determines which mode is selected.
When pulls high, the device enters into A/A Mux mode. When pulls low,
FWH/LPC mode is selected. This pin must be setup during power-up or system
reset, and stays no change during operation. This pin is internally pulled down
with a resistor between 20-100 KΩ.
X
X
Initialize: This is the second reset pin for in-system use. INIT and RST pin are
internally combined and initialize a device reset when driven low.
X
These four pins are part of the mechanism that allows multiple FWH devices to
be attached to the same bus. The strapping of these pins is used to identify the
component. The boot device must have ID[3:0]=0000b and it is recommended
that all subsequent devices should use sequential up-count strapping. These
pins are internally pulled-down with a resistor between 20-100 KΩ.
GPI[4:0]
IN
X
X
FWH/LPC General Purpose Inputs: Used to set the GPI_REG for system design
purpose only. The value of GPI_REG can be read through FWH interface. The
state of these pins can be read immediately at boot, through FWH/LPC internal
registers. These pins should be set at desired state before the start of the PCI
clock cycle for read operation and should remain on change until the end of the
Read cycle. Unused GPI pins must not be floated.
TBL
IN
X
X
Top Block Lock: When pulls low, it enables the hardware write protection the
state for top boot block. When pulls high, it disables the hardware write
protection.
FWH[3:0]
I/O
X
CLK
IN
X
FWH4
IN
X
RST
IN
WP
IN
R/ C
IN
LAD[3:0]
I/O
X
LPC Address and Data: The major i/o pins for transmitting data, addresses and
command code in LPC mode.
LFRAME
IN
X
LPC Frame: To indicate the start of a LPC memory cycle operation. Also used to
abort a LPC memory cycle in progress.
X
X
Reserved. Reserved function pins for future use.
X
FWH Address and Data: The major I/O pins for transmitting data, address and
command code in FWH mode.
X
FWH/LPC Clock: To provide a synchronous clock for FWH and LPC mode
operations.
FWH Input: To indicate the start of a FWH memory cycle operation. Also used to
abort a FWH memory cycle in progress.
X
X
Reset: To reset the operation of the device and return to standby mode.
X
X
Write Protect: When pulls low, it enables the hardware write protection to the
memory array except the top boot block. When pulls high, it disables hardware
write protection except the top boot block.
Row/Column Select: To indicate to the row or column address in A/A Mux mode.
When this pin goes low, the row address is latched. When this pin goes high, the
column address is latched.
RES
VDD
X
X
X
Device power supply.
VSS
X
X
X
Ground.
NC
X
X
X
No Connection.
Notes: IN=Input, I/O=Input/Output.
PRELIMINARY
(September, 2005, Version 0.0)
5
AMIC Technology, Corp.
A49FL004
FWH MODE SELECTION
FWH Write Operation
The A49FL004 can operate in two configurable interfaces:
The In-System Hardware interface and Address/Address
Multiplexed (A/A Mux) interface controlled by IC pin. If the IC
pin is set to logic high (VIH), the devices enter into A/A Mux
interface mode. If the IC pin is set logic low (VIL), the device
will be in in-system hardware interface mode. During the insystem hardware interface mode, the device can
automatically detect the Firmware Hub (FWH) or Low Pin
Count (LPC) memory cycle sent from host system and
response to the command accordingly. The IC pin must be
setup during power-up or system reset, and stays no change
during device operation.
FWH Write operations write the FWH Interface or FWH
registers. A valid FWH Write operation starts when FWH4 is
Low as CLK rises and a START value “1110b” is on
FWH[3:0]. Addresses and data are transferred to and from
the device decided by a series of “fields”. Field sequences
and contents are strictly defined for FWH Write operations.
Refer to Table 3 for FWH Write Cycle Definition.
FWH Abort Operation
The FWH4 signal indicates the start of a memory cycle or the
termination of a cycle in FWH mode. Asserting FWH4 for one
or more clock cycle with a valid START value on FWH[3:0]
will initiate a memory read or memory write cycle. If the
FWH4 is driven low again for one or more clock cycles during
this cycle, this cycle will be terminated and the device will
wait for the ABORT command “1111b” to release the
FWH[3:0] bus. If the abort occurs during the program or
erase operation such as checking the operation status with
Data Polling (I/O7) or Toggle Bit (I/O6) pins, the read status
cycle will be aborted but the internal program or erase
operation will not be affected. Only the reset operation
initiated by RST or INIT pin can terminate the program or
erase operation.
When working in-system, typically on a PC or Notebook for
Intel Platform, the A49FL004 enters into the FWH mode
automatically. The device is configured to interface with its
host using Intel’s Firmware Hub proprietary protocol.
Communication between the host (Intel ICH) and the
A49FL004 occurs via the 4-bit I/O communication signal,
FWH[3:0] and FWH4. In A/A Mux mode, the device is
programmed via 11-bit address A[10:0] and 8-pin data
I/O[7:0] interfaces. The address inputs are multiplexed in row
and column selected by column the control signal R/ C . The
column addresses are mapped to the higher internal
addresses, and the row addresses are mapped to the lower
internal addresses.
Response To Invalid Fields
FWH MODE OPERATION
During FWH operations, the device will not explicitly indicate
that it has received invalid field sequences. The response to
specific invalid fields or sequences is as follows:
In FWH mode, the A49FL004 is connected through a 5-pin
communication interface - FWH[3:0] and FWH4 pins to work
with Intel® Family of I/O Controller Hubs (ICH) chipset
platforms. The FWH mode also supports JEDEC standard
Software Data Protection (SDP) product ID entry, byte
program, sector erase, and block erase command
sequences. The chip erase command sequence is only
available in A/A Mux mode.
Address out range: The FWH address sequence is 7 fields
long (28 bits), but only the last five address fields (20 bits)
will be decoded by A49FL004. Address A22 has the special
function of directing reads and writes to the flash memory
(A22=1) or to the register space (A22=0).
The addresses and data are transmitted through the 4-bit
FWH[3:0] bus synchronized with the input clock on CLK pin
during a FWH memory cycle operation. The address or data
on FWH[3:0] bus is latched on the rising edge of the clock.
The device enters standby mode when FWH4 is high and no
internal operation is in progress. The device is in ready mode
when FWH4 is low and no activity is on the bus.
Invalid IMSIZE Field: If the FWH device receives and invalid
size field during a Read or Write operation, the device will
reset and no operation will be attempted. The A49FL004 will
not generate any kind of response in this situation. Invalid
size field for a Read/Write cycles are anything but “0000b”.
FWH Read Operation
FWH Read Operations read from the memory cells or
specific registers in the FWH device. A valid FWH Read
operation starts when FWH4 is Low as CLK rises and a
START value “1101b” is on FWH[3:0]. Addresses and data
are transferred to and from the device decided by a series of
“fields”. Field sequences and contents are strictly defined for
FWH Read Operations. Refer to Table 2 for FWH Read
Cycle definition.
PRELIMINARY
(September, 2005, Version 0.0)
6
AMIC Technology, Corp.
A49FL004
Table 2: FWH Read Cycle
Clock
Cycle
Field
FWH[3:0]
Direction
Descriptions
1
START
1101
IN
Start of Cycle: “1101b” to indicate the start of a memory read
cycle. FWH4 must be active (low) for the part to respond. Only the
last start field (before FWH4 transition high) should be recognized.
The start field contents indicate and FWH read cycle.
2
IDSEL
0000 to 1111
IN
ID Select Cycle: Indicates which FWH device should respond. If
the IDSEL field matches the value set on ID[3:0] pins, then the
particular FWH device will respond to subsequent commands.
3-9
IMADDR
YYYY
IN
Address Cycle: This is the 28-bit memory address. The addressed
transfer most-significant nibble first and least-significant nibble
last. (i.e., a27-24 on FWH[3:0] first, and A3-A0 on FWH[3:0] last).
10
IMSIZE
0000
IN
Memory Size Cycle: Indicates how many bytes will be or
transferred during multi-byte operations. The A49FL004 only
support “0000b” for one byte operation.
11
TAR0
1111
IN
then Float
Turn-Around cycle 0: The master (Intel ICH) has driven the bus to
all”1”s and then float the bus.
12
TAR1
1111
(Float)
Float
then OUT
Turn-Around cycle 1: The device takes control of the bus during
this cycle.
13
RSYNC
0000
(READY)
OUT
Ready Sync: The FWH device indicates the least-significant nibble
of data byte will be ready in next clock cycle.
14-15
DATA
YYYY
OUT
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on
FWH[3:0] first, then I/O7 – I/O4 on FWH[3:0] last).
16
TAR0
1111
OUT
then Float
Turn-Around cycle 0: The FWH device has driven the bus to all
“1”s and then float the bus.
17
TAR1
1111
(Float)
Float
then IN
Turn-Around cycle 1: The master (Intel ICH) resumes control of
the bus during this cycle.
Figure 4: FWH Memory Read Cycle Waveforms
1
2
START
IDSEL
3
4
5
6
7
8
9
10
11
12
13
IMSIZE
TAR0
TAR1
RSYNC
14
15
16
17
TAR0
TAR1
CLK
FWH4
FWH[3:0]
PRELIMINARY
IMADDR
(September, 2005, Version 0.0)
7
DATA
AMIC Technology, Corp.
A49FL004
Table 3: FWH Write Cycle
Clock
Cycle
Field
FWH[3:0]
Direction
Descriptions
1
START
1101
IN
Start of Cycle: “1101b” to indicate the start of a memory write cycle.
FWH4 must be active (low) for the part to respond. Only the last
start field (before FWH4 transitioning high) should be recognized.
The START field contents indicate an FWH write cycle.
2
IDSEL
0000 to 1111
IN
ID Select Cycle: Indicates which FWH device should respond. If the
IDSEL field matches the value set on ID[3:0] pins, then the particular
FWH device will respond to subsequent commands.
3-9
IMADDR
YYYY
IN
Address Cycle: This is the 28-bit memory address. The addressed
transfer most-significant nibble first and least-significant nibble last.
(i.e., a27-24 on FWH[3:0] first, and A3-A0 on FWH[3:0] last).
10
IMSIZE
0000
IN
Memory Size Cycle: Indicates how many bytes will be or transferred
during multi-byte operations. The A49FL004 only supports “0000b”
for one byte operation.
11-12
DATA
YYYY
IN
Data Cycles: The 8-bits data transferred with least-significant nibble
first and most-significant nibble last. (i.e., I/O3 – I/O0 on FWH[3:0]
first, then I/O7 – I/O4 on FWH[3:0] last).
13
TAR0
1111
IN
Turn-Around cycle 0: The master (Intel ICH) has driven the bus to
then Float all”1”s and then float the bus.
14
TAR1
1111
(Float)
Float
Turn-Around cycle 1: The device takes control of the bus during this
then OUT cycle.
15
RSYNC
0000
(Ready)
16
TAR0
1111
17
TAR1
1111
(Float)
Ready Sync: The FWH device indicates that it has received the data
or command.
OUT
OUT
Turn-Around cycle 0: The FWH device has driven the bus to all “1”s
then Float and then float the bus.
Float
then IN
Turn-Around cycle 1: The master (Intel ICH) resumes control of the
bus during this cycle.
Figure 5: FWH Write Waveforms
1
2
START
IDSEL
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
TAR0
TAR1
RSYNC
TAR0
TAR1
CLK
FWH4
FWH[3:0]
PRELIMINARY
IMADDR
(September, 2005, Version 0.0)
IMSIZE
8
DATA
AMIC Technology, Corp.
A49FL004
LPC MODE SELECTION
the rising edge of the clock. The pulse of LFRAME signal
inserted for one or more clocks indicates the start of a LPC
memory read or write cycle.
The A49FL004 can operate in two configurable interfaces:
The In-System Hardware interface and Address/Address
Multiplexed (A/A Mux) interface controlled by IC pin. If the IC
pin is set to logic high (VIH), the devices enter into A/A Mux
interface mode. If the IC pin is set logic low (VIL), the devices
will be in in-system hardware interface mode. During the insystem hardware interface mode, the devices can
automatically detect the Firmware Hub (FWH) or Low Pin
Count (LPC) memory cycle sent from host system and
response to the command accordingly. The IC pin must be
setup during power-up or system reset, and stays no change
during device operation.
Once the LPC memory cycle is started, asserted by
LFRAME , a START value “0000b” is expected by the device
as a valid command cycle.
Then a CYCTYPE + DIR value (“010xb” for memory read
cycle or “011xb” for memory write cycle) is used to indicates
the type of memory cycle. Refer to Table 4 and 5 for LPC
Memory Read and Write Cycle Definition.
There are 8 clock fields in a LPC memory cycle that gives a
32 bit memory address A31 - A0 through LAD[3:0] with the
most-significant nibble first. The memory space of A49FL004
is mapped directly to top of 4 Gbyte system memory space.
See Figure 8 for System Memory Map.
When working in-system, typically on a PC or Notebook for
non Intel Platform, the A49FL004 is connected to the host
system through a 5-pin communication interface operated
based on a 33-MHz synchronous clock. The 5-pin interface is
The A49FL004 is mapped to the address location of
(FFFFFFFFh - FFF80000h), the A31- A19 must be loaded
with “1” to select and activate the device during a LPC
memory operation. Only A18 - A0 is used to decode and
access the 512 KByte memory.
defined as LAD[3:0] and LFRAME pins under LPC mode for
easy understanding as to those existing compatible products.
When working off-system, typically on a EPROM
Programmer, the device is operated through 11-pin
multiplexed address - A[10:0] and 8-pin data I/O - I/O[7:0]
interfaces. The memory addresses of device are input
through two bus cycles as row and column addresses
LPC Abort Operation
controlled by a R/ C pin.
The LFRAME is driven low for one or more clock cycles
during a LPC cycle, the cycle will be terminated and the
device will wait for the ABORT command. The host may drive
the LAD[3:0] with “1111b” (ABORT command) to return the
device to the ready mode. If abort occurs during a Write
operation such as checking the operation status with
Data Polling (I/O7) or Toggle Bit (I/O6) pins, the read status
cycle will be aborted but the internal program or erase
operation will not be affected. In this case, only the reset
operation initiated by RST or INIT pin can terminate the
write operation.
LPC MODE OPERATION
In LPC mode, the A49FL004 is connected through a 5-pin
communication interface - LAD[3:0] and LFRAME pins to
work with non Intel® Family of South Bridge chipset
platforms. The LPC mode also supports JEDEC standard
Software Data Protection (SDP) product ID entry, byte
program, sector erase, and block erase command sequences.
The chip erase command sequence is only available in A/A
Mux mode.
Response TO Invalid Fields
The addresses and data are transmitted through the 4-bit
LAD[3:0] bus synchronized with the input clock on CLK pin
during a LAD memory cycle operation. The address or data
on LAD[3:0] bus is latched on the rising edge of the clock.
During LPC operations, the A49FL004 will not explicitly
indicate that it has received invalid field sequences. The
responses to specific invalid fields or sequence is as follows:
The pulse of LFRAME pin is inserted for one clock indicates
the start of a LPC memory read or memory write cycle. The
address or data on LAD[3:0] is latched on the rising edge of
Address out of range: The A49FL004 will only response to
address range as specified in Table 9. Address A22 has the
special function of directing reads and writes to the flash
memory (A22=1) or to the register space (A22=0).
CLK. The device enters standby mode when LFRAME is
high and no internal operation is in progress. The device is in
ready mode when LFRAME is low and no activity is on the
LPC bus.
ID mismatch: The A49FL004 will compare ID bits in the
address field with the hardware strapping. If there is a
mismatch, the device will ignore the cycle.
LPC Mode Memory Read/Write Operation
In LPC mode, the A49FL004 uses the 5-pin LPC interface
includes 4-bit LAD[3:0] and LFRAME pins to communicate
with the host system. The addresses and data are
transmitted through the 4-bit LAD[3:0] bus synchronized with
the input clock on CLK pin during a LPC memory cycle
operation. The address or data on LAD[3:0] bus is latched on
PRELIMINARY
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AMIC Technology, Corp.
A49FL004
Table 4: LPC Memory Read Cycle Definition
Clock
Cycle
Field
LAD[3:0]
Direction
Descriptions
1
START
0000
IN
Start of Cycle: “0000b” indicates the start of a LPC memory
cycle. LFRAME must be active low (low) for the part to respond.
Only the last field latched before LFRAME transitions high will be
recognized.
2
CYCTYPE
+ DIR
010x
IN
IN
Cycle Type: Indicates the type of a LPC memory read cycle.
CYCTYPE: Bits 3-2 must be “01b” for memory cycle.
DIR: Bit 1 = “0b” indicates the type of cycle for Read. Bit 0 is
reserved.
Address Cycles: This is the 32-bit memory address. The
addressed transfer most-significant nibble first and least-significant
nibble last. (i.e., a31-28 on LAD[3:0] first, and A3-A0 on LAD[3:0]
last).
3-10
ADDR
YYYY
11
TAR0
1111
12
TAR1
1111
(Float)
IN
Then Float
Float
then OUT
13
SYNC
0000
OUT
Sync: The device indicates the least-significant nibble of data byte
will be ready in next clock cycle.
14-15
DATA
1111
OUT
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on
LAD[3:0] first, then I/O7 – I/O4 on LAD[3:0] last).
16
TAR0
1111
IN
then Float
Turn-Around cycle 0: The host has driven the bus to all “1”s and
then float the bus.
17
TAR1
1111
(Float)
Float
then OUT
Turn-Around cycle 1: The A49FL004 resumes control of the bus
during this cycle.
Turn-Around cycle 0: The host has driven the bus to all”1”s and
then float the bus.
Turn-Around cycle 1: The A49FL004 takes control of the bus
during this cycle.
Figure 6: LPC Single-Byte Read Waveforms
1
2
3
4
5
6
7
8
9
10
11
12
13
TAR0
TAR1
SYNC
14
15
16
17
TAR0
TAR1
LCLK
LFRAME
LAD[3:0]
START
ADDRESS
DATA
CYCTYPE +
DIR
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AMIC Technology, Corp.
A49FL004
Table 5: LPC Memory Write Cycle Definition
Clock
Cycle
1
2
Field
LAD[3:0]
START
Direction
Descriptions
IN
Start of Cycle: “0000b” to indicate the start of a LPC memory
cycle. LFRAME must be active low (low) for the part to respond.
Only the last field latched before LFRAME transitions high will be
recognized.
0000
CYCTYPE
+ DIR
011x
IN
Cycle Type: Indicates the type of a LPC memory write cycle.
CYCTYPE: Bits 3-2 must be “01b” for memory cycle.
DIR: Bit 1 = “1b” indicates the type of cycle for Write. Bit 0 is
reserved.
Address Cycles: This is the 32-bit memory address. The
addressed transfer most-significant nibble first and least-significant
nibble last. (i.e., a31-28 on LAD[3:0] first, and A3-A0 on LAD[3:0]
last).
3-10
ADDR
YYYY
IN
11-12
DATA
YYYY
IN
13
TAR0
1111
14
TAR1
1111
(Float)
IN
then Float
Float
then OUT
15
SYNC
0000
OUT
Sync: The device indicates the least-significant nibble of data byte
will be ready in next clock cycle.
16
TAR0
1111
OUT
then Float
Turn-Around cycle 0: The A49FL004 has driven the bus to all “1”s
and then float the bus.
17
TAR1
1111
(Float)
Float
then IN
Turn-Around cycle 1: The host resumes control of the bus during
this cycle.
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on
LAD[3:0] first, then I/O7 – I/O4 on LAD[3:0] last).
Turn-Around cycle 0: The host has driven the bus to all”1”s and
then float the bus.
Turn-Around cycle 1: The A49FL004 takes control of the bus
during this cycle.
Figure 7: LPC Write Waveforms
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
TAR0
TAR1
SYNC
TAR0
TAR1
LCLK
LFRAME
LAD[3:0]
START
ADDRESS
DATA
CYCTYPE
+ DIR
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AMIC Technology, Corp.
A49FL004
Multiple Device Selection
Multiple Device Selection for
LPC Memory Cycle
Multiple A49FL004 devices may be strapped to
increase memory densities in a system. The four ID
pins, ID[3:0], allow up to 16 devices to be attached to
the same bus by using different ID strapping in a
system, BIOS support, bus loading, or the attaching
bridge may limit this number. The boot device must
have an ID of “0000b” (determined by ID[3:0]);
subsequent devices use incremental numbering,
equal density must be used with multiple devices.
For LPC Memory Read/Write cycles, ID information is
included in the address bits of every cycle. The ID
bits in the address field are the reverse of the
hardware strapping. See Table x2 for multiple device
selection configurations. The A49FL004 will compare
these bits with ID[3:0]’s strapping values. If there is a
mismatch, the device will ignore the remainder of the
cycle.
Table 7: LPC
Configuration
Multiple Device Selection for
Firmware Hub Memory Cycle
Device #
0 (Boot Device)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
For Firmware Memory Read/Write cycles, hardware
strapping values on ID[3:0] must match the values in
IDSEL field. See Table x for multiple device selection
configurations. The A49FL004 will compare the
IDSEL field with ID[3:0] ‘s strapping values. If there is
a mismatch, the device will ignore the reminder of the
cycle.
Table 6: FWH
Configuration
Device #
0 (Boot Device)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PRELIMINARY
Multiple
ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Device
Selection
IDSEL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
(September, 2005, Version 0.0)
12
Multiple
ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Device
Selection
Address Range
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
AMIC Technology, Corp.
A49FL004
Table 8: General Purpose Inputs Register
Register
The A49FL004 has two registers include the General
Purpose Inputs Register (GPI_REG) and Block Locking
Register (BL_REG). Both registers are available in FWH
and LPC mode only. The GPI_REG can be read at
FFBC0100h in the 4 GByte system memory map. The
BL_REG can be read through FFBx0002h where x=F-0h.
Refer to table 9 for BL_REG.
General Purpose Inputs Register
The A49FL004 contains and 8-bit General Purpose Inputs
Register (GPI_REG) available in FWH and LPC modes.
Only Bit 4 to Bit 0 are used in the current version, and bit 7
to bit 5 are reserved for the future use. The GPI_REG is a
pass-through register with the value set by GPI[4:0] pin
during power-up. The GPI_REG is used for the system
design purpose only, the device does not use this register.
This register is read only and can be read at address
location FFBC0100h in the 4 Gbyte system memory map
through a memory read cycle. Refer to Table 8 for General
Purpose Input Register Definition.
Bit
Bit
Name
Function
Pin Number
7:5
4
3
2
1
0
GPI[4]
GPI[3]
GPI[2]
GPI[1]
GPI[0]
Reserved
GPI_REG Bit 4
GPI_REG Bit 3
GPI_REG Bit 2
GPI_REG Bit 1
GPI_REG Bit 0
32-PLCC 32-TSOP
30
6
3
11
4
12
5
13
6
14
Block Locking Registers
The A49FL004 supports block read-lock, write-lock, and
lockdown features through a set of Block Locking Registers.
Each memory block has an associated 8-bit read/writable
block locking register. Only Bit 2 to Bit 0 are used in current
version and Bit 7 to Bit 3 are reserved for future use. The
default value of BL_REG is “01h” at power up. The
definition of BL_REG is listed in Table 8. The FWH/LPC
Register Configuration Map of A49FL004 is shown in Table
9.
Unused
register
will
be
read
as
00h
Table 9: A49FL004 Block Locking Register Address
Memory
Address
Mnemonic
Register Name
Protected Block
Address Range
FFBF0002h
T_BLOCK_LK
Top Block Lock Register (Block 64)
70000h – 7FFFFh
FFBE0002h
T_MINUS01_LK
Top Block [-1] Lock Register (Block 64)
60000h – 6FFFFh
FFBD0002h
T_MINUS02_LK
Top Block [-2] Lock Register (Block 64)
50000h – 5FFFFh
FFBC0002h
T_MINUS03_LK
Top Block [-3] Lock Register (Block 64)
40000h – 4FFFFh
FFBB0002h
T_MINUS04_LK
Top Block [-4] Lock Register (Block 64)
30000h – 3FFFFh
FFBA0002h
T_MINUS05_LK
Top Block [-5] Lock Register (Block 64)
20000h – 2FFFFh
FFB90002h
T_MINUS06_LK
Top Block [-6] Lock Register (Block 64)
10000h – 1FFFFh
FFB80002h
T_MINUS07_LK
Top Block [-7] Lock Register (Block 64)
00000h – 0FFFFh
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AMIC Technology, Corp.
A49FL004
Table 10: Block Lock Register Bit Definition
Reserved
Read-Lock
Lock-Down
Write-Lock
Bit 7:3
Bit 2
Bit 1
Bit 0
00h
00000
0
0
0
Full Access.
01h
00000
0
0
1
Write locked. Default state at power-up.
02h
00000
0
1
0
Locked open (full access locked down).
03h
00000
0
1
1
Write-locked down.
04h
00000
1
0
0
Read locked.
05h
00000
1
0
1
Read and Write locked.
06h
00000
1
1
0
Read-locked down
07h
00000
1
1
1
Read-locked and Write-locked down
Data
Data
7:3
Function
Function
Reserved
Read-Lock
2
1 = Prevents read operations in the block where set
0 = Normal operation for reads in the block where clear. This is the default state.
Lock-Down
1 = Prevents further set or clear operations to the Write-Lock and Read-Lock bits. Lock-Down only can be set
1
but not clear. The block will remain lock-down until reset (with RST or INIT ), or until the device
is power-on reset.
0 = Normal operation for Write-Lock and Read-Lock bit altering in the block where clear. This is the default state.
Write-Lock
0
1 = Prevents program or erase operations in the block where set. This is the default state.
0 = Normal operation for programming and erase in the block where clear.
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AMIC Technology, Corp.
A49FL004
ADDRESS/ADDRESS MULTIPLEXED (A/A
MUX) MODE
The 11 multiplex address pins - A[10:0] and a R/ C pin are
used to load the row and column addresses for the target
memory location. The row addresses (internal address A10 -
Read/Write Operation
The A49FL004 offers a Address/Address Multiplexed (A/A
Mux) mode for off-system operation, typically on an EPROM
Programmer, similar to a traditional Flash memory except the
address input is multiplexed. In the A/A Mux mode, the
A0) are latched on the falling edge of R/ C pin. The column
addresses (internal address A21 - A11) are latched on the
programmer must drive the OE pin to low (VIL) for read or
rising edge of R/ C pin. The A49FL004 use A18 - A0
respectively.
WE pins to low for write operation. The devices have no
Chip Enable ( CE ) pin for chip selection and activation as
During a read operation, the OE signal is used to control the
output of data to the 8 I/O pins - I/O[7:0]. During a write
traditional Flash memory. The R/ C , OE and WE pins are
used to activate the device and control the power.
operation, the WE signal is used to latch the input data from
I/O[7:0]. See Table 11 for Bus Operation Modes.
Table 11: A/A Mux Mode Operation Selection
Mode
RST
OE
WE
Address
Read
VIH
VIL
VIH
X (1)
I/O
DOUT
Write
VIH
VIH
VIL
X
DIN
Standby
VIH
VIH
VIH
X
High Z
Output Disable
VIH
VIH
X
X
High Z
Reset
VIL
X
X
X
High Z
A2 – A21 = X, A1 = VIL, A0 = VIL,
Product Identification
VIH
VIL
and
VIH
A1 = VIH, A0 = VIH
A2 – A21= X, A1 = VIL, A0 = VIH
Manufacturer ID (2)
Device ID
Notes:
1. X can be VIL OR VIH.
2. Refer to Table 12 for the Manufacturer ID and Device ID of devices.
The A49FL004 provides three levels of data protection for
the critical BIOS code of PC and Notebook. It includes
memory hardware write protection, hardware data protection
and software data protection.
the six-byte command sequence through six consecutive
write memory cycles with Block Erase Command (50h), and
Block address (BA) in the last bus cycle.
In A/A Mux mode, an erase operation is activated by writing
the six-byte command in six consecutive bus cycles. Preprograms the block is not required prior to an erase operation.
Sector-Erase Operation
The A49FL004 contains 128 uniform 4 KByte sectors. A
sector erase command is used to erase an individual sector.
See Table 11 for Sector/Block Address Table.
Chip-Erase
The entire memory array can be erased by chip erase
operation available under the A/A Mux mode operated by
EPROM Programmer only. Pre-programs the device is not
required prior to the chip erase operation. Chip erase starts
immediately after a six-bus-cycle chip erase command
sequence. All commands will be ignored once the chip erase
operation has started. The Data Polling on I/O7 or Toggle Bit
on I/O6 can be used to detect the progress or completion of
erase operation. The device will return back to standby mode
after the completion of the chip erase.
In FWH/LPC mode, an erase operation is activated by writing
the six-byte command sequence through six consecutive
write memory cycles with Sector Erase Command (30h), and
sector address (SA) in the last bus cycle.
In A/A Mux mode, an erase operation is activated by writing
the six-byte command in six consecutive bus cycles. Preprograms the sector is not required prior to an erase
operation.
Block-Erase Operation
Write Operation Status Detection
The A49FL004 contains eight uniform 64 KByte blocks. A
block erase command is used to erase an individual block.
See Table 13 for Sector/Block Address Table.
In program operation, the data is programmed into the
devices (to a logical “0”) on a byte-by-byte basis. In FWH and
LPC mode, a program operation is activated by writing the
three-byte command sequence and program address/data
In FWH/LPC mode, an erase operation is activated by writing
PRELIMINARY
(September, 2005, Version 0.0)
15
AMIC Technology, Corp.
A49FL004
through four consecutive memory write cycles. In A/A Mux
mode, a program operation is activated by writing the threebyte command sequence and program address/data through
four consecutive bus cycles.
protected. Any attempt to erase or program a sector or block
within this area will be ignored.
The row address (A10 - A0) is latched on the falling edge of
operation. A logic level change on TBL or WP pin during a
program or erase operation may cause unpredictable results.
Both TBL and WP pins must be set low (VIL) for protection
or high (VIH) for un-protection prior to a program or erase
R/ C and the column address (A21 - A11) is latched on the
rising edge of R/ C . The data is latched on the rising edge
The TBL and WP pins work in combination with the block
locking registers. When active, these pins write protect the
appropriate blocks regardless of the associated block locking
registers setting.
of WE . Once the program operation is started, the internal
control logic automatically handles the internal programming
voltages and timing.
A data “0” can not be programmed back to a “1”. Only erase
operation can convert “0”s to “1”s. The Data Polling on I/O7
or Toggle Bit on I/O6 can be used to detect when the
programming operation is completed in FWH, LPC, and A/A
Mux modes.
Hardware Data Protection
Hardware data protection protects the devices from
unintentional erase or program operation. It is performed by
the device automatically in the following three ways:
(a) VDD Detection: if VDD is below 1.8 V (typical), the program
and erase functions are inhibited.
Data Polling (I/O7)
(b) Write Inhibit Mode: holding any of the signal OE low, or
The device provides a Data Polling feature to indicate the
progress or the completion of a program or erase operation
in all modes. During a program operation, an attempt to read
the device will result in the complement of the last loaded
data on I/O7. Once the program cycle is complete, the true
data of the last loaded data is valid on all outputs. During an
erase operation, an attempt to read the device will result a
“0” on I/O7. After the erase cycle is complete, an attempt to
read the device will result a “1” on I/O7.
WE high inhibits a write cycle (A/A Mux mode only).
(c) Noise/Glitch Protection: pulses of less than 5 ns (typical)
on the WE input will not initiate a write cycle (A/A Mux mode
only).
Reset
Any read, program, or erase operation to the devices can be
reset by the INIT or RST pins. INIT and RST pins are
internally hard-wired and have same function to the devices.
The INIT pin is only available in FWH and LPC modes. The
Toggle Bit (I/O6)
The A49FL004 also provides a Toggle Bit feature to detect
the progress or the completion of a program or erase
operation. During a program or erase operation, an attempt
to read data from the devices will result in I/O6 toggling
between “1” and “0”. When the program or erase operation is
complete, I/O6 will stop toggling and valid data will be read.
Toggle bit may be accessed at any time during a program or
erase operation.
RST pin is available in all modes. It is required to drive
INIT or RST pins low during system reset to ensure proper
initialization.
During a memory read operation, pulls low the INIT or RST
pin will reset the devices back to standby mode and then the
FWH[3:0] of FWH interface or the LAD[3:0] of LPC interface
will go to high impedance state. During a program or erase
operation, pulls low the INIT or RST pin will abort the
program or erase operation and reset the devices back to
standby mode. A reset latency will occur before the devices
resume to standby mode when such reset is performed.
When a program or erase operation is reset before the
completion of such operation, the memory contents of
devices may become invalid due to an incomplete program
or erase operation.
Data Protection
The device features a software data protection function to
protect the device from an unintentional erase or program
operation. It is performed by JEDEC standard Software Data
Protection (SDP) command sequences. See Table 14 for
SDP Command Definition. A program operation is initiated by
three memory write cycles of unlock command sequence.
A chip (only available in A/A Mux mode), sector or block
erase operation is initiated by six memory write cycles of
unlock command sequence. During SDP command
sequence, any invalid command or sequence will abort the
operation and force the device back to standby mode.
Product Identification
The product identification mode can be used to read the
Manufacturer ID and the Device ID by a software Product ID
Entry command in both in-system hardware interface and
A/A Mux interface modes. The product identification mode is
activated by three-bus-cycle command. Refer to Table 12 for
the Manufacturer ID and Device ID of A49FL004 and Table
14 for the SDP Command Definition.
Memory Hardware Write Protection
The A49FL004 has a 64 KByte top boot block. When working
in-system, the memory hardware write protection feature can
be activated by two control pins - Top Block Lock ( TBL ) and
Write Protection ( WP ) for both FWH and LPC modes. When
In FWH mode, the product identification can also be read
directly at FFBC0000h for Manufacturer ID - “99h” and
FFBC0001h for Device ID in the 4 GByte system memory
map.
TBL is pulled low (VIL), the boot block is hardware write
protected. A sector erase, block erase, or byte program
command attempts to erase or program the boot block will be
ignored. When WP is pulled low (VIL), the Block 0 ~ Block 6
of A49FL004 (except the boot block) are hardware write
PRELIMINARY
(September, 2005, Version 0.0)
16
AMIC Technology, Corp.
A49FL004
Table 12: Product Identification
Description
Manufacturer ID
Address
Data
00000h
37h
00003h
7Fh
00001h
99h
Device ID
A49FL004
Figure 8: System Memory Map and Device Memory Map for A49FL004
S y s te m M e m o r y
(T o p 4 M B y t e s )
A 49FL004
D e v ic e M e m o r y
07FFFF
FFFFFFFFh
B lo c k 7
(6 4 K B y te s )
TBL
070000
06FFFF
B lo c k 6
(6 4 K B y te s )
060000
05FFFF
B lo c k 5
(6 4 K B y te s )
050000
04FFFF
B lo c k 4
(6 4 K B y te s )
040000
03FFFF
B lo c k 3
(6 4 K B y te s )
WP
fo r B lo c k 6 ~ 0
030000
02FFFF
B lo c k 2
(6 4 K B y te s )
020000
01FFFF
B lo c k 1
(6 4 K B y te s )
010000
00FFFF
B lo c k 0
(6 4 K B y te s )
FFF80000h
000000
R a n g e fo r
A d d itio n a l F W H D e v ic e s
FFC 0000h
PRELIMINARY
(September, 2005, Version 0.0)
17
AMIC Technology, Corp.
A49FL004
Table 13: Sector/Block Address Table
Block Size
Sector
Hardware
Block
(Kbytes)
TBL
Block 7(Boot Block)
WP
PRELIMINARY
64
16
Sector Size
Sector Number
(K bytes)
4 Kbytes/Sector
Address Range
127
7F000h - 7FFFFh
126
7E000h – 7EFFFh
125
7D000h – 7DFFFh
124
7C000h – 7CFFFh
123
7B000h – 7BFFFh
122
7A000h – 7AFFFh
121
79000h – 79FFFh
120
78000h – 78FFFh
119
77000h – 77FFFh
118
76000h – 76FFFh
117
75000h – 75FFFh
116
74000h – 74FFFh
115
73000h - 73FFFh
114
72000h – 72FFFh
113
71000h – 71FFFh
112
70000h - 70FFFh
Block 6
64
16
4 Kbytes/Sector
111 - 96
60000h - 6FFFFh
Block 5
64
16
4 Kbytes/Sector
95 - 80
50000h - 5FFFFh
Block 4
64
16
4 Kbytes/Sector
79 - 64
40000h - 4FFFFh
Block 3
64
16
4 Kbytes/Sector
63 - 48
30000h - 3FFFFh
Block 2
64
16
4 Kbytes/Sector
47 - 32
20000h - 2FFFFh
Block 1
64
16
4 Kbytes/Sector
31 -16
10000h - 1FFFFh
Block 0
64
16
4 Kbytes/Sector
15 - 0
00000h - 0FFFFh
(September, 2005, Version 0.0)
18
AMIC Technology, Corp.
A49FL004
Table 14: Software Data Protection Command Definition
Command
1st Cycle (1)
Bus
Cycles Addr(2) Data
Block Erase
6
5555H
Read
1
Addr
Sector Erase
6
5555H
(1)
6
Byte Program
4
Chip Erase
2nd Cycle
Addr
AAH 2AAAH
Data
3rd Cycle
Addr
Data
4th Cycle
Addr
5th Cycle
Data
Addr
6th Cycle
Data
Addr
Data
(4)
50H
55H
5555H
80H
5555H
AAH 2AAAH
55H
BA
AAH 2AAAH
55H
5555H
80H
5555H
AAH 2AAAH
55H
SA (3)
30H
5555H
AAH 2AAAH
55H
5555H
80H
5555H
AAH 2AAAH
55H
5555H
10H
5555H
AAH 2AAAH
55H
5555H
A0H
Addr
55H
5555H
90H
55H
5555H
F0H
DOUT
Product ID Entry
3
5555H
AAH 2AAAH
Product ID Exit (5)
1
XXXXH
F0H
Product ID Exit (5)
3
5555H
AAH 2AAAH
DIN
Notes:
1. Chip erase is available in A/A Mux Mode only.
2. Address A[15:0] is used for SDP command decoding internally and A15 must be “0” in FWH/LPC and A/A Mux modes.
AMS - A16 = Don’t care where AMS is the most-significant address of A49FL004.
3. SA = Sector address to be erased.
4. BA = Block address to be erased.
5. Either one of the Product ID Exit command can be used.
PRELIMINARY
(September, 2005, Version 0.0)
19
AMIC Technology, Corp.
A49FL004
DC and AC Operating Range
Range
A49FL004
Operating Temperature
0°C to +70°C
VDD Power Supply
3.0V –3.6V
Table 15: DC Operating Characteristics
Limits
Symbol Parameter
Min
VCC Active Read Current
ICC1
(FWH/LPC)
ICC2 (2)
ISB
IRY
VCC Program/Erase Current
Max
Units
2
15
mA
7
20
mA
500
µA
10
mA
100
µA
±1
µA
VIN = 0V to VDD, VDD = VDD Max
VI/O = 0V to VDD, VDD = VDD Max
Standby VCC Current
(FWH/LPC Mode)
Ready Mode VCC Current
(FWH/LPC Mode)
Input Leakage Current for IC,
II
ID[3:0] Pins
ILI
Input Leakage Current
Test Conditions
Typ
FWH4 or LFRAME = VIL, f = 33MHz,
IOUT = 0mA, VDD = VDD Max
FWH4 or LFRAME = VIH, f = 33MHz,
VDD = VDD Max
FWH4 or LFRAME = VIL, f = 33MHz,
IOUT = 0mA, VDD = VDD Max
VIN = 0V to VDD, VDD = VDD Max
ILO
Output Leakage Current
±1
µA
VIH
Input High Voltage
0.7VDD
VDD+0.5
V
VIL
Input Low Voltage
-0.5
0.3VDD
V
0.1VDD
V
IOL= 2.0mA, VDD = VDD Min
V
IOH = -100µA, VDD = VDD Min
VOL
Output Low Voltage
VOH
Output High Voltage
0.9VDD
Notes:
1. Characterized but not 100％ tested.
Table 16: Pin Impedance (VDD=3.3V, T=25°C, f=1MHz)
Parameter
Description
Test Condition
Max
CI/O (1)
I/O Pin Capacitance
VI/O = 0V
12pF
CIN (1)
Input Capacitance
VIN = 0V
12pF
LPIN (2)
Pin Inductance
20nH
Notes:
1. These parameters are characterized but not 100％ tested.
2. Refer to PCI specification.
Table 17: FWH/LPC Interface Clock Characteristics
Symbol
Parameter
Min
Max
Units
tCYC
CLK Cycle Time
30
ns
tHIGH
CLK High Time
11
ns
tLOW
PRELIMINARY
CLK Low Time
11
CLK Slew Rate (peak-to-peak)
1
INIT or RST Slew Rate
50
(September, 2005, Version 0.0)
20
ns
4
V/ns
mV/ns
AMIC Technology, Corp.
A49FL004
Table 18: FWH/LPC Memory Read/Write Operations Characteristics
Parameter
Symbol
Min
Max
Units
tCYC
Clock Cycle Time
30
ns
tSU
Input Set Up Time
7
ns
tH
Input Hold Time
0
tVAL
Clock to Data Out
2
tON
Clock to Active Time (Float to Active Delay)
2
tOFF
Clock to Inactive Time (Active to Float Delay)
ns
11
ns
28
ns
ns
Table 19: FWH/LPC Interface Measurement Condition Parameters
Symbol
Value
Units
VTH4
0.6 VDD
V
VTL1
0.2 VDD
V
VTEST
0.4 VDD
V
VMAX1
0.4 VDD
V
Input Signal Edge Rate
1V/ns
Notes: The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no
more overdrive that this. VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production
testing may use different voltage values, but must correlate results back to these parameters.
Figure 9: Input Timing Parameters
VTH
CLK
VTEST
VTL
TSU
TDH
FWH[3:0] or
LAD[3:0]
(Valid Input Data)
PRELIMINARY
(September, 2005, Version 0.0)
Valid Inputs
21
VMAX
AMIC Technology, Corp.
A49FL004
Figure 10: Output Timing Parameters
V TH
CLK
V TEST
V TL
T VAL
FWH[3:0] or
LAD[3:0]
(Valid Output Data)
FWH[3:0] or
LAD[3:0]
(Float Output Data)
T ON
T OFF
PRELIMINARY
(September, 2005, Version 0.0)
22
AMIC Technology, Corp.
A49FL004
Table 20: FWH/LPC Interface AC Input/Output Characteristics
Symbol
Parameter
Test Conditions
Min
0 < VOUT ≤ 0.3VDD
IOH (AC)
Switching Current High
0.3VDD < VOUT ≤ 0.9VDD
Max
-12 VDD
mA
-17.1(VDD-VOUT)
0.7VDD < VOUT ≤ VDD
(Test Point)
Switching Current Low
ICH
slewr
(2)
slewf (2)
(1)
mA
-32 VDD
0.6VDD > VOUT > 0.1VDD
16VDD
mA
-17.1(VDD – VOUT)
(Test Point)
VOUT=0.18VDD
Low Clamp Current
-3 < VIN ≤ -1
High Clamp Current
VDD+4 > VIN > VDD+1
mA
Equation D (1)
0.18VDD > VOUT > 0
ICL
mA
Equation C
VOUT = 0.7VDD
VDD > VOUT ≥ 0.6VDD
IOL (AC)
Units
mA
38VDD
-25+(VIN+1)/0.015
mA
25+(VIN-VDD-1)/0.015
mA
Output Rise Slew Rate
0.2VDD-0.6VDD load
1
4
V/ns
Output Fall Slew Rate
0.6VDD-0.2VDD load
1
4
V/ns
Max
Units
Notes:
1. See PCI specification.
2. PCI specification output load is used.
Table 21: FWH Mode Interface Reset Timing Parameters, VDD=3.0-3.6V
Symbol
Parameter
Min
tPRST
Reset Active Time to VCC Stable
1
ms
tKRST
Reset Active Time to Clock Stable
100
µs
tRSTP
Reset Pulse Width
100
ns
tRSTF
Reset Active to Output Float Delay
tRST (1)
Reset Inactive Time to Input Active
50
1
ns
ns
Note:
There will be an 10 µs reset latency if a reset procedure is performed during a programming or erase operation.
Figure 11: Reset Timing Diagram
VDD
TPRST
CLK
TKRST
TRSTP
RST / INIT
TRSTF
TRSTE
TRST
Program or Erase
Operation Aborted
FWH[3:0] or
LAD[3:0]
FWH4
PRELIMINARY
(September, 2005, Version 0.0)
23
AMIC Technology, Corp.
A49FL004
Figure 12: A/A Mux Mode AC Input/Output Reference Waveforms
VIHT
INPUT
VIT
Reference Points
VOT
OUTPUT
VILT
AC test inputs are driven at V IHT (0.9VDD) for a logic HIGH and VILT (0.1VDD) for a
logic LOW. Measurement reference points for inputs and outputs are VIT (0.5VDD)
and VOT (0.5VDD). Input rise and fall times (10% <-> 90%) are < 5ns
Note:
V IT: VINPUT Test
V OT: VOUTPUT Test
V IHT: VINPUT HIGH Test
V ILT: VINPUT LOW Test
Figure 13: A/A Mux Mode Test Load Condition
TO TESTER
TO DUT
CL=30pF
PRELIMINARY
(September, 2005, Version 0.0)
24
AMIC Technology, Corp.
A49FL004
A/A MUX MODE AC CHARACTERISTICS
Table 22: A/A Mux Mode Read Operations Characteristics
Parameter
Symbol
Min
Max
Units
tRC
Read Cycle Time
270
ns
tRST
RST High to Row Address Setup Time
1
ms
tAS
R/ C Address Set-up Time
45
ns
tAH
R/ C Address Hold Time
45
tAA
Address to Output Delay
tOE
OE to Output Delay
tDF
OE Output High Z
0
tVCS
VDD Setup Time
50
µs
tOH
Output Hold from OE or Address, whichever occurred first
0
ns
ns
120
ns
50
ns
30
ns
Table 21: A/A Mux Write (Program/Erase) Operations Characteristics
Parameter
Symbol
Min
Max
Units
tRST
RST High to Row Address Setup Time
1
ms
tAS
R/ C Address Setup Time
50
ns
tAH
R/ C Address Hold Time
50
ns
tCWH
R/ C to WE High Time
50
ns
tOES
OE High Setup Time
20
ns
tOEH
OE High Hold Time
20
ns
tWP
Write Pulse Width
100
ns
tWPH
WE Pulse Width High
100
ns
tDS
Data Setup Time
50
ns
tDH
Data Hold Time
5
tBP
Byte Programming Time
tEC
Chip, Sector or Block Erase Cycle Time
tVCS
VDD Setup Time
ns
40
µs
80
ms
µs
50
Figure 14: A/A Mux Mode Read Cycle Timing Diagram
TRSTP
RST
TRST
Address
TRC
Row Address
TAS
TAH
Column Address
TAS
Row Address
Column Address
TAH
R/C
WE
VIH
TAA
TOH
OE
TOE
I/O7-I/O0
PRELIMINARY
TOHZ
TOLZ
High-Z
High-Z
Data Valid
(September, 2005, Version 0.0)
25
AMIC Technology, Corp.
A49FL004
Figure 15: A/A Mux Mode Write Cycle Timing Diagram
TR STP
RS T
TRST
Address
R ow A ddress
TAS
C olumn A ddress
TAH
TAS
TAH
R/C
TCWH
OE
TOES
T OEH
T WP
TWPH
WE
TDS
I/O7 -I/O0
TDH
High-Z
D ata Valid
Figure 16: A/A Mux Mode Data# Polling Timing Diagram
Row
Address
Address
Column
Address
Row
Address
Column
Address
Row
Address
Column
Address
Row
Address
Column
Address
R/C
WE
TOEP
OE
I/O7
High-Z
Data
In
Data#
Data#
Data
Final Input Command
Status Bit
Status Bit
Data
Write Operation In
Progress
Command Input
Write Operation
Complete
Figure 17: A/A Mux Mode Toggle Bit Timing Diagram
Row
Address
Address
Column
Address
Row
Address
Column
Address
Row
Address
Column
Address
Row
Address
Column
Address
R/C
WE
T OET
OE
I/O 6
High-Z
Data
In
Final Input Command
Command Input
PRELIMINARY
(September, 2005, Version 0.0)
Data
Status Bit
Write Operation In
Progress
26
Status Bit
Data
Write Operation
Complete
AMIC Technology, Corp.
A49FL004
Figure 18: A/A Mux Mode Byte Program Timing Diagram
Four-Byte Byte Program Command Sequence
5555
2AAA
5555
PA
Address
R/C
OE
TWP
TWPH
TBP
WE
I/O7-I/O0
High-Z
AA
55
A0
PD
Byte Program Command Input
Byte Program Operation In Progress
PA = Byte Program Address
PD = Byte Program Data
Figure 19: A/A Mux Mode Block Erase Timing Diagram
Six-Byte Block Erase Command Sequence
5555
2AAA
5555
5555
2AAA
BA
Address
R/C
OE
TWP TWPH
TBE
WE
I/O7-I/O0
High-Z
AA
55
80
AA
Block Erase Command Input
55
30/50
Block Erase Operation In Progress
BA = Block Address
PRELIMINARY
(September, 2005, Version 0.0)
27
AMIC Technology, Corp.
A49FL004
Figure 20: A/A Mux Mode Chip Erase Timing Diagram
Six-Byte Chip Erase Command Sequence
5555
2AAA
5555
5555
2AAA
5555
Address
R/C
OE
TWP TWPH
TSCE
WE
I/O7-I/O0
High-Z
AA
55
80
AA
55
10
Chip Erase Command Input
Chip Erase Operation In Progress
Figure 21: A/A Mux Mode Product ID Entry and Read Timing Diagram
Three-Byte Product ID Entry
Command Sequence
5555
2AAA
5555
0000
0001
0003
Address
R/C
OE
TIDA
TWP TWPH
WE
I/O7-I/O0
TAA
High-Z
AA
55
90
37
95
7F
Figure 22: A/A Mux Mode Product ID Exit and Reset Timing Diagram
Three-Byte Product ID Exit and
Reset Command Sequence
5555
2AAA
5555
Address
R/C
OE
TWP TWPH
WE
I/O7-I/O0
High-Z
PRELIMINARY
AA
55
(September, 2005, Version 0.0)
F0
28
AMIC Technology, Corp.
A49FL004
Figure 23: Automatic Byte Program Algorithm
Start
Write Command
Address: 5555H
Data: AAH
Write Command
Address: 2AAAH
Data: 55H
Write Command
Address: 5555H
Data: A0H
Write Command
Address: PA
Data: PD
NO
I/O7 = Data ?
Or
I/O6 Stop Toggle?
YES
Byte Program
Completed
PRELIMINARY
(September, 2005, Version 0.0)
29
PA: Byte Program Address
PD: Byte Program Data
AMIC Technology, Corp.
A49FL004
Figure 24: Automatic Block Erase Algorithm
Start
Write Command
Address: 5555H
Data: AAH
Write Command
Address: 2AAAH
Data: 55H
Write Command
Address: 5555H
Data: 80H
Write Command
Address: 5555H
Data: AAH
NO
I/O7 = Data ?
Or
I/O6 Stop Toggle?
Write Command
Address: 2AAAH
Data: 55H
YES
Write Command
Address: BA
Data: 30H or 50H
Block Erase
Completed
BA: Block Address
PRELIMINARY
(September, 2005, Version 0.0)
30
AMIC Technology, Corp.
A49FL004
Figure 25: Automatic Chip Erase Algorithm
Start
Write Command
Address: 5555H
Data: AAH
Write Command
Address: 2AAAH
Data: 55H
Write Command
Address: 5555H
Data: 80H
Write Command
Address: 5555H
Data: AAH
NO
I/O7 = Data ?
Or
I/O6 Stop Toggle?
Write Command
Address: 2AAAH
Data: 55H
YES
Write Command
Address: 5555H
Data: 10H
PRELIMINARY
(September, 2005, Version 0.0)
Chip Erase
Completed
31
AMIC Technology, Corp.
A49FL004
Figure 26: Product ID Command Flowchart
Start
Start
OR
PRELIMINARY
Write Command
Address: 5555H
Data: AAH
Write Command
Address: 5555H
Data: AAH
Write Command
Address: 2AAAH
Data: 55H
Write Command
Address: 2AAAH
Data: 55H
Write Command
Address: 5555H
Data: 90H
Write Command
Address: 5555H
Data: F0H
Enter
Product ID Mode
Exit
Product ID Mode
(September, 2005, Version 0.0)
32
Write Command
Address: XXXXH
Data: F0H
AMIC Technology, Corp.
A49FL004
Ordering Information
A49FL004T x - 33 C
Temperature Range
C = Commercial (0°C to +85°C)
Clock Frequency
33 = 33MHz
Package Type
L = PLCC
X = TSOP (8mmX14mm)
Device Number
4 Mbit FWH Flash Memory
Boot Block
Location
Temperature
Range
Package Type
A49FL004TL-33
Top
0°C to +85°C
32-pin PLCC
A49FL004TL-33F
Top
0°C to +85°C
32-pin Pb-Free PLCC
A49FL004TX-33
Top
0°C to +85°C
32-pin TSOP
(8mm X 14 mm)
A49FL004TX-33F
Top
0°C to +85°C
32-pin Pb-Free TSOP
(8mm X 14 mm)
Part No.
Clock Frequency
(MHz)
33
PRELIMINARY
(September, 2005, Version 0.0)
33
AMIC Technology, Corp.
A49FL004
Package Information
unit: inches/mm
PLCC 32L Outline Dimension
HD
D
13
5
1
E
4
HE
14
32
20
30
29
c
L
A1
b
e
A
A2
21
D
b1
GD
GE
y
θ
Dimensions in inches
Symbol
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.134
-
-
3.40
A1
0.0185
-
-
0.47
-
-
A2
0.105
0.110
0.115
2.67
2.80
2.93
b1
0.026
0.028
0.032
0.66
0.71
0.81
b
0.016
0.018
0.021
0.41
0.46
0.54
C
0.008
0.010
0.014
0.20
0.254
0.35
D
0.547
0.550
0.553
13.89
13.97
14.05
E
0.447
0.450
0.453
11.35
11.43
11.51
e
0.044
0.050
0.056
1.12
1.27
1.42
GD
0.490
0.510
0.530
12.45
12.95
13.46
GE
0.390
0.410
0.430
9.91
10.41
10.92
HD
0.585
0.590
0.595
14.86
14.99
15.11
HE
0.485
0.490
0.495
12.32
12.45
12.57
L
0.075
0.090
0.095
1.91
2.29
2.41
y
-
-
0.003
-
-
0.075
θ
0°
-
10°
0°
-
10°
Notes:
1. Dimensions D and E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
PRELIMINARY
(September, 2005, Version 0.0)
34
AMIC Technology, Corp.
A49FL004
Package Information
unit: inches/mm
TSOP 32L TYPE I (8 X 14mm) Outline Dimensions
c
E
A
A2
0.254
Pin1
Gage Plane
A1
θ
L
D1
Detail "A"
D
Detail "A"
b
D
e
Dimensions in inches
Symbol
Min
Nom
Max
y
Dimensions in mm
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.041
0.95
1.00
1.05
b
0.0067
0.0087
0.0106
0.17
0.22
0.27
c
0.004
-
0.0083
0.10
-
0.21
E
0.311
0.315
0.319
7.90
8.00
8.10
e
-
0.0197
-
-
0.50
-
D
0.543
0.551
0.559
13.80
14.00
14.20
D1
0.484
0.488
0.492
12.30
12.40
12.50
L
0.020
0.024
0.028
0.50
0.60
0.70
y
0.000
-
0.003
0.00
-
0.076
θ
0°
3°
5°
0°
3°
5°
Notes:
1. Dimension E does not include mold flash.
2. Dimension D1 does not include interlead flash.
2. Dimension b does not include dambar protrusion.
PRELIMINARY
(September, 2005, Version 0.0)
35
AMIC Technology, Corp.