LTC1456 12-Bit Rail-to-Rail Micropower DAC with Clear Input U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1456 is a complete single supply, rail-to-rail voltage output, 12-bit digital-to-analog converter (DAC) in an SO-8 package. It includes a rail-to-rail output buffer amplifier and an easy-to-use 3-wire cascadable serial interface. The LTC1456 includes a CLR pin that asynchronously clears the DAC to zero scale. SO-8 Package 12-Bit Resolution Buffered True Rail-to-Rail Voltage Output Asynchronous Clear Input Built-In Reference Schmitt Trigger On Clock Input Allows Direct Optocoupler Interface Power-On Reset Clears DAC to 0V 3-Wire Cascadable Serial Interface Maximum DNL Error: 0.5LSB Low Cost The LTC1456 has an internal 2.048V reference and a fullscale output of 4.095V. It operates on a 4.5V to 5.5V supply, dissipating 2.2mW. The low power supply current and the space saving SO-8 package make the LTC1456 ideal for battery-powered applications. U APPLICATIONS ■ ■ ■ ■ , LTC and LT are registered trademarks of Linear Technology Corporation. Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones U TYPICAL APPLICATION Functional Block Diagram: 12-Bit Rail-to-Rail DAC with Clear Input VCC 2 DIN 4.5V TO 5.5V 0.5 2.048V 1 CLK µP 3 CS/LD + 12-BIT SHIFT REG AND DAC LATCH 12-BIT DAC – VOUT 7 RAIL-TO-RAIL VOLTAGE OUTPUT DNL ERROR (LSB) 8 Differential Nonlinearity vs Input Code 0 4 DOUT TO OTHER DACS 6 CLR POWER-ON RESET –0.5 GND 5 0 1456 TA01 512 1024 1536 2048 2560 3072 3584 4095 CODE 1456 TA02 1 LTC1456 W U U W W W VCC to GND .............................................. – 0.5V to 7.5V Logic Inputs to GND ................................ – 0.5V to 7.5V VOUT .............................................. – 0.5V to VCC + 0.5V Maximum Junction Temperature ......... – 65°C to 125°C Operating Temperature Range LTC1456C ............................................ 0°C to 70°C LTC1456I ........................................ – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW CLK 1 8 VCC DIN 2 7 VOUT CS/LD 3 6 CLR DOUT 4 5 GND N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO LTC1456CN8 LTC1456IN8 LTC1456CS8 LTC1456IS8 S8 PART MARKING TJMAX = 125°C, θJA = 100°C/W (N8) TJMAX = 125°C, θJA = 150°C/W (S8) 1456 1456I Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VCC = 4.5V to 5.5V, VOUT unloaded, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DAC Resolution ● 12 Bits DNL Differential Nonlinearity Guaranteed Monotonic (Note 1) ● ±0.5 LSB INL Integral Nonlinearity TA = 25°C (Note 1) ● ±3.5 ±4 LSB LSB ● ±12 ±18 mV mV VOS Offset Error VOSTC Offset Error Temperature Coefficient VFS Full-Scale Voltage TA = 25°C ±15 TA = 25°C ● VFSTC 4.065 4.045 4.095 4.095 µV/°C 4.125 4.145 ± 24 Full-Scale Voltage Temperature Coefficient V V ppm/°C Power Supply VCC Positive Supply Voltage For Specified Performance ● ICC Supply Current (Note 4) ● Short-Circuit Current Low VOUT Shorted to GND Short-Circuit Current High Output Impedance to GND 4.5 5.5 V 650 µA ● 120 mA VOUT Shorted to VCC ● 120 mA Input Code = 0 ● 120 Ω Voltage Output Slew Rate (Note 2) ● Voltage Output Settling Time (Notes 2, 3) to ±0.5LSB 430 Op Amp DC Performance 40 AC Performance Digital Feedthrough 2 0.4 1.0 V/µs 14 µs 0.3 nV • s LTC1456 ELECTRICAL CHARACTERISTICS VCC = 4.5V to 5.5V, VOUT unloaded, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.8 V Digital I/O VIH Digital Input High Voltage ● VIL Digital Input Low Voltage ● VOH Digital Output High Voltage VOL ILEAK CIN 2.4 V IOUT = – 1mA, DOUT Only ● VCC – 1.0 V Digital Output Low Voltage IOUT = 1mA, DOUT Only ● 0.4 V Digital Input Leakage VCC = 5V, VIN = GND to VCC ● ±10 µA Digital Input Capacitance Guaranteed by Design. Not Subject to Test. ● 10 pF Switching t1 DIN Valid to CLK Setup ● 40 ns t2 DIN Valid to CLK Hold ● 0 ns t3 CLK High Time ● 40 ns t4 CLK Low Time ● 40 ns t5 CS/LD Pulse Width ● 50 ns t6 LSB CLK to CS/LD ● 40 ns t7 CS/LD Low to CLK ● 20 ns t8 DOUT Output Delay t9 CLK Low to CS/LD Low ● 20 ns t10 CLR Pulse Width ● 65 ns CLOAD = 15pF, VCC = 5V The ● denotes specifications which apply over the full operating temperature range. Note 1: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 4095 (full scale). Note 2: Load is 5kΩ in parallel with 100pF. 150 ● ns Note 3: DAC switched between all 1s and the code corresponding to VOS for the part. Note 4: Digital inputs at 0V or VCC. 3 LTC1456 U W TYPICAL PERFORMANCE CHARACTERISTICS Differential Nonlinearity (DNL) 0.5 2.0 0.4 1.6 1.4 0 – 0.1 – 0.2 VCC – VOUT (V) 0.1 1.0 0.8 INL ERROR (LSB) 0.2 0.4 0 – 0.4 – 0.8 – 0.3 –1.2 – 0.4 –1.6 0 0 512 1024 1536 2048 2560 3072 3584 4095 CODE 125°C Output Swing vs Load Resistance CODE: ALL 0s ALL DIGITAL INPUTS TIED TOGETHER 1.615 600 4.0 25°C – 55°C 200 100 1.210 1.075 0.940 0.805 0 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 LOGIC INPUT VOLTAGE (V) Offset Voltage vs Temperature Supply Current vs Temperature 550 CODE: ALL 1s 540 4.0 0.8 3.0 2.5 2.0 1.5 RL 530 SUPPLY CURRENT (µA) OFFSET VOLTAGE (mV) 3.5 0.7 0.6 0.5 520 510 500 0.4 480 460 0 10k 1456 G07 0.3 – 55 VCC = 5.5V 490 VCC = 5V 470 0.5 100 1k LOAD RESISTANCE (Ω) 10k 1456 G06 0.9 10 100 1k LOAD RESISTANCE (Ω) 10 4.5 5 1456 G05 Output Swing vs Load Resistance OUTPUT SWING (V) 1.5 0.5 4.5 4 2.0 0.535 1456 G04 1.0 RL 2.5 1.0 8 10 12 14 16 18 20 4 6 OUTPUT SINK CURRENT (mA) VCC 3.0 0.670 0.400 0 3.5 1.345 OUTPUT SWING (V) SUPPLY CURRENT (mA) 1.480 400 30 25 4.5 1.750 700 500 20 15 10 LOAD CURRENT (mA) 5 1456 G03 Supply Current vs Logic Input Voltage Minimum Output Voltage vs Output Sink Current OUTPUT PULL-DOWN VOLTAGE (mV) 0 1456 G02 1456 G01 300 0.6 0.2 0 512 1024 1536 2048 2560 3072 3584 4095 CODE 0.8 0.4 – 2.0 – 0.5 ∆VOUT < 1LSB CODE: ALL 1s VOUT = 4.095V 1.2 1.2 0.3 DNL (LSB) Minimum Supply Headroom for Full Output Swing vs Load Current Integral Nonlinearity (INL) – 25 5 35 65 TEMPERATURE (°C) 95 125 1456 G08 450 – 55 VCC = 4.5V – 25 35 65 5 TEMPERATURE (°C) 95 125 1456 G09 LTC1456 U U U PIN FUNCTIONS CLK (Pin 1): The Serial Interface Clock. Internal Schmitt trigger on this input allows direct optocoupler interface. DOUT (Pin 4): The Output of the Shift Register Which Becomes Valid on the Rising Edge of the Serial Clock. DIN (Pin 2): The Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. GND (Pin 5): Ground. CS/LD (Pin 3): The Serial Interface Enable and Load Control. When CS/LD is low the CLK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. When CS/LD is high the CLK is disabled internally. CLR (Pin 6): The Clear Input. When pulled low, this pin asynchronously clears the internal shift and DAC registers to zero scale. Should be tied high for normal operation. VOUT (Pin 7): The Buffered DAC Output. VCC (Pin 8): The Positive Supply Input. 4.5V ≤ VCC ≤ 5.5V. Requires a bypass capacitor to ground. W BLOCK DIAGRA CLK 1 8 VCC 2.048V LD DIN 2 12-BIT SHIFT REGISTER 12-BIT DAC DAC REGISTER + 7 VOUT – CS/LD 3 POWER-ON RESET 6 CLR DOUT 4 5 GND 1146 BD WU W TI I G DIAGRA t1 t2 t6 CLK t4 t7 t3 t9 DIN B11 MSB B0 PREVIOUS WORD CS/LD DOUT B0 LSB B1 B10 t8 B11 PREVIOUS WORD B10 t5 B1 B0 B11 CURRENT WORD 1456 TD 5 LTC1456 U U DEFI ITIO S Resolution (n): Resolution is defined as the number of digital input bits, n. It defines the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Voltage Offset Error (VOS): The theoretical voltage at the output when the DAC is loaded with all zeros. The output amplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below zero. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 1. The offset of the part is measured at the code that corresponds to the maximum offset specification: VOS = VOUT – [(Code • VFS)/(2n – 1)] Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the end-points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below zero, the linearity is measured between full scale and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated as follows: INL = [VOUT – VOS – (VFS – VOS)(code/4095)]/LSB VOUT = The output voltage of the DAC measured at the given input code Differential Nonlinearity (DNL): DNL is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆VOUT – LSB)/LSB ∆VOUT = The measured voltage difference between two adjacent codes Least Significant Bit (LSB): One LSB is the ideal voltage difference between two successive codes. LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/4095 LSB = 4.095/4095 = 1mV Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). OUTPUT VOLTAGE NEGATIVE OFFSET 0V DAC CODE 1456 F01 Figure 1. Effect of Negative Offset 6 LTC1456 U OPERATIO Serial Interface The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first. The DAC register loads the data from the shift register when CS/LD is pulled high. The CLK is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. When CLR is pulled low it asynchronously resets the shift and DAC registers to all zeros. The buffered output of the 12-bit shift register is available on the DOUT pin which swings from GND to VCC. Multiple LTC1456s may be daisy-chained together by connecting the DOUT pin to the DIN pin of the next chip, while the CLK and CS/LD signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all of them simultaneously. Voltage Output The LTC1456's rail-to-rail buffered output can source or sink 5mA over the entire operating temperature range while pulling to within 300mV of the positive supply voltage or ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40Ω when driving a load to the rails. The output can drive 1000pF without going into oscillation. U TYPICAL APPLICATION 12-Bit 5V Single Supply Voltage Output DAC The circuit below shows a digitally programmable current source from an external voltage source using an external op amp, an LT ®1077 and an NPN transistor (2N3440). Any digital word from 0 to 4095 is loaded into the LTC1456 and its output correspondingly swings from 0V to 4.095V. In the configuration shown, this voltage will be forced across the resistor RA. If RA is chosen to be 410Ω the output current will range from 0mA at zero scale to 10mA at full scale. The minimum voltage for VS is determined by the load resistor RL and Q1’s VCESAT voltage. With a load resistor of 50Ω, the voltage source can be as low as 5V. 4.5V TO 5.5V 0.1µF VCC DIN CLK µP LTC1456 VOUT CS/LD DOUT CLR OUTPUT 0V TO 4.095V GND TO NEXT DAC FOR DAISY-CHAINING 1456 TA03 Digitally Programmable Current Source 5V VS + 5V TO 100V FOR RL ≤ 50Ω 0.1µF CLR µP CLK VCC LTC1456 VOUT + DIN CS/LD LT1077 GND D • 4.095 IOUT = IN ≈ 0mA TO 10mA 4096 • RA RL Q1 2N3440 – RA 410Ω 1456 TA04 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7 LTC1456 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.025 0.325 –0.015 +0.635 8.255 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.400* (10.160) MAX 0.130 ± 0.005 (3.302 ± 0.127) 0.065 (1.651) TYP 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.125 (3.175) MIN 0.005 (0.127) MIN 0.018 ± 0.003 0.100 ± 0.010 (0.457 ± 0.076) (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 0.015 (0.380) MIN N8 0695 S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 8 0.004 – 0.010 (0.101 – 0.254) 7 6 5 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.050 (1.270) BSC 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) SO8 0695 1 2 3 4 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1257 Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1450/LTC1450L Single 12-Bit VOUT DACs with Parallel Interface LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1451 Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Same as LTC1456 Except REF Out Pin Replaces CLR Pin LTC1452 Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package LTC1453 Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454/LTC1454L Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com 1456fs, sn1456 LT/TP 0697 7K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1996