T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8101C The TQ8101C meets ANSI, Bellcore, and ITU requirements for a SONET/ SDH device. With a 51.84-MHz reference clock, the phase-locked loop (PLL) provides 77.76-MHz or 19.44-MHz output for the multiplexer and 77.76-MHz or 19.44-MHz and 51.84-MHz output for the demultiplexer. Typical SONET/SDH system applications for the TQ8101C include: • • • • • • Transmission system transport cards Switch and cross-connect line cards Repeaters ATM physical layer interfaces Test equipment Add/drop multiplexers TOUT(7:0) 8-bit data VEE DXDT(7:0) OHFP OOF OOF fix* OOF TCLK MXCK0 RIFP DXSYNC RICLK 600 Ω 0.68 µF MXDT(7:0) 8-bit data Driver and LASER OC-3 or OC-12 O/E Rx + TQ8103 CDR OC-3 or OC-12 • Choice of STS-12/STM-4 or STS-3/STM-1 transmission rates • Configurable master or slave reference clock generation and PLL bypass for external clocking • 77.76 MHz or 19.44 MHz output for the multiplexer; 77.76 MHz or 19.44 MHz and 51.84 MHz output for the demultiplexer • Frame-synchronous and bytealigned demultiplexer output, compliant with SONET and SDH • Search, detect, and recovery of framing on out-of-frame input • Standard TTL and differential or single-ended ECL I/O (except TXCK) • Tristate TTL output for factory circuit-board testability • 68-pin TriQuint MLC controlled-Z surface-mount package with integral heat spreader DXCK CNTL(3:0) 51.84 MHz CMOS OSC *Contact PMC-Sierra for application note. • Byte-wide Multiplexing, Demultiplexing, Framing, and PLL (MDFP) in one device • Pass-through mode and three loopback modes for enhanced filed diagnostics TQ8101C MDFP RIN(7:0) Features • External RC loop filter Figure 1. Logical Application PM5312 or PM5355 STTX S/UNI-622 622/155 Mb/s SONET/SDH MDFP TELECOM PRODUCTS The TQ8101C is a SONET/SDH transceiver that integrates Multiplexing, Demultiplexing, SONET/SDH Framing, clock synthesis PLL (MDFP), and loopback functions in a single monolithic integrated circuit. Implementation with the TQ8101C requires only a simple external RC loop filter and standard TTL and ECL power supplies. For optimal performance, the TQ8101C MDFP is packaged in a 68-pin multilayer ceramic (MLC) surface-mount package with an integral CuW heat spreader. The TQ8101C provides an integrated solution for physical interfaces intended for use in STS-12/STM-4 (622.08-Mb/s) and STS-3/STM-1 (155.52-Mb/s) SONET/SDH systems. • Dual-supply operation (+5V, –5.2V) • Low power dissipation (2.3W nom.) For additional information and latest specifications, see our website: www.triquint.com 1 TQ8101C Figure 2. TQ8101C Block Diagram MXDT(7:0) Mux 2 TXDT TXCK CNTL(3:0) MO Control Block Loopback Block Serial-to-Parallel Converter TUNE PLL Clock Synthesizer IOUT RXDT 2 RXCK Mux MXCK(2:0) MXHC 2 +5V GND –5.2V Framer 2 MXLRC DXSYNC DXRCK DXCK DXDT(7:0) Demux OOF Figure 3. TQ8101C Package—68-pin MLC 1.170 ± .006 .950 ± .010 .800 4 plcs Pin 1 index 1 2 3 4 A A .950 Ceramic or metal lid ± .010 .050 n-4 plcs .016 n plcs Chip capacitor CuW heat spreader 4 plcs TOP VIEW BOTTOM VIEW .060 ± .005 .650 ± .005 .125 .050 SECTION A 2 A For additional information and latest specifications, see our website: www.triquint.com TQ8101C Multiplexing Byte-wide input data on MXDT(7:0)1 is continuously strobed into the multiplexer on the rising edge of the multiplexer clock output, MXCK(2:0).2 Any of these three MXCK pins may be used as a reference point for relative timing. (See Table␣ 8 for setup, hold, and skew times. See Table␣ 1 for clock selection options.) Either an on-chip synthesized clock (see “PLL Clock Synthesis”) or an external high-speed multiplexer Demultiplexing As shown in Figure 4, The demultiplexer block converts incoming serial data on DXDTIN3. Byte-wide output data is presented on DXDT(7:0)4 slightly after the falling edge of the output demultiplexer clock, DXCK. (See Table␣ 8 for setup, hold, and skew times.) The demultiplexer block also includes clock divider circuitry, which is used by the demultiplexer to control divide-by-8 output on DXCK. The MDFP provides a divide-by-3 or divide-by-12 output, DXRCK. (See Table 1 for mode selection options.) Figure 4. Demultiplexer Functional Block DXDTIN DXHSCK Shift Register XFD Parallel Register Frame Detection and Recovery OOF DXSYNC 1/8 1/2 1/3 DXDT(7:0) DXCK 1/2 Mux DXRCK 1/3 RT Notes: 1. MXDT(0) is defined as the least significant bit. 2. MXCK(2:0) nominally runs at 77.76 MHz in STS-12/STM-4 mode, and at 19.44 MHz in STS-3/STM-1 mode. 3. Internal signal. See Figure 5, "TQ8101C Loopback Modes." 4. DXDT (0) is defined as the least significant bit. For additional information and latest specifications, see our website: www.triquint.com 3 PRODUCTS Figure 2 shows a block diagram of the TQ8101C multiplexer, demultiplexer, framer, and PLL clock synthesizer (MDFP). The primary purpose of TQ8101C is to integrate the conversion of serial and parallel SONET/SDH data with bit alignment and clock synthesis in a single device. clock, MXHC, serializes the input data bytes. In the normal mode of operation, the serial data is then buffered as ECL-compatible output on TXDT. An ECL output is provided for the transmit clock, TXCK. SONET/SDH/ATM TELECOM Functional Description TQ8101C Framing PLL Clock Synthesis The demultiplexer block (see Figure 2) includes a frame-detection and recovery block. Regardless of the state of the OOF input signal, this block takes DXSYNC high for one period of DXCK whenever it detects a pattern of three “A1” bytes followed by three “A2” bytes. The PLL utilizes a monolithic voltage-controlled oscillator with a typical tuning constant of 50 to 100 MHz per volt on the TUNE input. This configuration provides jitter performance superior to other technologies. In a typical SONET/SDH application the TUNE input and charge pump output IOUT are connected and tied to VEE through a 600-ohm resistor and 0.68-µF capacitor. Frame recovery is initiated by the rising edge of the OOF input signal. The recovery process involves a search for a bit rotation that satisfies the three-“A1”– three-“A2” byte pattern specified for SONET/SDH. Once the pattern is found, DXSYNC goes high and the bit rotation is synchronized to the correct byte boundaries. No further byte boundary adjustments are made, regardless of “A1”-“A2” indication, unless they have been preceded by an OOF rising edge. Loopback The TQ8101C features four loopback modes: normal (pass-through), equipment loopback, split loopback, and facility loopback. Loopback modes are controlled by pins CNTL(3:0). Note␣ that the loopback mode does not affect the latched selection of clock modes and rates. Note that the RXCK input is␣ directly connected to the TXCK output in most loopback modes (see below). Figure 5. TQ8101C Loopback Modes Normal Equipment Loopback RXDT DXDTIN DXDTIN RXCK DXHSCK DXHSCK TXDT MXDTOUT TXDT MXDTOUT TXCK MXHSCK TXCK MXHSCK Split Loopback 4 Facility Loopback RXDT DXDTIN RXDT DXDTIN RXCK DXHSCK RXCK DXHSCK TXDT MXDTOUT TXDT TXCK MXHSCK TXCK For additional information and latest specifications, see our website: www.triquint.com TQ8101C At power-up or during initialization, CNTL(3) should be set to logic 1. During reset, all internal counters, dividers, and loopback states, and the phasefrequency detector, are reset or deactivated. Note that frame search is initiated only by a rising edge on OOF. SONET/SDH/ATM TELECOM The signals on pins CNTL(3:0) can be used to control the clock rate, clock mode, loopback scheme, and tristate pins. Also, the internal PLL high-speed clock may be disabled, allowing an external clock source to be used on the MXHCN and MXHCP pins. Note that the NAND tree enable normally is used only for device testing of the VIH and VIL parameters. Table 1. Modes of Operation CNTL(3:0) Notes: • • • • Modes of operation 0h 1h 2h 3h Reset Tristate all TTL outputs except DXRCK and MO NAND-tree test all TTL inputs except CNTL(3:0) DXRCK tristate 4h 5h 6h 7h 8h Frame recovery disable Equipment loopback Facility loopback Split loopback Bypass, slave, internal VCO disabled, STS-3 rate 9h Ah Bh Ch Dh Eh Fh Bypass, master, internal VCO disabled, STS-3 rate Bypass, slave, internal VCO disabled, STS-12 rate Bypass, master, internal VCO disabled, STS-12 rate Normal, slave, internal VCO enabled, STS-3 rate Normal, master, internal VCO enabled, STS-3 rate Normal, slave, internal VCO enabled, STS-12 rate Normal, master, internal VCO enabled, STS-12 rate “Bypass” indicates the use of the external high-speed clock in lieu of the internal transmit PLL. “Normal” indicates use of the internal transmit PLL. “Master” derives PLL timing from the reference 51.84-MHz oscillator input, MXLRC “Slave” derives PLL timing from the demultiplexer clock input, RXCK. For additional information and latest specifications, see our website: www.triquint.com 5 PRODUCTS Control TQ8101C Table 2. Absolute Maximum Ratings Parameter Symbol Level Minimum Maximum Unit Positive supply VCC Negative supply Output voltage VEE VO — 0 7 V — ECL –7 VEE – 0.5 0 +0.5 V V Output current IO ECL — 40 mA Input voltage Input current VI II ECL ECL VEE – 0.5 –1 +0.5 1 V mA Output voltage Output current Input voltage Input current Junction temperature VO IO VI II TJ TTL TTL TTL TTL — –0.5 — –0.5 –1 –55 VCC + 0.5 20 VCC + 0.5 1 +150 V mA V mA ˚C Storage temperature TS — –65 +175 ˚C Symbol Minimum Nominal Maximum Unit VCC VEE TO 4.75 –5.5 0 5 –5.2 5.25 –4.75 70 V V ˚C Table 3. Recommended Operating Conditions Parameter Positive supply Negative supply Operating ambient temperature Table 4. Power Consumption Function +5 V supply –5.2 V supply Unit Nominal Max 40 55 320 420 mA mA Parameter Symbol Thermal resistance, junction-case 6 Level Minimum θJC For additional information and latest specifications, see our website: www.triquint.com Maximum Unit 4 ˚C / W TQ8101C 17 GND 36 GND 16 DXRC 37 MXDT7 15 OOF 38 MXDT6 14 GND 39 GND 13 MO 40 MXDT5 12 TXDTN 41 MXDT4 11 GND TQ8101C MDFP 42 GND 43 MXDT3 10 TXDTP 9 TXCK 68 GND 67 CNTL0 66 CNTL1 65 GND 64 CNTL2 63 TUNE 62 GND 61 IOUT 1 VEE 60 CNTL3 2 GND 51 GND 59 GND 3 RXCKP 50 MXCK1 58 MXHCP 4 RXCKN 49 MXCK2 57 MXHCN 5 GND 48 GND 56 GND 47 MXDT0 55 MXLRC 6 RXDTN 54 MXCK0 7 RXDTP 46 MXDT1 53 GND 8 GND 45 GND 52 VCC 44 MXDT2 Figure 7. Recommended Package Footprint .026 .096 1.150 1.150 For additional information and latest specifications, see our website: www.triquint.com 7 PRODUCTS 35 VEE SONET/SDH/ATM TELECOM 18 VCC 19 GND 20 DXDT7 21 DXDT6 22 GND 23 DXDT5 24 DXDT4 25 GND 26 DXDT3 27 DXDT2 28 GND 29 DXDT1 30 DXDT0 31 GND 32 DXCK 34 GND 33 DXSYN Figure 6. Pinout Diagram (heat spreader side—top view) TQ8101C Table 5. Signal Descriptions Pin Signal Type Description 1 VEE 2 3 GND RXCKP Negative power supply input (–5.2V) In Ground Receive bit-serial clock; differential ECL, positive 4 RXCKN In Receive bit-serial clock; differential ECL, negative 5 6 GND RXDTN In Ground Receive bit-serial data (MSB first); differential ECL, negative 7 8 9 10 11 RXDTP GND TXCK TXDTP GND 12 13 14 15 16 TXDTN MO GND OOF DXRCK 17 18 19 20 21 GND VCC GND DXDT7 DXDT6 22 23 24 25 26 27 28 29 30 31 32 33 34 GND DXDT5 DXDT4 GND DXDT3 DXDT2 GND DXDT1 DXDT0 GND DXCK DXSYNC GND In Out Out Out Out Receive bit-serial data (MSB first); differential ECL, positive Ground Transmit bit-serial clock; single-ended ECL level Transmit bit-serial data (MSB first); differential ECL, positive Ground In Tri Out Transmit bit-serial data (MSB first); differential ECL, negative NAND tree monitor output; TTL level Ground Out of frame; TTL level; rising-edge initiated frame search Demultiplexer reference clock; TTL level; 50-pF backplane driving capacity Tri Out Tri Out Ground Positive power supply input (+5.0V) Ground Demultiplexer byte-serial data (bit 7); TTL level Demultiplexer byte-serial data (bit 6); TTL level Tri Out Tri Out Tri Out Tri Out Tri Out Tri Out Tri Out Tri Out Ground Demultiplexer byte-serial data (bit 5); TTL level Demultiplexer byte-serial data (bit 4); TTL level Ground Demultiplexer byte-serial data (bit 3); TTL level Demultiplexer byte-serial data (bit 2); TTL level Ground Demultiplexer byte-serial data (bit 1); TTL level Demultiplexer byte-serial date (bit 0); TTL level Ground Demultiplexer byte-serial clock; TTL level Demultiplexer synchronization; TTL level Ground (Continues on next page) 8 For additional information and latest specifications, see our website: www.triquint.com TQ8101C Table 5. Signal Descriptions (continued) Type Description 35 VEE 36 GND Negative power supply input (–5.2V) 37 MXDT7 In Multiplexer byte-serial data (bit 7); TTL level 38 MXDT6 In Multiplexer byte-serial data (bit 6); TTL level 39 GND 40 MXDT5 In Multiplexer byte-serial data (bit 5); TTL level 41 MXDT4 In Multiplexer byte-serial data (bit 4); TTL level 42 GND 43 44 MXDT3 MXDT2 In In Multiplexer byte-serial data (bit 3); TTL level Multiplexer byte-serial data (bit 2); TTL level 45 46 47 48 49 GND MXDT1 MXDT0 GND MXCK2 50 51 52 53 54 MXCK1 GND VCC GND MXCK0 Tri Out 55 56 57 58 59 MXLRC GND MXHCN MXHCP GND In 60 61 62 63 64 65 66 67 68 CNTL3 IOUT GND TUNE CNTL2 GND CNTL1 CNTL0 GND Ground Ground Ground In In Tri Out Tri Out In Out In In Multiplexer byte-serial clock (bit 1); TTL level. See Table 1 for output rate. Ground Positive power supply input (+5.0V) Ground Multiplexer byte-serial clock (bit 0); TTL level. See Table 1 for output rate. Multiplexer low-speed reference clock (51.84 MHz); TTL level Ground Multiplexer high-speed reference clock (max. 640 MHz); differential ECL, negative Multiplexer high-speed reference clock (max. 640 MHz); differential ECL, positive Ground In In In In Ground Multiplexer byte-serial data (bit 1); TTL level Multiplexer byte-serial data (bit 0); TTL level Ground Multiplexer byte-serial clock (bit 2); TTL level. See Table 1 for output rate. Control (bit 3); TTL level Tristate charge pump output (analog); connect to pin 63 Ground VCO tune (analog); connect to external loop filter and pin 61 Control (bit 2); TTL level Ground Control (bit 1); TTL level Control (bit 0); TTL level Ground For additional information and latest specifications, see our website: www.triquint.com 9 PRODUCTS Signal SONET/SDH/ATM TELECOM Pin TQ8101C Table 6. DC Characteristics—ECL I/O (1) Parameter Condition Symbol Minimum Nominal Maximum Unit Internal ECL reference (2) VREF — 0.26 VEE Common mode voltage Differential voltage (3) (3) VCOM VDIFF –1500 200 — — –1100 1200 mV mV Input HIGH voltage (4) VIH –1100 — –400 mV Input LOW voltage Output HIGH voltage (5) VIL VOH VEE –1000 — 0 –1500 –500 mV mV VIH (MAX) VIL (MIN) (6) (6) VOL IIH IIL IOH IOL VTT – 100 — — 20 –2 — — — 23 5 –1600 30 –30 30 8 mV mA mA mA mA (1) CIN COUT VESD — — 500 3 3 — — — — pF pF V Condition Symbol Minimum Nominal Maximum Unit VIH (MAX) VIH VIL IIH 2.0 0 — — — — VCC 0.8 100 V V mA IIL VOH VOL IOZ CIN COUT VESD –100 2.4 0 –100 — — 1000 — — — — 8 10 — — VCC 0.4 100 — — — mA V V mA pF pF V Output LOW voltage Input HIGH current Input LOW current Output HIGH current Output LOW current Input capacitance Output capacitance ESD breakdown (5) mV Table 7. DC Characteristics—TTL I/O (1) Parameter Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Output HIGH voltage Output LOW voltage Tristate current Input capacitance Output capacitance ESD breakdown VIL (MIN) IOH = 3 mA IOL = –1 mA (1) Notes (tables 6 and 7): 1. Specifications apply over recommended operating ranges. 2. Single-ended inputs 3. Differential inputs 4. VREF = –1300 mV 5. RLOAD = 50 ohms to VTT = –2.0V 6. Not tested; consistent with VOH and VOL tests 10 For additional information and latest specifications, see our website: www.triquint.com TQ8101C Symbol Minimum Nominal Maximum Unit RXCK clock period TC(RXCK) 1.6 — — ns MXHC clock period TXCK clock period TC(MXHC) TC(TXCK) 1.6 1.6 — — — — ns ns MXCK clock period TC(MXCK) 12.8 — — ns DXCK clock period MXLRC clock period TC(DXCK) TC(MXTRC) 12.8 18.87 — 19.29 — 19.61 ns ns DXRCK clock period RXCK clock duty cycle MXHC clock duty cycle TXCK clock duty cycle MXCK clock duty cycle TC(DXRCK) TDC(RXCK) TDC(MXHC) TDC(TXCK) TDC(MXCK) 4.80 30 30 40 40 19.29 50 50 50 50 — 70 70 60 60 ns % % % % DXCK clock duty cycle MXLRC clock duty cycle DXRCK clock duty cycle High-speed rise/fall time1 (more than 79 MHz) Low-speed rise/fall time1 (less than 79 MHz) TDC(DXCK) TDC(MXIRC) TDC(DXRCK) TH(R/F) TL(R/F) 40 30 40 — — 50 50 50 — — 60 70 60 320 2.56 % % % ps ns CNTL(2:0) Setup Time to CNTL(3) CNTL(2:0) Hold Time to CNTL(3) RXDT setup time to RXCK RXDT hold time to RXCK OOF rising edge before A1 changes to A2 TS(CNTL) TH(CNTL) TS(RXDT) TH(RXDT) T(OOFH) 5500 2000 225 125 51.44 — — — — — — — — — — ps ps ps ps ns OOF pulse width DXSYNC rising edge from parallel data output change from A1 to A2 DXSYNC pulse width DXCK falling edge to valid parallel data output MXDT(0:7) setup time to MXCK MXDT(0:7) hold time to MXCK TXCK falling edge to TXDT T(OOFPW) T(DSYNC) 12.86 — — 25.72 — — ns ns 12.86 TC(RXCK) 4500 –2000 — — TC(RXCK) + 0.5 — — — — TC(RSCK) + 1.5 — — 500 ns ns ps ps ps Notes: T(DXSYNCPW) TP(DXDT) TS(MXDT) TH(MXDT) TP(TXDT) SONET/SDH/ATM TELECOM Parameter 1. 20% to 80% of min VOH and max VOL levels. For additional information and latest specifications, see our website: www.triquint.com 11 PRODUCTS Table 8. AC Characteristics TQ8101C Figure 8. Input Timing RXCKP TS(RXDT) TH(RXDT) TS(MXDT) TH(MXDT) RXDT MXCK(2:0) MXDT(7:0) Figure 9. Output Timing TXCK TP(TXDT) TXDT DXCK TP(DXDT) DXDT(7:0) TP(DXSYNC) DXSYNC 12 For additional information and latest specifications, see our website: www.triquint.com TQ8101C Figure 10. Multiplexer Timing MXDT(7:0) TXCK TXDT Figure 11. Demultiplexer Timing RXCK RXDT A1 #1 A1 #2 A1 #n A2 #1 A2 #2 A2 #3 OOF T(OOFPW) T(DXSYNC) T(OOFH) DXSYNC T(DXSYNCPW) DXCK DXCK Resync DXDT(7:0) A1 #1 A1 #2 A1 #n A2 #1 A2 #2 A2 #3 For additional information and latest specifications, see our website: www.triquint.com 13 PRODUCTS SONET/SDH/ATM TELECOM MXCK(2:0) TQ8101C SONET/SDH Considerations Jitter Tolerance Jitter Generation This measurement does not apply to the TQ8101C, since data is transmitted from the input parallel bus relative to a TQ8101C-generated clock output (MXCK[2:0]). The user must meet setup and hold time requirements in order to ensure that data tracking is maintained. By exploiting material characteristics, fully differential SCFL logic, and on-chip reactive elements, the TQ8101C typically has a jitter generation of 0.008 UI RMS (where 1 UI is 1/622.08E06) using recommended loop filter component values. Ordering Information TQ8101-M SONET/SDH MDFP Evaluation Board Please contact a TriQuint representative or the factory for availability and pricing. Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997 14 For additional information and latest specifications, see our website: www.triquint.com