TRIQUINT TQ5122

WIRELESS COMMUNICATIONS DIVISION
TQ5122
DATA SHEET
GND 1
16
GND
GND
2
15
GND
Vdd MXR
3
14
IF Output/Vdd
MXR LO 4
13
GND
5
12
MXR RF
Input
GND
6
11
GND
RF IN
7
10
LNA
Out
GND
8
9
Sleep
Control
VDD LNA
3V Cellular TDMA/AMPS
Receiver IC With PowerDown
Features
Product Description

Power-Down, “Sleep” Mode

Single 2.8V operation

Low-current operation

The TQ5122 is a 3V, RF receiver IC designed specifically for Cellular band TDMA
applications. It’s RF performance meets the requirements for products designed to the 
IS-136 TDMA and the AMPS standards. The TQ5122 includes a power–down mode
which allows current saving during standby and the non-operating portion of the TDMA
pulse. The TQ5122 contains LNA and Mixer circuits matched to the 800MHz cellular
band.
Small QSOP-16 plastic package
Few external components
The mixer uses a high-side LO frequency. The IF has a usable frequency range of 85
to 150MHz. The LNA Output and Mixer Input ports are internally matched to simplify
the design and keep the number of external components to a minimum. The TQ5122
achieves excellent RF performance with low current consumption which yields long
standby times in portable applications. The small QSOP-16 package is ideally suited
for Cellular band mobile phones.
Applications
Electrical Specifications1
Parameter
Min
Frequency
869
Gain
Typ
Max
Units
894
MHz
18.5
dB
Noise Figure
2.7
dB
3rd
-8.5
dBm
12.0
mA
Input
Order Intercept
DC supply Current
Note 1: Test Conditions: Vdd=2.8VDC, Tc=25°C, Filter IL=2.5dB, RF=881MHz, LO=1016MHz,
IF=135MHz, LO input=-7dBm
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
IS-136 TDMA Mobile Phones

Dual Mode TDMA/AMPS Mobile Phones

AMPS Mobile Phones
1
TQ5122
Data Sheet
Electrical Characteristics1,2
Parameter
Conditions
Min.
Typ/Nom
Max.
Units
RF Frequency
869
894
MHz
LO Frequency
954
1044
MHz
IF Frequency
85
150
MHz
LO input level
-7
-4
0
dBm
Supply voltage
2.7
2.8
4.0
V
Gain
16.0
18.5
Gain Variation vs. Temp.
-40 to 85 °C
Noise Figure
Input
3rd
2.7
Order Intercept
Return Loss
Isolation
IF Output Impedance
Power Down, “sleep”
-11.0
dB
+/-2.0
dB
3.5
dB
-8.5
dBm
LNA input – with external match
10
dB
LNA output
10
dB
Mixer RF input
10
dB
Mixer LO input
10
dB
LO to LNA RF in
35
dB
LO to IF; after IF match
40
dB
RF to IF; after IF match
20
dB
Vdd = 2.8V; Sleep mode, Device On
500
Ohm
Vdd = 2.8V; Sleep mode, Device Off
Approx. Open
Ohm
Vdd = 0V
<50
Ohm
Device On Voltage
Vdd
Device Off Voltage
0
Vdd
0
VDC
VDC
Supply Current, Sleep mode, Device On
Tc = + 25 °C
12
15
mA
Supply Current, Sleep mode, Device Off
Enable voltage = 0, LO Drive off
100
1000
µA
25
+85
°C
Operating Temperature, case
-40
Note 1: Test Conditions: Vdd=2.8VDC, Filter IL=2.5dB, RF=881MHz, LO=1016MHz, IF=135MHz, LO input=-7dBm, TC = 25°C, unless otherwise specified.
Note 2: Min./Max. limits are at +25°C case temperature unless otherwise specified.
Absolute Maximum Ratings
Parameter
Value
Units
DC Power Supply
5.0
V
Power Dissipation
500
mW
Operating Temperature
-55 to 100
°C
Storage Temperature
-60 to 150
°C
Signal level on inputs/outputs
+20
dBm
Voltage to any non supply pin
-0.3 to Vdd + 0.3
V
2
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TQ5122
Data Sheet
Typical Performance
Test Conditions (Unless Otherwise Specified): Vdd=2.8VDC, Tc=25°C, filter IL=2.5dB, RF=881MHz, LO=1016MHz, IF=135MHz, LO input=-7dBm
Gain vs. Vdd vs. Temperature
25
20
20
Gain (dB)
Gain (dB)
Gain vs. Frequency vs. Temperature
25
15
10
-40C
+85C
10
+25C
+25C
5
15
-40C
5
+85C
0
0
869
872
875
878
881
884
887
890
893
2.7
2.8
2.9
3
Frequency (MHz)
Input IP3 vs. Frequency vs. Temperature
3.2
3.3
3.4
3.5
3.6
Input IP3 vs. Vdd vs. Temperature
-4
-4
-6
-6
-8
Input IP3 (dBm)
Input IP3 (dBm)
3.1
Vdd (volts)
-10
-12
85C
-14
-8
-10
-12
+85C
25C
+25C
-14
-40C
-16
-40C
-16
-18
869
872
875
878 881 884 887
Frequency (MHz)
890
2.7
893
2.8
NF vs. Frequency vs. Temperature
2.9
3
3.1 3.2 3.3
Vdd (volts)
3.4
3.5
3.6
3.4
3.5
3.6
NF vs. Vdd vs. Temperature
4
4
3.5
3
NF (dB)
NF (dB)
3
2
2
1.5
+85C
+25C
-40C
1
2.5
+85C
+25C
-40C
1
0.5
0
0
869
872
875
878 881 884
Frequency (MHz)
887
890
893
2.7
2.8
2.9
3
3.1 3.2
Vdd (volts)
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3.3
3
TQ5122
Data Sheet
Application/Test Circuit
1
16
2
15
3
14
C5
V IF
C3
V MX
L3
C4
IF out
L2
LO in
V LNA
4
13
5
12
6
11
7
10
8
9
C6
C2
F881
L1
LNA in
C1
Sleep Control
Bill of Material for TQ5122 Receiver Application/Test Circuit*
Component
Reference Designator
Part Number
Receiver IC
U1
TQ5122
Capacitor
C1
2.7pF
0603
Capacitor
C2, C3
22pF
0603
Capacitor
C4
10pF
0603
Capacitor
C5
1000pF
0603
Capacitor
C6
8.2 pF
0603
Inductor
L1
22nH
0603
Inductor
L2
12nH
0603
Inductor
L3
150nH
0805
Toyocom (select)
F1
T726881A
Value
627-881A
* May vary due to printed circuit board layout and material.
4
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Size
Manufacturer
QSOP-16
TriQuint Semiconductor
Toyocom
TQ5122
Data Sheet
presented to the input pin. Highest gain and lowest return loss
TQ5122 Product Description
occur when Γs is equal to the complex conjugate of the LNA
The TQ5122 3V RFIC Downconverter is designed specifically
for cellular band TDMA/AMPS applications. The TQ5122
contains LNA, Mixer and LO buffer circuits matched to the 800
MHz cellular frequency band. The IF frequency may be selected
input impedance. A different source reflection coefficient, Γopt,
which is experimentally determined, will provide the lowest noise
figure, Fmin.
between 85 and 150 MHz. Most RF ports are internally
The noise resistance, Rn, provides an indication of the sensitivity
matched to 50 Ω simplifying the design and minimizing the
of the noise performance to changes in Γs as seen by the LNA
number of external components. The TQ5122 also includes a
input.
power–down mode switch which allows current saving during
Γopt − ΓS
4 RN
⋅
Z 0 1 + Γopt 2 ⋅ 1 − Γs 2
2
standby and the non-operating portion of the TDMA pulse.
FLNA = FMIN +
Operation
Components such as filters and mixers placed after the LNA
Please refer to the test circuit above.
degrade the overall system noise figure according to the
(
)
following equation:
Low Noise Amplifier (LNA)
The LNA section of the TQ5122 are cascaded common source
FSYSTEM = FLNA +
FET’s, see Figure 1. It is designed to operate on DC supply
F2 − 1
GLNA
voltages from 2.7V to 5V. The source terminal must be
FLNA and GLNA represent the linear noise factor and gain of the
grounded as close as possible to Pin 8 to avoid significant gain
LNA and F2 is the noise factor of the next stage. The system
reduction due to degeneration. The LNA requires an input
noise figure is a compromise between the highest gain and
matching circuit to obtain best noise figure, gain and return loss.
minimum noise figure of the LNA. See Table 1 for noise
The LNA output is close to 50 Ω for direct connection to a 50 Ω
parameters.
image reject filter.
Table 1. TQ5122 Noise Parameters
Vdd
LOAD
LNA
out
LNA
in
BIAS
BIAS
Freq.
MHz
830
880
930
|Gopt|
/ Gopt
Fmin
Rn
0.88
0.83
0.82
34.5
37.8
40.0
0.75
0.89
0.97
51.2
50.4
50.0
LNA Output Match
The output impedance of the LNA was designed for 50Ω. The
Figure 1. Simplified Schematic of LNA Section
internal 50Ω match eliminates the need for external
components at this port. It also improves IP3 performance and
LNA Input Match
power gain.
The designer can make some Noise Figure and Gain trade off
The output of the LNA is intended to be connected directly to an
by varying the off chip LNA input matching circuit values and
image reject filter. Depending on the filter, additional
topology. This allows the TQ5122 to be optimized for specific
components may be needed to better match to the LNA output.
system requirements.
Some image reject filters may require a series inductor to
The LNA gain, noise figure and input return loss are a function
of the source impedance (Zs), or reflection coefficient (Γs),
smooth the frequency response and improve overall
performance.
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5
TQ5122
Data Sheet
Mixer
degradation in conversion gain and system noise figure.
The mixer of the TQ5122 uses a common source depletion
mode MESFET. The mixer is designed to operate on supply
voltages from 2.7V to 5V. A 50Ω matched on-chip buffer
amplifier allows direct connection of the LO input to
commercially available VCO’s with output drive levels down to
Sensitivity to the phenomena depends on the particular filter
model and the line length between the mixer input pin and the
filter. In some cases a small inductance can be added between
the filter and the mixer input to compensate. With some line
lengths and filter combinations, no inductor is necessary.
-7dBm. The common-gate LO buffer provides good input match
LO Buffer & Calculation of Nominal L2 Value
and supplies the voltage gain needed to drive the mixer FET.
The node between the LO buffer amplifier and the mixer FET is
The mixer also has an "open-drain" IF output which provides
brought out to Pin 3 (V MX) and connected by an inductor to AC
flexibility in matching to various IF frequencies and filter
ground. This inductor is selected to resonate with internal on
impedances, see Figure 2.
chip capacitance at the LO frequency in order to reduce out-ofband gain and improve noise performance.
LO Bias
and
Tuning
Mixer RF
Input
Open Drain
IF Output
LO Input
The internal capacitance of the LO amplifier output plus the
stray capacitance on the board surrounding Pin 3 is
approximately 1.5 pF. The inductor is selected to resonate with
the total capacitance at the LO frequency using the following
equation:
Figure 2, Mixer Section
LO Input Port
L=
1
C(2Πf )
2
, where ⋅ C = 1.5 pF
The final values must be confirmed with measurements on a
The LO input port is matched to 50Ω. This allows the TQ5122
board approximating the final layout. The final layout will affect
to operate at low LO drivel levels. However, the values and
the value and position of L2 and its bypass capacitor, C3, see
positions of L2 and C3 shown in the applications circuit effect
Figure 5.
the gain of the LO buffer amplifier and are important to the
proper operation of the TQ5122. See “Calculation of nominal L2
Value” below
Network
Analyzer
The common gate buffer amplifier provides the voltage gain
Port 1 Port 2
needed to drive the gate of the mixer FET while using very little
current (approximately 1.5mA).
Probe
Because of the 50Ω input match of the buffer amplifier and the
3
4
TQ5122
internal DC blocking capacitor, the system VCO output can be
-30
directly connected to the TQ5122 LO input via a 50Ω
Mixer Input
-32
S21 (dB)
transmission line with no additional components.
-34
-36
-38
-40
-42
Although the mixer input port is matched to 50Ω, TriQuint has
700
800
900
1000 1100 1200
Frequency (MHz)
found that LO leakage through the Mixer RF input pin, can in
some cases, reflect off the SAW image reject filter and return
Figure 3. LO Buffer Frequency Response
back to the mixer out of phase. This may cause some
6
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TQ5122
Data Sheet
Measuring the LO Frequency Response
topology must contain either an RF choke or shunt inductor. An
The frequency response of the LO driver amplifier can be
measured using a semi-rigid probe, see Figure 3, and a network
analyzer.
extra DC blocking capacitor is not necessary if the output will be
attached directly to a SAW or crystal bandpass filters.
Figure 5 illustrates a shunt L, series C, shunt C IF matching
Connect port 1 to the LO input (Pin 4) of the TQ5122 with the
source power set to deliver -7 dBm. Connect the coaxial probe
to Port 2 and place the probe tip approximately 0.1 inch away
network. It is one of the simplest matching networks and
requires the fewest components. DC current can be easily
injected through the shunt inductor and the series C provides a
DC block, if needed. The shunt C, is used to reduce the LO
from either Pin 3 or the inductor.
leakage.
If the calculated shunt inductor (L2) is not a standard value, the
10 pF
AC ground bypass capacitor C3 can be positioned along the
transmission line to adjust for the right inductance, see Figure 4.
Pin 14
IF out
150nH
Once this is completed, the peak of the response should be
centered at the center of the LO frequency band.
8.2pF
Pin 13
1000pF
GND
Placement of C3 will adjust between standard values of
inductors.
V IF
Figure 5, IF Output Match, 135 MHz
Pin 2
C3
Power down, “sleep” mode
Pin 3
The power down circuit is used to reduce average power
L2
consumption in TDMA applications by toggling the receiver on
Figure 4, Adjusting the AC Ground
and off within the receive time slot when no signal is present.
Mixer IF Port
The Mixer IF output is an "open-drain" configuration, allowing for
flexibility in efficient matching to various filter types and at
various IF frequencies.
The power down circuitry operates through the incorporation of
enhancement-mode FET switches in all DC paths. Level
shifting circuitry is incorporated for the purpose of providing an
interface compatible with CMOS logic levels. The entire chip
For evaluation of the LNA and mixer, it is usually necessary to
nominally draws 100uA when the power-down pin is at 0V.
impedance match the IF port to the 50Ω test systems. When
When the power-down pin is at 2.8V (Vdd), the chip draws
verifying or adjusting the matching circuit on the prototype circuit
nominal specified current. The power-down pin itself, Pin 9,
board, the LO drive should be injected at pin 4 at the nominal
draws approximately 40uA when 2.8V is applied. Less than 1uA
power level of -4 dBm, since the LO level does have an impact
is sourced from the power-down pin when 0V is applied.
on the IF port impedance.
There are several networks that can be used to properly match
the IF port to the SAW or crystal IF filter. The mixer supply
voltage is applied through the IF port, so the matching circuit
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7
TQ5122
Data Sheet
Package Pinout
GND 1
16
GND
GND
2
15
GND
Vdd MXR
3
14
IF Output/Vdd
MXR LO 4
13
GND
5
12
MXR RF
Input
GND
6
11
GND
RF IN
7
10
LNA
Out
GND
8
9
Sleep
Control
VDD LNA
Pin Descriptions
Pin Name
Pin #
GND
1
Ground
Description and Usage
GND
2
Ground
VDD_MXR
3
Mixer LO buffer supply voltage. Series inductor required for LO buffer tuning. Local external bypass capacitor required.
MXR LO IN
4
Mixer LO input. DC blocked, matched to 50Ω
VDD LNA
5
LNA DC supply voltage. Local external bypass capacitor required.
GND
6
Ground
LNA IN
7
LNA RF input. DC blocked. Requires external matching elements for noise match and match to 50Ω
GND, LNA
8
LNA first stage ground connection. Direct connection to ground required.
SLEEP
9
Power-Down mode control.
LNA OUT
10
LNA RF output. DC blocked. Matched to 50Ω.
GND
11
Ground
MXR_RF
12
Mixer RF input, DC blocked. Matched to 50Ω.
GND
13
Ground
IF OUT
14
IF output. Open drain output, connection to Vdd required. External matching is required.
GND
15
Ground
GND
16
Ground
For ground pins 1, 2, 6, 11, 13, 15, and 16, TriQuint recommends use of several via holes to the backside ground immediately adjacent to
the pin.
8
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TQ5122
Data Sheet
Package Type: Power QSOP-16 Plastic Package
D
NOTE A
E
E1
b
NOTE B
c
A
e
DESIGNATION
A
A1
b
c
D
e
E
E1
L
θ
A1
DESCRIPTION
OVERALL HEIGHT
STANDOFF
LEAD WIDTH
LEAD THICKNESS
PACKAGE LENGTH
LEAD PITCH
LEAD TIP SPAN
PACKAGE WIDTH
FOOT LENGTH
FOOT ANGLE
L
ENGLISH
0.064 +/-.005 in
0.007 +/-.003 in
0.010 +/-.002 in
0.085 +/-.015 in
0.193 +/-.004 in
0.025
BSC
0.236 +/-.008 in
0.154 +/-.003 in
0.033 +/-.017 in
4
+/-4 DEG
θ
METRIC
1.63
+/-.13 mm
0.18
+/-.08 mm
0.25
+/-.05 mm
2.16
+/-.38 mm
4.90
+/-.10 mm
0.635
BSC
5.99
+/-.20 mm
3.91
+/-.08 mm
0.84
+/-.43 mm
4
+/-4 DEG
NOTE
C
C
C
C
A, C
C
B, C
C
NOTES:
A.
The D dimension does not include mold flashing and mismatch. Mold flashing and mismatch shall not exceed .006 in (.15 mm) per
side.
B.
The E1 dimension does not include mold flashing and mismatch. Mold flashing and mismatch shall not exceed .010 in (.25 mm)
per side.
C. Primary units are English inches. The metric equivalents are subject to rounding error.
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Tel: (503) 615-9000
Email: [email protected]
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of
this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or
licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1999 TriQuint Semiconductor, Inc. All rights reserved.
Revision D, August 19, 1999
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9