Revised April 1999 74ACTQ00 Quiet Series Quad 2-Input NAND Gate General Description Features The ACTQ00 contains four 2-input NAND gates and utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance. ■ ICC reduced by 50% ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Improved latch-up immunity ■ Outputs source/sink 24 mA ■ Has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACTQ00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 74ACTQ00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Assignment for DIP and SOIC Pin Descriptions Pin Names Description An, Bn Inputs On Outputs FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010888.prf www.fairchildsemi.com 74ACTQ00 Quiet Series Quad 2-Input NAND Gate August 1990 74ACTQ00 Absolute Maximum Ratings(Note 1) DC Latch-up Source ±300 mA or Sink Current −0.5V to +7.0V Supply Voltage (VCC) Junction Temperature (TJ) DC Input Diode Current (IIK) PDIP VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Recommended Operating Conditions −0.5V to VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) Supply Voltage (VCC) −0.5V to VCC + 0.5V ±50 mA 0V to VCC −40°C to +85°C VIN from 0.8V to 2.0V 125 mV/ns VCC @ 4.5V, 5.5V ±50 mA per Output Pin (ICC or IGND) 0V to VCC Output Voltage (VO) Minimum Input Edge Rate (∆V/∆t) DC VCC or Ground Current Storage Temperature (TSTG) 4.5V to 5.5V Input Voltage (VI) Operating Temperature (TA) DC Output Source or Sink Current (IO) 140°C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not −65°C to +150°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter VCC TA = +25°C TA = −40°C to +85°C (V) Typ Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units Conditions Guaranteed Limits V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH 4.5 4.86 4.76 V IOH = −24 mA (Note 2) Maximum LOW Level 4.5 0.001 0.1 0.1 V IOUT = 50 µA Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 VOL IOH = −24 mA VIN = VIL or VIH IOL = 24 mA IOL = 24 mA (Note 2) 5.5 0.36 0.44 V IIN Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µA VI = VCC, GND ICCT Maximum ICC/Input 5.5 1.5 mA V I = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent Supply Current 5.5 20.0 µA VIN = VCC or GND VOLP Quiet Output Maximum Dynamic 5.0 0.6 2.0 1.1 1.5 V VOLV Quiet Output Minimum Dynamic Figure 1, Figure 2 (Note 4)(Note 5) VOL 5.0 −0.6 −1.2 V VOL Figure 1, Figure 2 (Note 4)(Note 5) VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 4)(Note 6) VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 4)(Note 6) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: DIP package. Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND. Note 6: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 Symbol Parameter Propagation Delay tPLH VCC TA = +25°C (V) CL = 50 pF (Note 7) Min 5.0 5.0 Typ TA = −40°C to +85°C CL = 50 pF Units Max Min Max 2.0 7.5 2.0 8.0 ns 2.0 7.5 2.0 8.0 ns 1.0 ns Data to Output tPHL Propagation Delay Data to Output tOSHL Output to Output tOSLH Skew (Note 8) 5.0 0.5 1.0 Note 7: Voltage Range 5.0 is 5.0V ±0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 74 pF VCC = 5.0V 3 Conditions www.fairchildsemi.com 74ACTQ00 AC Electrical Characteristics 74ACTQ00 FACT Noise Characteristics VOLP/VOLV and VOHP/VOHV: The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the word generator channels before testing. This will ensure that the outputs switch simultaneously. • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope • Next decrease the input HIGH voltage level.V IH until the output begins to oscillate or steps out a mine of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. Note 9: VOHV and VOLP are measured with respect to ground reference. Note 10: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms FIGURE 2. Simultaneous Switching Test Circuit www.fairchildsemi.com 4 74ACTQ00 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A 5 www.fairchildsemi.com 74ACTQ00 Quiet Series Quad 2-Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP) JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.