4124 TGF4124-EPU • • • • • 24 mm Discrete HFET 0.5 um gate finger length Nominal Pout of 12 Watts at 2.3 GHz Nominal PAE of 51.5% at 2.3 GHz Nominal Gain of 10.8 dB at 2.3 GHz Die size 36.0 x 81.0 x 4.0 mils (0.914 x 2.057 x 0.102 mm) TGF4124-EPU RF Performance at F = 2.3 GHz Vd = 8.0 V, Vg = -1.1 V, Iq = 2.17 A and T A = 25°C 55 50 Pout 50 PAE 46 45 44 40 42 35 40 30 38 25 36 20 34 15 32 10 30 5 20 22 24 26 28 30 Power Added Efficiency % Output Power (dBm) 48 32 Input Power (dBm) 1 TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com 140 42 130 41 120 40 110 39 100 38 90 37 Tch 80 36 70 35 Pout 60 Vg = -1.1V Vg = -1.3 V Vg = -1.5 V 50 40 Output Power (dBm) Predicted Channel Temp (°C) TGF4124-EPU RF Performance for Vd = 7.0 V, F = 2.3 GHz, and TA = 25°C Quiescent Id is 2.24 A (Vg = -1.1 V), 1.81 A (Vg = -1.3 V), and 1.37 A (Vg = -1.5 V) 34 33 32 55 Power Added Efficiency % 50 45 40 35 30 25 20 15 Vg = -1.1V Vg = -1.3 V Vg = -1.5 V 10 5 14 13 Gain (dB) 12 11 10 9 Vg = -1.1V Vg = -1.3 V Vg = -1.5 V 8 7 20 21 22 23 24 25 26 27 28 Input Power (dBm) 29 30 31 32 2 TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com 150 42 140 41 130 40 120 39 110 38 Tch 100 37 90 36 80 35 Pout 70 Vg = -1.1V Vg = -1.3 V Vg = -1.5 V 60 50 Output Power (dBm) Predicted Channel Temp (°C) TGF4124-EPU RF Performance for Vd = 8.0 V, F = 2.3 GHz, and TA = 25°C Quiescent Id is 2.17 A (Vg = -1.1 V), 1.80 A (Vg = -1.3 V), and 1.40 A (Vg = -1.5 V) 34 33 32 55 Power Added Efficiency % 50 45 40 35 30 25 20 15 Vg = -1.1V Vg = -1.3 V Vg = -1.5 V 10 5 14 13 Gain (dB) 12 11 10 9 Vg = -1.1V Vg = -1.3 V Vg = -1.5 V 8 7 20 21 22 23 24 25 26 27 28 Input Power (dBm) 29 30 31 32 3 TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com 170 42 160 41 150 40 140 39 130 38 Tch 120 37 110 36 100 35 90 34 Pout 80 Vg = -1.1V Vg = -1.3 V Vg = -1.5 V 70 60 Output Power (dBm) Predicted Channel Temp (°C) TGF4124-EPU RF Performance for Vd = 9.0 V, F = 2.3 GHz, and TA = 25°C Quiescent Id is 2.11 A (Vg = -1.79 V), 1.79 A (Vg = -1.3 V), and 1.43 A (Vg = -1.5 V) 33 32 31 55 Power Added Efficiency % 50 45 40 35 30 25 20 15 Vg = -1.1V Vg = -1.3 V Vg = -1.5 V 10 5 14 13 Gain (dB) 12 11 10 9 Vg = -1.1V Vg = -1.3 V Vg = -1.5 V 8 7 20 21 22 23 24 25 26 27 Input Power(dBm) 28 29 30 31 32 4 TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com DC Characteristics for the TGF4124-EPU DC probe Parameters Nominal Unit IDSS Drain Saturation Current 5880 mA GM Transconductance 3960 mS VP Pinch Off Voltage -1.85 V BVGS Breakdown Voltage Gate-Source -22 V BVGD Breakdown Voltage Gate-Drain -22 V Example of DC I-V Curves Vg = 0.0 V to -2.75 V in 0.25 steps TA = 25°C 6000 5500 5000 Drain Current (mA) 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0 1 2 3 4 5 6 7 8 9 D r a in V o l t a g e ( V ) Absolute Maximum Ratings Drain-to-source Voltage, Vds..............................… … … … … … … … … … … … … … … … ..........12 V Gate-to-source Voltage, Vgs..................… … … … … … … … … … … … … … … … .............-5 V to 0 V Mounting Temperature.................… … … … … … … … … … … … … … … .… .........… … … … … … 320°C Storage Temperature.....................… … … … … … … … … … … … … … .… .............… -65°C to 200°C Power Dissipation...........… … … … … .… … … … … … … … … … … … … … … ...refer to Thermal Model Operating Channel Temperature… … … … … … … … … … … … … … … … ..… .refer to Thermal Model Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in this document is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability. 5 TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com TGF4124-EPU Linear Model Vds = 8 V and Ids = 1.84 A at T = 25°C FET Elements Lg = .00103 nH Rg = 0.53233 Ω Rgs = 4086 Ω Ri = 0.030 Ω Cgs = 26.9096 pF Cdg = 0.99024 pF Rdg = 102026 Ω Rs = 0.04943 Ω Ls = 0.00808 nH Rds = 5.39715 Ω Cds = 4.30372 pF Rd = 0.19448 Ω Ld = 0.00965 nH VCCS Parameters M = 2.668 S A=0 R1 = 1E19 R2 = 1E19 F=0 T = 4.50 pS Cdg Rdg Lg Rg Rd VCCS Ld D G Ri Rgs Cds R1 R2 Rds Cgs Rs Ls Freq-GHz MAG-S11 ANG-S11 MAG-S21 ANG-S21 MAG-S12 ANG-S12 MAG-S22 ANG-S22 0.5 0.9655 -162.057 3.91809 95.2201 0.00638 15.0344 0.85618 -178.832 1 0.96563 -171.022 1.9714 86.9895 0.00651 16.8356 0.8587 -178.929 1.5 0.96577 -174.063 1.3101 81.7652 0.00665 21.478 0.86075 -178.77 2 0.96596 -175.605 0.97656 77.3514 0.00684 26.7416 0.86327 -178.562 2.5 0.96619 -176.548 0.77485 73.316 0.00709 32.1233 0.8663 -178.354 3 0.96646 -177.19 0.6393 69.5245 0.0074 37.4067 0.8698 -178.163 3.5 0.96676 -177.663 0.54171 65.9265 0.00778 42.4614 0.87367 -177.998 4 0.96708 -178.031 0.46793 62.5019 0.00822 47.2001 0.87783 -177.864 4.5 0.96742 -178.329 0.41013 59.243 0.00874 51.567 0.88221 -177.762 5 0.96777 -178.579 0.36358 56.1476 0.00931 55.5339 0.88672 -177.694 6 TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com Thermal Model of TGF4124-EPU Channel Temperature (°C) Predicted Channel Temperature vs Base Plate Temperature With a .020" CM15 (15/85 Copper Molybdenum) carrier plate solder attached using 0.0015" AuSn (80/20) solder 250 240 230 220 210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 Pd = 7 Watts Pd = 13 Watts 25 35 45 55 65 75 85 95 105 115 125 Base Plate Temperature (°C) Tch = 0.6458 + 5.886 x Pd + 0.0882 x Pd 2 + (1.001 + 0.01633 x Pd + 0.0001833 x Pd 2) x Tbase (Predicted Channel Temperature equation for the given assembly stack up) This model assumes a perfect solder connection (no voids) between the FET and the carrier plate. HFETChannel Temperature vs Median Life 350 Channel Temperature (°C) 300 250 200 150 100 0 1 2 3 4 5 6 7 8 9 10 Median Life (10^X Hours) 7 TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com Mechanical Drawing of TGF4124-EPU 81.0 (2.057) 76.3 (1.938) 69.0 (1.753) 65.3 (1.659) 61.6 (1.565) 52.5 (1.333) 48.8 (1.239) Drain Gate 45.1 (1.145) 35.9 (0.913) 32.2 (0.819) 28.5 (0.725) 19.4 (0.493) 15.7 (0.399) 12.0 (0.305) 4.7 (0.119) 0.0 0.0 7.4 (0.187) 28.1 (0.714) 36.0 (0.914) Alternate drain pad Alternate gate pad Units: mils (mm) Thickness: 4.0 (0.10) Gate pad sizes are 4.0 x 4.0 (0.10 x 0.10) Drain pad sizes are 4.7 x 14.5 (0.12 x 0.37) A minimum of four gate bonds and eight drain bonds is recommended for operation. Sources are connected to backside metalization. Alternate gate and drain pads are located on either end of the FET for paralleling TGF4124-EPUs. 8 TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com Application circuit for the TGF4124-EPU at 2.3 GHz The FET is soldered using AuSn solder at 300°C for 30 secs. Input and output matching networks are 0.381 mm ZrSn Tioxide substrates (Er = 38). The design load impedance is between 3 Ω and 4 Ω with the 8 pF output capacitance of the FETincluded in the output network. For further explanation refer to the application note “Designing High Efficiency Amplifiers using HFETs”. The carrier plate is 0.51 mm gold plated copper molybdenum. Gold wire 0.018 mm diameter is used for the bonds. Four gate bonds are required with a length of 0.42 mm. Eight drain bonds are required with a length of 0.42 mm. Bondwire end points on the FET are in the middle of the bond pads. Refer to the figures above for bondwire locations. Connection between the 50 ohm line input to the input match is made by a parallel RC network. R1 in this network is 10 ohms, and C1 is 5.6 pF. R1 and C1 are surface mount 0603 piece parts. 9 TriQuint Semiconductor Texas Phone: 972 994-8465 Fax 972 994-8504 Web: www.triquint.com