16-Bit, 8-Channel Simultaneous Sampling Data Acquisition System ADAS3023 Data Sheet FUNCTIONAL BLOCK DIAGRAM Ease-of-use, 16-bit complete data acquisition system Simultaneous sampling selection of 2, 4, 6, and 8 channels Differential input voltage range: ±20.48 V maximum High impedance 8-channel input: >500 MΩ High input common-mode rejection: 95.0 dB User-programmable input ranges On-chip 4.096 V reference and buffer No latency/pipeline delay (SAR architecture) Serial 4-wire 1.8 V to 5 V SPI-/SPORT-compatible interface 40-lead LFCSP package (6 mm × 6 mm) −40°C to +85°C industrial temperature range VDDH AVDD DVDD DIFF TO COM IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM VIO RESET PD CNV LOGIC/ INTERFACE BUSY CS TRACK AND HOLD PulSAR ADC PGIA SCK DIN SDO ADAS3023 REFIN BUF REF VSSH AGND DGND REFx APPLICATIONS 10942-001 FEATURES Figure 1. Multichannel data acquisition and system monitoring Process control Power line monitoring Automated test equipment Patient monitoring Spectrum analysis Instrumentation GENERAL DESCRIPTION The ADAS3023 is a complete 16-bit successive approximationbased analog-to-digital data acquisition system. This device is capable of simultaneously sampling up to 500 kSPS for two channels, 250 kSPS for four channels, 167 kSPS for six channels, and 125 kSPS for eight channels manufactured on the Analog Devices, Inc., proprietary iCMOS® high voltage industrial process technology. The ADAS3023 integrates eight channels of low leakage track and hold, a programmable gain instrumentation amplifier (PGIA) stage with a high common-mode rejection offering four differential input ranges, a precision low drift 4.096 V reference and buffer, and a 16-bit charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC). The ADAS3023 can resolve differential input ranges of up to ±20.48 V when using ±15 V supplies. Rev. 0 The ADAS3023 simplifies design challenges by eliminating signal buffering, level shifting, amplification and attenuation, common-mode rejection, settling time, or any of the other analog signal conditioning challenges, yet allows for smaller form factor, faster time to market, and lower costs. The ADAS3023 is factory calibrated and its operation is specified from −40°C to +85°C. Table 1. Typical Input Range Selection Single-Ended Signals1 0 V to 1 V 0 V to 2.5 V 0 V to 5 V 0 V to 10 V 1 Input Range, VIN ±1.28 V ±2.56 V ±5.12 V ±10.24 V See Figure 39 and Figure 40 in the Analog Inputs section for more information. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAS3023 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Application Connection Diagram .............................. 21 Applications ....................................................................................... 1 Analog Inputs.............................................................................. 21 Functional Block Diagram .............................................................. 1 Voltage Reference Input/Output .............................................. 22 General Description ......................................................................... 1 Power Supply............................................................................... 24 Revision History ............................................................................... 2 Power Dissipation Modes.......................................................... 24 Specifications..................................................................................... 3 Conversion Modes ..................................................................... 25 Timing Specifications .................................................................. 6 Digital Interface .............................................................................. 26 Absolute Maximum Ratings ....................................................... 9 Conversion Control ................................................................... 26 ESD Caution .................................................................................. 9 RESET and Power-Down (PD) Inputs .................................... 26 Pin Configuration and Function Descriptions ........................... 10 Serial Data Interface ................................................................... 27 Typical Performance Characteristics ........................................... 12 General Timing........................................................................... 28 Terminology .................................................................................... 17 Configuration Register .............................................................. 29 Theory of Operation ...................................................................... 19 Packaging and Ordering Information ......................................... 30 Overview...................................................................................... 19 Outline Dimensions ................................................................... 30 Operation..................................................................................... 19 Ordering Guide .......................................................................... 30 Transfer Functions...................................................................... 20 REVISION HISTORY 5/13—Revision 0: Initial Version Rev. 0 | Page 2 of 32 Data Sheet ADAS3023 SPECIFICATIONS VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%; VIO = 1.8 V to AVDD, Internal Reference VREF = 4.096 V, fS = 500 kSPS, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT (IN0 to IN7, COM) Input Impedance Operating Input Voltage Range 2 Differential Input Voltage Ranges, VIN THROUGHPUT Conversion Rate Transient Response 3 DC ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Gain Error 4 Gain Error Match, Delta Mean Gain Error Temperature Drift Offset Error4 Offset Error Match, Delta Mean Offset Error Temperature Drift AC ACCURACY 5 Signal-to-Noise Ratio Signal-to-Noise + Distortion (SINAD) Test Conditions/Comments Min 16 ZIN VIN, on any single pin VINX − COM PGIA gain = 0.2, VIN = 40.96 V p-p PGIA gain = 0.4, VIN = 20.48 V p-p PGIA gain = 0.8, VIN = 10.24 V p-p PGIA gain = 1.6, VIN = 5.12 V p-p 500 VSSH + 2.5 VDDH − 2.5 MΩ V −5VREF −2.5VREF −1.25VREF −0.625VREF +5VREF +2.5VREF +1.25VREF +0.625VREF V V V V 0 0 0 0 500 250 167 125 820 kSPS kSPS kSPS kSPS ns Two channels Four channels Six channels Eight channels Full-scale step PGIA gain = 0.2, 0.4, or 0.8, COM = 0 V PGIA gain = 1.6, COM = 0 V All PGIA gains, COM = 0 V PGIA gain = 0.2 or 0.4 PGIA gain = 0.8 PGIA gain = 1.6 External reference, all PGIA gains External reference, all PGIA gains External reference, PGIA gain = 0.2, 0.4, or 0.8 External reference, PGIA gain = 1.6 External reference, PGIA gain = 0.2 External reference, PGIA gain = 0.4 External reference, PGIA gain = 0.8 External reference, PGIA gain = 1.6 External reference, PGIA gain = 0.2, 0.4, 0.8, or 1.6 External reference, PGIA gain = 0.2 or 0.4, IN0 to IN7 External reference, PGIA gain = 0.8, IN0 to IN7 External reference, PGIA gain = 1.6, IN0 to IN7 Internal reference fIN = 1 kHz, COM = 0 V PGIA gain = 0.2 PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 fIN = 1 kHz, two, four, six, and eight channels PGIA gain = 0.2 PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 Rev. 0 | Page 3 of 32 16 −2.5 −3 −0.95 Typ ±1 ±1 ±0.5 6 7 10 −0.075 −0.05 Max +2.5 +3 +1.25 +0.075 +0.05 1 2 +12 +12 +10 250 +15 2 3 5 Unit 1 Bits Bits LSB LSB LSB LSB LSB %FS %FS ppm/°C ppm/°C LSB LSB LSB LSB LSB ppm/°C ppm/°C ppm/°C −65 −85 −10 0 −15 0 0 0 −35 −45 0 130 ±1 0.5 1.5 2.5 90.0 89.5 87.5 85.0 91.5 91.0 89.0 86.5 dB dB dB dB 89.5 89.0 87.0 84.0 91.0 90.5 88.5 86.0 dB dB dB dB ADAS3023 Parameter Dynamic Range Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk DC Common-Mode Rejection Ratio (CMRR) −3 dB Input Bandwidth INTERNAL REFERENCE REFx Pins Output Voltage Output Current Temperature Drift Line Regulation Internal Reference Buffer Only REFIN Output Voltage 6 Turn-On Settling Time EXTERNAL REFERENCE Voltage Range Current Drain DIGITAL INPUTS Logic Levels VIL VIH VIL VIH IIL IIH DIGITAL OUTPUTS 7 Data Format VOL VOH POWER SUPPLIES VIO AVDD DVDD VDDH VSSH Data Sheet Test Conditions/Comments fIN = 1 kHz, −60 dB input PGIA gain = 0.2 PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 fIN = 1 kHz, all PGIA gains fIN = 1 kHz, all PGIA gains fIN = 1 kHz, all channels inactive All channels Min Typ 91.0 90.5 88.0 86.0 92 91.5 89.5 87.0 −100 105 95 dB dB dB dB dB dB dB 95.0 95.0 95.0 95.0 8 dB dB dB dB MHz PGIA gain = 0.2 PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 −40 dBFS TA = 25°C TA = 25°C REFEN bit = 1 REFEN bit = 0, REFIN pin = 2.5V AVDD = 5 V ± 5% AVDD = 5 V ± 5% TA = 25°C CREFIN, CREF1, CREF2 = 10 µF||0.1 µF REFEN bit = 0 REFx input, REFIN = 0 V REFIN input (buffered) fS = 500 kSPS VIO > 3 V VIO > 3 V VIO ≤ 3 V VIO ≤ 3 V 4.088 2.495 4.000 4.096 250 ±5 ±1 20 4 2.5 100 4.096 2.5 100 −0.3 0.7 × VIO −0.3 0.9 × VIO −1 −1 Max 4.104 2.505 Unit 1 V µA ppm/°C ppm/°C μV/V ppm V ms 4.104 2.505 V V µA +0.3 × VIO VIO + 0.3 +0.1 × VIO VIO + 0.3 +1 +1 V V V V µA µA ISINK = +500 µA ISOURCE = −500 µA Twos complement 0.4 VIO − 0.3 V V VDDH > input voltage + 2.5 V VSSH < input voltage − 2.5 V 1.8 4.75 4.75 14.25 −15.75 V V V V V Rev. 0 | Page 4 of 32 5 5 15 −15 AVDD + 0.3 5.25 5.25 15.75 −14.25 Data Sheet Parameter IVDDH IVSSH IAVDD IDVDD IVIO Power Supply Sensitivity TEMPERATURE RANGE Specified Performance ADAS3023 Test Conditions/Comments Two channels Four channels Six channels Eight channels PD = 1 Two channels Four channels Six channels Eight channels All PGIA gains, PD = 1 All PGIA gains, PD = 0, reference buffer enabled All PGIA gains, PD = 0, reference buffer disabled All PGIA gains, PD = 1 All PGIA gains, PD = 0 All PGIA gains, PD = 1 All PGIA gains, PD = 0, VIO = 3.3 V All PGIA gains, PD = 1 External reference, TA = 25°C PGIA gain = 0.2 or 0.4, VDDH/VSSH = ±15 V ± 5% PGIA gain = 0.8, VDDH/VSSH = ±15 V ± 5% PGIA gain = 1.6, VDDH/VSSH = ±15 V ± 5% PGIA gain = 0.2 or 0.4, AVDD, DVDD = ±5 V ± 5% PGIA gain = 0.8, AVDD, DVDD = ±5 V ± 5% PGIA gain = 1.6, AVDD, DVDD = ±5 V ± 5% TMIN to TMAX Min −5.5 −6.5 −10.0 −10.0 Typ 5.0 6.0 9.5 9.5 10.0 +5.0 +5.5 −8.5 −8.5 10.0 16.0 10.0 Unit 1 mA mA mA mA µA mA mA mA mA µA mA mA µA mA µA mA µA ±0.1 ±0.2 ±0.4 ±1.0 ±1.5 ±2.5 LSB LSB LSB LSB LSB LSB 100 2.5 100 Max 5.5 7.0 10.5 10.5 17.0 15.5 3 1.0 −40 +85 °C The LSB unit means least significant bit. The weight of the LSB, referred to input, changes depending on the input voltage range. See the Programmable Gain section for the LSB size. 2 Full-scale differential input ranges of ±2.56 V, ±5.12 V, ±10.24 V, and ±20.48 V are set by the configuration register. 3 If using the external multiplexer in front of the ADAS3023, it must be switched at least 820 ns prior to the rising edge of CNV. 4 See the Terminology section. These parameters are specified at ambient temperature with an external reference. All other influences of temperature and supply are measured and specified separately. 5 All ac specifications expressed in decibels are referenced to the full-scale input range (FSR) and are tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 6 This is the output from the internal band gap reference. 7 There is no pipeline delay. Conversion results are available immediately after a conversion is completed. 1 Rev. 0 | Page 5 of 32 ADAS3023 Data Sheet TIMING SPECIFICATIONS VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, Internal Reference VREF = 4.096 V, fS = 500 kSPS, all specifications TMIN to TMAX, unless otherwise noted.1 Table 3. Parameter TIME BETWEEN CONVERSIONS Warp 2 Mode, CMS = 0 Two Channels Four Channels Six Channels Eight Channels Normal Mode (Default), CMS = 1 Two Channels Four Channels Six Channels Eight Channels CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE Warp Mode, CMS = 0 Two Channels Four Channels Six Channels Eight Channels Normal Mode (Default), CMS = 1 Two Channels Four Channels Six Channels Eight Channels CNV Pulse Width CNV High to Hold Time (Aperture Delay) CNV High to BUSY/SDO2 Delay SCK Period Low Time High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 4.5 V VIO > 3 V VIO > 2.7 V VIO > 2.3 V VIO > 1.8 V CS/RESET/PD CS/RESET/PD Low to SDO D15 MSB Valid VIO > 4.5 V VIO > 3 V VIO > 2.7 V VIO > 2.3 V VIO > 1.8 V CS/RESET/PD High to SDO High Impedance CNV Rising to CS Symbol tCYC Min Typ Max Unit 2.0 4.0 6.0 8.0 1000 1000 1000 1000 µs µs µs µs 2.1 4.1 6.1 8.1 1000 1000 1000 1000 µs µs µs µs 1485 2850 4215 5580 1630 3340 5000 6700 ns ns ns ns 1575 2940 4305 5670 1720 3430 5090 6790 ns ns ns ns 520 ns ns ns tCONV tCNVH tAD tCBD 10 tSCK tSCKL tSCKH tSDOH tSDOV tSDOV + 3 5 5 4 2 ns ns ns ns 12 18 24 25 37 ns ns ns ns ns 7 8 10 15 20 25 ns ns ns ns ns ns ns tEN tDIS tCCS Rev. 0 | Page 6 of 32 5 Data Sheet ADAS3023 Parameter DIN DIN Valid Setup Time from SCK Falling Edge DIN Valid Hold Time from SCK Falling Edge RESET/PD HIGH PULSE 1 2 Symbol Min tDINS tDINH tRH 4 4 5 See Figure 2 and Figure 3 for load conditions. Exceeding the maximum time has an effect on the accuracy of the conversion (see the Conversion Modes section). Circuit and Voltage Diagrams 500µA IOL 1.4V TO SDO 500µA 10942-002 CL 50pF IOH Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 12V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V. 20.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V. Figure 3. Voltage Levels for Timing Rev. 0 | Page 7 of 32 10942-003 tDELAY tDELAY Typ Max Unit ns ns ns ADAS3023 Data Sheet Timing Diagrams SOC SOC SOC tCYC EOC EOC tCONV POWER UP PHASE NOTE 1 NOTE 2 CONVERSION (n) ACQUISITION (n + 1) NOTE 1 CONVERSION (n + 1) ACQUISITION (n + 2) CNV tCNVH NOTE 4 tAD NOTE 3 CS 1 16 1 16 1 16 1 16 1 16 1 16 NOTE 2 SCK DIN CFG (n + 2) SDO CH0 BUSY/ SDO2 CFG (n + 3) CH1 CH7 CH0 CH1 CH7 DATA (n) DATA (n + 1) NOTES 1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC). 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED WITH CONVERSION. 3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL. 4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, tAD, SHOULD LAPSE PRIOR TO DATA ACCESS. 10942-004 tCBD Figure 4. General Timing Diagram with BUSY/SDO2 Disabled SOC SOC SOC tCYC EOC EOC tCONV POWER UP PHASE NOTE 1 NOTE 1 CONVERSION (n) ACQUISITION (n + 1) CONVERSION (n + 1) ACQUISITION (n + 2) CNV tCNVH NOTE 4 tAD NOTE 3 1 SCK 16 1 16 1 16 1 16 1 16 1 16 1 16 1 16 NOTE 2 DIN CFG (n + 2) SDO CH0 CH1 CH2 CH3 CFG (n + 3) CH0 CH1 CH2 CH3 BUSY/ SDO2 CH4 CH5 CH6 CH7 CH4 CH5 CH6 CH7 DATA (n + 1) DATA (n) NOTES 1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC). 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED WITH CONVERSION. 3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL. 4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, tAD, SHOULD LAPSE PRIOR TO DATA ACCESS. Figure 5. General Timing Diagram with BUSY/SDO2 Enabled Rev. 0 | Page 8 of 32 10942-005 CS Data Sheet ADAS3023 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Analog Inputs/Outputs INx, COM to AGND REFx to AGND REFIN to AGND REFN to AGND Ground Voltage Differences AGND, RGND, DGND Supply Voltages VDDH to AGND VSSH to AGND AVDD, DVDD, VIO to AGND ACAP, DCAP, RCAP to AGND Digital Inputs/Outputs CNV, DIN, SCK, RESET, PD, CS to DGND SDO, BUSY/SDO2 to DGND Internal Power Dissipation Junction Temperature Storage Temperature Range Thermal Impedance θJA (LFCSP) θJC (LFCSP) Rating VSSH − 0.3 V to VDDH + 0.3 V AGND − 0.3 V to AVDD + 0.3 V AGND − 0.3 V to +2.7 V ±0.3 V ±0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION –0.3 V to +16.5 V +0.3 V to −16.5 V −0.3 V to +7 V −0.3 V to +2.7 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V 2W 125°C −65°C to +125°C 44.1°C/W 0.28°C/W Rev. 0 | Page 9 of 32 ADAS3023 Data Sheet 40 AGND 39 VDDH 38 VSSH 37 REFN 36 REFN 35 RGND 34 REF2 33 REF1 32 REFIN 31 RCAP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADAS3023 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 AGND AGND AVDD DVDD ACAP DCAP AGND AGND DGND DGND NOTES 1. CONNECT THE EXPOSED PAD TO VSSH. 10942-006 CS DIN RESET AGND PD SCK VIO SDO BUSY/SDO2 CNV 11 12 13 14 15 16 17 18 19 20 IN0 1 IN1 2 IN2 3 IN3 4 AGND 5 IN4 6 IN5 7 IN6 8 IN7 9 COM 10 Figure 6. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 to 4 6 to 9 5, 14, 23, 24, 29, 30, 40 10 Mnemonic IN0 to IN3 IN4 to IN7 AGND Type 1 AI AI P Description Input Channel 0 to Input Channel 3. Input Channel 4 to Input Channel 7. Analog Ground. Connect AGND to the system analog ground plane. COM AI 11 CS 12 DIN DI 13 RESET DI 15 PD DI 16 17 SCK VIO DI P 18 SDO DO 19 BUSY/SDO2 DO 20 21, 22 25 CNV DGND DCAP DI P P 26 ACAP P IN0 to IN7 Common Channel Input. Input Channel IN0 to Input Channel IN7 are referenced to a common point. The maximum voltage on this pin is ±10.24 V for all PGIA gains. Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use the CS pin when sharing the serial bus. For a dedicated and simplified ADAS3023 serial interface, tie CS to DGND or CNV. Data Input. DIN is the serial data input for writing the 16-bit configuration (CFG) word that is clocked into the device on the SCK rising edges. The CFG is an internal register that is updated on the rising edge of the next end of a conversion pulse, which coincides with the falling edge of BUSY/SDO2. The CFG register is written into the device on the first 16 clocks after conversion. To avoid corrupting a conversion due to digital activity on the serial bus, do not write data during a conversion. Asynchronous Reset. A low-to-high transition resets the ADAS3023. The current conversion, if active, is aborted and the CFG register is reset to the default state. Power-Down. A low-to-high transition powers down the ADAS3023, minimizing the device operating current. Note that PD must be held high until the user is ready to power on the device. After powering on the device, the user must wait 100 ms until the reference is enabled and then wait for the completion of one dummy conversion before the device is ready to convert. Note that the RESET pin remains low for 100 ns after the release of PD. See the Power-Down Mode section for more information. Serial Clock Input. The DIN and SDO data sent to and from the ADAS3023 are synchronized with SCK. Digital Interface Supply. Nominally, it is recommended that VIO be at the same voltage as the supply of the host interface: 1.8 V, 2.5 V, 3.3 V, or 5 V. Serial Data Output. The conversion result is output on this pin and synchronized to the SCK falling edges. The conversion results are presented on this pin in twos complement format. Busy/Serial Data Output 2. The converter busy signal is always output on the BUSY/SDO2 pin when CS is logic high. If SDO2 is enabled when CS is brought low after the EOC, the SDO outputs the data. The conversion result is output on this pin and synchronized to the SCK falling edges. The conversion results are presented on this pin in twos complement format. Convert Input. A conversion is initiated on the rising edge of the CNV pin. Digital Ground. Connect DGND to the system digital ground plane. Internal 2.5 V Digital Regulator Output. Decouple DCAP, an internally regulated output, using a 10 μF and a 0.1 μF local capacitor. Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and to all of the supporting analog circuits, except for the internal reference. Decouple this internally regulated output (ACAP) using a 10 μF capacitor and a 0.1 μF local capacitor. Rev. 0 | Page 10 of 32 Data Sheet ADAS3023 Pin No. 27 Mnemonic DVDD Type 1 P 28 AVDD P 31 RCAP P 32 REFIN 33, 34 REF1, REF2 AI/O 35 36, 37 RGND REFN P P 38 VSSH P 39 VDDH P EP N/A Description Digital 5 V Supply. Decouple the DVDD supply to DGND using a 10 μF capacitor and 0.1 μF local capacitor. Analog 5 V Supply. Decouple the AVDD supply to AGND using a 10 μF capacitor and 0.1 μF local capacitor. Internal 2.5 V Analog Regulator Output. RCAP supplies power to the internal reference. Decouple this internally regulated output (RCAP) using a 10 μF capacitor and a 0.1 μF local capacitor. Internal 2.5 V Band Gap Reference Output, Reference Buffer Input, or Reference Power-Down Input. REF1 and REF2 must be tied together externally. See the Voltage Reference Input/Output section for more information. Reference Input/Output. Regardless of the reference method, REF1 and REF2 need individual decoupling using external 10 μF ceramic capacitors connected as close to REF1, REF2, and REFN as possible. See the Voltage Reference Input/Output section for more information. Reference Supply Ground. Connect RGND to the system analog ground plane. Reference Input/Output Ground. Connect the 10 μF capacitors that are on REF1 and REF2 to the REFN pins, then connect the REFN pins to the system analog ground plane. High Voltage Analog Negative Supply. Nominally, the supply of VSSH is −15 V. Decouple VSSH using a 10 μF capacitor and a 0.1 μF local capacitor. Connect the exposed pad to VSSH. High Voltage Analog Positive Supply. Nominally, the supply of VDDH is 15 V. Decouple VDDH using a 10 μF capacitor and a 0.1 μF local capacitor. Exposed Pad. Connect the exposed pad to VSSH. AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, P = power, and N/A means not applicable. 1 Rev. 0 | Page 11 of 32 ADAS3023 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDDH = 15 V, VSSH = −15 V, AVDD = DVDD = 5 V, VIO = 1.8 V to AVDD, unless otherwise noted. 400000 350000 300000 0.5 250000 24576 32768 40960 49152 57344 65536 CODE 0 0 0 0 962 1481 1 0 0 CODE IN HEX Figure 10. Histogram of a DC Input at Code Center, PGIA Gain = 0.4 1.00 400000 0.75 350000 0.50 300000 0.25 250000 COUNT 0 PGIA GAIN = 0.8 fS = 500kSPS INTERNAL REFERENCE 248346 188714 200000 –0.25 150000 –0.50 100000 43158 50000 2 0 0 8006 8007 908 8005 201 8004 0 8003 0 8002 CODE 0 8001 57344 65536 8000 49152 7FFF 40960 10942-102 32768 7FFE 18671 7FFD CODE IN HEX Figure 8. Differential Nonlinearity (DNL) vs. Code for All PGIA Gains 300000 350000 300000 278780 250000 200000 150000 150000 100000 100000 50000 50000 185455 171423 CODE IN HEX 9497 6254 238 806D 8069 56261 806C 450 806B 6 806A 0 8068 0 10942-103 0 8007 8000 0 8006 7FFF 7 8005 7FFE 6909 8004 83 8003 0 8002 0 8001 0 7FFD 0 23813 8067 70413 3 8071 190408 200000 8070 COUNT 250000 COUNT PGIA GAIN = 1.6 fS = 500kSPS INTERNAL REFERENCE 806F 350000 400000 PGIA GAIN = 0.2 fS = 500kSPS INTERNAL REFERENCE 806E 400000 Figure 11. Histogram of a DC Input at Code Center, PGIA Gain = 0.8 CODE IN HEX Figure 12. Histogram of a DC Input at Code Center, PGIA Gain = 1.6 Figure 9. Histogram of a DC Input at Code Center, PGIA Gain = 0.2 Rev. 0 | Page 12 of 32 10942-106 DNL (LSB) Figure 7. Integral Nonlinearity (INL) vs. Code for All PGIA Gains –0.75 FOR ALL PGIA GAINS DNL MAX = 0.794 DNL MIN = –0.661 –1.00 0 8192 16384 24576 10942-104 16384 10942-105 8192 8001 0 8000 50000 7FFF –1.5 97631 74640 7FFE 100000 7FFD –1.0 7FFC 150000 7FFB –0.5 –2.0 325285 200000 7FFA 0 PGIA GAIN = 0.4 fS = 500kSPS INTERNAL REFERENCE 7FF9 COUNT 1.0 10942-101 INL (LSB) 1.5 7FF8 FOR ALL PGIA GAINS INL MAX = 0.875 INL MIN = –1.216 7FF7 2.0 Data Sheet ADAS3023 60 0 PGIA GAIN = 0.4 fS = 500kSPS fIN = 1.12kHz SNR = 91.2dB SINAD = 91.1dB THD = –107.0dB SFDR = 106.0dB INTERNAL REFERENCE –20 50 AMPLITUDE (dBFS) –40 30 20 0 1 2 3 4 5 –100 6 5 7 6 8 –140 2 3 9 10 11 12 13 14 15 2 3 REFERENCE DRIFT (ppm/°C) –160 0 50 100 60 0 –20 AMPLITUDE (dBFS) –40 28 20 –60 –80 –100 –120 13 10 –140 0 1 2 3 1 4 5 6 7 8 9 10 11 12 13 14 15 REFERENCE BUFFER DRIFT (ppm/°C) –160 10942-117 0 2 0 50 100 0 PGIA GAIN = 0.2 fS = 500kSPS fIN = 1.12kHz SNR = 91.3dB SINAD = 91.3dB THD = –110.6dB SFDR = 106.6dB INTERNAL REFERENCE –40 –60 –40 –80 –100 –60 –80 –100 –120 –140 –140 –160 50 100 150 200 FREQUENCY (kHz) 250 10942-107 –120 0 250 PGIA GAIN = 1.6 fS = 500kSPS fIN = 1.12kHz SNR = 87.3dB SINAD = 87.2dB THD = –103.0dB SFDR = 106.0dB INTERNAL REFERENCE –20 AMPLITUDE (dBFS) –20 200 Figure 17. 1 kHz FFT, PGIA Gain = 0.8 Figure 14. Reference Buffer Drift, Internal Reference 0 150 FREQUENCY (kHz) 10942-109 COUNT 40 AMPLITUDE (dBFS) 250 PGIA GAIN = 0.8 fS = 500kSPS fIN = 1.12kHz SNR = 89.7dB SINAD = 89.6dB THD = –104.0dB SFDR = 105.0dB INTERNAL REFERENCE 46 30 200 Figure 16. 1 kHz FFT, PGIA Gain = 0.4 Figure 13. Reference Drift, Internal Reference 50 150 FREQUENCY (kHz) 10942-108 3 0 –80 –120 11 10 10942-116 14 15 13 13 –60 –160 0 50 100 150 200 FREQUENCY (kHz) Figure 18. 1 kHz FFT, PGIA Gain = 1.6 Figure 15. 1 kHz FFT, PGIA Gain = 0.2 Rev. 0 | Page 13 of 32 250 10942-110 COUNT 40 –80 CH1, CH3, CH4, CH4, CH4, 2 ACTIVE CHANNELS, 4 ACTIVE CHANNELS, 6 ACTIVE CHANNELS, 8 ACTIVE CHANNELS, 8 ACTIVE CHANNELS, 500kSPS, 200kSPS, 100kSPS, 100kSPS, 100kSPS, PGIA GAIN = PGIA GAIN = PGIA GAIN = PGIA GAIN = PGIA GAIN = 0.8 0.8 0.8 0.2 0.4 VSSH CURRENT (mA) CROSSTALK (dB) –85 Data Sheet –90 –95 –100 CH4, 8 ACTIVE CHANNELS, 100kSPS, PGIA GAIN = 0.8 CH4, 8 ACTIVE CHANNELS, 100kSPS, PGIA GAIN = 1.6 1k 10k 100k 1M FREQUENCY (Hz) 10942-113 –105 100 –2.0 VSSH = –15V –2.5 –3.0 2 ACTIVE CHANNELS, PGIA GAIN = 0.2 –3.5 2 ACTIVE CHANNELS, PGIA GAIN = 1.6 –4.0 –4.5 –5.0 4 ACTIVE CHANNELS, PGIA GAIN = 0.2 –5.5 4 ACTIVE CHANNELS, PGIA GAIN = 1.6 –6.0 –6.5 –7.0 8 ACTIVE CHANNELS, PGIA GAIN = 0.2 –7.5 6 ACTIVE CHANNELS, PGIA GAIN = 0.2 –8.0 –8.5 –9.0 8 ACTIVE CHANNELS, PGIA GAIN = 1.6 –9.5 –10.0 6 ACTIVE CHANNELS, PGIA GAIN = 1.6 –10.5 –11.0 10 100 1000 THROUGHPUT (kSPS) Figure 19. Crosstalk vs. Frequency 110 Figure 22. VSSH Current vs. Throughput 20 PGIA GAIN = 0.2 PGIA GAIN = 0.4 PGIA GAIN = 0.8 PGIA GAIN = 1.6 100 AVDD = 5V 19 18 AVDD CURRENT (mA) 90 CMRR (dB) 10942-118 ADAS3023 80 70 60 17 16 INTERNAL REFERENCE 15 14 13 EXTERNAL REFERENCE 12 50 10 100 1k 10k FREQUENCY (Hz) 10 10 THROUGHPUT (kSPS) 1000 Figure 23. AVDD Current vs. Throughput 3.5 DVDD = 5V 3.2 DVDD CURRENT (mA) 2.9 2.6 2.3 2.0 1.7 1.4 1.1 0.8 10942-115 VDDH CURRENT (mA) Figure 20. CMRR vs. Frequency 11.0 6 ACTIVE CHANNELS, PGIA GAIN = 1.6 10.5 VDDH = 15V 10.0 8 ACTIVE CHANNELS, PGIA GAIN = 1.6 9.5 9.0 8.5 6 ACTIVE CHANNELS, PGIA GAIN = 0.2 8.0 8 ACTIVE CHANNELS, PGIA GAIN = 0.2 7.5 7.0 6.5 6.0 4 ACTIVE CHANNELS, PGIA GAIN = 1.6 5.5 5.0 4.5 4 ACTIVE CHANNELS, PGIA GAIN = 0.2 4.0 2 ACTIVE CHANNELS, PGIA GAIN = 1.6 3.5 3.0 2.5 2 ACTIVE CHANNELS, PGIA GAIN = 0.2 2.0 10 100 1000 100 THROUGHPUT (kSPS) Figure 21. VDDH Current vs. Throughput 0.5 10 100 THROUGHPUT (kSPS) Figure 24. DVDD Current vs. Throughput Rev. 0 | Page 14 of 32 1000 10942-120 1 10942-114 40 10942-119 11 Data Sheet ADAS3023 –4 130 120 110 90 100 80 70 60 50 40 30 20 0 –3 –4 CH0 CH4 CH1 CH5 CH2 CH6 CH3 CH7 130 10942-123 10942-124 120 110 100 90 80 70 60 50 40 30 20 –5 130 TEMPERATURE (°C) –2 10 130 120 110 100 90 80 70 60 50 40 30 20 10 0 –10 –20 –30 –40 –50 –60 –120 10942-112 –115 0 –1 0 –110 1 –10 –105 2 –20 –100 3 TEMPERATURE (°C) Figure 26. THD vs. Temperature Figure 29. Normalized Offset Error Drift, PGIA Gain = 0.8 5 10 CH0 CH4 CH1 CH5 CH2 CH6 CH3 CH7 120 110 100 90 80 70 –10 60 130 120 110 100 90 80 70 60 50 40 30 20 10 0 –10 –20 –30 –40 –50 –60 TEMPERATURE (°C) Figure 27. Normalized Offset Error Drift, PGIA GAin = 0.2 –8 50 CH3 CH7 40 CH2 CH6 30 CH1 CH5 –6 20 CH0 CH4 –5 10942-121 –4 –4 10 –3 0 –2 0 –2 2 –10 0 –1 4 –20 1 6 –30 2 PGIA GAIN = 1.6 EXTERNAL REFERENCE fS = 125kSPS TA = 25°C 8 –40 3 NORMALIZED OFFSET ERROR DRIFT (LSB) PGIA GAIN = 0.2 EXTERNAL REFERENCE fS = 125kSPS TA = 25°C 4 –50 THD (dB) –95 PGIA GAIN = 0.8 EXTERNAL REFERENCE fS = 125kSPS TA = 25°C 4 –30 –90 NORMALIZED OFFSET ERROR DRIFT (LSB) CH3 CH7 5 PGIA GAIN = 0.4, fS = 500kSPS PGIA GAIN = 0.8, fS = 250kSPS PGIA GAIN = 0.8, fS = 125kSPS PGIA GAIN = 1.6, fS = 167kSPS –60 –85 CH2 CH6 Figure 28. Normalized Offset Error Drift, PGIA Gain = 0.4 NORMALIZED OFFSET ERROR DRIFT (LSB) CH1, CH2, CH5, CH3, CH1 CH5 TEMPERATURE (°C) Figure 25. SNR vs. Temperature –80 CH0 CH4 –5 10942-122 TEMPERATURE (°C) –3 10 130 120 110 90 100 80 70 60 50 40 30 20 0 10 –10 –20 –30 –40 –50 –60 80 10942-111 82 –2 –10 84 –1 –20 86 0 –30 88 1 –40 90 –50 92 2 –60 SNR (dB) 94 3 –40 96 PGIA GAIN = 0.4 EXTERNAL REFERENCE fS = 125kSPS TA = 25°C 4 –60 98 5 PGIA GAIN = 0.4, fS = 500kSPS PGIA GAIN = 0.8, fS = 250kSPS PGIA GAIN = 0.8, fS = 125kSPS PGIA GAIN = 1.6, fS = 167kSPS –50 CH1, CH2, CH5, CH3, NORMALIZED OFFSET ERROR DRIFT (LSB) 100 TEMPERATURE (°C) Figure 30. Normalized Offset Error Drift, PGIA Gain = 1.6 Rev. 0 | Page 15 of 32 ADAS3023 Data Sheet 5 CH2 CH6 CH3 CH7 130 120 110 90 100 80 10942-127 CH1 CH5 TEMPERATURE (°C) Figure 31. Normalized Gain Error Drift Error, PGIA Gain = 0.2 Figure 33. Normalized Gain Error Drift Error, PGIA Gain = 0.8 5 10 CH0 CH4 CH1 CH5 CH2 CH6 CH3 CH7 130 120 110 100 90 80 70 60 50 –10 TEMPERATURE (°C) Figure 34. Normalized Gain Error Drift Error, PGIA Gain = 1.6 Rev. 0 | Page 16 of 32 10942-128 TEMPERATURE (°C) Figure 32. Normalized Gain Error Drift Error, PGIA Gain = 0.4 –8 40 130 120 110 100 90 80 70 60 50 40 30 20 10 0 –10 –20 –30 –40 –50 –5 –6 30 CH3 CH7 20 CH2 CH6 10 CH1 CH5 0 CH0 CH4 10942-126 –4 –4 –10 –3 0 –2 –20 –2 2 –30 0 –1 4 –40 1 6 –50 2 PGIA GAIN = 1.6 EXTERNAL REFERENCE fS = 125kSPS TA = 25°C 8 –60 3 NORMALIZED GAIN ERROR DRIFT (LSB) PGIA GAIN = 0.4 EXTERNAL REFERENCE fS = 125kSPS TA = 25°C 4 –60 NORMALIZED GAIN ERROR DRIFT (LSB) CH0 CH4 –5 70 130 120 110 90 100 80 70 60 50 40 30 20 0 10 –10 –20 –30 –40 –50 –60 TEMPERATURE (°C) –4 60 CH3 CH7 50 CH2 CH6 30 CH1 CH5 40 CH0 CH4 –5 –3 20 –4 –2 0 –3 –1 10 –2 0 –10 –1 1 –20 0 –30 1 2 –40 2 3 –50 3 PGIA GAIN = 0.8 EXTERNAL REFERENCE fS = 125kSPS TA = 25°C 4 –60 4 NORMALIZED GAIN ERROR DRIFT (LSB) PGIA GAIN = 0.2 EXTERNAL REFERENCE fS = 125kSPS TA = 25°C 10942-125 NORMALIZED GAIN ERROR DRIFT (LSB) 5 Data Sheet ADAS3023 TERMINOLOGY Operating Input Voltage Range Operating input voltage range is the maximum input voltage range, including common-mode, which can be applied to the input channels, IN0 to IN7, and COM. Differential Input Voltage Range Differential input voltage range is the maximum differential full-scale input range. The value changes according to the selected programmable gain setting. Channel Off Leakage Channel off leakage is the leakage current with the channel turned off. Channel On Leakage Channel on leakage is the leakage current with the channel turned on. Common-Mode Rejection Ratio (CMRR) CMRR is computed as the ratio of the signal magnitude of the converted result, referred to input, in the converted result to the amplitude of the common modulation signal applied to an input pair, expressed in decibels. CMRR is a measure of the ability of the ADAS3023 to reject signals, such as power line noise, that are common to the inputs. This specification is tested and specified for all input channels, IN0 to IN7, with respect to COM. Transient Response Transient response is a measure of the time required for the ADAS3023 to properly acquire the input after a full-scale step function is applied to the system. Least Significant Bit (LSB) The LSB is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is 2V LSB (V) = REF 2N Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 37). Offset Error Ideally, the MSB transition occurs at an input level that is ½ LSB above analog ground. The offset error is the deviation of the actual transition from that point. Gain Error Ideally, the last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation in LSB (or percentage of full-scale range) of the actual level of the last transition from the ideal level after the offset error is removed. Closely related is the fullscale error (also in LSB or percentage of full-scale range), which includes the effects of the offset error. Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with a −60 dBFS input signal applied to the inputs. The value for dynamic range is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed. Rev. 0 | Page 17 of 32 ADAS3023 Data Sheet Channel-to-Channel Crosstalk Channel-to-channel crosstalk is a measure of the level of crosstalk between any channel and all other channels. The crosstalk is measured by applying a dc input to the channel under test and applying a full-scale, 10 kHz sine wave signal to all other channels. The crosstalk is the amount of signal that leaks into the test channel expressed in decibels. Reference Voltage Temperature Coefficient The reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of devices at the maximum and minimum reference output voltage (VREF) measured at TMIN, TA (25°C), and TMAX expressed in ppm/°C. TCV REF (ppm/°C) = V REF ( Max ) – V REF ( Min) V REF (25°C ) × (T MAX – TMIN ) × 10 6 where: VREF (Max) is the maximum VREF at TMIN, TA (25°C), or TMAX. VREF (Min) is the minimum VREF at TMIN, TA (25°C), or TMAX. VREF (25°C) = VREF at 25°C. TMAX = +85°C. TMIN = −40°C. Rev. 0 | Page 18 of 32 Data Sheet ADAS3023 THEORY OF OPERATION OVERVIEW The ADAS3023 offers true high impedance inputs in a differential structure and rejects common-mode signals present on the inputs. This architecture does not require additional input buffers (op amps) that are usually required for signal buffering, level shifting, amplification, attenuation, and kickback reduction when using switched capacitor-based SAR ADCs. The ADAS3023 is a 16-bit, 8-channel simultaneous system on a single chip that integrates the typical components used in a data acquisition system in one easy to use, programmable device. It is capable of converting two channels simultaneously up to 500,000 samples per second (500 kSPS) throughput. The ADAS3023 features • • High impedance inputs High common-mode rejection An 8-channel, low leakage track and hold A programmable gain instrumentation amplifier (PGIA) with four selectable differential input ranges from ±2.56 V to ±20.48 V A 16-bit PulSAR® ADC with no missing codes An internal, precision, low drift 4.096 V reference and buffer The conversion results are output in twos complement format on the serial data output (SDO) and through an optional secondary serial data output on the BUSY/SDO2 pin. The digital interface uses a dedicated chip select (CS) to control data access to and from the ADAS3023 together with a BUSY/SDO2 output, asynchronous reset (RESET), and power-down (PD) inputs. The internal reference of the ADAS3023 uses an internal temperature compensated 2.5 V output band gap reference, followed by a precision buffer amplifier to provide the 4.096 V high precision system reference. The ADAS3023 uses the Analog Devices patented high voltage iCMOS process allowing up to a ±20.48 V differential input voltage range when using ±15 V supplies, which makes the device suitable for industrial applications. All of these components are configured through a serial (SPIcompatible), 16-bit CFG register. Configuration and conversion results are read after the conversions are completed. The device is housed in a small 6 mm × 6 mm, 40-lead LFCSP package and can operate over the industrial temperature range of −40°C to +85°C. A typical discrete multichannel data acquisition system containing similar circuitry requires more space on the circuit board than the ADAS3023. Therefore, advantages of the ADAS3023 solution include a reduced footprint and less complex design requirements, leading to faster time to market and lower costs. The ADAS3023 requires a minimum of three power supplies +15 V, −15 V, and +5 V. Internal low dropout regulators provide the necessary 2.5 V system voltages that must be decoupled externally via dedicated pins (ACAP, DCAP, and RCAP). The ADAS3023 can be interfaced to any 1.8 V to 5 V digital logic family using the dedicated VIO logic level voltage supply (see Table 9). OPERATION A rising edge on the CNV pin initiates a conversion and changes the ADAS3023 from track to hold. In this state, the ADAS3023 performs the analog signal conditioning and conversion. When the signal conditioning is completed, the ADAS3023 returns to the track state while, at the same time, quantizes the sample. This two-tiered process satisfies the necessary settling time requirement and achieves a fast throughput rate of up to 500 kSPS with 16-bit accuracy. The analog circuitry of the ADAS3023 consists of a high impedance, low leakage, track-and-hold PGIA with a high common-mode rejection that can accept the full-scale differential voltages of ±2.56 V, ±5.12 V, ±10.24 V, and ±20.48 V (see Figure 15). The ADAS3023 can be configured to sample two, four, six, or eight channels simultaneously. VDDH AVDD DVDD DIFF TO COM IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM VIO RESET PD CNV LOGIC/ INTERFACE BUSY CS TRACK AND HOLD PulSAR ADC PGIA SCK DIN SDO ADAS3023 REFIN BUF REF VSSH AGND DGND REFx Figure 35. Simplified Block Diagram Rev. 0 | Page 19 of 32 10942-007 • • • • Digital control of the programmable gain setting of each channel input is set via the configuration (CFG) register. ADAS3023 Data Sheet TRANSFER FUNCTIONS CONVERSION ACQUISITION PHASE 10942-008 CNV Figure 36. System Timing Regardless of the type of signal, (single-ended symmetric or asymmetric), the ADAS3023 converts all signals present on the enabled inputs and COM pin in a differential fashion identical to an industry-standard difference or instrumentation amplifier. The conversion results are available after the conversion is complete and can be read back at any time before the end of the next conversion. Avoid reading back data during the quiet period, indicated by BUSY/SDO2 being active high. Because the ADAS3023 has an on-board conversion clock, the serial clock (SCK) is not required for the conversion process; it is only required to present results to the user. The ideal transfer characteristic for the ADAS3023 is shown in Figure 37. The inputs are configured for differential input ranges and the data outputs are in twos complement format, as listed in Table 6. TWOS STRAIGHT COMPLEMENT BINARY 011...111 111...111 011...110 011...101 111...110 111...101 100...010 000...010 100...001 000...001 100...000 000...000 –FSR –FSR + 1LSB –FSR + 0.5LSB +FSR – 1LSB +FSR – 1.5LSB ANALOG INPUT Figure 37. ADC Ideal Transfer Function Table 6. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR Differential Analog Inputs, VREF = 4.096 V (32,767 × VREF)/(32,768 × PGIA gain) (VREF/(32,768 × PGIA gain)) 0 −(VREF/(32,768 × PGIA gain)) −(32,767 × VREF)/(32,768 × PGIA gain) −VREF × PGIA gain Rev. 0 | Page 20 of 32 Digital Output Code (Twos Complement Hex) 0x7FFF 0x0001 0x0000 0xFFFF 0x8001 0x8000 10942-009 tACQ ADC CODE tCYC tCONV Data Sheet ADAS3023 D2 + L2 47µH COUT3 4.7µF C2 1µF + 1.78Ω RFILT L1 47µH +5V VIN = +5V + D1 CIN + 1µF L3 C1 1µF 1µF COUT1 + 1µF RB0 1Ω +15V + COUT2 2.2µF VDDH 50kΩ ADP1613 COMP + VIO RESET PD CC2 10pF R C1 100kΩ DIFF TO COM RS1 0Ω IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 SS FB FREQ EN VIN GND SW CNV LOGIC/ INTERFACE CS TRACK AND HOLD RF2 4.22kΩ CSS + 1µF SCK PulSAR ADC PGIA DIN SDO REFIN BUF COM CV5 + RS2 DNI 1µF BUSY ADAS3023 REF Z1 DNI VSSH AGND DGND +5V +5V 4.096V –15V RF1B 47.5kΩ REFx + ADR434 – 10942-200 ENABLE C C1 + 12nF AVDD DVDD REN AD8031 Figure 38. Complete 5 V, Single-Supply, 8-Channel Data Acquisition System with PGIA TYPICAL APPLICATION CONNECTION DIAGRAM TRACK AND HOLD INx OR COM PGIA CPIN VSSH ANALOG INPUTS 10942-010 As shown in Figure 38, the ADP1613 is used in an inexpensive SEPIC-Ćuk topology, which is an ideal candidate for providing the ADAS3023 with the necessary high voltage ±15 V robust supplies (at 20 mA) and low output ripple (3 mV maximum) from an external 5 V supply. The ADP1613 satisfies the specification requirements of the ADAS3023 using minimal external components yet achieves greater than 86% efficiency. See the CN-0201 circuit note for complete information about this test setup. VDDH AGND Input Structure Figure 39. Equivalent Analog Input Circuit The ADAS3023 uses a differential input structure between each of the channel inputs, IN0 to IN7, and a common reference (COM), all of which sample simultaneously. Figure 39 shows an equivalent circuit of the inputs. The diodes provide ESD protection for the analog inputs (IN0 to IN7) and COM from the high voltage supplies (VDDH and VSSH). Ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this can cause the diodes to become forward-biased and to start conducting current. The voltages beyond the absolute maximum ratings may cause permanent damage to the ADAS3023 (see Table 4). Programmable Gain The ADAS3023 incorporates a programmable gain instrumentation amplifier (PGIA) with four selectable ranges. The PGIA settings are specified in terms of the maximum absolute differential input voltage across an input pin and the COM pin, for example INx to COM. The power on and default conditions are preset to the ±20.48 V (PGIA = 11) input range. Note that because the ADAS3023 can use any input type, such as bipolar single-ended and pseudo bipolar, setting the PGIA is important to make full use of the allowable input span. Rev. 0 | Page 21 of 32 ADAS3023 Data Sheet Table 7 describes each differential input range and the corresponding LSB size, PGIA bit settings, and PGIA gain. INx+ +2.56V 0V Table 7. Differential Input Ranges, LSB Size, and PGIA Settings Differential Input Ranges, INx − COM (V) ±20.48 ±10.24 ±5.12 ±2.56 LSB (μV) 625 312.5 156.3 78.13 Common-Mode Operating Range The differential input common-mode range changes according to the input range selected for a given channel and the high voltage power supplies. Note that the operating input voltage of any input pin, as defined in the Specifications section, requires a minimum of 2.5 V of headroom from the VDDH/VSSH supplies or The following sections offer some examples of setting the PGIA for various input signals. Note that the ADAS3023 always takes the difference between the INx and COM signals. Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) When a 5.12 V p-p signal with a 2.56 V dc offset is connected to one of the inputs (INx+) and the dc ground sense of the signal is connected to COM, the PGIA gain configuration is set to 01 for the ±5.12 V range because the maximum differential voltage across the inputs is +5.12 V. This scenario uses only half the codes available for the transfer function. 5.12V p-p ADAS3023 VOFF COM COM 10942-011 VOFF 0V 10942-012 Figure 41. Optimal Single-Ended Configuration Using All Codes Notice that the voltages in the examples are not integer values due to the 4.096 V reference and the scaling ratios of the PGIA. The maximum allowed dc offset voltage on the COM input pin for various PGIA gains in this case is shown in Table 8. Table 8. DC Offset Voltage on COM Input and PGIA Settings1 PGIA Gain (V/V) 0.2 0.4 0.8 1.6 DC Offset Voltage on COM (V) 0 0 ±5.12 ±7.68 Full-scale signal on INx. VOLTAGE REFERENCE INPUT/OUTPUT The ADAS3023 allows the choice of an internal reference, an external reference using an internal buffer, or an external reference. The internal reference of the ADAS3023 provides excellent performance and can be used in nearly any application. Setting the reference selection mode uses the internal reference enable bit, REFEN, and the REFIN pin as described in the following sections (Internal Reference, External Reference and Internal Buffer, External Reference, and Reference Decoupling). Internal Reference The precision internal reference is factory trimmed and is suitable for most applications. INx+ +5.12V COM 1 (VSSH + 2.5 V) ≤ INx/COM ≤ (VDDH – 2.5 V) INx+ ADAS3023 5.12V p-p COM –2.56V PGIA Gain (V/V) 0.2 0.4 0.8 1.6 PGIA CFG 11 00 01 10 INx+ Figure 40. Typical Single-Ended Unipolar Input Using Only Half of the Codes Single-Ended Signals with a 0 V DC Offset (Symmetrical) Compared with the example in the Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) section, a better solution for single-ended signals, when possible, is to remove as much differential dc offset between INx and COM such that the average voltage is 0 V (symmetrical around the ground sense). The differential voltage across the inputs is never greater than ±2.56 V, and the PGIA gain configuration is set for a ±2.56 V range (10). This scenario uses all of the codes available for the transfer function, making full use of the allowable differential input range. Setting the REFEN bit in the CFG register to 1 (default) enables the internal reference and produces 4.096 V on the REF1 and REF2 pins; this 4.096 V output serves as the main system reference. The unbuffered 2.5 V (typical) band gap reference voltage is output on the REFIN pin, which requires an external parallel combination of 10 μF and 0.1 μF capacitors to reduce the noise on the output. Because the current output of REFIN is limited, it can be used as a source when followed by a suitable buffer, such as the AD8031. Note that excessive loading of the REFIN output lowers the 4.096 V system reference because the internal amplifier uses a fixed gain. The internal reference output is trimmed to the targeted value of 4.096 V with an initial accuracy of ±8 mV. The reference is also temperature compensated to provide a typical drift of ±5 ppm/°C. When the internal reference is used, decouple the ADAS3023, as shown in Figure 42. Note that both the REF1 and REF2 connections are shorted together and externally decoupled with Rev. 0 | Page 22 of 32 Data Sheet ADAS3023 loading for op amps usually refers to the ability of the amplifier to remain marginally stable in ac applications but can also play a role in dc applications, such as a reference source. suitable decoupling on the REFIN output and the RCAP internally regulated supply. 0.1µF 0.1µF 0.1µF 10µF REFN REFN REF2 Keep in mind that the reference source sees the dynamics of the bit decision process on the reference pins and further analysis beyond the scope of this data sheet may be required. 10µF 10µF REF1 REFIN REFN REFERENCE SOURCE = 4.096V BAND GAP 0.1µF 0.1µF RCAP 1µF 10µF 10942-013 ADAS3023 RGND REFN 10µF REF2 REFN REFIN REF1 Figure 42. 4.096V Internal Reference Connection ADAS3023 The external reference and internal buffer are useful where a common system reference is used or when improved drift performance is required. Setting Bit REFEN to 0 disables the internal band gap reference, allowing the user to provide an external voltage reference (2.5 V typical) to the REFIN pin. The internal buffer remains enabled, thus reducing the need for an external buffer amplifier to generate the main system reference. Where REFIN = 2.5 V and REF1 and REF2 output 4.096 V, this serves as the main system reference. For this configuration, connect the external source, as shown in Figure 43. Any type of 2.5 V reference can be used in this configuration (low power, low drift, small package, and so forth) because the internal buffer handles the dynamics of the ADAS3023 reference requirements. REFN 0.1µF 10µF REF2 REFN ADAS3023 0.1µF 10µF REF1 REFN BAND GAP REFERENCE SOURCE = 2.5V REFIN RCAP 1µF RGND 10942-014 0.1µF 10µF Figure 43. External Reference Using Internal Buffer External Reference For applications that require a precise, low drift, 4.096 V reference, an external reference can be used. Note that in this mode, disabling the internal buffer requires setting REFEN to 0, and driving or connecting REFIN to AGND; thus, both hardware and software control are necessary. Attempting to drive the REF1 and REF2 pins alone prior to disabling the internal buffer can cause source/sink contention in the outputs of the driving amplifiers. Connect the precision 4.096 V reference directly to REF1 and REF2, which are the main system reference (see Figure 44); two recommended references are the ADR434 or ADR444. If an op amp is used as an external reference source, take note of the concerns regarding driving capacitive loads. Capacitive BAND GAP RGND RCAP 1µF 10942-015 External Reference and Internal Buffer Figure 44. External Reference Reference Decoupling With any of the reference topologies described in the Voltage Reference Input/Output section, the REF1 and REF2 reference pins of the ADAS3023 have dynamic impedances and require sufficient decoupling, regardless of whether the pins are used as inputs or outputs. This decoupling usually consists of a low ESR capacitor connected to each REF1 and REF2 pin and to the accompanying REFN return paths. Ceramic chip capacitors (X5R, 1206 size) are recommended for decoupling in all of the reference topologies described in the Voltage Reference Input/Output section. The placement of the reference decoupling capacitors plays an important role in system performance. Using thick printed circuit board (PCB) traces, mount the decoupling capacitors on the same side as the ADAS3023, close to the REF1 and REF2 pins. Route the return paths to the REFN inputs that, in turn, connect to the analog ground plane of the system. When it is necessary to connect to an internal PCB, minimize the resistance of the return path to ground by using as many through vias as possible. Using the shortest distance and several vias, connect the REFN and RGND inputs to the analog ground plane of the system, preferably adjacent to the solder pads. One common mistake is to route these traces to an individual trace that connects to the ground of the system. This can introduce noise, which may adversely affect the LSB sensitivity. To prevent such noise, use PCBs with multiple layers, including ground planes, rather than using single or double sided boards. Smaller reference decoupling capacitor values (as low as 2.2 µF) can be used with little impact, mainly on DNL and THD. Furthermore, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) that is common in decoupling schemes for high frequency noise rejection. For applications that use multiple ADAS3023 devices or other PulSAR ADCs, using the internal reference buffer is most effective Rev. 0 | Page 23 of 32 ADAS3023 Data Sheet to buffer the external reference voltage and, thereby, reduce SAR conversion crosstalk. VIO is the variable digital input/output supply and allows direct interface with any logic between 1.8 V and 5 V (DVDD supply maximum). To reduce the supplies that are required, VIO can, alternatively, be connected to DVDD when DVDD is supplied from the analog supply through an RC filter. The recommended low dropout regulators are ADP3334, ADP1715, ADP7102, and ADP7104 for the AVDD, DVDD, and VIO supplies. Note that the user must bring up the ADAS3023 power supplies in the following sequence: The voltage reference temperature coefficient (TC) directly affects the full-scale accuracy of the system; therefore, in applications where full-scale accuracy is crucial, care must be taken with the TC. For example, a ±15 ppm/°C TC of the reference changes the full-scale accuracy by ±1 LSB/°C. POWER SUPPLY The ADAS3023 uses five supplies: AVDD, DVDD, VIO, VDDH, and VSSH (see Table 9). Note that the ACAP, DCAP, and RCAP pins are for informational purposes only because they are the outputs of the internal supply regulators. Table 9. Supplies Mnemonic AVDD DVDD Function Analog 5 V core Digital 5 V core VIO Digital input/output VDDH VSSH Positive high voltage Negative high voltage Analog 2.5 V core Digital 2.5 V core Analog 2.5 V core ACAP DCAP RCAP Required Yes Yes, or can connect to AVDD Yes, and can connect to DVDD (for the 5 V level) Yes, +15 V typical Yes, −15 V typical The high voltage bipolar supplies, VDDH and VSSH, are required and must be at least 2.5 V larger than the maximum operating input voltage. Specifically, any operating input voltage (as defined in Table 2) of an input pin requires 2.5 V of headroom from the VDDH/VSSH supplies or (VSSH + 2.5 V) ≤ INx/COM ≤ (VDDH − 2.5 V) No, on chip No, on chip No, on chip Sufficient decoupling of these supplies is also required, consisting of at least a 10 μF capacitor and 100 nF capacitor on each supply. POWER DISSIPATION MODES The ADAS3023 offers two power dissipation modes: fully operational mode and power-down mode. The AVDD and DVDD pins supply the ADAS3023 analog and digital cores, respectively. Sufficient decoupling of these supplies is required, consisting of at least a 10 μF capacitor and 100 nF capacitor on each supply. Place the 100 nF capacitors as close as possible to the ADAS3023. To reduce the number of supplies that are required, supply the DVDD from the analog supply by connecting a simple RC filter between AVDD and DVDD, as shown in Figure 45. 20Ω 10µF + 10µF 100nF +1.8V TO +5V DIGITAL I/O SUPPLY 10µF –15V VIO VDDH + + Power-Down Mode 100nF 100nF 10µF + ADAS3023 100nF DGND VSSH 10942-016 10µF In fully operational mode, the ADAS3023 can perform the conversions normally. 100nF AVDD AGND DVDD DGND +15V Fully Operational Mode +5V DIGITAL SUPPLY + Figure 45. Supply Connections VIO VDDH VSSH DVDD AVDD REFx High Voltage Supplies Core Supplies +5V ANALOG SUPPLY 1. 2. 3. 4. 5. 6. To minimize the operating currents of the device when it is idle, place the device in full power-down mode by bringing the PD input high; this places the ADAS3023 into a deep sleep mode in which CNV activity is ignored and the digital interface is inactive. Refer to the RESET and Power-Down (PD) Inputs section for timing details. In deep sleep mode, the internal regulators (ACAP, RCAP, and DCAP) and the voltage reference are powered down. To reestablish operation, return PD to logic low. Note that, before the device can operate at the specified performance, the reference voltage must charge up the external reservoir capacitor(s) and be allowed the specified settling time. RESET must be applied after returning PD to low to restore the ADAS3023 digital core, including the CFG register, to its default state. Therefore, the desired CFG must be rewritten to the device and one dummy conversion must be completed before the device operation is restored to the configuration programmed prior to PD assertion. Note that when using the internal reference, sufficient time is required to settle it to the nominal value. For a typical connection, it requires 100 ms to settle to the nominal value (see Figure 41). Rev. 0 | Page 24 of 32 Data Sheet ADAS3023 CONVERSION MODES Normal Mode (CMS = 1, Default) The ADAS3023 offers two conversion modes to accommodate varying applications, and both modes are set with the conversion mode select bit, CMS (Bit 1) of the CFG register. Setting CMS to 1 is useful for all applications where the full 500 kSPS sample rate of the device is not required. In this mode, there is no maximum time restriction between conversions. This mode is the default condition from the assertion of an asynchronous reset. The main difference between the normal mode and warp mode is that the BUSY/SDO2 time, tCONV, is slightly longer in normal mode than in warp mode. Warp Mode (CMS = 0) Setting CMS to 0 is useful where the full 2-channel throughput of 500 kSPS is required. However, in this mode, the maximum time between conversions is restricted. If this maximum period is exceeded, the conversion result can be corrupted. Therefore, the warp mode is best suited for continuously sampled applications. Rev. 0 | Page 25 of 32 ADAS3023 Data Sheet DIGITAL INTERFACE The ADAS3023 digital interface consists of asynchronous inputs and a 4-wire serial interface for conversion result readback and configuration register programming. the current configuration is applied to future conversions. This pipeline ensures that the ADAS3023 has sufficient time to acquire the next sample to the specified 16-bit accuracy. This interface uses the three asynchronous signals (CNV, RESET, and PD) and a 4-wire serial interface comprised of CS, SDO, SCK, and DIN. CS can also be tied to CNV for some applications. Register Pipeline The CNV input initiates conversions for N enabled channels as defined in the CFG register. The ADAS3023 is fully asynchronous and can perform conversions at any frequency from dc up to 500 kSPS, depending on the settings specified in the configuration register and the system serial clock rate. The CFG register is written on the first 16 SCKs following the EOC event, and it is updated on the next EOC event. To ensure that all CFG updates are applied during a known safe instant to the various circuit elements, the asynchronous data transfer is synchronized to the ADAS3023 timing engine using the EOC event. This synchronization introduces an inherent delay between updating the CFG register setting and the application of the configuration to a conversion. This pipeline, from the end of the current conversion (n), consists of a one-deep delay before the CFG setting takes effect. This means that two SOC and EOC events must elapse before the setting (that is, the new channel, gain, and so forth) takes effect. Note that the nomenclature (n), (n + 1), and so forth is used in the remainder of the following digital sections (Serial Data Interface, General Timing, and Configuration Register) for simplicity. Note, however, that there is no pipeline after the end of a conversion before data can be read back. CNV Rising—Start of Conversion (SOC) RESET AND POWER-DOWN (PD) INPUTS A rising edge on the CNV changes the state of the ADAS3023 from track mode to hold mode, as well as all that is necessary to initiate a conversion. All conversion clocks are generated internally. After a conversion is initiated, the ADAS3023 ignores other activity on the CNV line (governed by the throughput rate) until the end of the conversion. The asynchronous RESET and PD inputs can be used to reset and power down the ADAS3023, respectively. Timing details are shown in Figure 46. CONVERSION CONTROL Although CNV is a digital signal, take care to ensure fast, clean edges with minimal overshoot, undershoot, and ringing. In addition, avoid digital activity close to the sampling instant because such activity can result in degraded SNR performance. BUSY/SDO2 Falling Edge—End of Conversion (EOC) The EOC is indicated by BUSY/SDO2 returning low and can be used as a host interrupt. In addition, the EOC gates data access to and from the ADAS3023. If the conversion result is not read prior to the next EOC event, the data is lost. Furthermore, if the CFG update is not completed prior to the EOC, it is discarded and SEE NOTE CNV n–1 RESET/ PD While the ADAS3023 is performing a conversion and the BUSY/ SDO2 output is driven high, the ADAS3023 uses a unique 2-phase conversion process, allowing for safe data access and quiet time. The CNV signal is decoupled from the CS pin, allowing multiple ADAS3023 devices to be controlled by the same processor. For applications where SNR is critical, the CNV source requires very low jitter, which is achieved by using a dedicated oscillator or by clocking CNV with a high frequency, low jitter clock. For applications where jitter is more tolerable or a single device is in use, tie CNV to CS. For more information on sample clock jitter and aperture delay, see the MT-007 Mini Tutorial, Aperture Time, Aperture Jitter, Aperture Delay Time—Removing the Confusion. tACQ tRH n BUSY CS tCCS n–2 SDO CFG tEN tDIS x n+1 UNDEFINED x DEFAULT x x SEE NOTE NOTES 1. WHEN THE PART IS RELEASED FROM RESET, tACQ MUST BE MET FOR CONVERSION n IF USING THE DEFAULT CFG SETTING FOR CHANNEL IN0. WHEN THE PART IS RELEASED FROM POWER-DOWN, tACQ IS NOT REQUIRED, AND THE FIRST TWO CONVERSIONS, n AND n + 1, ARE UNDEFINED. 10942-017 Conversion results are presented to the serial data output pin (SDO) after the end of a conversion. The 16-bit configuration word, CFG, is programmed on the serial data input pin, DIN during the first 16 SCKs of any data transfer. This CFG register controls the settings, such as selecting the number of channels to be converted, the programmable gain settings for each channel group, and the reference choice (see Configuration Register section for more information). Figure 46. RESET and PD Timing A rising edge on RESET or PD aborts the conversion process and places SDO into high impedance, regardless of the CS level. Note that RESET has a minimum pulse width (active high) time for setting the ADAS3023 into the reset state. See the Configuration Register section for the default CFG setting when the ADAS3023 returns from the reset state. If this default setting is used after RESET is deasserted (Logic 0), for the conversion result to be valid, a period equal to the acquisition time (tACQ) must elapse before CNV can be asserted; otherwise, if a conversion is initiated, the result is corrupted. In addition, the output data from the previous conversion is cleared upon a reset; attempting Rev. 0 | Page 26 of 32 Data Sheet ADAS3023 to access the data result prior to initiating a new conversion produces an invalid result. interface uses the CS, SCK, SDO, and DIN signals. Timing signals for a serial interface are shown in Figure 47. Upon the device returning from power-down mode or from a reset when the default CFG is not used, there is no tACQ requirement because the first two conversions from power-up are undefined/ invalid because the one-deep delay pipeline requirement must be satisfied to reconfigure the device to the desired setting. SDO is activated when CS is asserted. The conversion result is output on SDO and updated on the SCK falling edges. Simultaneously, the 16-bit CFG word is updated, if needed, on the serial data input (DIN). The state of BUSY/SDO2 (Bit 0) determines the output format of the MSB data when SDO is activated after the EOC. Note that, in Figure 47, SCK is shown as idling high. SCK can idle high or low, requiring the system developer to design an interface that suits setup and hold times for both SDO and DIN. SERIAL DATA INTERFACE The ADAS3023 uses a simple 4-wire interface and is compatible with FPGAs, DSPs, and common serial interfaces such as a serial peripheral interface (SPI), QSPI™, and MICROWIRE®. The tSCK tSCKH tSCKL CS tDIS SCK tSDOH tEN tSDOV SDO (MISO) tDINS tDINH Figure 47. Serial Timing Rev. 0 | Page 27 of 32 10942-018 DIN (MOSI) ADAS3023 Data Sheet GENERAL TIMING The converter busy signal is always output on the BUSY/SDO2 pin when CS is logic high. When the BUSY/SDO2 output is enabled when CS is brought low after the EOC, the SDO outputs the data of Channel 0 to Channel 3 (CH0, CH1, CH2, and CH3), and the SDO2 outputs the data of Channel 4 to Channel 7 (CH4, CH5, CH6, and CH7) after 16 SCK rising edges, as shown in Figure 49. The conversion result output on BUSY/SDO2 pin synchronizes to the SCK falling edges. The conversion results are in twos complement format. Reading or writing data during the quiet conversion phase (tCONV) may cause incorrect bit decisions. Figure 48 and Figure 49 conversion timing diagrams show the specific timing parameters, including the complete register to conversion and readback pipeline delay. These figures detail the timing from a power up or from returning from a full power down by use of the PD input. When the BUSY/SDO2 output is not enabled after the EOC, the data available on the SDO output (MSB first) can be read after the16 SCK rising edges in sequential fashion (from Channel 0 (CH0) to Channel 7 (CH7)), as shown in Figure 48. SOC SOC SOC tCYC EOC EOC tCONV POWER UP PHASE NOTE 2 NOTE 1 CONVERSION (n) NOTE 1 CONVERSION (n + 1) ACQUISITION (n + 1) ACQUISITION (n + 2) CNV tCNVH NOTE 4 tAD NOTE 3 CS 1 16 1 16 1 16 1 16 1 16 1 16 NOTE 2 SCK DIN CFG (n + 2) SDO CH0 BUSY/ SDO2 CFG (n + 3) CH1 CH7 CH0 CH1 CH7 tCBD 10942-019 DATA (n) DATA (n + 1) NOTES 1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC). 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED WITH CONVERSION. 3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL. 4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, tAD, SHOULD LAPSE PRIOR TO DATA ACCESS. Figure 48. General Timing Diagram with BUSY/SDO2 Disabled SOC SOC SOC tCYC EOC tCONV POWER UP PHASE EOC NOTE 1 NOTE 1 CONVERSION (n) ACQUISITION (n + 1) CONVERSION (n + 1) ACQUISITION (n + 2) CNV tCNVH NOTE 4 tAD NOTE 3 1 16 16 1 1 16 1 16 1 16 1 16 1 16 1 16 NOTE 2 DIN CFG (n + 2) SDO CH0 CH1 CH2 CH3 CFG (n + 3) CH0 CH1 CH2 CH3 BUSY/ SDO2 CH4 CH5 CH6 CH7 CH4 CH5 CH6 CH7 DATA (n) DATA (n + 1) NOTES 1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC). 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED WITH CONVERSION. 3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL. 4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY, tAD, SHOULD LAPSE PRIOR TO DATA ACCESS. Figure 49. General Timing Diagram with BUSY/SDO2 Enabled Rev. 0 | Page 28 of 32 10942-020 CS SCK Data Sheet ADAS3023 CONFIGURATION REGISTER required for the user specified CFG to take effect. To ensure the digital core is in the default state, apply an external reset after the deassertion of PD. The default value is CFG[15:0] = 0xFFFF. To read back the contents of the configuration register, CFG, an additional 16 SCKs are provided after all of the channel data have been read, and CFG is made available on the SDO output. The default CFG settings configure the ADAS3023 as follows: The configuration register, CFG, is a 16-bit programmable register for selecting all of the user-programmable options of the ADAS3023 (see Table 11). The register is loaded when data is read back for the first 16 SCK rising edges, and it is updated at the next EOC. Note that there is always a one-deep delay when writing to CFG, and when reading back from CFG, it is the setting associated with the current conversion. • • • • • • The default CFG setting is applied when the ADAS3023 returns from the reset state (RESET = high) to the operational state (RESET = low). Returning from the full power-down state (PD = high) to an enabled state (PD = low), the default CFG setting is not applied and at least one dummy conversion is Overwrites contents of the CFG register. Selects the eight input channels mode. Configures the PGIA gain to 0.20 (±20.48 V). Enables the internal reference. Selects normal conversion mode. Disables the SDO2 readout mode. Table 10. Configuration Register, CFG Bit Map; Default Value = 0xFFFF (1111 1111 1111 1111) 15 CFG 14 INx 13 INx 12 RSV 11 PGIA 10 PGIA 9 PGIA 8 PGIA 7 PGIA 6 PGIA 5 PGIA 4 PGIA 3 RSV 2 REFEN 1 CMS 0 BUSY/SDO2 Table 11. Configuration Register Description Bit No. 15 Bit Name CFG [14:13] INx 12 [11:4] RSV PGIA [11:10] [9:8] [7:6] [5:4] 3 2 PGIA PGIA PGIA PGIA RSV REFEN 1 CMS 0 BUSY/SDO2 Description Configuration update. 0 = keeps current configuration settings. 1 = overwrites contents of register. Selection of the number of channels to be converted simultaneously. Bit 14 Bit 13 Channels 0 0 2 0 1 4 1 0 6 1 1 8 Reserved. Setting or clearing this bit has no effect. Programmable gain selection (see the Programmable Gain section). Bit (Odd) Bit (Even) PGIA Gain 0 0 ±10.24 V 0 1 ±5.12 V 1 0 ±2.56 V 1 1 ±20.48 V (default) Sets the gain of IN0. Sets the gain of IN1. Sets the gain of IN3 to IN2. Sets the gain of IN4 to IN7. Reserved. Setting or clearing this bit has no effect. Internal reference (see the Pin Configuration and Function Descriptions and Voltage Reference Input/Output sections). 0 = disables the internal reference. Disable the internal reference buffer by pulling REFIN to ground. 1 = enables the internal reference (default). Conversion mode selection (see the Conversion Modes section). 0 = uses the warp mode for conversions with a time between conversion restriction. 1 = uses the normal mode for conversions (default). Secondary data output control using the BUSY/SDO2 pin. 0 = enables the device busy status when the CS pin is held high. On the CS falling edge, the MSB of Channel 1 is presented on the BUSY/SDO2 input and subsequent data is presented on the SCK falling edges. 1 = enables the device busy status only (default). All data is transmitted via the SDO pin on the SCK falling edge. Rev. 0 | Page 29 of 32 ADAS3023 Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 0.30 0.25 0.18 31 30 0.50 BSC TOP VIEW 1.00 0.95 0.85 0.45 0.40 0.35 1 21 11 20 PIN 1 INDICATOR *4.70 4.60 SQ 4.50 EXPOSED PAD 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 40 10 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION. 07-19-2012-B PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 50. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-15) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADAS3023BCPZ ADAS3023BCPZ-RL7 EVAL-ADAS3023EDZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 30 of 32 Package Option CP-40-15 CP-40-15 Data Sheet ADAS3023 NOTES Rev. 0 | Page 31 of 32 ADAS3023 Data Sheet NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10942-0-5/13(0) Rev. 0 | Page 32 of 32