PANASONIC AN5367FB

ICs for TV
AN5367FB
NTSC video, chroma, and deflection signal processing circuit
■ Overview
Unit: mm
14.0±0.3
12.0±0.2
36
25
24
12.0±0.2
14.0±0.3
(1.6)
37
■ Features
1
12
0.80
0.35 +0.10
– 0.05
Seating plane
(1.0)
+0.10
(1.6)
13
1.95±0.20
48
0.1±0.1
• Luminance signal processing
• Incorporating 3.58 MHz trap
• Black side gradation control is possible by black expansion circuit
• Adopting delay line aperture control
• Color signal processing
• Incorporating band-pass filter
• Incorporating ACC filter
• Deflection signal processing
• Stable sync. signal generation by the use of double
AFC circuit and countdown circuit
• Vertical directional screen position is adjustable
• Others
• Incorporating 3-input composite signal changeover
SW
• DAC output for adjusting sound volume and screen
height
0.15 – 0.05
The AN5367FB is an IC to demodulate the NTSC
composite signal. It is possible to control the all functions by the I2C bus. The use of flat package allows a space
saving in sets design.
0° to 10°
0.5±0.2
QFP048-P-1212
■ Applications
• Color televisions and combined CTV/VCR set
1
AN5367FB
ICs for TV
FSC
25
OSD-B in
Spot killer
26
27
OSD-G in
OSD-R in
28
29
APC filter
30
SC out
Killer filter
31
32
BL start
ABL/ACL
33
34
BL det.
Video
42
19
43
18
44
17
I2C
45
16
Sync.
46
Limiter
R out
G out
B out
YS
H out
BLK in
GND (main)
FBP in
L det. filter
H VCC (6.2 V)
12
H AFC1
H OSC
X-ray
11
10
V out
9
8
Mute
13
GND (Jungle)
Video1
14
L det. out
48
15
SW
7
47
1
Video2
20
Hold down ref.
VCC2 (5 V)
41
HSYNC in
Video3
21
6
Killer out
40
5
SDA
22
RGB
VSYNC in
SCL
39
DAC2 (sound)
APL det.
Chroma
4
Y in
23
3
DAC1 (V height)
38
Video out
P clamp
24
2
VCC1 (9 V)
37
VSYNC
VCCREF
35
36
C in
■ Block Diagram
■ Pin Descriptions
Pin No.
2
Description
Pin No.
Description
1
Video signal input pin 1
11
Hold down input pin
2
Vertical signal clamp pin
12
Horizontal oscillation pin
3
Video signal output pin
13
Horizontal AFC1 filter pin
4
DAC output pin 1
14
Horizontal stabilized power supply pin (6.2 V)
5
Vertical sync. separation input pin
15
Lock detection filter pin
6
Horizontal sync. separation input pin
16
FBP input pin
7
Hold down reference voltage pin
17
GND pin
8
Lock detection output pin
18
Blanking pulse input pin
9
GND pin (sync. system)
19
Horizontal pulse output pin
10
Vertical pulse output pin
20
YS input pin
ICs for TV
AN5367FB
■ Pin Descriptions (continued)
Pin No.
Description
Pin No.
Description
21
B output pin
35
Black level detection filter pin
22
G output pin
36
Chroma signal input pin
23
R output pin
37
VCC1 reference voltage pin (9.6 V)
24
Output limiter pin
38
Power supply pin (VCC1: 9 V)
25
Chroma oscillator pin
39
Capacitor pin for Y clamp
26
Spot killer pin
40
DAC output pin 2
27
External B input pin
41
Y signal input pin
28
External G input pin
42
APL detection filter pin
29
External R input pin
43
SCL pin (for I2C bus)
30
Chroma APC filter pin
44
SDA pin (for I2C bus)
31
Subcarrier output pin
45
Killer output pin
32
Killer filter pin
46
Video signal input pin 3
33
ABL/ACL input pin
47
Power supply pin (VCC2: 5 V)
34
Black extension start adjusting pin
48
Video signal input pin 2
■ Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
VCC
Supply current
Unit
VCC1 (38)
9.9
V
VCC3 (47)
5.5
I38
47
I47
31
I14
13
I37
5
ICC
Power dissipation *2
Operating ambient temperature
Storage temperature
Rating
*1
*1
mA
PD
775
mW
Topr
−20 to +70
°C
Tstg
−55 to +150
°C
Note) *1 : Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C.
*2 : The power dissipation shown is the value for Ta = 70°C.
■ Recommended Operating Range
Parameter
Supply voltage
Supply current
Symbol
Range
Unit
VCC1
8.55 to 9.45
V
VCC2
4.75 to 5.25
I14
6.0 to 12
I37
1.0 to 4.5
mA
3
AN5367FB
ICs for TV
■ Electrical Characteristics at Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SW and power supply
Circuit current 1 (ICC1)
(9 V system)
I38
No signal input, I14 = 8 mA,
VCC1 = 9 V,VCC2 = 5 V
28
36
43
mA
Circuit current 2 (ICC2)
(5 V system)
I47
No signal input, I14 = 8 mA,
VCC1 = 9 V,VCC2 = 5 V
18
23
28
mA
9.6 V reference voltage
V37
I37 = 2.4 mA
9.0
9.6
10.2
V
Operating resistance
R37
I37 = 1.0 mA to 5.0 mA
0
11
30
Ω
Zener maximum current
IVD
Largest possible sink current
5


mA
SW circuit gain
GSW
f = 1 MHz, 0.7 V[p-p]
4.9
5.9
6.9
dB
Frequency characteristics
fSW
Attenuation amount at 7 MHz with f =
1 MHz as reference
−3
−1.3

dB
Crosstalk
CT
f = 1 MHz, input signal 0.7 V[p-p],
sine wave
−50


dB
Clamp current
I1 , I46 , Sink current of each input pin, when
I48
applying 3 V to pin 1, pin 46 and pin 48
6
10
14
µA
Total gain
GTOTAL Gain dispersion from each input to output
−19
0
+19
%
VCC: Typ., input pin voltage measurement
1.1
1.5
1.9
V
Y signal processing
Video input pin voltage
V41
Y typical output
EOSTD
Input 2 V[p-p] stair steps
2.6
3.2
3.8
V[0-p]
Video voltage gain relative ratio
∆GY
As same as the above, G/R, B/R
−1.0
0
+1.0
dB
Video voltage gain
GY
Input 2 V[p-p] stair steps, contrast: typ.
1.7
2.1
2.5
V[0-p]
Video frequency characteristics
fY
Attenuation amount at 6 MHz with
f = 1 MHz as reference
−5.0
−2.0

dB
Picture quality variable range 1
GS1
Input 0.2 V[p-p], sine wave f = 2.5 MHz,
sharpness: typ./min.
5.9
9.0
11.4
dB
Contrast ratio
GC
Input 2 V[p-p] stair steps,
contrast: max./min.
6
9
12
dB
Brightness variable range
BR
Input: Without input, cut-off: max. ,
brightness: min. to max. , pedestal level
measurement
2.15
2.40
2.80
V
Typical pedestal voltage
PLSTD
Input: Without input
1.95
2.60
3.10
V
DC restoration ratio 1
TDC1
Input 2.0 V[p-p] total white, APL 10%
to 90%, DC restoration ratio correction:
Off (pin 42: 0 V)
94
100
106
%
RGB output BLK level
YBLK
VCC: typ.
1.0
1.5
2.0
V
Black level correction amplitude 1
VBL1
Input signal: Total black, black level
detection pin: external RC → 9 V,
BL start = 20 kΩ
−100
0
+100
mV
Note) Unless otherwise specified, refer to "• Typical conditions for testing" for the conditions of I2C bus and each pin.
4
ICs for TV
AN5367FB
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Y signal processing (continued)
Black level correction amplitude 2
VBL2
Input signal: Total black, black level
detection pin: 3 V, BL start = 20 kΩ
0.46
0.80
1.14
V
Black level correction amplitude 3
VBL3
Adjust output amplitude to 0.8 V[p-p],
black level detection pin: 9 V → external
RC, BL start = 20 kΩ
0.10
0.25
0.40
V
Black level correction amplitude 4
VBL4
Adjust output amplitude to 2.0 V[p-p], − 0.1
black level detection pin: 9 V → external
RC, BL start = 20 kΩ
0
+0.1
V
330
410
490
ns
Y signal delay time
tD1
Input 2.0 V[p-p] stair step, B.P.F. SW:
On, trap SW: On, measurement of time
delay between input and output
Sub-contrast adjustment range 1
EOADJ1 Sub-contrast typ. → min.,
input: 2 V[p-p] stair step
−40
−30
−22
%
Sub-contrast adjustment range 2
EOADJ2 Sub-contrast typ. → max.,
input: 2 V[p-p] stair step
35
46
55
%
Trap attenuation amount
GTRAP
f = 3.579545 MHz, trap on/off
23


dB
∆tD
Difference of amount of delay between
B.P.F. on/off
90
120
150
ns
ACL variable range
∆ACL
Pin 33 7.5 V → 2.5 V, stair step 2 V[p-p]
12
20
28
%
ABL variable range
∆ABL
Without input, pin 33: 4.5 V → 2.5 V,
pedestal voltage of RGB output
0.4
0.6
0.8
V
ACC characteristics 1
ACC1
Color bar input: 6 dB up,
(R−Y) output measurement,
burst typical input = 150 mV[p-p]
0.9
1.0
1.1
Times
ACC characteristics 2
ACC2
Color bar input: 20 dB down,
(R−Y) output measurement,
burst typical input = 150 mV[p-p]
0.7
0.9
1.1
Times
Delay line
Color signal processing
Color killer tolerance 1
eK1
Level at which demodulation output does
not appear when color bar input level is
being attenuated. Typical input level: 0 dB
−53
−43
−34
dB
Color difference output (B−Y) 1
eO1
Color bar input, color: typ., tint: Center
1.55
2.00
2.45
V[0-p]
Color difference output (B−Y) 2
eO2
Color bar input, color: max., tint: Center 2.85
3.7
4.5
V[0-p]
Color residue
eLC
Color bar input, color: min.

15
60
mV
Color bar input, contrast: min. → max.
5.2
8.2
11.2
dB
Chroma contrast
CCONT
Free-running frequency
fC0
For f0 of typical sample,
f0 = 3.579545 MHz
−300
0
+300
Hz
APC pull-in range 1
fAPC
Color bar: Typical input, B.P.F.: On
±450
±600

Hz
Tint center data
TC
Rainbow signal, tint data at which
B−Y output becomes typical.
15
1D
25
H
Note) Unless otherwise specified, refer to "• Typical conditions for testing" for the conditions of I2C bus and each pin.
5
AN5367FB
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Color signal processing (continued)
Tint variable range
∆θ
Tint = min. to max.
±30
±45

deg
Demodulation output ratio R/B
R/B
Rainbow input
0.76
0.96
1.15
Times
Demodulation output ratio G/B
G/B
Rainbow input
0.27
0.36
0.45
Times
Demodulation angle ∠R
∠R
Reference is ∠B
96
104
112
deg
Demodulation angle ∠G
∠G
Reference is ∠B
225
235
245
deg
Demodulation output residual carrier
AFSC
fSC component of demodulation output

20
50
mV[p-p]
CW output DC level 1
V31(1)
Subcarrier output: Off
1.4
1.9
2.4
V
CW output DC level 2
V31(2)
Subcarrier output: On
5.6
6.1
6.6
V
CW Out output level
ACW
Output level of fSC
250
350
500 mV[p-p]
High-level killer output
KILH
Pin 45 voltage measurement, V32 = 5.5 V
4.0
4.6

V
Low-level killer output
KILL
Pin 45 voltage measurement, V32 = 4 V

0.4
1.0
V
Killer output open
KILOP
At VV mode, I45 measurement,
V32 = 4 V or 5.5 V
−1
0
+1
µA
RGB output DC difference voltage
∆PL1
∆V = VR −VG , VG −VB , VB −VR ,
burst input only, cut off: min.
−300
0
+300
mV
RGB output limit level
VLIM
Input: 2.0 V[p-p], total white, contrast:
max., cut off: max., bright: max.
6.6
6.9
7.2
V
External RGB input clip level 1
EG1
YS: H, contrast: max., difference from
internal pedestal voltage, cut off: min.,
drive: typ.
2.2
2.6
3.0
V
External RGB input clip level 2
EG2
YS: H, contrast: min., difference from
internal pedestal voltage, cut off: min.,
drive: typ.
1.1
1.6
2.1
V
RGB processing
External RGB input clip level
difference
∆EG1
YS: H, contrast: max., external input
clip level difference among R, G and
B channel
−300
0
+300
mV
External RGB gain
GEXT
YS: H, contrast: max., input voltage:
0.3 V[p-p], sine wave, 1 MHz
1.6
2.3
3.0
Times
External RGB frequency
characteristics
fEXT
YS: H, contrast: max., input voltage:
−4.8
0.3 V[p-p], sine wave, reference: 1 MHz,
attenuation amount at 7 MHz
−1.8

dB
Internal/external pedestal
difference voltage
∆PL2
Burst input only, YS: high/low
50
250
600
mV
YS
Pin 20 voltage at which inside and
outside change over
1.1
1.6
2.1
V
Cut-off variable range
∆CO
Without input, cut off: min. to max.
1.2
1.5
1.8
V
Drive variable range
∆DR
Input: staircase, 2.0 V[p-p], drive: min.
to max.
5
7
9
dB
YS threshold level
Note) Unless otherwise specified, refer to "• Typical conditions for testing" for the conditions of I2C bus and each pin.
6
ICs for TV
AN5367FB
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Horizontal signal processing
Horizontal stabilized power supply
voltage
V14
Pin voltage, when power supply pin
input current I14 = 8 mA
5.7
6.1
6.8
V
Horizontal stabilized power supply
maximum current
I14
Maximum input current for which power
supply is stabilized
13


mA
Horizontal stabilized power supply
on-state resistance
R14
On-state resistance, when input current
I14 = 6 mA to 13 mA
0
14
30
Ω
Horizontal output start voltage
VFHS
Horizontal stabilized power supply
voltage, when horizontal output pulse
becomes 1 V[p-p] or more. Do not
apply other power supply voltage.

4.5
5.2
V
Horizontal output pulse duty
τHO
Horizontal output pulse high level duty 46.9
50.0
53.1
%
High-level horizontal output
V19H
Horizontal output pulse high level
4.0
4.3
4.6
V
Low-level horizontal output
V19L
Horizontal output pulse low level

0.2
0.5
V
Horizontal output free-running
frequency
fHO
Horizontal output frequency, when there 15.45 15.73 16.05
is no horizontal sync. separation input
Hor. pull-in range
fHP
Frequency at which horizontal sync.
separation input frequency pulls in.
Sync. signal 0.57 V[p-p].
±500
±600

kHz
Hz
Screen position fluctuation 1
HPOS1
Phase change of horizontal sync. signal
and FBP, H-center (0A): 67 → 60
−1.70 −2.12 −2.55
µs
Screen position fluctuation 2
HPOS2
Phase change of horizontal sync. signal
and FBP, H-center (0A): 67 → 6F
1.97
2.46
3.14
µs
Hold Down operation level
VHD
Voltage at which X-ray input pin voltage
holds down. Hold down pin reference
voltage: 6.2 V
5.9
6.2
6.5
V
High-level lock det. output
LDH
At horizontal AFC unlocked,
RL = 56 kΩ
4.5


V
Low-level lock det. output
LDL
At horizontal AFC locked,
RL = 56 kΩ


0.7
V
1.7
2.2
2.7
V
Pulse width at horizontally/vertically
synchronized state
610
640
670
µs
BLK-in input threshold voltage
BLKST Pin 18 threshold voltage (BLK is applied
to RGB output stage only)
Vertical signal processing
Ver. out pulse width
τVO
High-level ver. out 1
V10H1
Vertical output pulse high level
pin 10: open
4.0
4.3
4.6
V
High-level ver. out 2
V10H2
Vertical output pulse high level
pin 10: − 0.2 mA
3.75
4.10
4.60
V
High-level ver. out 3
V10H3
Vertical output pulse high level
pin 10: − 0.5 mA
3.3
3.9
4.6
V
Note) Unless otherwise specified, refer to "• Typical conditions for testing" for the conditions of I2C bus and each pin.
7
AN5367FB
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Vertical signal processing (continued)
Low-level ver. out
V10L
Vertical output pulse low level

0
0.3
V
VOUT free-running frequency
fVO
Ver. out frequency, when there are no
hor. and ver. sync. signals input.
58
60
62
Hz
Vertical pull-in range
fVP
Sync. input: 2 V[p-p], measurement should
be conducted from not pulled in state.
56

64
Hz
V position: min. → max.

31

H
1.5

3.0
V


0.4
V
VOUT position shift
I2 C
VPOS
processing
SCL, SDA input threshold voltage VSCL , VSDA
Sink capability at ACK
ACK
I = 3 mA when pull-up resistor is 1.6 kΩ
High level DAC output 1
V4H
Pin 4 output DC voltage, 0D = 7F
8.25
8.75
9.25
V
High level DAC output 2
V40H
Pin 40 output DC voltage, 0C = 7F
4.5
5.0
5.5
V
Low level DAC output 1
V4L
Pin 4 output DC voltage, 0D = 00
0.60
0.90
1.20
V
Low level DAC output 2
V40L
Pin 40 output DC voltage, 0C = 00
0
0.1
0.2
V
Note) Unless otherwise specified, refer to "• Typical conditions for testing" for the conditions of I2C bus and each pin.
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
−1.4
−1.8
−2.2
mV/°C
1 V[p-p] is reference (0 dB),
VCC1 = 9 V, VCC2 = 5 V
6


dB
V1 , V46 , Without input, pin 1, pin 46 and pin 48
V48
voltage
1.8
2.2
2.6
V
2.6
3.0
3.4
V
SW power supply
Reference voltage-temperature
characteristics
SW input dynamic range
Input clamp voltage
SW output voltage
∆V37 /Ta I37 = 2.4 mA, T = −20°C to +70°C
SWD
V3
Without input, pin 3 voltage
SW output−Y input
DC difference voltage
V3 −V41 Without input, difference voltage
between pin 3 and pin 41
1.0
1.2

V
SW output−H. Sync.
DC difference voltage
V3 −V6 Without input, difference voltage
between pin 3 and pin 6
1.0
1.2

V
SW output−V. Sync.
DC difference voltage
V3 −V5 Without input, difference voltage
between pin 3 and pin 5
1.0
1.2

V
Brightness: max.

7.5

V
Y signal processing
Video maximum output voltage
8
EOmax
Y signal input dynamic range
YIN
Input D range measurement, contrast:
typ., sub-contrast: typ.

4.0

V[p-p]
Picture quality variable range 2
GS2
Input: 0.2 V[p-p], sine wave, f = 2.5 MHz,
sharpness: max./min.

13

dB
ICs for TV
AN5367FB
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
−300

+300 mV[p-p]
Same as the above G/R, B/R,
brightness: min. → max.
0.9
1
1.1
Times
VBLSTA BL start external resistor: 20 kΩ

53

IRE

0
0.25
V[p-p]/
V

−1.8

mV/°C
Input: 2.0 V[p-p], stair step, noise meter
measurement, contrast: max., sharpness: min.
53
55

dB
Service SW operation 1
SRSW1 Input: 2.0 V[p-p], stair step, service SW:
Measurement of output amplitude, when
SW is on.

10
150
mV[p-p]
Service SW operation 2
SRSW2 Service SW: On, DC voltage measurement at no-appearance of VOUT .
3.8
4.3
4.8
V
Y signal processing (continued)
Contrast fluctuation with picture ∆ASC
quality control
Brightness relative control
sensitivity
Black level correction starting
point voltage
Video signal output supply voltage
dependency
Output DC voltage ambient
temperature dependency
Y S/N
∆BR
∆EO /
VCC
Input: 2.0 V[p-p], stair step,
sharpness: max./min.
Input: 2.0 V[p-p], stair step, output
amplitude change of VCC = ±5%
∆EODC / Pedestal level change ratio, when Ta
Ta
changes from 50°C to 75°C, contrast:
max.,brightness: typ.
YS/N
DC restoration ratio 2
TDC2
2.0 V[p-p], stair step, APL det. = 20 kΩ

120

%
Trap center frequency
f0TRAP
Difference from f = 3.579545 MHz
−70

+70
kHz
Delay amount of trap
τTRAP
f = 0.5 MHz, comparison of delay
amount between trap on/off

40

ns
Temperature characteristics of
trap attenuation amount
∆GTRAP / f = 3.579545 MHz, −20°C to +70°C
Ta
23


dB
Temperature characteristics of
trap frequency
∆fTRAP / −20°C to +70°C
Ta
−50

+50
kHz
ACL start voltage
ACLSTA Pin 33 voltage at which ACL starts to
become effective

7.1

V
ACL stop voltage
ACLSTO Pin 33 voltage at which ACL stops

2.9

V
ABL start voltage
ABLSTA Pin 33 voltage at which ABL starts to
become effective

4.0

V
ABL stop voltage
ABLSTO Pin 33 voltage at which ABL stops

3.0

V

4.5

V[0-p]
−250

+250
Hz

2.8

Hz/mV
Color signal processing
Maximum color difference output
eOmax
Color bar input, brightness: min.,
color: max., pedestal to peak voltage
Free-running frequency supply
voltage dependency
∆fCO /
VCC
VCC = ±5%
VCO control sensitivity
β
Check change in oscillation frequency,
when VAPC = 5.6 V to 5.8 V
9
AN5367FB
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit

−2.9

Hz/°C
Color signal processing (continued)
Free-running frequency ambient ∆fCO /Ta Ambient temperature: −20°C to +70°C
temperature dependency
Phase detection sensitivity
µ
{1/ (∆φ × β)} × 100

22.3

mV/deg
Phase hold characteristic
∆φ
Change amount of tint, when fSC is
shifted by ±300 Hz

1.6

deg/
100 Hz
Demodulation output frequency
characteristic
∆f−3
Frequency at which color output pin
becomes −3 dB

1.1

MHz

0

%

±7

%
Demodulation output supply
voltage dependency
∆eO /VCC Tint: typ., contrast: typ., VCC ±5%,
color: typ.
Demodulation output ambient ∆eO /Ta Ta = −20°C to +70°C, +25°C is typ.
temperature dependency
Tint Center shift
∆TC
Change amount of tint center, when
B.P.F. is used and not.

±4

H
H.P.F. frequency characteristic
fHPF
Gain at f = fSC

−12

dB
H.P.F. group delay amount
τHPF
Group delay amount at f = fSC

140

ns
Color killer tolerance 2
eK2
B.P.F. on state

−43

dB
Chroma delay amount
τCHO
Delay from pin 36 input to pin 21 output

375

ns
C−Y/Y Color data, when C−Y/Y ratio becomes 1.0

40

H
Y output amplitude fluctuation ∆EOTRAP 2 V[p-p] staircase input, amplitude
(trap on/off)
fluctuation at trap on/off

±10

%
∆EOBPF 2 V[p-p] staircase input, amplitude
fluctuation at B.P.F. on/off

±10

%
Y output amplitude fluctuation ∆EOSHARP 2 V[p-p] staircase input, sharpness:
(sharpness)
min. → max.

±5

%
Spot killer operation
VCC1 voltage at which RBRGB output
becomes high, when pin 26 voltage = 8.25 V

7.6

V
Sync. separation clamp voltage
V5 , V6 Clamp voltage of sync. separation input
pin (pin 5 and pin 6)

1.4

V
Black out operation level
VBLOUT Voltage at which Y output blacks out
when X-ray input pin voltage is raised
from 0 V

6.3

V
Frequency of HOUT at the time of hold
down when X-ray input pin voltage is
raised from 0 V
16.3
16.4
16.8
kHz
BGPSTA Phase difference from rear edge of hor.
sync. to BPG at horizontal AFC loop on
0.3
0.5
0.7
µs
C−Y/Y ratio
RGB processing
Y output amplitude fluctuation
(B.P.F. on/off)
VSPK
Horizontal signal processing
Operating frequency at hold
down
BGP start position
10
fHD
ICs for TV
AN5367FB
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Horizontal signal processing (continued)
BGP pulse width
BGPW
BGP width at horizontal AFC loop on
2.5
3.0
3.5
µs
FBP level 1
VFBP1
AFC operation DC level at FBP input pin
1.4
2.0
2.2
V
FBP level 2
VFBP2
HBLK operation DC level at FBP input pin
0.3
0.7
1.1
V
τFBP
Range of normal operation, when
delay amounts are being changed from
raise of HOUT to FBP center.
10.0
to
22.0
µs

±100

Hz
VBLKW VBLK width at R,G,B out in
horizontall/verticall synchronization

17.0

H
FBP delay operating range
Horizontal oscillation frequency ∆fHO/Ta Change in ambient temperature from
temperature characteristics
−20°C to +70°C
Vertical signal processing
V. BLK pulse width
I2C processing
Each DAC precision for 4-bit,
5-bit, 6-bit
DAC1
1LSB = {data (max.) − data (min.)}/
(2N−1)
0.1
1
1.9
LSB/
step
Each DAC precision for 7-bit,
7+1-bit, (40) excluded
DAC2
1LSB = {data (max.) − data (min.)}/
(2N−1)
0.1
1
1.9
LSB/
step
Each DAC precision for 7-bit,
7+1-bit, (40) only
DAC3
1LSB = {data (max.) − data (min.)}/
(2N−1)
−1
1
2
LSB/
step
Each DAC precision for 7+1-bit
(7F → 80)
DAC4
1LSB = {data (max.) − data (min.)}/
−9.25 −6.25
(2N−1), sub address; 06, 07
(Change amount/total change amount) × 100
0
%
• Typical conditions for testing
1. Input signal
1) Video: 10-step staircase, 2.0 V[p-p]
2) Chroma: Color bar signal: Burst level 150 mV[p-p]
Rainbow signal: Burst level 150 mV[p-p]
3) Sync. signal: Video signal 1.5 V[p-p] to 2.5 V[p-p] for both horizontal and vertical sync. signal input
2. I2C bus conditions
Sub address
Control
Data (H) Sub address
Control
Data (H)
00
Color
40
08
Drive G
40
01
Tint
20
09
Drive B
40
02
Brightness
40
0A
Y-adjust, H-center
67
03
Contrast
3F
0B
Test, V-position
00
04
Sharpness
00
0C
DAC1
40
05
Cut off R
00
0D
DAC2
40
06
Cut off G
00
0E
SW
50
07
Cut off B
00
11
AN5367FB
ICs for TV
■ Electrical Characteristics at Ta = 25°C (continued)
• Typical conditions for testing (continued)
3. State of each pin
Pin No.
Symbol
State
18
BLK in
0V
20
YS
1.1 V
24
Limiter
VCC1
33
ABL/ACL
7.5 V
34
BL start
20 kΩ
35
BL det.
VCC1
38
VCC1
Applied from outside (9 V)
42
APL det.
0V
47
VCC2
5V
• Functions of SW controlled by I2C bus
Data-bit
Functions of SW
Contents
0E-D0
0E-D1
AV SW changeover
D1
D0
Output
0
0
Video1
0
1
Video2
1
0
Video3
1
1
Mute
1. Composite signal changeover
Input Video1: Pin 1
Video2: Pin 48
Video3: Pin 46
Output
: Pin 3
2. No output at mute
0E-D2
Chroma trap SW
(0 → without trap)
1. Video circuit chroma trap changeover
(Y signal phase leads by about 40 ns at trap off
(1 → with trap)
0E-D3
Chroma B.P.F. SW
(0 → without B.P.F.)
(1 → with B.P.F.)
0E-D4
0E-D7
EE/VV SW
D7
D4
0
0
0
1
1
0
1
1
Killer out fSC out
Killer result
Yes
Open
No
Killer result
Yes
Open
Yes
(through))
1. Chroma circuit band-pass filter changeover
(Video signal delay amount varies according to
B.P.F. on/off)
1. Tuner (EE) and VTR (VV) changeover
In principle change over by D4
Tuner (EE): Killer result is output
fSC is output
VTR (VV): Killer result is not output
fSC is not output
However, fSC is output if D7 = 1 even at VV.
Killer out: Pin 45, fSC out: Pin 31
0E-D5
SSW (service SW)
(0 → normal)
(1 → service mode)
1. At service mode (no vertical scanning, white
balance adjustment)
Vertical output pulse stops (DC about 4.3 V)
Y output off, chroma output small
0E-D6
BLK off SW
(0 → normal)
(1 → output without BLK)
12
1. RGB output blanking (BLK) off changeover
To be used when RGB output signal without
BLK is required.
ICs for TV
AN5367FB
■ Terminal Equivalent Circuits
Pin No.
Equivalent circuit
Description
1
38 VCC1
9V
200 Ω
200 Ω
25 µA
1.25 kΩ
10 µF
1
10 µA
Video signal input pin 1:
• Video signal input pin
• Typical input 1.0 V[p-p]
• Input through capacitor, and sync. top
is clamped at 2.2 V
• Input video signal with low impedance
Voltage
AC
1.0 V[p-p]
2.2 V
2.75 V
2
3 kΩ
30 kΩ
10 kΩ
47 VCC2
5V
Vertical signal clamp pin:
• Peak clamp pin for separating vertical
sync. signal
AC
f = fV
Video signal output pin:
• Outputs signals inputted from pin 1,
pin 46 and pin 48
• Control of output signal is carried out
by I2C bus
• Recommended range of use is from
−2 mA to +2 mA
AC
To ver.
count down
50 kΩ
10 kΩ
200 Ω
2
211 Ω
220 Ω
2.2 µA
3
38
200 Ω
3
100 µA
50 Ω
400 Ω
200 Ω
100 µA
4
38
12 V
100 µA
1 kΩ
1 kΩ
40 kΩ
0 µA to
200 µA
4
4 kΩ
200 Ω
5
6
16 kΩ
16 kΩ
400 Ω
RV
560 Ω 1 µF
5
680 pF CV
RH 0.1 µF
270 Ω
6
1200 pF
CH
400 Ω
1.75
kΩ
1.75
kΩ
20
µA
20
µA
DAC output pin 1:
• Output voltage is adjustable in 128
stages (7-bit organization) by subaddress of I2C bus (0D).
• Recommended range of use is from
−70 µA to +70 µA
Pin 5: Vertical sync. separation input pin:
Pin 6: Horizontal sync. separation input pin:
16 kΩ
• RV >RH so that slice level is made
To H sync. sep.
deep for vertical sync. and shallow for
To V sync. sep.
horizontal sync.
• Cutoff frequency determined by RH
1.3 V
and CH shall be about 500 kHz.
• R → large, slice level becomes
deeper. (Weak in sync. compression)
• R → small, slice level is shallow.
(Weak in fluctuation such as V sag)
2.0 V[p-p]
3.0 V
DC
0.95 V
to
8.75 V
AC
47
2 V[p-p]
13
AN5367FB
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
7
Description
12 V
38
760 Ω
50 µA
6.2 V
7
100 Ω
65
kΩ
1 kΩ
1 kΩ
11
10 µF
10
kΩ
100
µA
50
µA
25
µA
8
5 kΩ
56 kΩ
1.2 kΩ
8
60 kΩ

9
10
47
200 Ω
50 kΩ
20 kΩ
10
1.8 V
0V
43 kΩ
11
12 V
38
760 Ω
DC
6.2 V
Lock detection output pin:
DC
• Pin which outputs whether vertical
0.7 V or less
sync. signal of input and HOUT are
at lock,
synchronizing.
4.5 V or more
• Recommended range of use is from
at unlock
0 mA to 0.2 mA
5V
47
Voltage
Hold down reference voltage pin:
• Operates hold down by comparing
voltage inputted to pin 11
V7 >V11: Normal operation
V7 <V11: Out of horizontal sync.
V7 +0.1 V<V11: Output with all BLK.
• Recommended range of use is from
3 V to 7 V
50 µA
GND pin:
• Sync. system GND

Vertical pulse output pin:
• Negative polarity, pulse width 10H
• Recommended range of use is from
− 0.7 mA to 0 mA
AC
Hold down reference voltage pin:
• Voltage in proportion to a hightension of CRT is applied.
DC
4.3 V
0V
6.2 V
7
100 Ω
65
kΩ
1 kΩ
1 kΩ
11
10 µF
10
kΩ
100
µA
25
µA
50
µA
12
270 Ω
100
µA
200
µA
Horizontal oscillation pin:
• Oscillates at 32fH ≅ 503 kHz by means
of ceramic oscillator element
• Makes horizontal and vertical pulse
by internal countdown circuit of IC.
270 Ω
435 Ω
300 Ω
12
CSB
503F38
220 pF (N750)
14
10
kΩ
10
kΩ
(
AC
f = 32fH
approx.
503 kHz
)
ICs for TV
AN5367FB
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
13
14
Description
Horizontal AFC1 filter pin:
• Charges and discharges the capacitor
connected to pin 13 after comparing
the phase of horizontal sync. signal
and pulse inside IC.
• R1, R2, C1 and C2 are lag-lead filter
for AFC1.
4.3 V
R1
27 kΩ
27 kΩ
200 Ω 200 Ω
2.2
kΩ
1.5 V
Duty 50%
4.4 2.2
kΩ kΩ
4.4
kΩ
13
fH
C2
10 µF
R2
2.2 kΩ
Hor. sync.
1 000 µA
Hor.
OSC
200 µA
C1
0.018 µF
DC
typ. 4.3 V
Horizontal
β curve
V13
14
Horizontal stabilized power supply pin:
• Stabilized power supply for horizontal
circuit.
A constant voltage circuit is inside.
• Recommended range of use is from
6 mA to 12 mA
12 V
760 Ω
14
0.01 µF
47 µF
6.1 V
15
47
10 kΩ
200 Ω 200 Ω
3.7 V
200 Ω
800 µA
12 kΩ
1.5 V
800 µA
Voltage
200 Ω
10 µA
15
DC
6.1 V
Lock detection pin:
DC
In synchronization
• Detects phase of horizontal sync.
signal and horizontal output pulse,
approx. 4.5 V
and outputs the results.
In asynchronization
• Color control becomes minimum and approx. 0.7 V
chroma output becomes zero in
asynchronous.
• Pin 15 becomes low in out of sync.
0.022 µF
16
FBP input pin:
• FBP input pin for horizontal blanking
50
100
and AFC circuit.
µA
µA
• Threshold level
HBLK: 0.75 V
16
2.7 kΩ
AFC: 1.9 V
•
Burst
gate
pulse monitor pin
2.7 kΩ
Current is flowing out at BGP timing
500 Ω
100 kΩ • Voltage input of 0 V or less is inhibited
• Recommended range of use is from
0 V to 5 V
47
100
µA
12 kΩ
50
µA
100
µA
39 kΩ
1.95 V
24 kΩ
0.75 V
60 500 Ω
kΩ
To AFC
17
40
kΩ
To HBLK

GND pin:
• Main GND
AC
FBP
5V
0V

15
AN5367FB
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
18
38
50 µA
5 kΩ
117.5 kΩ
2.7 kΩ
18
27.5 kΩ
Voltage
Blanking pulse input pin:
• Input threshold voltage: 2.1 V
• Operation
V18 <1.6 V: Normal operation
V18 >2.6 V: RGB outputs are blanked
• Recommended range of use is from
0 V to 5 V
AC
Horizontal pulse output pin:
• Output pulse duty is 50%
• Recommended range of use is from
−7 mA to 0 mA
AC
Pulse
5V
0V
100 kΩ
40 kΩ 200 Ω
19
14
200 Ω
300 µA
4.3 V
0.2 V
19
40 kΩ
20
38
1.3 kΩ
50 µA
8 kΩ
8 kΩ
2.25 V
1.2 kΩ 2.7 kΩ
20
30 kΩ
21
22
23
50 µA
500 Ω
38
VCC1
9V
200 Ω
100 µA
50 Ω
R, G, B
signal
100 µA
Pin 21
22
23
AC
Pulse
Pin 21: B output pin:
Pin 22: G output pin:
Pin 23: R output pin:
• Those are R,G,B output pin
• Recommended range of use is from
−2 mA to +2mA
AC
1.5 V
200 Ω
24
38
57 kΩ
69 kΩ
24
123 kΩ
16
YS input pin:
• Fast blanking input pulse input pin for
OSD
• Input threshold voltage 1.6 V
Low: Normal output
High: OSD output
• Recommended range of use is from
0 V to 5 V
Output limiter pin:
• This pin determines the voltage to
clip high side of R,G,B output.
• R,G,B output is clipped at 6.8 V at
open.
• Recommended range of use is from
0 V to VCC1
DC
ICs for TV
AN5367FB
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
25
38
600 Ω
600 Ω
100 Ω
Voltage
Chroma oscillation pin:
• Pattern of pin and oscillator element
should be as short as possible.
f = 3.58 MHz
AC
f = fC0
approx.
0.3 V[p-p]
Spot killer pin:
• This is used for quick discharging
CRT electric charge, when set power
is turned off.
• Operating speed varies by changing
external capacitance
• Recommended range of use is from 0
V to 9 V
DC
Pin 27: External B input pin:
Pin 28: External G input pin:
Pin 29: External R input pin:
• External input pin for OSD
• Input limit voltage varies according
to contrast control level
• Recommended range of use is from
0 V to 5.5 V
AC
25
1.5 kΩ
15 pF
500 µA
200 µA
50 µA
200 µA
26
38 VCC1
47.25 kΩ
10 kΩ
9V
1.75 kΩ
26
1 µF
100 kΩ
27
28
29
38 VCC1
25 µA
To RGB output
circuit
Pin 27, 28, 29
2.7 kΩ
100 Ω
200 Ω
VREF
30
38
25 µA
200 Ω 84 kΩ
R1
30
230 Ω
C1
1 µF
3.6 kΩ
R2
6.3 V
50 µA
Chroma APC filter pin:
• Filter pin for APC detection circuit
(operates for BGP period).
• External R2 → larger, detection
sensitivity becomes larger.
(It is tends to be pulled in easily but
tends to be affected by noise)
• Lag-lead filter is organized by R1,
R2, C1 and C2
0V
DC
5.5 V
C2
0.027 µF
17
AN5367FB
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
31
38
500 Ω
25 µA
200 Ω
25 µA
31
500 Ω
32
38
500 Ω
2.7 V
3 kΩ
Voltage
Subcarrier output pin:
fSC
• Controls output by 0E-D4, D7 of
300 mV[p-p]
I2C bus.
• There is fSC output.
DC: 6.1 V, AC: 350 mV[p-p]
DC
• There is no fSC output.
DC: 1.9 V, AC: 0 mV[p-p]
• Recommended range of use is from
− 0.4 mA to +0.4 mA
7.3 kΩ
5.0 V
50 µA
Killer filter pin:
• Filter pin for killer detection circuit
(operates for BGP period)
High: Killer on (B&W)
Low: Killer on (color)
DC
ABL/ACL pin:
• Apply voltage inversely proportional
to brightness of CRT screen.
• Operating range is 7 V to 2 V
• Controls contrast and brightness in
inverse proportion to applied voltage
• Recommended range of use is from
0 V to VCC1
DC
Black extension start adjusting pin:
• When current flowing out of this pin
becomes larger, black extension start
point comes closer to white side.
• Recommended range of use is from
− 0.4 mA to +0.1 mA
DC
Black level detection filter pin:
• Adjusts black level detection area
• Recommended range of use is from
0 V to 8 V
DC
32
1.25 kΩ
1.25 kΩ
0.1 µF
10 kΩ
33
38
25 µA
25 µA
100 µA
40 kΩ
5 kΩ
7V
5 kΩ
33
40 kΩ
4.75 V
34
38
20 kΩ
8 kΩ
1.2 kΩ
34
20 kΩ
35
38
5 kΩ
2 kΩ
5.18 kΩ
10 kΩ
10 kΩ
6.5 V
35
2.5 kΩ
18
4.7 µF
220 kΩ
ICs for TV
AN5367FB
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
36
38 VCC1
200 Ω
5.25 V
20 kΩ
36
Chroma signal input pin:
• 2 V[p-p] composite signal in using
H.P.F. of IC inside.
• Chroma signal of burst = 150 mV[p-p]
at externally separating Y/C.
Voltage
AC
2 V[p-p]
0.01 µF
150 mV[p-p]
200 µA
37
17 µA
300 µA
VCC1 reference voltage pin:
• Reference voltage circuit for generating
9 V power supply.
• Recommended range of use is from
1.5 mA to 4.5 mA
DC
9.6 V
Power supply pin VCC1:
• Power supply for chroma, video,
RGB and AVSW.
• Recommended range of use (typ.: 9 V)
DC
38
Capacitor pin for Y clamp:
• Clamps the pedestal level of Y signal.
• Place clamp capacitor close to pin.
DC
38
DAC output pin 2:
• Output voltage is adjustable in 128
stages (7-bit organization) by I2C subaddress (0C).
• External circuit should be high
impedance
DC
0 V to 5 V
12 V
1 kΩ
37
0.01 µF
0.01 µF
100 µF
9.6 V
Zener
38
VCC1

38
39
5 kΩ
10 µA
5 kΩ
1 kΩ
39
0.01 µF
40
2.5 kΩ
2.5 kΩ
0 µF to
100 µF
40
25 kΩ
0.01 µF
5 kΩ
10 kΩ
19
AN5367FB
ICs for TV
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
Description
41
38
200 Ω
50 µA
200 Ω
Y signal input pin:
• Video signal input pin.
• Input 2 V[p-p] signal.
Voltage
AC
2 V[p-p]
2.75 V
10 µF
41
500 Ω
10 µA
50 µA
42
38
2 kΩ
61.2 kΩ
4 kΩ
Y signal APL detection filter pin:
• Current flows out according to APL
and is smoothed by external CR to
generate DC voltage.
DC
42
4.7 µF
20 kΩ
43
47
20 µA
5V
50 µA
3.25 V
10 kΩ
4.7 kΩ
1 kΩ
43
Clock
51 kΩ
2 kΩ
SCL pin (for I2C bus):
• Low-level input: 1.5 V or less
• High-level input: 3.0 V or more
• Recommended range of use is from
0 V to VCC2
AC
(Pulse)
5V
0V
30
kΩ
30
kΩ
To logic circuit
44
47
20 µA
5V
50 µA 3.25 V
10 kΩ
4.7 kΩ
1 kΩ
51 kΩ
44
2 kΩ
Data
30
kΩ
ACK
Killer output pin:
• Output pin of killer detection circuit
• Output logic
At color: Low
At B&W: High
However, if 0E-D4 is set at "1" by
I2C bus, output becomes open.
• Recommended range of use is from
−300 µA to +300 µA
DC
5V
0V
To logic circuit
47
5 kΩ
1 kΩ
45
20
AC
(Pulse)
30
kΩ
45
40 kΩ
SDA pin (for I2C bus):
• Low-level input: 1.5 V or less
• High-level input: 3.5 V or more
• ACK sink capability: 3 mA
• Recommended range of use is from
0 V to VCC
ICs for TV
AN5367FB
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
46
200 Ω
Description
38 VCC1
9V
25 µA
200 Ω
1.25 kΩ
10 µF
46
10 µA
2.75 V

47
48
200 Ω
38 VCC1
9V
25 µA
200 Ω
1.25 kΩ
10 µF
48
2.75 V
10 µA
Video signal input pin 3:
• Video signal input pin
• Typical input 1.0 V[p-p]
• Input should be done through capacitor,
and sync. top is clamped at 2.0 V.
• Video signal should be inputted in
low impedance
Voltage
AC
1.0 V[p-p]
2V
Power supply pin (VCC2: 5 V):
• I2 C
• To be used for sync. block
• Using range from 4.75 V to 5.25 V
(typ.: 5 V)
DC
Video signal input pin 2:
• Video signal input pin
• Typical input 1.0 V[p-p]
• Input should be done through capacitor,
and sync. top is clamped at 2.0 V.
• Video signal should be inputted in
low impedance
AC
1.0 V[p-p]
2V
Note) 1. Do not apply external currents or voltages to any pins not specifically mentioned.
For circuit currents, '+' denotes current flowing into the IC, and '−' denotes current flowing out of the IC.
2. The following pins are not resistant to surge so that the precautions should be observed when using this IC.
The + side surge withstanding voltage for pin 15, pin 16 and pin 18 is approximately 200 V when a surge source capacitance
is 200 pF. Do not apply a surge voltage higher than that.
21
AN5367FB
ICs for TV
2SD1991A
VCCREF
0.01 µF
0.33 µF
20 kΩ 10 µF
4.7 µF
4.7 kΩ
Killer out
10 µF
Video3
FSC
100 Ω
requires when
adjusting
25
26
27
28
29
30
31
32
Spot killer
1 µF
OSD-B in
OSD-G in
100 Ω
100 Ω
0.027 µF
OSD-R in
APC filter
1 µF 3.6 kΩ
SC out
Killer filter
0.1 µF
ABL/ACL
56 kΩ
33
34
23
Chroma
22
RGB
40
21
41
20
Limiter
R out
100 Ω
G out
100 Ω
B out
100 Ω
YS
Video
42
19
43
18
44
17
I2C
45
H out
BLK in
GND (main)
16
Sync.
46
47
15
FBP in
0.022 µF
0.01 µF
48
0.018 µF
13
Mute
Hold down ref.
HSYNC in
VSYNC in
DAC2 (sound)
Video out
VSYNC
12 V
12
11
10
9
10 µF 2.2 kΩ
CSB503F38
220 pF
(N750)
H OSC
10 µF
100 Ω
X-ray
V out
GND (jungle)
L det. out
560 Ω
6V
270 Ω
560 Ω
8
7
0.1 µF
6
1 µF 5
680 pF
1 200 pF
2.2 µF
4
1
10 µF
0.01 µF
760 Ω
12 V
H VCC (6.2 V)
H AFC1
10 µF
Video1
L det. filter
14
SW
12 V
22
9 V Normally open,
47 µF
100 µF
Video2
38
0.01 µF
5V
5V
4.7 kΩ
VCC2 (5 V)
24
3
SDA
VSXSO190
39
0.01 µF
SCL
(N750)
15 pF
37
220 Ω
P clamp
DAC1
(V height)
Y in
APL det.
9V
100 µF
2
VCC1 (9 V)
0.01 µF
35
1 kΩ
36
12 V
4.7 µF
0.1 µF
C in
220 kΩ
BL det.
BL start
■ Application Circuit Example