TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 • • • • • • • • • • • • High-Resolution, Solid-State Frame-Transfer Image Sensor 13.5-mm Image-Area Diagonal 1000 (H) × 510 (V) Active Elements in Image-Sensing Area Square Pixels Low Dark Current Electron-Hole Recombination Antiblooming Dynamic Range . . . More Than 60 dB High Sensitivity High Photoresponse Uniformity High Blue Response Single-Phase Clocking Solid-State Reliability With No Image Burn-in, Residual Imaging, Image Distortion, Image Lag, or Microphonics DUAL-IN-LINE PACKAGE (TOP VIEW) OUT1 1 24 ABGS AMP GND 2 23 SAG OUT2 3 22 ABGI ADB 4 21 IAG SUB 5 20 SUB RST2 6 19 TDB RST1 7 18 SUB CDB 8 17 SUB SRG1 9 16 IAG SRG2 10 15 ABGI TRG 11 14 SAG IDB 12 13 ABGS description The TC213 is a frame-transfer charge-coupled device (CCD) image sensor that provides very high-resolution image acquisition for image-processing applications such as robotic vision, medical X-ray analysis, and metrology. The image format measures 12.00 mm horizontally by 6.12 mm vertically; the image-area diagonal is 13.5 mm. The image-area pixels are 12-µm square. The image area contains 510 active lines with 1000 active pixels per line. Two additional dark reference lines give a total of 512 lines in the image area, and 24 additional dark-reference pixels per line give a total of 1024 pixels per horizontal line. The storage section of the TC213 contains 512 lines with 1024 pixels per line. This area is protected from exposure to light by an aluminum light shield. Photoelectric charge that is generated in the image area of the TC213 can be transferred into the storage section in less than 500 µs. After image capture (integration time), the readout is accomplished by transferring the charge, one line at a time, into two serial registers located below the storage area, each of which contains 512 data elements and 12 dummy elements. One serial-register clocks out charge that is generated in the odd-numbered columns of pixels in the imaging area; the other serial-register processes charge from the even-numbered columns of the imaging area. The typical serial-register data rate is 10 megapixels per second. Three transfer gates are used to isolate the serial registers. If the storage area or storage and image areas need to be cleared of all charge, charge may be quickly transferred across the serial registers and into the clearing drain, which is located below the serial-register section. This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. Copyright 1991, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-1 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 description (continued) Gated floating-diffusion detection structures are used with each serial register to convert charge to signal voltage. External resets allow the application of off-chip correlated clamp sample-and-hold amplifiers for low-noise performance. To provide high output-drive capability, both outputs are buffered by low-noise, two-stage, source-follower amplifiers. These two output signals can provide a data rate of 20 megapixels per second when combined off chip. An output of 30 frames per second with one field per frame is typical. At room temperature, the readout noise is 55 elecrons and a minimum dynamic range of 60 dB is available. The blooming protection incorporated into the sensor is based on recombining excess charge with charge of opposite polarity in the substrate. This antiblooming is activated by supplying clocking pulses to the antiblooming gate, which is an integral part of each image-sensing element. The storage area antiblooming gate is clocked only for charge transfer in normal use. The TC213 is built using TI-proprietary virtual-phase technology, which provides devices with high blue response, low dark signal, good uniformity, and single-phase clocking. The TC213 is characterized for operation from –10°C to 40°C. functional block diagram Top Drain TDB 19 16 IAG ABGI SAG ABGS ADB RST2 OUT2 RST1 OUT1 21 Image Area With Blooming Protection 22 IAG ABGI 24 Dark Reference Elements 23 14 24 4 13 Amplifiers 6 SAG ABGS Storage Area 3 IDB 12 7 10 9 1 Multiplexer, Transfer Gates, and Serial Registers Clearing Drain 12 Dummy Elements 2 AMP GND 2-2 15 8 CDB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SRG2 SRG1 TRG TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 sensor topology diagram 1000 Pixels 22 Pixels 1 Pixel 510 Lines 1 Pixel 2 Lines 512 Lines Dummy Pixels 12 511 12 511 Terminal Functions TERMINAL I/O DESCRIPTION NAME ABGI† NO. 15 I Antiblooming gate for image area ABGI† ABGS† 22 I Antiblooming gate for image area 13 I Antiblooming gate for storage area ABGS† 24 I Antiblooming gate for storage area ADB 4 I Supply voltage for amplifier drain bias AMP GND 2 CDB IAG† 8 I Supply voltage for clearing drain bias 16 I Image-area gate IAG† 21 I Image-area gate IDB 12 I Supply voltage for input diode bias OUT1 1 O Output signal 1 OUT2 3 O Output signal 2 RST1 7 I Reset gate 1 RST2 SAG† 6 I Reset gate 2 14 I Storage-area gate SAG† 23 I Storage-area gate SRG1 9 I Serial-register gate 1 SRG2 SUB† 10 I Serial-register gate 2 5 Substrate and clock return SUB† SUB† 17 Substrate and clock return 18 Substrate and clock return SUB† 20 TDB 19 I TRG 11 I Amplifier ground Substrate and clock return Supply voltage for top drain bias Transfer gate † All pins of the same name should be connected together externally (i.e., pin 15 to pin 22, pin 13 to pin 24, etc.). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-3 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 detailed description The TC213 consists of four basic functional blocks: (1) the image-sensing area, (2) the image-storage area, (3) the multiplexer block with serial registers and transfer gates, and (4) the low-noise signal-processing amplifier block with charge-detection nodes. The location of each of these blocks is identified in the functional block diagram. image-sensing and image-storage areas Figures 1 and 2 show cross sections with potential well diagrams and top views of image-sensing elements. As light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential wells of the sensing elements. During this time, blooming protection is activated by applying a burst of pulses to the antiblooming gate inputs every horizontal blanking interval. This prevents blooming caused by the spilling of charge from overexposed elements into neighboring elements. After integration is complete, the signal charge is transferred into the storage area (see Figure 5). There are 24 full columns of elements at the left edge of the image-sensing area that are shielded from incident light; these elements provide the dark reference used in subsequent video-processing circuits to restore the video black level. There are also two dark lines at the bottom of the image-sensing area that prevent charge leakage from the image-sensing area into the image-storage area. multiplexer with transfer gates and serial registers The multiplexer and transfer gates transfer charge line by line from the image-storage area columns into the corresponding serial registers and prepare it for readout. Figure 3 illustrates the layout of the multiplexing gate that vertically separates the pixels for input into the serial registers. Figure 4 shows the layout of the interface region between the serial-register gates and the transfer gates. Multiplexing is activated during the horizontal blanking interval by applying appropriate pulses to the transfer gates and serial registers; the required pulse timing is shown in Figure 6. A drain is also included to provide the capability to clear the image-sensing area of unwanted charge. Such charge can accumulate in the imager during the start-up of operation or under special circumstances when nonstandard timing is desired. The clear timing is given as part of the parallel-transfer timing in Figure 5. serial-register readout and video processing After transfer into the serial registers, the pixels are normally read out 180° out of phase (see Figure 7). Each serial register must be reset to the reference level before the next pixel is read out. The timing for the resets and their relationships to the serial-register pulses is shown in Figure 8. Figure 8 also shows the timing for the pixel clamp and sample and hold needed for an off-chip double-correlated sampling circuit. These two output signals can provide a data rate of 20 million pixels per second when combined off chip. After the charge is placed on the detection node, it is buffered and amplified by a low-noise, dual-stage source follower. Each serial register contains 12 dummy elements that are used to span the distance between the serial register and the output amplifier. A schematic is shown in Figure 9. The location of the dummy elements, which are considered to be part of the amplifiers, is shown in the functional block diagram. Figure 10 gives the timing for a single frame of video. An output of 30 frames per second with one field per frame is typical. 2-4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 12 µm(H) Light Clocked Barrier φ-IAG 12 µm(V) Virtual Barrier φ-ABG Antiblooming Clocking Levels Antiblooming Gate Virtual Well Clocked Well Accumulated Charge Figure 1. Charge-Accumulation Process φ-PS Clocked Phase Virtual Phase Channel Stops Figure 2. Charge-Transfer Process Channel Stops Channel Stop Virtual Well Clocked Wells SerialRegister Gate Clocked Well Multiplexing Gate Transfer Gate Figure 3. Multiplexing-Gate Layout POST OFFICE BOX 655303 Figure 4. Interface-Region Layout • DALLAS, TEXAS 75265 2-5 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 1 µs Line 1 Line 2 Line 511 Line 512 IAG SAG High Intermediate ABGI Low Intermediate ABGS TRG SRG1† SRG2† RST1 RST2 High High † SRG1 and SRG2 pulses are extended to equal TRG and SAG pulse widths during parallel transfers from the storage area to the clearing drain. Figure 5. Parallel-Transfer Timing 2-6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 CSYNC CBLNK TRG SRG1† SRG2† RST1 High RST2 High CL1 Low CL2 Low SH1 Low SH2 Low SAG ABGS Intermediate ABGI CPOB1 CPOB2 IAG Low † SRG1 and SRG2 pulses are extended to equal TRG and SAG pulse widths during horizontal line transfer operation for readout. Figure 6. Horizontal Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-7 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 Dummy 1 2 3 Black Reference 11 12 1 2 Image 11 12 1 2 3 SRG2 1 2 3 12 1 2 12 1 2 3 SRG1 NOTE A: A minimum of 524 clock pulses is required to transfer out all elements of a serial register. Overclocking is recommended. Figure 7. Start of Serial-Transfer Timing 2-8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 OUT CCD SRG Buffer RST Pixel Clamp Sampleand-Hold Amplifier CL SH SRG1 RST1 OUT1 CL1 SH1 SRG2 RST2 OUT2 CL2 SH2 NOTE A: The video-processing (off-chip) pulses are defined as follows: CL1 = Clamp pulse for video from OUT1 CL2 = Clamp pulse for video from OUT2 SH1 = Sample pulse for the sample-and-hold amplifier for video 1 SH2 = Sample pulse for the sample-and-hold amplifier for video 2 CSYNC = Composite video-sync pulse CBLNK = Composite video-blanking pulse CPOB1 = Dark-reference clamp pulse for video from OUT1 CPOB2 = Dark-reference clamp pulse for video from OUT2 Figure 8. Video-Process Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-9 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 Reference Generator ADB CCD Register Clocked Virtual Gate Gate Reset Gate and Output Diode Detection Node Two-Stage SourceFollower Amplifier OUTn SRGn RSTn Figure 9. Buffer Amplifier and Charge-Detection Node 2-10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 Horizontal Timing Vertical Timing IAG SAG TRG 541 Pulses 512 Pulses SRG1 SRG2 ABGI ABGS RST1 RST2 CBLNK Figure 10. Clock Timing Requirements – Continuous Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-11 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 spurious nonuniformity specification The spurious nonuniformity specification of the TC213 CCD grades – 30 and – 40 is based on several sensor characteristics: • • • Amplitude of the nonuniform line or pixel Polarity of the nonuniform pixel – Black – White Nonuniform line or pixel count The CCD sensors are characterized in both an illuminated condition and a dark condition. In the dark condition, the nonuniformity is specified in terms of absolute amplitude as shown in Figure 11. In the illuminated condition, the nonuniformity is specified as a percentage of the total illumination as shown in Figure 12. The pixel nonuniformity specification for the TC213 is as follows (CCD video-output signal is 50 mV ±10 mV): NONUNIFORMITY TYPE TC213-30 TC213-40 Maximum amplitude = 1.4 mV Line Number with amplitude greater than 1 mV is ≤ 6 White spot (40°C) Maximum amplitude = 25 mV White spot (25°C) Maximum amplitude = 8 mV Maximum amplitude = 12 mV Number with amplitude greater than 6 mV = B Number with amplitude greater than 10 mV = B Maximum amplitude = 20% Maximum amplitude = 25% Black spot (% of total illumination) Number with amplitude greater than 10% = C Number with amplitude greater than 15% = C Total number of nonuniformities B + C < 11 B + C < 51 mV Amplitude % of Total Illumination t Figure 11. Pixel Nonuniformity, Dark Condition 2-12 POST OFFICE BOX 655303 t Figure 12. Pixel Nonuniformity, Illuminated Condition • DALLAS, TEXAS 75265 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range for ADB, CDB, IDB, TDB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 15 V Input voltage range for ABGI, ABGS, IAG, RST1, RST2, SAG, SRG1, SRG2, TRG . . . . . . . . –15 V to 15 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10°C to 40°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the substrate terminal. recommended operating conditions Supply voltage for ADB, CDB, IDB, TDB MIN NOM MAX 11 12 13 Substrate bias voltage 0 IAG SAG SRG Input voltage, VI‡ RST1 RST2 RST1, ABGI, ABGS TRG High level 1.5 Low level –11 High level 1.5 Low level –11 High level 1.5 Low level –11 High level 1.5 Low level –11 Capacitive load V V 2 2.5 2 2.5 2 2.5 –9 –9 –9 2 2.5 V –9 High level (ABGI only) Intermediate level§ 5 5.5 6 –1.5 –1. 2 – 0.9 Low level –7.5 –7 – 6.5 High level 1.5 2 2.5 Low level –11 RST1, RST2, SRG1, SRG2, TRG Clock frequency, fclock UNIT –9 10 IAG, SAG 1 ABGI, ABGS 1 OUT1, OUT2 MHz 8 pF Operating free-air temperature, TA – 10 40 °C ‡ The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for clock voltage levels. § Adjustment is required for optimal performance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-13 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 electrical characteristics over recommended operating ranges of supply voltage and free-air temperature PARAMETER MIN Dynamic range (see Note 2) TYP† MAX 60 Charge conversion factor dB µV/e 6 Charge transfer efficiency (see Note 3) UNIT 0.99990 Signal response delay time, τ (see Note 4 and Figure 16) Gamma (see Note 5) Output resistance 1/f noise (5 kHz) Noise voltage 18 20 22 0.89 0.94 0.99 600 800 0.1 Random noise (f = 100 kHz) 60 Rejection ratio at 10 MHz ADB (see Note 6) 20 SRGn (see Note 7) 40 ABGx (see Note 8) 30 Supply current electrons dB 9 IAG, SAG mA 15000 ABGI, ABGS Input capacitance, capacitance Ci Ω µV/√Hz 0.08 Noise equivalent signal ns 8000 TRG 350 pF SRG1, SRG2 200 † All typical values are at TA = 25°C. NOTES: 2. Dynamic range is – 20 times the logarithm of the mean noise signal divided by the saturation output signal. 3. Charge transfer efficiency is one minus the charge loss per transfer in the output register (1046 transfers). The test is performed in the dark using an electrical input signal. 4. Signal-response delay time is the time between the falling edge of the SRG clock pulse and the output signal valid state. 5. Gamma (γ) is the value of the exponent in the equation below for two points on the linear portion of the transfer function curve (this value represents points near saturation): ǒ Ǔ +ǒ Exposure (2) Exposure (1) g Ǔ Output signal (2) Output signal (1) 6. ADB rejection ratio is – 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on ADB. 7. SRGn rejection ratio is – 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on SRGn. 8. ABGx rejection ratio is – 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on ABGx. 2-14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 optical characteristics, TA = 25°C, integration time = 33 ms (unless otherwise noted) PARAMETER No IR filter Sensitivity (see Note 9) With IR filter MIN TYP MAX UNIT 518 Measured at VU (see Note 10) mV/lx 64 Saturation signal, Vsat (see Note 11) 320 mV Maximum usable signal, Vuse 200 mV Blooming overload ratio (see Note 12) 100 60 x 103 Image-area well capacity Smear (see Note 13) electrons 0.0016 Dark current Dark signal (see Note 14) TA = 40°C Pixel uniformity Column uniformity Shading TA = 21°C TC213-30 nA/cm2 0.027 5 TC213-40 5 TC213-30 8 TC213-40 12 TC213-30 1.4 TC213-40 1.4 VO = 1/2 VU (see Note 10) mV mV mV 15% NOTES: 9. Sensitivity is measured at an integration time of 33 ms with a source temperature of 2859 K. A CM-500 filter is used. Sensitivity is measured at any illumination level that gives an output voltage level less than VU. 10. VU is the output voltage that represents the threshold of operation of antiblooming. VU ≈ 1/2 saturation signal. 11. Saturation is the condition in which further increase in exposure does not lead to further increase in output signal. 12. Blooming is the condition in which charge is induced in an element by light incident on another element. Blooming overload ratio is the ratio of blooming exposure to saturation exposure. 13. Smear is the measure of error induced by transferring charge through an illuminated pixel in shutterless operation. It is equivalent to the ratio of the single-pixel transfer time during a fast dump to the exposure time using an illuminated section that is 1/10 of the image area vertical height with recommended clock frequencies. Exposure time is 33 ms, the fast dump clocking rate during vertical timing is 1 MHz, and the illuminated section is 1/10 of the height of the image section. 14. Dark-signal level is measured from the dark dummy pixels. timing requirements MIN IAG tr Rise time SRG 10 SAG 200 TRG 200 ABGI, ABGS 100 RST1, RST2 Fall time UNIT ns 10 IAG tf MAX 200 200 SRG 10 SAG 200 TRB 200 ABGI, ABGS 100 RST1, RST2 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 2-15 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 PARAMETER MEASUREMENT INFORMATION Blooming Point With Antiblooming Enabled VO Blooming Point With Antiblooming Disabled Dependent On Well Capacity Vsat (min) Level Dependent Upon Antiblooming Gate High Level Vuse (max) Vuse (typ) DR Vn Lux (light input) DR (dynamic range) + camera whiteVn clip voltage Vn = noise floor voltage Vsat (min) = minimum saturation voltage Vuse (max) = maximum usable voltage Vuse (typ) = typical user voltage (camera white clip) NOTES: A. Vuse (typ) is defined as the voltage determined to equal the camera white clip. This voltage must be less than Vuse (max). B. A system trade-off is necessary to determine the system light sensitivity versus the signal/noise ratio. By lowering the Vuse (typ), the light sensitivity of the camera is increased; however, this sacrifices the signal/noise ratio of the camera. Figure 13. Typical Vsat, Vuse Relationship 2-16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 PARAMETER MEASUREMENT INFORMATION VIH min 100% 90% Intermediate Level 10% VIL max 0% tr tf Figure 14. Typical Clock Waveform for ABGI, ABGS, IAG, and SAG VIH min 100% 90% Intermediate Level 10% VIL max 0% tf tr Figure 15. Typical Clock Waveform for RST1, RST2, SRG1, SRG2, and TRG 1.5 V to 2.5 V SRG –9V – 9 V to – 11 V 0% OUT 90% 100% CCD Delay τ 10 ns 15 ns Sample and Hold Figure 16. SRG and OUT Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-17 TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 APPLICATION INFORMATION VSS OUT VCC GND GND V VCC TMS3473B Master Oscillator V IAG ABGI GT1 CBLNK ABGS CL2 GT2 CL1 SAG CSYNC RST2 SH2 RST1 SH1 SRG1 TRG SRG2 CLK CBLNK CL2 CL1 CSYNC SH2 SH1 User-Defined Timer VCC 1 2 3 4 5 6 7 8 9 10 VSS IASR ABSR VCC ABLVL IAOUT ABOUT SAOUT VCC VABG– IALVL I/N IAIN ABIN MIDSEL SAIN PD GND VAGB+ VSS 20 19 18 17 16 15 14 13 12 11 ABLVL 2N3904 12 V VABG – 100 Ω Parallel Driver OUT 2 1 kΩ VABG + TMS3473B V VCC 1 2 3 4 5 6 7 8 9 10 IALVL I/N IAIN ABIN MIDSEL SAIN PD GND VAGB+ VSS VSS IASR ABSR VCC ABLVL IAOUT ABOUT SAOUT VCC VABG – 20 19 18 17 16 15 14 13 12 11 2N3904 12 V 100 Ω ABLVL TC213 VABG – 1 2 3 4 5 6 7 8 9 10 11 12 Parallel Driver VABG + SN28846 VCC 1 2 3 4 5 6 7 8 9 10 SEL0OUT GND PD SRG3IN SRG2IN SRG1IN TRGIN NC SEL1OUT VSS VSS SEL0 NC VCC SRG3OUT SRG2OUT SRG1OUT TRGOUT VCC SEL1 20 19 18 17 16 15 14 13 12 11 12 V Serial Driver VCC SEL0OUT GND PD SRG3IN SRG2IN SRG1IN TRGIN NC SEL1OUT VSS VSS SEL0 NC VCC SRG3OUT SRG2OUT SRG1OUT TRGOUT VCC SEL1 24 OUT1 ABGS 23 AMP GND SAG 22 OUT2 ABGI 21 ADB IAG 20 SUB SUB 19 RST2 TDB 18 RST1 SUB 17 CDB SUB 16 SRG1 IAG 15 SRG2 ABGI 14 TRG SAG 13 IDB ABGS Image Sensor DC VOLTAGES 12 V ADB 5V VCC – 10 V VSS 2V V – 2.5 V ABLVL 4V VABG + –6 V VABG – SN28846 1 2 3 4 5 6 7 8 9 10 OUT 1 1 kΩ 20 19 18 17 16 15 14 13 12 11 Serial Driver SUPPORT CIRCUITS DEVICE PACKAGE APPLICATION FUNCTION SN28846DW 20 pin small outline Serial driver Driver for TRG, SRG1, SRG2, RST1, RST2 TMS3473BDW 20 pin small outline Parallel driver Driver for IAG, SAG, ABGI, ABGS Figure 17. Typical Application Circuit Diagram 2-18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 V TC213 1024- × 512-PIXEL CCD IMAGE SENSOR SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 MECHANICAL DATA The package for the TC213 consists of a ceramic base, a glass window, and a 24-lead frame. The glass window is sealed to the package by an epoxy adhesive. The package leads are configured in a dual in-line organization and fit into mounting holes with 2,54 mm (0.1 in) center-to-center spacings. 30,91 (1.217) 30,05 (1.183) 2,67 (0.105) NOM 2,54 (1.000) 4,93 (0.194) MAX 12,50 (0.492) NOM 3,81 (0.150) NOM 0,33 (0.013) 0,17 (0.007) 2,00 (0.079) NOM DIA +0.01 (+0.0004) 6,80 (0.268) 5,80 (0.228) 3,75 (0.148) 2,75 (0.108) Optical Center Package Center (see Note C) 22,83 (0.899) 22,38 (0.881) 20,93 (0.824) 20,83 (0.820) 23,29 (0.917) 22,43 (0.883) T.P. 20,93 (0.824) 20,83 (0.820) 1,40 (0.055) 0,64 (0.025) 6,30 (0.248) 4,70 (0.185) 2,54 (0.100) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 7/94 NOTES: A. Each pin centerline is located within 2,54 mm (0.1 inch) of its true longitudinal position. B. The optical center line and the center line of the ceramic package are not coincident. C. Maximum rotation is ± 3.5°. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-19 SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991 2-20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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