DISCRETE SEMICONDUCTORS DATA SHEET PSMN005-55B; PSMN005-55P N-channel logic level TrenchMOS(TM) transistor Product specification October 1999 Philips Semiconductors N-channel logic level Product specification TrenchMOS(TM) FEATURES transistor SYMBOL PSMN005-55B; PSMN005-55P QUICK REFERENCE DATA • ’Trench’ technology • Very low on-state resistance • Fast switching • Low thermal resistance d VDSS = 55 V ID = 75 A RDS(ON) ≤ 5.8 mΩ (VGS = 10 V) g RDS(ON) ≤ 6.3 mΩ (VGS = 5 V) s GENERAL DESCRIPTION SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:• d.c. to d.c. converters • switched mode power supplies The PSMN005-55P is supplied in the SOT78 (TO220AB) conventional leaded package. The PSMN005-55B is supplied in the SOT404 surface mounting package. PINNING SOT78 (TO220AB) PIN SOT404 (D2PAK) DESCRIPTION tab tab 1 gate 2 drain1 3 source tab 2 drain 1 1 23 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Continuous gate-source voltage Peak pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature MIN. MAX. UNIT Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 55 55 ± 15 V V V Tj ≤ 150 ˚C - ± 20 V - 55 752 752 240 230 175 A A A W ˚C Tmb = 25 ˚C; VGS = 5 V Tmb = 100 ˚C; VGS = 5 V Tmb = 25 ˚C Tmb = 25 ˚C 1 It is not possible to make connection to pin:2 of the SOT404 package 2 maximum current limited by package October 1999 2 Rev 1.200 Philips Semiconductors N-channel logic level Product specification TrenchMOS(TM) PSMN005-55B; PSMN005-55P transistor THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint TYP. MAX. UNIT - 0.65 K/W 60 50 - K/W K/W MIN. MAX. UNIT - 268 mJ - 75 A AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS EAS Non-repetitive avalanche energy Unclamped inductive load, IAS = 75 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 15 V; RGS = 50 Ω; VGS = 5 V IAS Non-repetitive avalanche current ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) IGSS IDSS Drain-source on-state resistance VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 4.5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C Gate source leakage current VGS = ± 10 V; VDS = 0 V Zero gate voltage drain VDS = 55 V; VGS = 0 V; current Tj = 175˚C TYP. MAX. UNIT 55 50 1.0 0.5 - 1.5 4.8 5.3 2 0.05 - 2.0 2.3 5.8 6.3 6.7 13.2 100 10 500 V V V V V mΩ mΩ mΩ mΩ nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 75 A; VDD = 44 V; VGS = 5 V - 103 15 52 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; RD = 1.2 Ω; VGS = 5 V; RG = 10 Ω Resistive load - 45 180 420 235 - ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 6500 1500 700 - pF pF pF October 1999 3 Rev 1.200 Philips Semiconductors N-channel logic level Product specification TrenchMOS(TM) PSMN005-55B; PSMN005-55P transistor REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr CONDITIONS MIN. Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V Reverse recovery time Reverse recovery charge October 1999 IF = 20 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V 4 TYP. MAX. UNIT - - 75 A - - 240 A - 0.85 1.1 1.2 - V V - 80 0.2 - ns µC Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS(TM) PSMN005-55B; PSMN005-55P transistor Normalised Power Derating, PD (%) Transient thermal impedance, Zth j-mb (K/W) 1 100 D = 0.5 90 0.2 80 0.1 70 0.1 60 0.05 50 0.02 40 P D 0.01 tp D = tp/T 30 single pulse 20 T 10 0.001 1E-06 0 0 25 50 75 100 125 150 Mounting Base temperature, Tmb (C) 175 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 400 Normalised Current Derating, ID (%) 100 90 80 5.0 4.8 4.6 10.0 7.0 6.0 ID/A VGS\V = 4.4 300 4.2 200 4.0 3.8 3.6 70 60 50 40 3.4 30 3.2 20 3.0 100 2.8 2.6 2.4 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 2 4 6 VDS/D 8 10 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) Peak Pulsed Drain Current, IDM (A) 1000 0 8.5 RDS(ON)/mOhm VGS/V = RDS(on) = VDS/ ID tp = 10 us 8 7.5 100 100 us 7 1 ms 3.0 D.C. 10 6.5 3.2 3.4 10 ms 100 ms 6 3.6 4.0 5.5 5.0 1 1 10 Drain-Source Voltage, VDS (V) 100 5 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp October 1999 0 20 40 ID/A 60 80 100 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) 5 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS(TM) PSMN005-55B; PSMN005-55P transistor 100 2.25 ID/A Threshold Voltage, VGS(TO) (V) 2 80 maximum 1.75 typical 1.5 60 1.25 minimum 1 40 Tj = 175 0.75 25 0.5 20 0.25 0 0 -60 -40 -20 0 0.5 1 1.5 2 2.5 3 3.5 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) VGS/V Fig.7. Typical transfer characteristics. ID = f(VGS) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 150 1.0E-01 gfs/S Drain current, ID (A) 1.0E-02 100 1.0E-03 minimum typical 1.0E-04 maximum 50 1.0E-05 1.0E-06 0 0 0 20 40 ID/A 60 80 0.5 100 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised On-state Resistance 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 100000 Capacitances, Ciss, Coss, Crss (pF) Ciss 10000 Coss 1000 Crss 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 0.1 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) October 1999 1 10 Drain-Source Voltage, VDS (V) 6 Rev 1.200 Philips Semiconductors Product specification N-channel logic level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TrenchMOS(TM) PSMN005-55B; PSMN005-55P transistor Gate-source voltage, VGS (V) Maximum Avalanche Current, IAS (A) 100 ID = 75 A Tj = 25 C 25 C VDD = 11 V 10 VDD = 44 V 0 25 50 75 100 125 150 175 Gate charge, QG (nC) 200 225 1 0.001 250 Tj prior to avalanche = 150 C 0.01 0.1 1 10 Avalanche time, tAV (ms) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load 100 IF/A 80 60 Tj/C = 25 175 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VSDS/V 0.7 0.8 0.9 1 1.1 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj October 1999 7 Rev 1.200 Philips Semiconductors Product specification TrenchMOS(TM) N-channel logic level PSMN005-55B; PSMN005-55P transistor MECHANICAL DATA Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 E SOT78 A A1 P q D1 D L1 L2(1) Q b1 L 1 2 3 c b e e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 c D D1 E e L L1 L2 max. P q Q mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 2.54 15.0 13.5 3.30 2.79 3.0 3.8 3.6 3.0 2.7 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 TO-220 Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g) Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". October 1999 8 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS(TM) PSMN005-55B; PSMN005-55P transistor MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.40 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 SOT404 Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". October 1999 9 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOS(TM) PSMN005-55B; PSMN005-55P transistor MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 603502/300/04/pp12 Date of release: October 1999 Document order number: 9397 750 06976