LINER LTC4441IS8-1

LTC4441/LTC4441-1
N-Channel MOSFET
Gate Driver
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FEATURES
DESCRIPTIO
■
The LTC®4441/LTC4441-1 is an N-channel MOSFET gate
driver that can supply up to 6A of peak output current. The
chip is designed to operate with a supply voltage of up to
25V and has an adjustable linear regulator for the gate
drive. The gate drive voltage can be programmed between
5V and 8V.
■
■
■
■
■
■
■
■
■
■
6A Peak Output Current
Wide VIN Supply Range: 5V to 25V
Adjustable Gate Drive Voltage: 5V to 8V
Logic Input can be Driven Below Ground
30ns Propagation Delay
Supply Independent CMOS/TTL Input Thresholds
Undervoltage Lockout
Low Shutdown Current: <12µA
Overtemperature Protection
Adjustable Blanking Time for MOSFET’s
Current Sense Signal (LTC4441)
Available in SO-8 and 10-Lead MSOP
(Exposed Pad) Packages
The LTC4441/LTC4441-1 features a logic threshold driver
input. This input can be driven below ground or above the
driver supply. A dual function control input is provided to
disable the driver or to force the chip into shutdown mode
with <12µA of supply current. Undervoltage lockout and
overtemperature protection circuits will disable the driver
output when activated. The LTC4441 also comes with an
open-drain output that provides adjustable leading edge
blanking to prevent ringing when sensing the source
current of the power MOSFETs.
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APPLICATIO S
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■
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Power Supplies
Motor/Relay Control
Line Drivers
Charge Pumps
The LTC4441 is available in a thermally enhanced 10-lead
MSOP package. The LTC4441-1 is the SO-8 version without the blanking function.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents
including 6677210.
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TYPICAL APPLICATIO
D1
L1
10µH 20A MBR10100
+
R5
R1
330k
VIN
FB
SHUTDOWN
Q2
R6
R2
86.6k
DRVCC
SGND
OUT
CVCC
10µF
X5R
LTC4441
EN/SHDN
LTC3803
SWITCHING
CONTROLLER
GATE
SENSE+
GND
IN
+
COUT
VOUT
52V
2A
TA = 25°C
180 DRVCC = 5V
160
Si7370
×2
PGND
BLANK
RISE/FALL Time vs CLOAD
200
R3
5mΩ
R7
RBLANK
22µF
25V
X7R
RISE/FALL TIME (ns)
VIN
6V TO 24V
R4
100Ω
140
120
100
RISE TIME
80
60
40
FALL TIME
20
R8
511k
FB
R9
8.06k
0
0
5
10 15 20 25 30 35 40 45 50
CLOAD (nF)
4441 TA01b
4441 TA01
44411f
1
LTC4441/LTC4441-1
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ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage
VIN ...................................................................... 28V
DRVCC .................................................................. 9V
Input Voltage
IN .......................................................... –15V to 15V
FB, EN/SHDN ........................ –0.3V to DRVCC + 0.3V
RBLANK, BLANK (LTC4441 Only) .......... –0.3V to 5V
OUT Output Current ............................................ 100mA
Operating Temperature Range (Note 2) .. – 40°C to 85°C
Junction Temperature (Note 8) ............................ 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER PART
NUMBER
TOP VIEW
PGND
BLANK
RBLANK
SGND
IN
1
2
3
4
5
11
10
9
8
7
6
OUT
DRVCC
VIN
FB
EN/SHDN
MSE PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 38°C/W (NOTE 3)
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
PGND 1
8
OUT
SGND 2
7
DRVCC
IN 3
6
VIN
EN/SHDN 4
5
FB
LTC4441EMSE
LTC4441IMSE
MSE PART
MARKING
ORDER PART
NUMBER
TOP VIEW
LTBJQ
LTBJP
LTC4441ES8-1
LTC4441IS8-1
S8 PART
MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
44411
4441I1
TJMAX = 125°C, θJA = 150°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 7.5V, DRVCC = 5V, unless otherwise specified.
SYMBOL
PARAMETER
VDRVCC
Driver Supply Programmable Range
IVIN
VIN Supply Current
CONDITIONS
MIN
●
EN/SHDN = 0V, IN = 0V
EN/SHDN = 5V, IN = 0V
fIN = 100kHz, COUT = 4.7nF (Note 4)
●
●
VIN = 7.5V
●
TYP
5
MAX
8
UNITS
V
5
250
3
12
500
6
µA
µA
mA
1.21
1.31
V
9
40
DRVCC Regulator
VFB
Regulator Feedback Voltage
1.11
∆VDRVCC(LINE) Regulator Line Regulation
VIN = 7.5V to 25V
mV
∆VDRVCC(LOAD) Load Regulation
Load = 0mA to 40mA
–0.1
%
VDROPOUT
Regulator Dropout Voltage
Load = 40mA
370
mV
VUVLO
FB Pin UVLO Voltage
Rising Edge
Falling Edge
1.09
0.97
V
V
VIH
IN Pin High Input Threshold
Rising Edge
●
2
2.4
2.8
V
VIL
IN Pin Low Input Threshold
Falling Edge
●
1
1.4
1.8
V
VIH-VIL
IN Pin Input Voltage Hysteresis
Rising-Falling Edge
IINP
IN Pin Input Current
VIN = ±10V
●
±0.01
±10
µA
IEN/SHDN
EN/SHDN Pin Input Current
VEN/SHDN = 9V
●
±0.01
±1
µA
VSHDN
EN/SHDN Pin Shutdown Threshold
Falling Edge
VEN
EN/SHDN Pin Enable Threshold
Rising Edge
Falling Edge
Input
VEN(HYST)
EN/SHDN Pin Enable Hysteresis
Rising-Falling Edge
1
V
0.45
●
1.036
1.21
1.09
0.12
V
1.145
V
V
V
44411f
2
LTC4441/LTC4441-1
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 7.5V, DRVCC = 5V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
0.35
0.8
UNITS
RONL
Driver Output Pull-Down Resistance
IOUT = 100mA
IPU
Driver Output Peak Pull-Up Current
DRVCC = 8V
IPD
Driver Output Peak Pull-Down Current
DRVCC = 8V
6
A
RON(BLANK)
BLANK Pin Pull-Down Resistance
IN = 0V, IBLANK = 100mA LTC4441 Only
11
Ω
VRBLANK
RBLANK Pin Voltage
RBLANK = 200kΩ LTC4441 Only
1.3
V
COUT = 4.7nF (Note 5)
30
ns
Output
●
Ω
6
A
Switching Timing
tPHL
Driver Output High-Low Propagation Delay
tPLH
Driver Output Low-High Propagation Delay
COUT = 4.7nF (Note 5)
36
ns
tr
Driver Output Rise Time
COUT = 4.7nF (Note 5)
13
ns
tf
Driver Output Fall Time
COUT = 4.7nF (Note 5)
8
ns
tBLANK
Driver Output High to BLANK Pin High
RBLANK = 200kΩ (Note 6)
200
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC4441E/LTC4441E-1 are guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC4441I/LTC4441I-1 are
guaranteed and tested over the – 40°C to 85°C operating temperature
range.
Note 3: Failure to solder the Exposed Pad of the MSE package to the PC
board will result in a thermal resistance much higher than 38°C/W.
Note 4: Supply current in normal operation is dominated by the current
needed to charge and discharge the external power MOSFET gate. This
current will vary with supply voltage, switching frequency and the external
MOSFETs used.
Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured from 50% of input to 20%/80% levels at driver
output.
Note 6: Blanking time is measured from 50% of OUT leading edge to 10%
of BLANK with a 1kΩ pull-up at BLANK pin. LTC4441 only.
Note 7: Guaranteed by design, not subject to test.
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the maximum operating junction temperature
may impair device reliability.
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TYPICAL PERFOR A CE CHARACTERISTICS
IN Low Threshold Voltage
vs Temperature
IN High Threshold Voltage
vs Temperature
1.8
2.8
1.26
1.6
1.5
1.4
1.3
1.2
2.6
2.5
2.4
2.3
2.2
1.1
2.1
1.0
–50
2.0
–50
75
50
25
TEMPERATURE (°C)
0
100
125
4441 G01
EN PIN INPUT THRESHOLD VOLTAGE (V)
VIN = 7.5V
2.7 DRVCC = 5V
IN PIN INPUT THRESHOLD (V)
IN PIN INPUT THRESHOLD (V)
VIN = 7.5V
1.7 DRVCC = 5V
–25
EN Pin Input Threshold Voltage
vs Temperature
–25
75
50
25
TEMPERATURE (°C)
0
100
125
4441 G02
VIN = 7.5V
DRVCC = 5V
1.24
1.22
1.20
RISING EDGE
1.18
1.16
1.14
1.12
FALLING EDGE
1.10
1.08
1.06
1.04
–50 –25
0
50
75
25
TEMPERATURE (°C)
100
125
4441 G03
44411f
3
LTC4441/LTC4441-1
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TYPICAL PERFOR A CE CHARACTERISTICS
FB Pin UVLO Threshold
vs Temperature
1.16
1.12
1.08
RISING EDGE
1.04
1.00
0.96
FALLING EDGE
0.92
0.88
0.84
–50 –25
0
50
75
25
TEMPERATURE (°C)
100
5.50
0.70
5.40
VIN = 7.5V
0.75 DRVCC = 5V
R1 = 330k
5.45 R2 = 100k
0.65
0.60
RISING EDGE
0.55
0.50
0.45
0
50
75
25
TEMPERATURE (°C)
100
5.00
–50
–25
0
50
75
25
TEMPERATURE (°C)
4441 G06
DRVCC DROPOUT VOLTAGE (mV)
DRVCC (V)
125
1000
5.15
5.10
5.10
100
DRVCC Dropout Voltage vs
Temperature
5.20
5.15
5.05
VIN = 7.5V
900 DRVCC = 5V
= 40mA
I
800 LOAD
700
600
500
400
300
200
100
5.05
0
5.00
20 40 60 80 100 120 140 160 180 200
ILOAD (mA)
0
5
10
15
20
25
0
–50
30
–25
VIN (V)
4441 G07
0
50
75
25
TEMPERATURE (°C)
tPLH, tPHL vs DRVCC
0.8
60
VIN = 7.5V
0.7 DRVCC = 5V
100
125
4441 G09
4441 G08
OUT Pin Pull-Down Resistance vs
Temperature
60
TA = 25°C
CLOAD = 4.7nF
tPLH, tPHL vs Temperature
DRVCC = 5V
CLOAD = 4.7nF
50
50
0.5
0.4
0.3
40
tPLH, tPHL (ns)
0.6
tPLH, tPHL (ns)
OUT PIN PULL-DOWN RESISTANCE (Ω)
VIN = 7.5V
5.15
125
TA = 25°C
R1 = 330k
5.25 R2 = 100k
VIN = 7.5V
5.45 TA = 25°C
R1 = 330k
5.40 R2 = 100k
5.35
DRVCC (V)
5.20
5.05
5.30
5.50
5.00
VIN = 25V
5.10
DRVCC Line Regulation
5.20
5.25
4441 G05
DRVCC Load Regulation
5.25
5.30
0.35
4441 G04
5.30
5.35
FALLING EDGE
0.40
0.30
–50 –25
125
DRVCC Voltage vs Temperature
0.80
DRVCC VOLTAGE (V)
VIN = 7.5V
SD PIN INPUT THRESHOLD VOLTAGE (V)
FB PIN UVLO THRESHOLD VOLTAGE (V)
1.20
SD Pin Input Threshold Voltage
vs Temperature
tPLH
30
tPHL
tPLH
40
30
tPHL
20
20
10
10
0.2
0.1
0
–50 –25
0
50
75
25
TEMPERATURE (°C)
100
125
4441 G10
0
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0
DRVCC (V)
4441 G11
0
–50 –25
0
50
75
25
TEMPERATURE (°C)
100
125
4441 G12
44411f
4
LTC4441/LTC4441-1
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TYPICAL PERFOR A CE CHARACTERISTICS
tPLH, tPHL vs CLOAD
30
TA = 25°C
90 DRVCC = 5V
30
TA = 25°C
CLOAD = 4.7nF
60
50
tPHL
40
30
RISE/FALL TIME (ns)
70
RISE/FALL TIME (ns)
tPLH
DRVCC = 5V
CLOAD = 4.7nF
25
25
80
tPLH, tPHL (ns)
RISE/FALL Time vs Temperature
RISE/FALL Time vs DRVCC
100
20
15
RISE TIME
10
FALL TIME
20
RISE TIME
15
10
FALL TIME
20
5
5
0
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0
DRVCC (V)
0
–50
10
0
0
5
10 15 20 25 30 35 40 45 50
CLOAD (nF)
4441 G13
RISE/FALL Time vs CLOAD
Blanking Time vs RBLANK
BLANKING TIME (ns)
100
RISE TIME
80
60
VIN = 7.5V
240 DRVCC = 5V
LTC4441
230
350
300
250
200
150
220
210
200
190
180
170
20
50
160
0
0
FALL TIME
5
10 15 20 25 30 35 40 45 50
CLOAD (nF)
100
0
200
300 400 500
RBLANK (kΩ)
600
VIN Operating Supply Current vs
Temperature
–25
0
50
75
25
TEMPERATURE (°C)
100
125
4441 G18
VIN Standby Supply Current vs
Temperature
500
15
EN = 5V
450 IN = 0V
EN = 0V
14 IN = 0V
13
400
350
VIN = 25V
300
250
VIN = 7.5V
200
150
100
12
VIN = 25V
11
10
9
8
7
VIN = 7.5V
6
5
50
0
–50 –25
150
–50
700
4441 G17
4441 G16
VIN SUPPLY CURRENT (µA)
0
125
Blanking Time vs Temperature
100
40
VIN SUPPLY CURRENT (µA)
RISE/FALL TIME (ns)
160
100
250
TA = 25°C
450 DRVCC = 5V
LTC4441
400
120
50
75
25
TEMPERATURE (°C)
4441 G15
500
TA = 25°C
180 DRVCC = 5V
140
0
4441 G14
BLANKING TIME (ns)
200
–25
4
0
50
75
25
TEMPERATURE (°C)
100
125
4441 G19
3
–50 –25
0
50
75
25
TEMPERATURE (°C)
100
125
4441 G20
44411f
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LTC4441/LTC4441-1
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TYPICAL PERFOR A CE CHARACTERISTICS
IVIN vs fIN
IVIN vs CLOAD
50
60
TA = 25°C
45 CLOAD = 4.7nF
50
40
35
40
DRVCC = 5V
30
IVIN (mA)
IVIN (mA)
TA = 25°C
fIN = 100kHz
25
20
DRVCC = 9V
30
20
15
DRVCC = 9V
10
DRVCC = 5V
10
5
0
0 100 200 300 400 500 600 700 800 900 1000
fIN (kHz)
0
0
5
10 15 20 25 30 35 40 45 50
CLOAD (nF)
4441 G21
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4441 G22
MSOP/SO-8
PGND (Pin 1/Pin 1): Driver Ground. Connect the DRVCC
bypass capacitor directly to this pin, as close as possible
to the IC. In addition, connect the PGND and SGND pins
together close to the IC, and then connect this node to the
source of the power MOSFET (or current sense resistor)
with as short and wide a PCB trace as possible.
EN/SHDN (Pin 6/Pin 4): Enable/Shutdown Input. Pulling
this pin above 1.21V allows the driver to switch. Pulling
this pin below 1.09V forces the driver output to go
low. Pulling this pin below 0.45V forces the LTC4441/
LTC4441-1 into shutdown mode; the DRVCC regulator
turns off and the supply current drops below 12µA.
BLANK (Pin 2/NA): Current Sense Blanking Output. Use
this pin to assert a blanking time in the power MOSFET’s
source current sense signal. The LTC4441 pulls this
open-drain output to SGND if the driver output is low. The
output becomes high impedance after a programmable
blanking time from the driver leading edge output. This
blanking time can be adjusted with the RBLANK pin.*
FB (Pin 7/Pin 5): DRVCC Regulator Feedback Input. Connect this pin to the center tap of an external resistive
divider between DRVCC and SGND to program the DRVCC
regulator output voltage. To ensure loop stability, use the
value of 330kΩ for the top resistor, R1.
RBLANK (Pin 3/NA): Blanking Time Adjust Input. Connect
a resistor from this pin to SGND to set the blanking time.
A small resistor value gives a shorter delay. Leave this pin
floating if the BLANK pin is not used.*
SGND (Pin 4/Pin 2): Signal Ground. Ground return for the
DRVCC regulator and low power circuitry.
IN (Pin 5/Pin 3): Driver Logic Input. This is the noninverting driver input under normal operating conditions.
*Available only on the lo-lead version of the LTC4441.
VIN (Pin 8/Pin 6): Main Supply Input. This pin powers the
DRVCC linear regulator. Bypass this pin to SGND with a 1µF
ceramic, tantalum or other low ESR capacitor in close
proximity to the LTC4441/LTC4441-1.
DRVCC (Pin 9/Pin 7): Linear Regulator Output. This output
pin powers the driver and the control circuitry. Bypass this
pin to PGND using a 10µF ceramic, low ESR (X5R or X7R)
capacitor in close proximity to the LTC4441/LTC4441-1.
OUT (Pin 10/Pin 8): Driver Output.
Exposed Pad (Pin 11/NA): Ground. The Exposed Pad
must be soldered to the PCB ground.
44411f
6
LTC4441/LTC4441-1
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BLOCK DIAGRA
VIN
BIAS
1.21V
–
+
FB
MREG
REG
UVLO
DRVCC
1.09V
IN
Q1
INB
P1
OUT
EN/SHDN
N1
PGND
EN
THERMAL
SHUTDOWN
1.21V
LEADING
EDGE DELAY
RBLANK
BLANK
SHDN
SGND
SHUTDOWN
MB
0.45V
FOR 10-LEAD
LTC4441
ONLY
4441 BD
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APPLICATIO S I FOR ATIO
Overview
Power MOSFETs generally account for the majority of
power lost in a converter. It is important to choose not only
the type of MOSFET used, but also its gate drive circuitry.
The LTC4441/LTC4441-1 is designed to drive an N-channel power MOSFET with little efficiency loss. The LTC4441/
LTC4441-1 can deliver up to 6A of peak current using a
combined NPN Bipolar and MOSFET output stage. This
helps to turn the power MOSFET fully “on” or “off” with a
very brief transition region.
The LTC4441/LTC4441-1 includes a programmable linear
regulator to regulate the gate drive voltage. This regulator
provides the flexibility to use either standard threshold or
logic level MOSFETs.
DRVCC Regulator
An internal, P-channel low dropout linear regulator provides the DRVCC supply to power the driver and the predriver logic circuitry as shown in Figure 1. The regulator
output voltage can be programmed between 5V and 8V
with an external resistive divider between DRVCC and
SGND and a center tap connected to the FB pin. The
regulator needs an R1 value of around 330k to ensure loop
44411f
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LTC4441/LTC4441-1
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APPLICATIO S I FOR ATIO
VIN
LTC4441
1.21V
R1
330k
–
+
FB
REG
MREG
R2
UVLO
ENABLE
DRIVER
1.09V
DRVCC
CVCC
OUT
DRIVER
PGND
4441 F01
Figure 1. DRVCC Regulator
stability; the value of R2 can be varied to achieve the
required DRVCC voltage:
R2 =
signal to drive standard power MOSFETs. The LTC4441/
LTC4441-1 contains an internal voltage regulator that
biases the input buffer, allowing the input thresholds (VIH
= 2.4V, VIL = 1.4V) to be independent of the programmed
driver supply, DRVCC, or the input supply, VIN. The 1V
hysteresis between VIH and VIL eliminates false triggering
due to noise during switching transitions. However, care
should be taken to isolate this pin from any noise pickup,
especially in high frequency, high voltage applications.
The LTC4441/LTC4441-1 input buffer has high input
impedance and draws negligible input current, simplifying
the drive circuitry required for the input. This input can
withstand voltages up to 15V above and below ground.
This makes the chip more tolerant to ringing on the input
digital signal caused by parasitic inductance.
Driver Output Stage
A simplified version of the LTC4441/LTC4441-1’s driver
output stage is shown in Figure 2.
406k
DRVCC – 1.21V
VIN
DRVCC
Q1
The DRVCC regulator can supply up to 100mA and is shortcircuit protected. The output must be bypassed to the
PGND pin in very close proximity to the IC pins with a
minimum of 10µF ceramic, low ESR (X5R or X7R) capacitor. Good bypassing is necessary as high transient supply
currents are required by the driver. If the input supply
voltage, VIN, is close to the required gate drive voltage, this
regulator can be disabled by connecting the DRVCC and FB
pins to VIN.
The LTC4441/LTC4441-1 monitors the FB pin for DRVCC’s
UVLO condition (UVLO in Figure 1). During power-up, the
driver output is held low until the DRVCC voltage reaches
90% of the programmed value. Thereafter, if the DRVCC
voltage drops more than 20% below the programmed
value, the driver output is forced low.
Logic Input Stage
The LTC4441/LTC4441-1 driver employs TTL/CMOS compatible input thresholds that allow a low voltage digital
LOAD
INDUCTOR
LTC4441
P1
OUT
N1
RO
N2
DRVCC
CGD
CGS
POWER
MOSFET
N3
PGND
4441 F02
Figure 2. Driver Output Stage
The pull-up device is the combination of an NPN transistor, Q1, and a P-channel MOSFET, P1. This provides both
the ability to swing to rail (DRVCC) and deliver large peak
charging currents.
The pull-down device is an N-channel MOSFET, N1, with
a typical on resistance of 0.35Ω. The low impedance of N1
provides fast turn-off of the external power MOSFET and
holds the power MOSFET’s gate low when its drain voltage
switches. When the power MOSFET’s gate is pulled low
(gate shorted to source through N1) by the LTC4441/
LTC4441-1, its drain voltage is pulled high by its load (e.g.,
44411f
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LTC4441/LTC4441-1
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APPLICATIO S I FOR ATIO
inductor or resistor). The slew rate of the drain voltage
causes current to flow to the MOSFET’s gate through its
gate-to-drain capacitance. If the MOSFET driver does not
have sufficient sink current capability (low output impedance), the current through the power MOSFET’s CGD can
momentarily pull the gate high and turn the MOSFET
back on.
A similar situation occurs during power-up when VIN is
ramping up with the DRVCC regulator output still low. N1
is off and the driver output, OUT, may momentarily pull
high through the power MOSFET’s CGD, turning on the
power MOSFET. The N-channel MOSFETs N2 and N3,
shown in Figure 2, prevent the driver output from going
high in this situation. If DRVCC is low, N3 is off. If OUT is
pulled high through the power MOSFET’s CGD, the gate of
N2 gets pulled high through RO. This turns N2 on, which
then pulls OUT low. Once DRVCC is >1V, N3 turns on to
hold the N2 gate low, thus disabling N2.
The predriver that drives Q1, P1 and N1 uses an adaptive
method to minimize cross-conduction currents. This is
done with a 5ns nonoverlapping transition time. N1 is fully
turned off before Q1 is turned on and vice-versa using this
5ns buffer time. This minimizes any cross-conduction
currents while Q1 and N1 are switching on and off without
affecting their rise and fall times.
Thermal Shutdown
The LTC4441/LTC4441-1 has a thermal detector that
disables the DRVCC regulator and pulls the driver output
low when activated. If the junction temperature exceeds
150°C, the driver pull-up devices, Q1 and P1, turn off while
the pull-down device, N1, turns on briskly for 200ns to
quickly pull the output low. The thermal shutdown circuit
has 20°C of hysteresis.
driver starts switching according to the input logic signal.
The driver enable comparator has a small hysteresis of
120mV.
Blanking
In some switcher applications, a current sense resistor is
placed between the low side power MOSFET’s source
terminal and ground to sense the current in the MOSFET.
With this configuration, the switching controller must
incorporate some timing interval to blank the ringing on
the current sense signal immediately after the MOSFET is
turned on. This ringing is caused by the parasitic inductance and capacitance of the PCB trace and the MOSFET.
The duration of the ringing is thus dependent on the PCB
layout and the components used and can be longer than
the blanking interval provided by the controller.
The 10-Lead LTC4441 includes an open-drain output that
can be used to extend this blanking interval. The 8-Lead
LTC4441-1 does not have this blanking function. Figure 3
shows the BLANK pin connection. The BLANK pin is
connected directly to the switching controller’s SENSE+
input. Figure 4 shows the blanking waveforms. If the
driver input is low, the external power MOSFET is off and
MB turns on to hold SENSE+ low. If the driver input goes
high, the power MOSFET turns on after the driver’s propagation delay. MB remains on, attenuating the ringing seen
by the controller’s SENSE+ input. After the programmed
blanking time, MB turns off to enable the current sense
VIN
LOAD
INDUCTOR
LTC4441
OUT
DRIVER
POWER
MOSFET
R4
LEADING
EDGE DELAY
TO
SWITCHING
CONTROLLER’S
CURRENT
SENSE
INPUT
R3
Enable/Shutdown Input
The EN/SHDN pin serves two functions. Pulling this pin
below 0.45V forces the LTC4441/LTC4441-1 into shutdown mode. In shutdown mode, the internal circuitry and
the DRVCC regulator are off and the supply current drops
to <12µA. If the input voltage is between 0.45V and 1.21V,
the DRVCC regulator and internal circuit power up but the
driver output stays low. If the input goes above 1.21V, the
SENSE+
SENSE–
BLANK
MB SGND
RBLANK
PGND
4441 F03
KEEP THIS
TRACE SHORT
R7
Figure 3. Blanking Circuit
44411f
9
LTC4441/LTC4441-1
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APPLICATIO S I FOR ATIO
where:
IN
IQ = LTC4441/LTC4441-1 static quiescent current, typically 250µA
OUT
f = Logic input switching frequency
POWER
MOSFET’s
CURRENT
QG = Power MOSFET total gate charge at corresponding
VGS voltage equal to DRVCC
POWER MOSFET’s
SOURCE TERMINAL
VIN = LTC4441/LTC4441-1 input supply voltage
TJ = Junction temperature
MB GATE
TA = Ambient temperature
BLANK/SENSE+
4441 F04
BLANKING TIME
Figure 4. Blanking Waveforms
signal. MB is designed to turn on and turn off at a
controlled slew rate. This is to prevent the gate switching
noise from coupling into the current sense signal.
The blanking interval can be adjusted using resistor R7
connected to the RBLANK pin. A small resistance value
gives a shorter interval with a default minimum of 75ns.
The value of the resistor R4 and the on-resistance of MB
(typically 11Ω) form a resistive divider attenuating the
ringing. R4 needs to be large for effective blanking, but not
so large as to cause delay to the sense signal. A resistance
value of 1k to 10k is recommended.
For optimum performance, the LTC4441/LTC4441-1
should be placed as close as possible to the power
MOSFET and current sense resistor, R3.
Power Dissipation
To ensure proper operation and long-term reliability, the
LTC4441/LTC4441-1 must not operate beyond its maximum temperature rating. The junction temperature can be
calculated by:
IQ(TOT) = IQ + f • QG
PD = VIN • (IQ + f • QG)
TJ = TA + PD • θJA
θJA = Junction-to-ambient thermal resistance. The
10-pin MSOP package has a thermal resistance of
θJA = 38°C/W.
The total supply current, IQ(TOT), consists of the LTC4441/
LTC4441-1’s static quiescent current, IQ, and the current
required to drive the gate of the power MOSFET, with the
latter usually much higher than the former. The dissipated
power, PD, includes the efficiency loss of the DRVCC
regulator. With a programmed DRVCC, a high VIN results
in higher efficiency loss.
As an example, consider an application with VIN = 12V. The
switching frequency is 300kHz and the maximum ambient
temperature is 70°C. The power MOSFET chosen is three
pieces of IRFB31N20D, which has a maximum RDS(ON) of
82mΩ (at room temperature) and a typical total gate
charge of 70nC (the temperature coefficient of the gate
charge is low).
IQ(TOT) = 500µA + 210nC • 300kHz = 63.5mA
PIC = 12V • 63.5mA = 0.762W
TJ = 70°C + 38°C/W • 0.762W = 99°C
This demonstrates how significant the gate charge current can be when compared to the LTC4441/LTC4441-1’s
static quiescent current. To prevent the maximum junction temperature from being exceeded, the input supply
current must be checked when switching at high VIN. A
tradeoff between the operating frequency and the size of
the power MOSFET may be necessary to maintain a
reliable LTC4441/LTC4441-1 junction temperature. Prior
to lowering the operating frequency, however, be sure to
44411f
10
LTC4441/LTC4441-1
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APPLICATIO S I FOR ATIO
check with power MOSFET manufacturers for their
innovations on low QG, low RDS(ON) devices. Power
MOSFET manufacturing technologies are continually improving, with newer and better performing devices being
introduced.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC4441/LTC4441-1:
A. Mount the bypass capacitors as close as possible
between the DRVCC and PGND pins and between the VIN
and SGND pins. The PCB trace loop areas should be
tightened as much as possible to reduce inductance.
B. Use a low inductance, low impedance ground plane to
reduce any ground drop. Remember that the LTC4441/
LTC4441-1 switches 6A peak current and any significant
ground drop will degrade signal integrity.
C. Keep the PCB ground trace between the LTC4441/
LTC4441-1 ground pins (PGND and SGND) and the external current sense resistor as short and wide as possible.
D. Plan the ground routing carefully. Know where the large
load switching current paths are. Maintain separate ground
return paths for the input pin and output pin to avoid
sharing small-signal ground with large load ground return. Terminate these two ground traces only at the GND
pin of the driver (STAR network).
E. Keep the copper trace between the driver output pin and
the load short and wide.
F. Place the small-signal components away from the high
frequency switching nodes. These components include
the resistive networks connected to the FB, RBLANK and
EN/SHDN pins.
U
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.794 ± 0.102
(.110 ± .004)
5.23
(.206)
MIN
0.889 ± 0.127
(.035 ± .005)
1
2.06 ± 0.102
(.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
10
0.254
(.010)
DETAIL “A”
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0° – 6° TYP
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.18
(.007)
SEATING
PLANE
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.127 ± 0.076
(.005 ± .003)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
10 9 8 7 6
0.497 ± 0.076
(.0196 ± .003)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
MSOP (MSE) 0603
1 2 3 4 5
44411f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC4441/LTC4441-1
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
2
.053 – .069
(1.346 – 1.752)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
3
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 0303
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®
44411f
12
Linear Technology Corporation
LT/TP 1104 1K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004