AD AD524AE

a
FEATURES
Low Noise: 0.3 ␮V p-p 0.1 Hz to 10 Hz
Low Nonlinearity: 0.003% (G = 1)
High CMRR: 120 dB (G = 1000)
Low Offset Voltage: 50 ␮V
Low Offset Voltage Drift: 0.5 ␮V/ⴗC
Gain Bandwidth Product: 25 MHz
Pin Programmable Gains of 1, 10, 100, 1000
Input Protection, Power On–Power Off
No External Components Required
Internally Compensated
MIL-STD-883B and Chips Available
16-Lead Ceramic DIP and SOIC Packages and
20-Terminal Leadless Chip Carriers Available
Available in Tape and Reel in Accordance
with EIA-481A Standard
Standard Military Drawing Also Available
Precision
Instrumentation Amplifier
AD524
FUNCTIONAL BLOCK DIAGRAM
–INPUT
PROTECTION
4.44kV
AD524
G = 10
404V
G = 100
40V
Vb
20kV
SENSE
G = 1000
20kV
20kV
20kV
20kV
RG1
VOUT
RG2
20kV
REFERENCE
+INPUT
PROTECTION
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD524 is a precision monolithic instrumentation amplifier
designed for data acquisition applications requiring high accuracy under worst-case operating conditions. An outstanding
combination of high linearity, high common mode rejection, low
offset voltage drift and low noise makes the AD524 suitable for
use in many data acquisition systems.
1. The AD524 has guaranteed low offset voltage, offset voltage
drift and low noise for precision high gain applications.
The AD524 has an output offset voltage drift of less than 25 µV/°C,
input offset voltage drift of less than 0.5 µV/°C, CMR above
90 dB at unity gain (120 dB at G = 1000) and maximum nonlinearity of 0.003% at G = 1. In addition to the outstanding dc
specifications, the AD524 also has a 25 kHz gain bandwidth
product (G = 1000). To make it suitable for high speed data
acquisition systems the AD524 has an output slew rate of 5 V/µs
and settles in 15 µs to 0.01% for gains of 1 to 100.
2. The AD524 is functionally complete with pin programmable
gains of 1, 10, 100 and 1000, and single resistor programmable for any gain.
3. Input and output offset nulling terminals are provided for
very high precision applications and to minimize offset voltage changes in gain ranging applications.
4. The AD524 is input protected for both power-on and poweroff fault conditions.
5. The AD524 offers superior dynamic performance with a gain
bandwidth product of 25 MHz, full power response of 75 kHz
and a settling time of 15 µs to 0.01% of a 20 V step (G = 100).
As a complete amplifier the AD524 does not require any external components for fixed gains of 1, 10, 100 and 1000. For
other gain settings between 1 and 1000 only a single resistor is
required. The AD524 input is fully protected for both power-on
and power-off fault conditions.
The AD524 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperature range.
The economical “A” grade, the low drift “B” grade and lower
drift, higher linearity “C” grade are specified from –25°C to
+85°C. The “S” grade guarantees performance to specification
over the extended temperature range –55°C to +125°C. Devices
are available in 16-lead ceramic DIP and SOIC packages and a
20-terminal leadless chip carrier.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD524–SPECIFICATIONS (@ V = ⴞ15 V, R = 2 k⍀ and T = +25ⴗC unless otherwise noted)
S
Model
GAIN
Gain Equation
(External Resistor Gain
Programming)
Gain Range (Pin Programmable)
Gain Error1
G=1
G = 10
G = 100
G = 1000
Nonlinearity
G=1
G = 10,100
G = 1000
Gain vs. Temperature
G=1
G = 10
G = 100
G = 1000
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
Output Offset Voltage
vs. Temperature
Offset Referred to the
Input vs. Supply
G=1
G = 10
G = 100
G = 1000
Min
AD524A
Typ
 40 , 000

 RG

+ 1 ± 20%

109
10
109
10
NOISE
Voltage Noise, 1 kHz
R.T.I.
R.T.O.
R.T.I., 0.1 Hz to 10 Hz
G=1
G = 10
G = 100, 1000
Current Noise
0.1 Hz to 10 Hz
AD524B
Typ
 40 , 000

 RG
Max

+ 1 ± 20%

±100
±10
AD524C
Typ
 40 , 000

 RG
Max

+ 1 ± 20%

Min
AD524S
Typ
 40 , 000

 RG
Max
Units

+ 1 ± 20%

1 to 1000
ⴞ0.05
ⴞ0.25
ⴞ0.5
±2.0
ⴞ0.03
ⴞ0.15
ⴞ0.35
ⴞ1.0
ⴞ0.02
ⴞ0.1
ⴞ0.25
ⴞ0.5
ⴞ0.05
ⴞ0.25
ⴞ0.5
ⴞ2.0
%
%
%
%
±0.01
±0.01
±0.01
± 0.005
± 0.005
± 0.01
± 0.003
± 0.003
± 0.01
± 0.01
± 0.01
± 0.01
%
%
%
5
15
35
100
5
10
25
50
5
10
25
50
5
10
25
50
ppm/°C
ppm/°C
ppm/°C
ppm/°C
250
2
5
100
100
0.75
3
50
50
0.5
2.0
25
100
2.0
3.0
50
µV
µV/°C
mV
µV/°C
ⴞ50
80
100
110
115
±100
ⴞ35
G

12 V – 
× VD 
 2

70
90
100
110
Min
1 to 1000
75
95
105
110
INPUT
Input Impedance
Differential Resistance
Differential Capacitance
Common-Mode Resistance
Common-Mode Capacitance
Input Voltage Range
Max Differ. Input Linear (V DL) 2
DYNAMIC RESPONSE
Small Signal – 3 dB
G=1
G = 10
G = 100
G = 1000
Slew Rate
Settling Time to 0.01%, 20 V Step
G = 1 to 100
G = 1000
A
1 to 1000
70
85
95
100
±100
OUTPUT RATING
VOUT, RL = 2 kΩ
Min
1 to 1000
INPUT CURRENT
Input Bias Current
vs. Temperature
Input Offset Current
vs. Temperature
Max Common-Mode Linear (V CM)
Common-Mode Rejection dc to
60 Hz with 1 kΩ Source Imbalance
G=1
G = 10
G = 100
G = 1000
Max
L
±100
ⴞ25
± 100
ⴞ15
± 100
10 9
10
10 9
10
±10
G

12 V – 
× VD 
 2

75
95
105
115
75
95
105
110
ⴞ15
± 100
ⴞ10
± 100
10 9
10
10 9
10
± 10
G

12 V – 
× VD 
 2

80
100
110
120
dB
dB
dB
dB
ⴞ50
ⴞ35
10 9
10
10 9
10
± 10
nA
pA/°C
nA
pA/°C
Ω
pF
Ω
pF
V
G

12 V – 
× VD 
 2

70
90
100
110
V
dB
dB
dB
dB
±10
±10
± 10
± 10
V
1
400
150
25
5.0
1
400
150
25
5.0
1
400
150
25
5.0
1
400
150
25
5.0
MHz
kHz
kHz
kHz
V/µs
15
75
15
75
15
75
15
75
µs
µs
7
90
7
90
7
90
7
90
nV/√Hz
nV√Hz
15
2
0.3
15
2
0.3
15
2
0.3
15
2
0.3
µV p-p
µV p-p
µV p-p
60
60
60
60
pA p-p
–2–
REV. E
AD524
Model
SENSE INPUT
RIN
IIN
Voltage Range
Gain to Output
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
TEMPERATURE RANGE
Specified Performance
Storage
POWER SUPPLY
Power Supply Range
Quiescent Current
Min
±10
±10
AD524A
Typ
Max
20
15
Min
±10
Max
20
15
Min
±10
AD524C
Typ
Max
20
15
Min
±10
AD524S
Typ
Max
l
1
l
40
15
40
15
40
15
40
15
±10
–25
–65
±15
3.5
10
1
+85
+150
–25
–65
ⴞ18
5.0
ⴞ6
±15
3.5
+85
+150
–25
–65
ⴞ18
5.0
ⴞ6
kΩ ±20%
µA
V
%
10
l
±15
3.5
1
+85
+150
–55
–65
ⴞ18
5.0
ⴞ6
±15
3.5
Units
kΩ ±20%
µA
V
%
20
15
l
l
ⴞ6
AD524B
Typ
+125
+150
°C
°C
ⴞ18
5.0
V
mA
NOTES
1
Does not include effects of external resistor RG.
2
VOL is the maximum differential input voltage at G = 1 for specified nonlinearity.
VDL at the maximum = 10 V/G.
VD = Actual differential input voltage.
Example: G = 10, VD = 0.50.
VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specification subject to change without notice.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to
calculate outgoing quality levels.
REV. E
–3–
AD524
ABSOLUTE MAXIMUM RATINGS l
CONNECTION DIAGRAMS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 450 mW
Input Voltage2
(Either Input Simultaneously) |VIN| + |VS | . . . . . . . . <36 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
(D, E) . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD524A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
AD524S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature (Soldering 60 secs) . . . . . . . . . . . . +300°C
Ceramic (D) and
SOIC (R) Packages
– INPUT 1
16
RG1
+ INPUT 2
15
OUTPUT NULL
RG2 3
14
OUTPUT NULL
13
G = 10
INPUT NULL 4
AD524
SHORT TO
RG2 FOR
DESIRED
GAIN
TOP VIEW
INPUT NULL 5 (Not to Scale) 12 G = 100
REFERENCE 6
11
–VS 7
10
SENSE
+VS 8
9
OUTPUT
G = 1000
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Max input voltage specification refers to maximum voltage to which either input
terminal may be raised with or without device power applied. For example, with ± 18
volt supplies max V IN is ± 18 volts, with zero supply voltage max V IN is ± 36 volts.
3
RG2
INPUT NULL
NC
INPUT NULL
REFERENCE
9 OUTPUT
8 +VS
0.103
(2.61)
OUTPUT
OFFSET NULL
OUTPUT
NULL
2 1 20 19
5
6
7
OUTPUT NULL
G = 10
SHORT TO
16 NC
RG2 FOR
DESIRED
15 G = 100
GAIN
14 G = 1000
18
4
AD524
TOP VIEW
8
17
7 –VS
RG2 3
5
4
INPUT INPUT
NULL NULL
6
REFERENCE
NC
OUTPUT
SENSE
9 10 11 12 13
1
+INPUT 2
–VS
+VS
–INPUT
14
+INPUT
–INPUT
NC
RG1
SENSE
10
RG1 16
5
Leadless Chip Carrier
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
OUTPUT
15
NULL
15
–VS
INPUT
OFFSET NULL
METALIZATION PHOTOGRAPH
OUTPUT
NULL G = 10 G = 100 G = 1000
11
14
13
12
4
+VS
7
19
5
18
–VS
+VS
INPUT
OFFSET NULL
0.170 (4.33)
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE
D-16 AND R-16 16-PIN CERAMIC PACKAGES.
NC = NO CONNECT
OUTPUT
OFFSET NULL
ORDERING GUIDE
Model
Temperature Ranges
Package Descriptions
Package Options
AD524AD
AD524AE
AD524AR-16
AD524AR-16-REEL
AD524AR-16-REEL7
AD524BD
AD524BE
AD524CD
AD524SD
AD524SD/883B
5962-8853901EA*
AD524SE/883B
AD524SCHIPS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
16-Lead Ceramic DIP
20-Terminal Leadless Chip Carrier
16-Lead Gull-Wing SOIC
Tape & Reel Packaging 13"
Tape & Reel Packaging 7"
16-Lead Ceramic DIP
20-Terminal Leadless Chip Carrier
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
20-Terminal Leadless Chip Carrier
Die
D-16
E-20A
R-16
*
D-16
E-20A
D-16
D-16
D-16
D-16
E-20A
Refer to official DESC drawing for tested specifications.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD524 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. E
AD524–Typical Characteristics
10
+258C
5
0
0
10
15
5
SUPPLY VOLTAGE – 6V
INPUT BIAS CURRENT – 6nA
QUIESCENT CURRENT – mA
4.0
2.0
0
0
5
10
15
SUPPLY VOLTAGE – 6V
5
0
5
10
15
SUPPLY VOLTAGE – 6V
10
40
14
30
12
10
8
6
4
10
0
–10
–20
–30
0
–40
10
15
5
SUPPLY VOLTAGE – 6V
10k
20
2
0
100
1k
LOAD RESISTANCE – V
Figure 3. Output Voltage Swing vs.
Load Resistance
16
20
20
Figure 5. Input Bias Current vs.
Supply Voltage
Figure 4. Quiescent Current vs.
Supply Voltage
20
0
10
20
Figure 2. Output Voltage Swing vs.
Supply Voltage
8.0
6.0
10
0
20
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
15
INPUT BIAS CURRENT – nA
15
30
OUTPUT VOLTAGE SWING – Vp-p
20
OUTPUT VOLTAGE SWING – 6V
INPUT VOLTAGE – 6V
20
–75
125
–25
25
75
TEMPERATURE – 8C
Figure 6. Input Bias Current vs.
Temperature
16
12
10
8
6
4
2
0
0
5
10
15
INPUT VOLTAGE – 6V
20
Figure 7. Input Bias Current vs. Input
Voltage
REV. E
0
1
1000
2
GAIN – V/V
DVOS FROM FINAL VALUE – mV
INPUT BIAS CURRENT – 6nA
14
3
4
100
10
1
5
6
0
1.0
2.0 3.0 4.0 5.0 6.0 7.0
WARM-UP TIME – Minutes
8.0
Figure 8. Offset Voltage, RTI, Turn
On Drift
–5–
0
10
100 1k 10k 100k
FREQUENCY – Hz
1M
10M
Figure 9. Gain vs. Frequency
AD524
FULL POWER RESPONSE – Vp-p
–120
G = 10
–100
G=1
–80
–60
–40
–20
10.0
G = 1, 10, 100
20
10
0
10
100 1k 10k 100k
FREQUENCY – Hz
1M
0
1k
10M
Figure 10. CMRR vs. Frequency RTI,
Zero to 1k Source Imbalance
POWER SUPPLY REJECTION – dB
POWER SUPPLY REJECTION – dB
140
120
G=
100
0
G=
100
G=
10
100
80
60
G=
40
1
20
10
100
1k
10k
FREQUENCY – Hz
100k
Figure 13. Positive PSRR vs.
Frequency
10
GAIN – V/V
1000
100
Figure 12. Slew Rate vs. Gain
1000
140
G=1
100
120
G=
100
0
G=
100
G=
10
100
80
60
G=
40
1
G = 10
10
G = 100, 1000
G = 1000
1
20
10
100
1k
10k
FREQUENCY – Hz
100k
Figure 14. Negative PSRR vs.
Frequency
0.1 – 10Hz
100k
1
–VS = –15V dc +
1V p-p SINEWAVE
0
0
G = 1000
0
1M
160
+VS = 15V dc +
1V p-p SINEWAVE
4.0
G10
10k
100k
FREQUENCY – Hz
Figure 11. Large Signal Frequency
Response
160
CURRENT NOISE SPECTRAL DENSITY – fA/ Hz
G100
6.0
2.0
BANDWIDTH LIMITED
G1000
0
8.0
VOLT NSD – nV/ Hz
CMRR – dB
30
G = 1000
G = 100
SLEW RATE –V/ms
–140
0.1
1
10
100
1k
FREQUENCY – Hz
10k
100k
Figure 15. RTI Noise Spectral
Density vs. Gain
0.1 – 10Hz
10k
1000
100
0
1
10
100
FREQUENCY – Hz
1k
10k
Figure 16. Input Current Noise vs.
Frequency
VERTICAL SCALE; 1 DIVISION = 5mV
Figure 17. Low Frequency Noise␣ –
G = 1 (System Gain = 1000)
–6–
VERTICAL SCALE; 1 DIVISION = 0.1mV
Figure 18. Low Frequency Noise –
G = 1000 (System Gain = 100,000)
REV. E
AD524
–12 TO +12
–12 TO +12
1%
0.1%
0.01%
–8 TO +8
–8 TO +8
–4 TO +4
–4 TO +4
OUTPUT
STEP – V
OUTPUT
STEP – V
+4 TO –4
+4 TO –4
+8 TO –8
1%
0.1%
1%
0.1%
0.01%
1%
0.1%
0.01%
+8 TO –8
0.01%
+12 TO –12
+12 TO –12
5
0
10
15
SETTLING TIME – ms
20
Figure 19. Settling Time Gain = 1
0
Figure 20. Large Signal Pulse
Response and Settling Time – G =1
–12 TO +12
1%
0.1%
5
10
15
SETTLING TIME – ms
Figure 21. Settling Time Gain = 10
0.01%
–8 TO +8
–4 TO +4
OUTPUT
STEP – V
+4 TO –4
+8 TO –8
1%
0
Figure 22. Large Signal Pulse
Response and Settling Time
G = 10
0.01%
0.1%
+12 TO –12
5
10
15
SETTLING TIME – ms
20
Figure 23. Settling Time Gain = 100
–12 TO +12
1%
0.1% 0.01%
1%
0.1% 0.01%
–8 TO +8
–4 TO +4
OUTPUT
STEP – V
+4 TO –4
+8 TO –8
+12 TO –12
0
10
20 30 40 50 60
SETTLING TIME – ms
70
80
Figure 25. Settling Time Gain = 1000
REV. E
Figure 26. Large Signal Pulse Response and Settling Time G = 1000
–7–
20
Figure 24. Large Signal Pulse
Response and Settling Time
G = 100
AD524
10kV
0.01%
INPUT
20V p-p
100kV
0.1%
1kV
10T
As RG is reduced to increase the programmed gain, the transconductance of the input preamp increases to the transconductance of the input transistors. This has three important advantages.
First, this approach allows the circuit to achieve a very high
open loop gain of 3 × 108 at a programmed gain of 1000, thus
reducing gain-related errors to a negligible 30 ppm. Second, the
gain bandwidth product, which is determined by C3 or C4 and
the input transconductance, reaches 25 MHz. Third, the input
voltage noise reduces to a value determined by the collector
current of the input transistors for an RTI noise of 7 nV/√Hz at
G = 1000.
10kV
0.1%
VOUT
+VS
RG1
G = 10
G = 100
11kV
0.1%
1kV
0.1%
100V
0.1%
G = 1000
AD524
RG2
–VS
Figure 27. Settling Time Test Circuit
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instrumentation amplifiers are often subjected to input overloads, i.e.,
voltage levels in excess of the full scale for the selected gain
range. At low gains, 10 or less, the gain resistor acts as a current
limiting element in series with the inputs. At high gains the
lower value of RG will not adequately protect the inputs from
excessive currents. Standard practice would be to place series
limiting resistors in each input, but to limit input current to
below 5 mA with a full differential overload (36 V) would require over 7k of resistance which would add 10 nV√Hz of noise.
To provide both input protection and low noise a special series
protect FET was used.
+VS
I1
50mA
I2
50mA
VB
A1
C3
–IN
CH2,
CH3, CH4
CH1
R57
20kV
Q1, Q3
RG1
I3
50mA
R52
20kV
A2
C4
SENSE
R53
20kV
A3
R56
20kV
4.44kV
Q2, Q4
G100
40V
VO
R55
20kV
REFERENCE
RG2
404V
R54
20kV
G1000
CH2, CH3,
CH4
I4
50mA
A unique FET design was used to provide a bidirectional current limit, thereby, protecting against both positive and negative
overloads. Under nonoverload conditions, three channels CH2,
CH3, CH4, act as a resistance (≈1 kΩ) in series with the input as
before. During an overload in the positive direction, a fourth
channel, CH1, acts as a small resistance (≈3 kΩ) in series with
the gate, which draws only the leakage current, and the FET
limits IDSS . When the FET enhances under a negative overload,
the gate current must go through the small FET formed by CH1
and when this FET goes into saturation, the gate current is
limited and the main FET will go into controlled enhancement.
The bidirectional limiting holds the maximum input current to
3 mA over the 36 V range.
+IN
CH1
–VS
Figure 28 Simplified Circuit of Amplifier; Gain Is Defined as
((R56 + R57)/(RG)) + 1. For a Gain of 1, RG Is an Open Circuit
Theory of Operation
The AD524 is a monolithic instrumentation amplifier based on
the classic 3 op amp circuit. The advantage of monolithic construction is the closely matched components that enhance the
performance of the input preamp. The preamp section develops
the programmed gain by the use of feedback concepts. The
programmed gain is developed by varying the value of RG (smaller
values increase the gain) while the feedback forces the collector
currents Q1, Q2, Q3 and Q4 to be constant, which impresses
the input voltage across RG.
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many smallsignal high-gain applications that don’t have this capability.
+VS
+Vs
10
100
AD524
1000
RG2
DUT
16.2kV
1mF
1/2
1mF
–VS
AD712
G1000
9.09kV
1/2
1mF
G1, 10, 100
1kV
100V
16.2kV
–VS
1.62MV
1.82kV
Figure 29. Noise Test Circuit
–8–
REV. E
AD524
Voltage offset and drift comprise two components each; input
and output offset and offset drift. Input offset is that component
of offset that is directly proportional to gain i.e., input offset as
measured at the output at G = 100 is 100 times greater than at
G = 1. Output offset is independent of gain. At low gains, output offset drift is dominant, while at high gains input offset drift
dominates. Therefore, the output offset voltage drift is normally
specified as drift at G = 1 (where input effects are insignificant),
while input offset voltage drift is given by drift specification at a
high gain (where output offset effects are negligible). All inputrelated numbers are referred to the input (RTI) which is to say
that the effect on the output is “G” times larger. Voltage offset
vs. power supply is also specified at one or more gain settings
and is also RTI.
For best results RG should be a precision resistor with a low
temperature coefficient. An external RG affects both gain accuracy
and gain drift due to the mismatch between it and the internal
thin-film resistors. Gain accuracy is determined by the tolerance
of the external RG and the absolute accuracy of the internal resistors (±20%). Gain drift is determined by the mismatch of the
temperature coefficient of RG and the temperature coefficient of
the internal resistors (– 50 ppm/°C typ).
+VS
–INPUT
RG1
1.5kV
2.105kV
AD524
VOUT
1kV
By separating these errors, one can evaluate the total error independent of the gain setting used. In a given gain configuration
both errors can be combined to give a total error referred to the
input (R.T.I.) or output (R.T.O.) by the following formula:
RG2
G=
–VS
The second technique uses the internal resistors in parallel with
an external resistor (Figure 32). This technique minimizes the
gain adjustment range and reduces the effects of temperature
coefficient sensitivity.
Total Error R.T.O. = (Gain × input error) + output error
As an illustration, a typical AD524 might have a +250 µV output offset and a –50 µV input offset. In a unity gain configuration, the total output offset would be 200 µV or the sum of the
two. At a gain of 100, the output offset would be –4.75 mV or:
+250 µV + 100(–50 µV) = –4.75 mV.
+VS
–INPUT
RG1
The AD524 provides for both input and output offset adjustment. This simplifies very high precision applications and minimize offset voltage changes in switched gain applications. In
such applications the input offset is adjusted first at the highest
programmed gain, then the output offset is adjusted at G = 1.
G = 10
4kV
Figure 32. Operating Connections for G = 20, Low Gain
T.C. Technique
The AD524 may also be configured to provide gain in the output stage. Figure 33 shows an H pad attenuator connected to
the reference and sense lines of the AD524. R1, R2 and R3
should be made as low as possible to minimize the gain variation
and reduction of CMRR. Varying R2 will precisely set the gain
without affecting CMRR. CMRR is determined by the match of
R1 and R3.
10kV
G = 10
VOUT
G = 1000
RG2
OUTPUT
SIGNAL
COMMON
+VS
R1
2.26kV
–INPUT
–VS
RG1
R2
5kV
G = 10
Figure 30. Operating Connections for G = 100
AD524
G = 100
The AD524 can be configured for gains other than those that
are internally preset; there are two methods to do this. The first
method uses just an external resistor connected between pins 3
and 16, which programs the gain according to the formula
G = 1000
RG2
G=
R3
2.26kV
(R2||40kV) + R1 + R3
(R2||40kV)
–VS
(R1 + R2 + R3)||RL $ 2kV
Figure 33. Gain of 2000
(see Figure 31).
–9–
VOUT
RL
+INPUT
40k
RG =
G = –1
REV. E
–VS
40,000
+1 = 20 617%
G=
4000||4444.44
*NOMINAL (620%)
RG1
+INPUT
REFERENCE
*R|G = 10 = 4444.44V
*R|G = 100 = 404.04V
*R|G = 1000 = 40.04V
INPUT
OFFSET
NULL
AD524
VOUT
RG2
The AD524 has internal high accuracy pretrimmed resistors for
pin programmable gain of 1, 10, 100 and 1000. One of the
preset gains can be selected by pin strapping the appropriate
gain terminal and RG2 together (for G = 1 RG2 is not connected).
G = 100
AD524
+INPUT
GAIN
–INPUT
40,000 +1 = 20 620%
2.105
Figure 31. Operating Connections for G = 20
Total Error R.T.I. = input error + (output error/gain)
+VS
REFERENCE
+INPUT
AD524
Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents will charge stray capacitances, causing
the output to drift uncontrollably or to saturate. Therefore,
when amplifying “floating” input sources such as transformers
and thermocouples, as well as ac-coupled sources, there must
still be a dc path from each input to ground.
Table I. Output Gain Resistor Values
Output
Gain
R2
R1, R3
Nominal
Gain
2
5
10
5 kΩ
1.05 kΩ
1 kΩ
2.26 kΩ
2.05 kΩ
4.42 kΩ
2.02
5.01
10.1
COMMON-MODE REJECTION
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of a dc amplifier. Bias currents are an additional
source of input error and must be considered in a total error
budget. The bias currents, when multiplied by the source resistance, appear as an offset voltage. What is of concern in calculating bias current errors is the change in bias current with respect to
signal voltage and temperature. Input offset current is the difference between the two input bias currents. The effect of offset
current is an input offset voltage whose magnitude is the offset
current times the source impedance imbalance.
+VS
AD524
LOAD
–VS
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. “Common-Mode
Rejection Ratio” (CMRR) is a ratio expression while “CommonMode Rejection” (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due to
varied stray capacitances or cable capacitances. In many applications shielded cables are used to minimize noise. This technique can create common mode rejection errors unless the
shield is properly driven. Figures 35 and 36 shows active data
guards that are configured to improve ac common mode rejection by “bootstrapping” the capacitances of the input cabling,
thus minimizing differential phase shift.
TO POWER
SUPPLY
GROUND
+VS
–INPUT
a. Transformer Coupled
G = 100
100V
RG2
+VS
AD524
VOUT
AD711
+INPUT
REFERENCE
–VS
AD524
Figure 35. Shield Driver, G ≥ 100
LOAD
–VS
TO POWER
SUPPLY
GROUND
–INPUT
AD712
100V
b. Thermocouple
+VS
RG1
AD524
+VS
VOUT
–VS
100V
REFERENCE
RG2
+INPUT
–VS
AD524
Figure 36. Differential Shield Driver
LOAD
GROUNDING
–VS
TO POWER
SUPPLY
GROUND
c. AC Coupled
Figure 34. Indirect Ground Returns for Bias Currents
Many data acquisition components have two or more ground
pins that are not connected together within the device. These
grounds must be tied together at one point, usually at the system power-supply ground. Ideally, a single solid ground would
be desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths
have resistance and inductance, hundreds of millivolts can be
generated between the system ground point and the data
–10–
REV. E
AD524
acquisition components. Separate ground returns should be
provided to minimize the current flow in the path from the sensitive points to the system ground point. In this way supply currents
and logic-gate return currents are not summed into the same
return path as analog signals where they would cause measurement errors.
REFERENCE TERMINAL
The reference terminal may be used to offset the output by up
to ± 10 V. This is useful when the load is “floating” or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. It must be remembered that the total output swing is ±10 volts to be shared between signal and reference offset.
Since the output voltage is developed with respect to the potential on the reference terminal, an instrumentation amplifier can
solve many grounding problems.
Any significant resistance from the reference terminal to ground
increases the gain of the noninverting signal path, thereby upsetting the common-mode rejection of the IA.
DIGITAL P.S.
+5V
C
ANALOG P.S.
+15V C –15V
0.1 0.1
mF mF
When the IA is of the three-amplifier configuration it is necessary that nearly zero impedance be presented to the reference
terminal.
0.1 0.1
mF mF
1mF 1mF
In the AD524 a reference source resistance will unbalance the
CMR trim by the ratio of 20 kΩ/RREF. For example, if the reference source impedance is 1 Ω, CMR will be reduced to 86 dB
(20 kΩ/1 Ω = 86 dB). An operational amplifier may be used to
provide that low impedance reference point as shown in Figure
39. The input offset voltage characteristics of that amplifier will
add directly to the output offset voltage performance of the
instrumentation amplifier.
1mF
DIG
COM
AD583
AD524
AD574A
SAMPLE
AND HOLD
6
*ANALOG
OUTPUT
REFERENCE
DIGITAL
DATA
OUTPUT
SIGNAL
GROUND
GROUND
+VS
SENSE
*IF INDEPENDENT; OTHERWISE RETURN AMPLIFIER REFERENCE
TO MECCA AT ANALOG P.S. COMMON
VIN +
Figure 37. Basic Grounding Practice
AD524
SENSE TERMINAL
The sense terminal is the feedback point for the instrument
amplifier’s output amplifier. Normally it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load, thus putting
the IxR drops “inside the loop” and virtually eliminating this
error source.
V+
–VS
VOFFSET
AD711
Figure 39. Use of Reference Terminal to Provide Output
Offset
An instrumentation amplifier can be turned into a voltage-tocurrent converter by taking advantage of the sense and reference
terminals as shown in Figure 40.
(SENSE)
OUTPUT
CURRENT
BOOSTER
VIN +
AD524
SENSE
+INPUT
R1
X1
(REF)
VIN –
LOAD
REF
VIN –
AD524
VX
RL
–INPUT
IL
REF
A2
V–
AD711
Figure 38. AD524 Instrumentation Amplifier with Output
Current Booster
Typically, IC instrumentation amplifiers are rated for a full ± 10
volt output swing into 2 kΩ. In some applications, however, the
need exists to drive more current into heavier loads. Figure 38
shows how a high-current booster may be connected “inside the
loop” of an instrumentation amplifier to provide the required
current boost without significantly degrading overall performance. Nonlinearities, offset and gain inaccuracies of the buffer
are minimized by the loop gain of the IA output amplifier. Offset drift of the buffer is similarly reduced.
REV. E
IL =
VX
VIN
40,000
=
= 1+
R1
R1
RG
(
)
LOAD
Figure 40. Voltage-to-Current Converter
By establishing a reference at the “low” side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain and the value of that resistor. Since only a small
current is demanded at the input of the buffer amplifier A2, the
forced current IL will largely flow through the load. Offset and
drift specifications of A2 must be added to the output offset and
drift specifications of the IA.
–11–
AD524
–IN
1
PROTECTION
16
+IN
2
PROTECTION
15
+VS
3
INPUT
OFFSET
TRIM
14
R1
10kV
4
G = 1000
K3
NC
13
20kV
20kV
12
20kV
–VS
7
+VS
8
RELAY
SHIELDS
404V
20kV
20kV
40V
6
C1
R2
10kV
G = 100
K2
G = 10
K1
4.44kV
5
1mF
35V
OUTPUT
OFFSET
TRIM
11
+5V
20kV
10
A1
AD524
D1
K1
OUT
K3
D2
K2
D3
9
C2
K1 – K3 =
THERMOSEN DM2C
4.5V COIL
D1 – D3 = IN4148
ANALOG
COMMON
GAIN TABLE
A B GAIN
0 0 10
0 1 1000
1 0 100
1 1 1
INPUTS A
GAIN
RANGE B
Y0
Y1
74LS138
DECODER
7407N
BUFFER
DRIVER
Y2
10mF
+5V
LOGIC
COMMON
NC = NO CONNECT
Figure 41. Three Decade Gain Programmable Amplifier
PROGRAMMABLE GAIN
Figure 41 shows the AD524 being used as a software programmable gain amplifier. Gain switching can be accomplished with
mechanical switches such as DIP switches or reed relays. It
should be noted that the “on” resistance of the switch in series
with the internal gain resistor becomes part of the gain equation
and will have an effect on gain accuracy.
(+INPUT)
–IN
1
(–INPUT)
+IN
2
PROTECTION
16
PROTECTION
15
+VS
3
INPUT
OFFSET
NULL
The AD524 can also be connected for gain in the output stage.
Figure 42 shows an AD711 used as an active attenuator in the
output amplifier’s feedback loop. The active attenuation presents a very low impedance to the feedback resistors, therefore
minimizing the common-mode rejection ratio degradation.
14
OUTPUT
OFFSET
NULL
TO –V
R2
10kV
4.44kV
4
13
10kV
20kV
20kV
5
20kV
20kV
20kV
404V
12
40V
6
11
20kV
–VS
7
+VS
8
10
AD524
VOUT
9
1mF
35V
20kV
10pF
VSS
VDD GND
+VS
39.2kV
AD711
–VS
1kV
28.7kV
1kV
316kV
1kV
AD7590
VDD A2 A3 A4 WR
Figure 42. Programmable Output Gain
–12–
REV. E
AD524
+VS
+INPUT
(–INPUT) 1
+INPUT
PROTECTION
4.44kV
G = 10 13
RG1
AD524
G = 10
404V
G = 100 12
Vb
40V
G = 1000 11
10
RG1 16
20kV
20kV
20kV
20kV
9
RG2 3
G = 1000
RG2
VOUT
–INPUT
39kV
AD589
PROTECTION
17
4
CS
15
16
DAC A/DAC B
1/2
AD712
3
DAC A
C1
DATA
INPUTS LSB
2
14 DB0
7 DB7
WR
R3
20kV
+VS
MSB
+VS
DATA
INPUTS
–VS
VREF
–VS
6
20kV
–INPUT 2
(+INPUT)
AD524
G = 100
20kV
+VS
1/2
AD712
R4
10kV
OUT1
AD7524
OUT2
CS
1/2
AD712
WR
256:1
R6
5kV
–VS
1
AD7528
GND
19
6
18
DAC B
5
Figure 44. Software Controllable Offset
20
1/2
AD712
In many applications complex software algorithms for autozero
applications are not available. For those applications Figure 45
provides a hardware solution.
Figure 43. Programmable Output Gain Using a DAC
Another method for developing the switching scheme is to use a
DAC. The AD7528 dual DAC, which acts essentially as a pair
of switched resistive attenuators having high analog linearity and
symmetrical bipolar transmission, is ideal in this application.
The multiplying DAC’s advantage is that it can handle inputs of
either polarity or zero without affecting the programmed gain.
The circuit shown uses an AD7528 to set the gain (DAC A) and
to perform a fine adjustment (DAC B).
+VS
15
16
8
RG1
10
14
VOUT
AD524
13
9
0.1mF LOW
LEAKAGE
RG2
1kV
–VS
12
11
AUTOZERO CIRCUITS
In many applications it is necessary to provide very accurate
data in high gain configurations. At room temperature the offset
effects can be nulled by the use of offset trimpots. Over the
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 44 show a CMOS DAC operating in the bipolar mode and connected to the reference terminal
to provide software controllable offset adjustments.
VDD
VSS
AD7510KD
GND
200ms
A1
A2
A3
A4
ZERO PULSE
Figure 45. Autozero Circuit
–13–
10
CH
AD711
REV. E
R5
20kV
AD524
ERROR BUDGET ANALYSIS
To illustrate how instrumentation amplifier specifications are
applied, we will now examine a typical case where an AD524 is
required to amplify the output of an unbalanced transducer.
Figure 46 shows a differential transducer, unbalanced by 100 Ω,
supplying a 0 to 20 mV signal to an AD524C. The output of the
IA feeds a 14-bit A-to-D converter with a 0 to 2 volt input voltage range. The operating temperature range is –25°C to +85°C.
Therefore, the largest change in temperature ∆T within the
operating range is from ambient to +85°C (85°C – 25°C = 60°C).
In many applications, differential linearity and resolution are of
prime importance. This would be so in cases where the absolute
value of a variable is less important than changes in value. In
these applications, only the irreducible errors (45 ppm = 0.004%)
are significant. Furthermore, if a system has an intelligent processor monitoring the A-to-D output, the addition of a autogain/autozero cycle will remove all reducible errors and may
eliminate the requirement for initial calibration. This will also
reduce errors to 0.004%.
+VS
+10V
10kV
350V
350V
RG1
G = 100
350V
14-BIT
ADC
0V TO 2V
F.S.
AD524C
350V
RG2
–VS
Figure 46. Typical Bridge Application
Table II. Error Budget Analysis of AD524CD in Bridge Application
Error Source
Effect on
Absolute
Accuracy
at TA = +85ⴗC
Effect
on
Resolution
± 0.25% = 2500 ppm
(25 ppm/°C)(60°C) = 1500 ppm
± 0.003% = 30 ppm
± 50 µV/20 mV = ± 2500 ppm
(± 0.5 µV/°C)(60°C) = 30 µV
30 µV/20 mV = 1500 ppm
± 2.0 mV/20 mV = 1000 ppm
(± 25 µV/°C)(60°C)= 1500 µV
1500 µV/20 mV = 750 ppm
(± 15 nA)(100 Ω) = 1.5 µV
1.5 µV/20 mV = 75 ppm
(± 100 pA/°C)(100 Ω)(60°C) = 0.6 µV
0.6 µV/20 mV= 30 ppm
(± 10 nA)(100 Ω) = 1 µV
1 µV/20 mV = 50 ppm
(100 pA/°C)(100 Ω)(60°C) = 0.6 µV
0.6 µV/20 mV = 30 ppm
(10 nA)(175 Ω) = 3.5 µV
3.5 µV/20 mV = 87.5 ppm
(100 pA/°C)(175 Ω)(60°C) = 1 µV
1 µV/20 mV = 50 ppm
115 dB = 1.8 ppm × 5 V = 8.8 µV
8.8 µV/20 mV = 444 ppm
2500 ppm
–
–
2500 ppm
2500 ppm
1500 ppm
–
2500 ppm
–
–
30 ppm
–
–
1000 ppm
1500 ppm
1000 ppm
–
–
–
750 ppm
–
75 ppm
75 ppm
–
–
30 ppm
–
50 ppm
50 ppm
–
–
30 ppm
–
87.5 ppm
87.5 ppm
–
–
50 ppm
–
444 ppm
444 ppm
–
0.3 µV p-p/20 mV = 15 ppm
–
–
15 ppm
6656.5 ppm
10516.5 ppm
45 ppm
AD524C
Specifications Calculation
± 0.25%
25 ppm
± 0.003%
± 50 µV, RTI
± 0.5 µV/°C
–
Output Offset Voltage*
± 2.0 mV
Output Offset Voltage Drift* ± 25 µV/°C
Gain Error
Gain Instability
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage Drift
Bias Current-Source
Imbalance Error
Bias Current-Source
Imbalance Drift
Offset Current-Source
Imbalance Error
Offset Current-Source
Imbalance Drift
Offset Current-Source
Resistance-Error
Offset Current-Source
Resistance-Drift
Common Mode Rejection
5 V dc
Noise, RTI
(0.1 Hz–10 Hz)
Effect on
Absolute
Accuracy
at TA = +25ⴗC
± 15 nA
± 100 pA/°C
± 10 nA
± 100 pA/°C
± 10 nA
± 100 pA/°C
115 dB
0.3 µV p-p
Total Error
*Output offset voltage and output offset voltage drift are given as RTI figures.
–14–
REV. E
AD524
Figure 47 shows a simple application, in which the variation of
the cold-junction voltage of a Type J thermocouple-iron(+)–
constantan–is compensated for by a voltage developed in series
by the temperature-sensitive output current of an AD590 semiconductor temperature sensor.
RA
NOMINAL
TYPE VALUE
J
K
E
T
S, R
52.3V
41.2V
61.4V
40.2V
5.76V
REFERENCE
JUNCTION
+158C < TA < +358C
+VS
7.5V
IA
TA
VA
and the circuit near 25°C. If resistors with low tempcos are
used, compensation accuracy will be to within ± 0.5°C, for
temperatures between +15°C and +35°C. Other thermocouple
types may be accommodated with the standard resistance values
shown in the table. For other ranges of ambient temperature,
the equation in the figure may be solved for the optimum values
of RT and R A.
2.5V
AD580
G = 100
+VS
AD590
AD524
RA
IRON
VT CONSTANTAN
MEASURING
JUNCTION
EO = VT – VA +
≅ VT
CU
52.3VIA + 2.5V
52.3V
1+
R
52.3V
EO
8.66kV
– 2.5V
RT
1kV
–VS
OUTPUT
AMPLIFIER
OR METER
NOMINAL VALUE
9135V
The microprocessor controlled data acquisition system shown in
Figure 48 includes both autozero and autogain capability. By
dedicating two of the differential inputs, one to ground and one
to the A/D reference, the proper program calibration cycles can
eliminate both initial accuracy errors and accuracy errors over
temperature. The autozero cycle, in this application, converts a
number that appears to be ground and then writes that same
number (8-bit) to the AD7524, which eliminates the zero error
since its output has an inverted scale. The autogain cycle converts the A/D reference and compares it with full scale. A multiplicative correction factor is then computed and applied to
subsequent readings.
For a comprehensive study of instrumentation amplifier design
and applications, refer to the Instrumentation Amplifier Application Guide, available free from Analog Devices.
Figure 47. Cold-Junction Compensation
The circuit is calibrated by adjusting RT for proper output voltage
with the measuring junction at a known reference temperature
AD7507
VREF
AD583
RG2
AD524
VIN
AD574A
AGND
RG1
–VREF
A0 A2
EN A1
20kV
20kV
10kV
AD7524
1/2
AD712
1/2
5kV AD712
DECODE
LATCH
CONTROL
MICROPROCESSOR
ADDRESS
ADDRESS
BUS BUS
Figure 48. Microprocessor Controlled Data Acquisition System
REV. E
–15–
AD524
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Ceramic DIP
(D-16)
16
C722e–0–4/99
0.080 (2.03) MAX
0.005 (0.13) MIN
9
0.310 (7.87)
0.220 (5.59)
1
8
PIN 1
0.840 (21.34) MAX
0.200 (5.08)
MAX
0.150
(3.81)
MAX
SEATING
0.070 (1.78)
PLANE
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.100
(2.54)
BSC
0.015 (0.38)
0.008 (0.20)
20-Terminal Leadless Chip Carrier
(E-20A)
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.358 (9.09)
0.342 (8.69)
SQ
0.095 (2.41)
0.075 (1.90)
0.358
(9.09)
MAX
SQ
TOP
VIEW
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.200 (5.08)
BSC
0.100 (2.54) BSC
3
4
19
18 20
1
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
0.050 (1.27)
BSC
8
14
13
0.015 (0.38)
MIN
9
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
16-Lead SOIC
(R-16)
1
8
PIN 1
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0192 (0.49)
0°
SEATING 0.0125 (0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
–16–
PRINTED IN U.S.A.
9
0.4193 (10.65)
0.3937 (10.00)
16
0.2992 (7.60)
0.2914 (7.40)
0.4133 (10.50)
0.3977 (10.00)
0.0500 (1.27)
0.0157 (0.40)
REV. E