Hot Swappable Dual I2C Isolators ADuM1250/ADuM1251 VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7 SDA2 SCL1 3 DECODE ENCODE 6 SCL2 GND1 4 ENCODE DECODE 5 GND2 06401-001 FUNCTIONAL BLOCK DIAGRAMS Bidirectional I2C communication Open-drain interfaces Suitable for hot swap applications 30 mA current sink capability 1000 kHz operation 3.0 V to 5.5 V supply/logic levels 8-lead SOIC lead-free package High temperature operation: 105°C Safety and regulatory approvals UL recognition 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A (pending) VDE Certificate of Conformity (pending) DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000 VIORM = 560 V peak Figure 1. ADuM1250 Functional Block Diagram VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7 SDA2 SCL1 3 ENCODE DECODE 6 SCL2 5 GND2 GND1 4 06401-002 FEATURES Figure 2. ADuM1251 Functional Block Diagram APPLICATIONS Isolated I2C, SMBus, or PMBus interfaces Multilevel I2C interfaces Power supplies Networking Power-over-Ethernet GENERAL DESCRIPTION 1 The ADuM1250/ADuM1251 are hot swappable digital isolators with non latching bidirectional communication channels compatible with I2C interfaces. This eliminates the need for splitting I2C signals into separate transmit and receive signals for use with standalone optocouplers. The ADuM1250 provides two bidirectional channels supporting a complete isolated I2C interface. The ADuM1251 provides one bidirectional channel and one unidirectional channel for those applications where a bidirectional clock is not required. 1 Both the ADuM1250 and ADuM1251 contain hot swap circuitry to prevent glitching data when an unpowered card is inserted onto an active bus. These isolators are based on iCoupler® chip scale transformer technology from Analog Devices, Inc. iCoupler is a magnetic isolation technology with functional, performance, size, and power consumption advantages as compared to optocouplers. With the ADuM1250/ADuM1251, iCoupler channels can be integrated with semiconductor circuitry, which enables a complete isolated I2C interface to be provided in a small form factor. Protected by U.S. Patents 5,952,849 and 6,873,065. Other patents pending. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADuM1250/ADuM1251 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications....................................................................................... 1 ESD Caution...................................................................................7 Functional Block Diagrams............................................................. 1 Pin Configuration and Function Descriptions..............................8 General Description ......................................................................... 1 Test Conditions..................................................................................9 Revision History ............................................................................... 2 Application Notes ........................................................................... 10 Specifications..................................................................................... 3 Functional Description.............................................................. 10 Electrical Characteristics............................................................. 3 Startup.......................................................................................... 10 Package Characteristics ............................................................... 5 Typical Application Diagram.................................................... 11 Regulatory Information............................................................... 5 Magnetic Field Immunity............................................................. 11 Insulation and Safety-Related Specifications............................ 5 Outline Dimensions ....................................................................... 12 DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics .............................................................................. 6 Ordering Guide .......................................................................... 12 Recommended Operating Conditions ...................................... 6 REVISION HISTORY 10/06—Revision 0: Initial Version 0 Rev. 0 | Page 2 of 12 ADuM1250/ADuM1251 SPECIFICATIONS ELECTRICAL CHARACTERISTICS DC Specifications All voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 5 V, unless otherwise noted. Table 1. Parameter ADuM1250 Input Supply Current, Side 1, 5 V Input Supply Current, Side 2, 5 V Input Supply Current, Side 1, 3.3 V Input Supply Current, Side 2, 3.3 V ADuM1251 Input Supply Current, Side 1, 5 V Input Supply Current, Side 2, 5 V Input Supply Current, Side 1, 3.3 V Input Supply Current, Side 2, 3.3V LEAKAGE CURRENTS SIDE 1 LOGIC LEVELS Logic Input Threshold 1 Logic Low Output Voltages Input/Output Logic Low Level Difference2 SIDE 2 LOGIC LEVELS Logic Low Input Voltage Logic High Input Voltage Logic Low Output Voltage Symbol Typ Max Unit Test Conditions IDD1 IDD2 IDD1 IDD2 2.8 2.7 1.9 1.7 5.0 5.0 3.0 3.0 mA mA mA mA VDD1 = 5 V VDD2 = 5 V VDD1 = 3.3 V VDD2 = 3.3 V IDD1 IDD2 IDD1 IDD2 ISDA1, ISDA2, ISCL1, ISCL2 2.8 2.5 1.8 1.6 0.01 6.0 4.7 3.0 2.8 10 mA mA mA mA μA VDD1 = 5 V VDD2 = 5 V VDD1 = 3.3 V VDD2 = 3.3 V VSDA1 = VDD1, VSDA2 = VDD2, VSCL1 = VDD1, VSCL2 = VDD2 700 900 850 mV mV mV mV 0.3 VDD2 V V mV VSDA1T, VSCL1T VSDA1OL, VSCL1OL ΔVSDA1, ΔVSCL1 VSDA2IL, VSCL2IL VSDA2IH, VSCL2IH VSDA2OL, VSCL2OL Min 500 600 600 50 0.7 VDD2 400 1 ISDA1 = ISCL1 = 3.0 mA ISDA1 = ISCL1 = 0.5 mA ISDA2 = ISCL2 = 30 mA VIL < 0.5 V, VIH > 0.7 V. 2 ΔVS1 = VS1OL – VS1T. This is the minimum difference between the output logic low level and the input logic threshold within a given component. This ensures that there is no possibility of the part latching up the bus to which it is connected. Rev. 0 | Page 3 of 12 ADuM1250/ADuM1251 AC Specifications All voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 5 V, unless otherwise noted. Refer to Figure 5. Table 2. Parameter MAXIMUM FREQUENCY OUTPUT FALL TIME 5 V Operation Symbol Min 1000 Typ Max Unit kHz Test Conditions 4.5 V ≤ VDD1,VDD2 ≤ 5.5 V, CL1 = 40 pF, R1 = 1.6 kΩ, CL2 = 400 pF, R2 = 180 Ω Side 1 Output (0.9 VDD1 to 0.9 V) Side 2 Output (0.9 VDD2 to 0.1 VDD2) 3 V Operation tf1 tf2 Side 1 Output (0.9 VDD1 to 0.9 V) Side 2 Output (0.9 VDD2 to 0.1 VDD2) PROPAGATION DELAY 5 V Operation tf1 tf2 13 32 26 52 120 120 ns ns 3.0 V ≤ VDD1,VDD2 ≤ 3.6 V, CL1 = 40 pF, R1 = 1.0 kΩ, CL2 = 400 pF, R2 = 120 Ω 13 32 32 61 120 120 ns ns 4.5 ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0, R1 = 1.6 kΩ, R2 = 180 Ω Side 1-to-Side 2, Rising Edge 1 Side 1-to-Side 2, Falling Edge 2 Side 2-to-Side 1, Rising Edge 3 Side 2-to-Side 1, Falling Edge 4 3 V Operation tPLH12 tPHL12 tPLH21 tPHL21 Side 1-to-Side 2, Rising Edge1 Side 1-to-Side 2, Falling Edge2 Side 2-to-Side 1, Rising Edge3 Side 2-to-Side 1, Falling Edge4 PULSE WIDTH DISTORTION 5 V Operation tPLH12 tPHL12 tPLH21 tPHL21 95 162 31 85 130 275 70 155 ns ns ns ns 3.0 V ≤ VDD1,VDD2 ≤ 3.6 V, CL1 = CL2 = 0, R1 = 1.0 kΩ, R2 = 120 Ω 82 196 32 110 125 340 75 210 ns ns ns ns 4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0, R1 = 1.6 kΩ, R2 = 180 Ω Side 1-to-Side 2, |tPLH12 − tPHL12| Side 2-to-Side 1, |tPLH21 − tPHL21| 3 V Operation PWD12 PWD21 Side 1-to-Side 2, |tPLH12 − tPHL12| Side 2-to-Side 1, |tPLH21 − tPHL21| COMMON-MODE TRANSIENT IMMUNITY5 PWD12 PWD21 |CMH|, |CML| 67 54 145 85 ns ns 3.0 V ≤ VDD1,VDD2 ≤ 3.6 V, CL1 = CL2 = 0, R1 = 1.0 kΩ, R2 = 120 Ω 25 114 77 35 215 135 1 ns ns kV/μs tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDD2. tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V. tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDD1. 4 tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V. 5 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 2 3 Rev. 0 | Page 4 of 12 ADuM1250/ADuM1251 PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input-Output) 1 Capacitance (Input-Output)1 Input Capacitance IC Junction-to-Case Thermal Resistance, Side 1 Symbol RI-O CI-O CI θJCI IC Junction-to-Case Thermal Resistance, Side 2 θJCO 1 Min Typ 1012 1.0 4.0 46 Max 41 Unit Ω pF pF °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside °C/W The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together. REGULATORY INFORMATION The ADuM1250/ADuM1251 has been approved by the following organizations: Table 4. UL Recognized under 1577 Component Recognition Program1 Basic insulation, 2500 V rms isolation rating File E214100 1 2 CSA (Pending) Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (560 V peak) maximum working voltage File 205078 VDE (Pending) Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2):2003-012 Basic insulation,400 V rms (560 V peak) maximum working voltage File 2471900-4880-0001 In accordance with UL1577, each device is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). In accordance with DIN EN 60747-5-2, each device is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 2500 4.90 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 4.01 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa mm V Rev. 0 | Page 5 of 12 Conditions 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM1250/ADuM1251 DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage. Table 6. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1) Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/3 VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure (See also Figure 3) Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS, VIO = 500 V Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 560 1050 VPEAK VPEAK VPR 896 672 VPEAK VTR 4000 VPEAK TS IS1 IS2 RS 150 160 170 >109 °C mA mA Ω 350 250 200 150 100 50 0 0 50 100 150 CASE TEMPERATURE (°C) 200 06401-003 SAFETY-LIMITING CURRENT (mA) 300 Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2 RECOMMENDED OPERATING CONDITIONS Table 7. Parameter Operating Temperature Supply Voltages 1 Input/Output Signal Voltage Capacitive Load, Side 1 Capacitive Load, Side 2 Static Output Loading, Side 1 Static Output Loading, Side 2 1 Symbol TA VDD1, VDD2 VSDA1, VSCL1, VSDA2, VSCL2 CL1 CL2 ISDA1, ISCL1 ISDA2, ISCL2 Min −40 3.0 0.5 0.5 All voltages are relative to their respective ground. See the Application Notes section for data on immunity to external magnetic fields. Rev. 0 | Page 6 of 12 Max +105 5.5 5.5 40 400 3 30 Unit °C V V pF pF mA mA ADuM1250/ADuM1251 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Table 8. Parameter Storage Temperature Ambient Operating Temperature Supply Voltages1 Input/Output Voltage1, Side 1 Input/Output Voltage1, Side 2 Average Output Current, per Pin2 Common-Mode Transients3 Symbol TST TA Min −55 −40 Max +150 +105 Unit °C °C VDD1, VDD2 VSDA1, VSCL1 VSDA2, VSCL2 IO −0.5 +7.0 V −0.5 VDD1 + 0.5 V −0.5 VDD2 + 0.5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION mA −100 +100 kV/μs 1 All voltages are relative to their respective ground. See Figure 3 for maximum rated current values for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum rating may cause latchup or permanent damage. 2 Rev. 0 | Page 7 of 12 ADuM1250/ADuM1251 VDD1 1 SDA1 2 SCL1 3 GND1 4 ADuM1250/ ADuM1251 TOP VIEW (Not to Scale) 8 VDD2 7 SDA2 6 SCL2 5 GND2 06401-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. ADuM1250/ADuM1251 Pin Configuration Table 9. ADuM1250 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 SDA1 SCL1 GND1 GND2 SCL2 SDA2 VDD2 Description Supply Voltage, 3.0 V to 5.5 V. Data Input/Output, Side 1. Clock Input/Output, Side 1. Ground 1. Ground reference for isolator Side 1. Ground 2. Isolated ground reference for isolator Side 2. Clock Input/Output, Side 2. Data Input/Output, Side 2. Supply Voltage, 3.0 V to 5.5 V. Table 10. ADuM1251 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 SDA1 SCL1 GND1 GND2 SCL2 SDA2 VDD2 Description Supply Voltage, 3.0 V to 5.5 V. Data Input/Output, Side 1. Clock Input, Side 1. Ground 1. Ground reference for isolator Side 1. Ground 2. Isolated ground reference for isolator Side 2. Clock Output, Side 2. Data Input/Output, Side 2. Supply Voltage, 3.0 V to 5.5 V. Rev. 0 | Page 8 of 12 ADuM1250/ADuM1251 TEST CONDITIONS R1 R1 SDA1 SCL1 CL1 CL1 GND1 VDD2 1 DECODE ENCODE 8 2 ENCODE DECODE 7 3 DECODE ENCODE 6 4 ENCODE DECODE 5 SDA2 R2 R2 CL2 CL2 SCL2 GND2 Figure 5. Timing Test Diagram Rev. 0 | Page 9 of 12 06401-005 VDD1 ADuM1250/ADuM1251 APPLICATION NOTES STARTUP FUNCTIONAL DESCRIPTION Both the VDD1 and VDD2 supplies have an under voltage lockout feature to prevent the signal channels from operating unless certain criteria are met. This avoids the possibility of input logic low signals from pulling down the I2C bus inadvertently during power-up/power-down. The ADuM1250/ADuM1251 interfaces on each side to a bidirectional I2C signal. Internally, the I2C interface is split into two unidirectional channels communicating in opposing directions via a dedicated iCoupler isolation channel for each. One channel (the bottom channel of each channel pair shown in Figure 6) senses the voltage state of the Side 1 I2C pin and transmits its state to its respective Side 2 I2C pin. The two criteria that must be met in order for the signal channels to be enabled are as follows: Both the Side 1 and the Side 2 I C pins are designed to interface to an I2C bus operating in the 3.0 V to 5.5 V range. A logic low on either causes the opposite pin to be pulled low enough to comply with the logic low threshold requirements of other I2C devices on the bus. Avoidance of I2C bus contention is ensured by an input low threshold at SDA1 or SCL1 guaranteed to be at least 50 mV less than the output low signal at the same pin. This prevents an output logic low at Side 1 being transmitted back to Side 2 and pulling down the I2C bus. • • Both supplies must be at least 2.5 V. At least 40 μs must elapse after both supplies exceeded the internal startup threshold of 2.0 V. Until both of these criteria are met for both supplies, the ADuM1250/ADuM1251 outputs are pulled high, ensuring a startup that avoids any disturbances on the bus. Figure 7 and Figure 8 illustrate the supply conditions for fast and slow input supply slew rates. Since the Side 2 logic levels/thresholds are standard I2C values, multiple ADuM1250/ADuM1251 devices connected to a bus by their Side 2 pins can communicate with each other and with other devices having I2C compatibility 1 . MINIMUM RECOMMENDED OPERATING SUPPLY, 3.0V SUPPLY VALID MINIMUM VALID SUPPLY, 2.5V INTERNAL STARTUP THRESHOLD, 2.0V However, since the Side 1 pin has a modified output level/input threshold, this side of the ADuM1250/ADuM1251 can only communicate with devices conforming to the I2C standard. In other words, Side 2 of the ADuM1250/ADuM1251 is I2Ccompliant while Side 1 is only I2C-compatible. The output logic low levels are independent of the VDD1 and VDD2 voltages. The input logic low threshold at Side 1 is also independent of VDD1. However, the input logic low threshold at Side 2 is designed to be at 0.3 VDD2, consistent with I2C requirements. The Side 1 and Side 2 pins have open-collector outputs whose high levels are set via pull-up resistors to their respective supply voltages. 40µs Figure 7. Start-Up Condition, Supply Slew Rate >12.5 V/ms MIN. RECOMMENDED OPERATING SUPPLY, 3.0V MIN. VALID SUPPLY, 2.5V SUPPLY VALID 1 DECODE ENCODE 8 SDA1 2 ENCODE DECODE 7 SCL1 3 DECODE ENCODE 6 GND1 4 ENCODE DECODE 5 SDA2 R2 R2 40µs Figure 8. Start-Up Condition, Supply Slew Rate <12.5 V/ms GND2 CL CL 06401-006 SCL2 Figure 6. ADuM1250 Block Diagram 1 Here a distinction is made between I2C compatibility and I2C compliance. I2C compatibility refers to situations in which a component's logic levels do not necessarily meet the requirements of the I2C specification but still allow the component to communication with an I2C-compliant device. I2C compliance refers to situations in which a component's logic levels meet the requirements of the I2C specification. Rev. 0 | Page 10 of 12 06401-008 INTERNAL STARTUP THRESHOLD, 2.0V VDD2 VDD1 06401-007 2 ADuM1250/ADuM1251 For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (with the worst-case polarity), it reduces the received pulse from > 1.0 V to 0.75 V. Note that this is still well above the 0.5 V sensing threshold of the decoder. SDA1 ADuM1250 8 2 7 SCL1 3 6 GND1 4 5 V2 SDA2 I2C BUS SCL2 GND2 Figure 9. Typical Isolated I2C Interface using ADuM1250 MAGNETIC FIELD IMMUNITY The ADuM1250 is extremely immune to external magnetic fields. The limitation on the ADuM1250’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM1250 is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ / dt )∑ Πrn2 ; n = 1, 2, ...N where: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM1250 transformers. Figure 11 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 11, the ADuM1250 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example, one would have to place a 0.5 kA current 5 mm away from the ADuM1250 to affect the component’s operation. 1000 DISTANCE = 1m 100 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 Given the geometry of the receiving coil in the ADuM1250 and an imposed requirement that the induced voltage is at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 10. 10 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 11. Maximum Allowable Current for Various Current-to-ADuM1250 Spacings 1 0.1 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 06401-010 0.01 0.001 1k 10k Note that at combinations of strong magnetic fields and high frequencies, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. 100 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 1k 06401-011 1 06401-009 VDD MAXIMUM ALLOWABLE CURRENT (kA) TYPICAL APPLICATION DIAGRAM Figure 10. Maximum Allowable External Magnetic Flux Density Rev. 0 | Page 11 of 12 ADuM1250/ADuM1251 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2440) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 060506-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 12. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters (inches) ORDERING GUIDE Model ADuM1250ARZ 1 ADuM1250ARZ-RL71 ADuM1251ARZ1 ADuM1251ARZ-RL71 1 Number of Inputs, VDD1 Side 2 2 2 2 Number of Inputs, VDD2 Side 2 2 1 1 Maximum Data Rate (Mbps) 1 1 1 1 Maximum Propagation Delay (ns) 150 150 150 150 Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06113-0-10/06(0) Rev. 0 | Page 12 of 12 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Package Option R-8 R-8 R-8 R-8