AD AD1953YST

a
SigmaDSP™ 3-Channel, 26-Bit
Signal Processing DAC
AD1953
FEATURES
APPLICATIONS
5 V 3-Channel Audio DAC System
2.0/2.1 Channel Audio Systems (2 Main Channels
Digital Audio Output (2-Channel or 6-Channel
Plus Subwoofer)
Packed Mode)
Multichannel Automotive Sound Systems
Accepts Sample Rates up to 48 kHz
Multimedia Audio
7 Biquad Filter Sections per Channel
Mini Component Stereo
Dual Dynamic Processor with Arbitrary Input/Output
Home Theater Systems (AC-3 Postprocessor)
Curve and Adjustable Time Constants
Musical Instruments
0 ms to 6 ms Variable Delay/Channel for Speaker Alignment
In-Seat Sound Systems (Aircraft, Motor Coaches)
Stereo Spreading Algorithm for Phat Stereo™ Effect
Program RAM Allows Complete New Program Download
PRODUCT OVERVIEW
via SPI Port
The AD1953 is a complete 26-bit, single-chip, 3-channel digital
Parameter RAM Allows Complete Control of More Than
audio playback system with built-in DSP functionality for speaker
200 Parameters via SPI Port
equalization, dual-band compression/limiting, delay compensaSPI Port Features Safe-Upload Mode for Transparent
tion, and image enhancement. These algorithms can be used to
Filter Updates
compensate for real-world limitations of speakers, amplifiers,
2 Control Registers Allow Complete Control of Modes
and listening environments, resulting in a dramatic improvement
and Memory Transfers
of perceived audio quality.
Differential Output for Optimum Performance
The signal processing used in the AD1953 is comparable to that
112 dB Signal-to-Noise (Not Muted) at 48 kHz Sample
found in high end studio equipment. Most of the processing is
Rate (A-Weighted Stereo)
done in full 48-bit double-precision mode, resulting in very good
70 dB Stop-Band Attenuation
low level signal performance and the absence of limit cycles or
On-Chip Clickless Volume Control
idle tones. The compressor/limiter uses a sophisticated two-band
Hardware and Software Controllable Clickless Mute
algorithm often found in high end broadcast compressors.
Digital De-emphasis Processing for 32 kHz, 44.1 kHz, 48 kHz
(continued on page 9)
Sample Rates
Flexible Serial Data Port with Right-Justified, Left-Justified,
I2S Compatible, and DSP Serial Port Modes
Auxiliary Digital Input
Graphical Custom Programming Tools
48-Lead LQFP Plastic Package
FUNCTIONAL BLOCK DIAGRAM
SERIAL DATA
OUTPUT
3
3
AD1953
SERIAL DATA
INPUTS
3
AUDIO DATA
MUX
3
MASTER CLOCK
OUTPUT
MASTER
CLOCK INPUTS
MCLK
MUX
26 22
DSP CORE
DAC – L
DATA FORMAT:
3.23 (SINGLE PRECISION)
3.45 (DOUBLE PRECISION)
DAC – R
MCLK
GENERATOR
(256/512 fS)
ANALOG
OUTPUTS
DAC – SW
AUX SERIAL
DATA INPUT
DATA CAPTURE
OUT/TDM OUT
SPI DATA
OUTPUT
SPI INPUT
3
DIGITAL
OUTPUT
SERIAL CONTROL
INTERFACE
RAM
ROM
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD1953
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7
TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 8
PERFORMANCE PLOTS . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal Processing Overview . . . . . . . . . . . . . . . . . . . . . . . 12
Numeric Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Coefficient Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Internal DSP Signal Data Format . . . . . . . . . . . . . . . . . . 13
High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Biquad Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Stereo Image Expander . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Main Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . 15
RMS Time Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RMS Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RMS Release Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Look-Ahead Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Post-Compression Gain . . . . . . . . . . . . . . . . . . . . . . . . . .
Subwoofer Compressor/Limiter . . . . . . . . . . . . . . . . . . . .
De-Emphasis Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Sub Reinjection Paths for Systems with No
Subwoofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interpolation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Volume Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter RAM Contents . . . . . . . . . . . . . . . . . . . . . . . .
Options for Parameter Updates . . . . . . . . . . . . . . . . . . . .
Soft Shutdown Mechanism . . . . . . . . . . . . . . . . . . . . . . .
Safeload Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of RAM Modes . . . . . . . . . . . . . . . . . . . . . . . .
SPI READ/WRITE DATA FORMATS . . . . . . . . . . . . . . .
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting the Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting the Data and MCLK Input Selectors . . . . . . . . . .
DATA CAPTURE REGISTERS AND OUTPUTS . . . . . .
SERIAL DATA INPUT/OUTPUT PORTS . . . . . . . . . . . .
Serial Data Input/Output Modes . . . . . . . . . . . . . . . . . . .
DIGITAL CONTROL PIN . . . . . . . . . . . . . . . . . . . . . . . .
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ANALOG OUTPUT SECTION . . . . . . . . . . . . . . . . . . . .
GRAPHICAL CUSTOM PROGRAMMING TOOLS . . . .
APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .
–2–
REV. 0
17
17
18
18
18
18
18
19
21
22
23
23
24
25
25
25
26
27
27
27
28
28
30
30
31
31
31
32
33
34
AD1953
SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED.
Supply Voltages (AVDD, DVDD)
Ambient Temperature
Input Clock
Input Signal
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance
Load Impedance
Input Voltage High
Input Voltage Low
5.0 V
25°C
12.288 MHz
1.000 kHz 0 dB Full Scale
48 kHz
20 Hz to 20 kHz
24 Bits
2200 pF
2.74 kΩ
2.1 V
0.8 V
ANALOG PERFORMANCE*
Parameter
Min
Typ
Max
Unit
RESOLUTION
24
Bits
SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Left/Right Output)
No Filter (Stereo)
With A-Weighted Filter
109
112
dB
dB
DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Left/Right Output)
No Filter
With A-Weighted Filter
108
109
112
dB
dB
TOTAL HARMONIC DISTORTION PLUS NOISE (Left/Right Output)
VO = –0.5 dB
–93
–100
dB
104
107
dB
dB
SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Subwoofer Output)
No Filter (Stereo)
With A-Weighted Filter
DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input) (Subwoofer Output)
No Filter
With A-Weighted Filter
104
104
107
dB
dB
TOTAL HARMONIC DISTORTION PLUS NOISE (Subwoofer Output)
VO = –0.5 dB
–90
–96
dB
ANALOG OUTPUTS
Differential Output Range (± Full Scale) (Left/Right Output)
Differential Output Range (± Full Scale) (Subwoofer Output)
2.72
2.79
V p-p
V p-p
CMOUT
2.50
V
DC ACCURACY
Gain Error (Left/Right Channel)
Gain Error (Subwoofer Channel)
Interchannel Gain Mismatch
Gain Drift
DC Offset
–5
–8
–0.250
+5
+8
+0.250
150
–35
+35
%
%
dB
ppm/°C
mV
INTERCHANNEL CROSSTALK (EIAJ Method)
–120
dB
INTERCHANNEL PHASE DEVIATION
± 0.1
Degrees
MUTE ATTENUATION
–107
dB
± 0.1
DE-EMPHASIS GAIN ERROR
*Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
REV. 0
–3–
dB
AD1953
DIGITAL I/O
Parameter
Min
Input Voltage High (VIH)
Input Voltage High (VIH) – RESETB
Input Voltage Low (VIL)
Input Leakage (IIH @ VIH = 2.1 V)
Input Leakage (IIL @ VIL = 0.8 V)
High Level Output Voltage (VOH), IOH = 2 mA
Low Level Output Voltage (VOL), IOL = 2 mA
Input Capacitance
2.1
2.25
Typ
Max
Unit
0.4
20
V
V
V
µA
µA
V
V
pF
0.8
10
10
DVDD – 0.5
Specifications subject to change without notice.
POWER
Parameter
SUPPLIES*
Voltage: Analog, and Digital
Analog Current
Analog Current, Power-Down
Digital Current
Digital Current, SPI Power-Down
Digital Current, Reset Power-Down
Min
Typ
Max
Unit
4.5
5
42
40
66
6
54
5.5
48
46
76
10
62
V
mA
mA
mA
mA
mA
DISSIPATION
Operation, Both Supplies
Operation, Analog Supplies
Operation, Digital Supplies
SPI Power-Down, Both Supplies
Reset Power-Down, Both Supplies
540
210
330
230
470
mW
mW
mW
mW
mW
POWER SUPPLY REJECTION RATIO
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
–80
–80
dB
dB
*ODVDD current is dependent on load capacitance and clock rate.
Specifications subject to change without notice.
TEMPERATURE RANGE
Parameter
Min
Specifications Guaranteed
Functionality Guaranteed
Storage
–40
–55
Typ
Max
Unit
105
125
°C
°C
°C
25
Specifications subject to change without notice.
–4–
REV. 0
AD1953
DIGITAL TIMING
Parameter
Min
tDMD
tDMD
tDMD
tDBH
tDBH
tDBD
tDLS
tDLH
tDLD
tDDS
tDDH
tDDD
tTFS
tTBS
tTOS
tCCL
tCCH
tCLS
tCLH
tCLD
tCDS
tCDH
tCOD
tCOH
tDCD
tDCH
tPDRP
45
40
MCLK Recommended Duty Cycle @ 12.288 MHz (256 fS Mode)
MCLK Recommended Duty Cycle @ 24.576 MHz (512 fS Mode)
MCLK Delay (All Mode)
BCLK Low Pulsewidth
BCLK High Pulsewidth
BCLK Delay (to BCLKO)
LRCLK Setup
LRCLK Hold
LRCLK Delay (to LRCLKO)
SDATA Setup
SDATA Hold
SDATA Delay (to SDATAO)
TDMFS Delay (from MCLK)
TDMBC Delay (from MCLK)
TDMO Delay (from TDMBC)
CCLK Low Pulsewidth
CCLK High Pulsewidth
CLATCH Setup
CLATCH Hold
CLATCH High Pulsewidth
CDATA Setup
CDATA Hold
COUT Delay
COUT Hold
DCSOUT Delay
DCSOUT Hold
PD/RST Low Pulsewidth
Typ
Max
Unit
55
60
25
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
25
0
10
25
0
10
25
35
35
5
12
12
10
10
10
0
10
35
2
35
2
5
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS at 44.1 kHz
Parameter
Min
Pass-Band Ripple
Stop-Band Attenuation
Pass Band
70
20
0.4535 ⫻ fS
24
0.5442 ⫻ fS
24.625/fS
Stop Band
Group Delay
Specifications subject to change without notice.
REV. 0
Typ
–5–
Max
Unit
± 0.01
dB
dB
kHz
kHz
sec
AD1953
ABSOLUTE MAXIMUM RATINGS *
Package Characteristics (48-Lead LQFP)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
ODVDD to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Inputs . . . . . . . . . . DGND – 0.3 V to DVDD + 0.3 V
Analog Inputs . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Reference Voltage . . . . . . . . . . . . . . . . . . . (AVDD + 0.3)/2 V
Maximum Junction Temperature . . . . . . . . . . . . . . . . 125∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C/10 sec
Min
␪JA (Thermal Resistance
[Junction-to-Ambient])
␪JC (Thermal Resistance
[Junction-to-Case])
Typ
Max
Unit
76
∞C/W
17
∞C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD1953YST
AD1953YSTRL
AD1953YSTRL7
EVAL-AD1953EB
–40∞C to +105∞C
–40∞C to +105∞C
–40∞C to +105∞C
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
Evaluation Board
ST-48
ST-48 on 13" Reel
ST-48 on 7" Reel
NC
VREF
FILTCAP
ZEROFLAG
DMUXO/TDMO
BMUXO/TDMBC
LRMUXO/TDMFS
ODVDD
DCSOUT
COUT
MCLKOUT
DGND
PIN CONFIGURATION
48-Lead LQFP
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
MCLK2 2
36 NC
PIN 1
IDENTIFIER
35 AGND
MCLK1 3
34 VOUTL–
MCLK0 4
33 VOUTL+
AUXDATA 5
MUTE 6
AD1953
DVDD 7
TOP VIEW
(Not to Scale)
32 AVDD
31 AGND
30 AVDD
SDATA2 8
29 VOUTR+
BCLK2 9
28 VOUTR–
LRCLK2 10
27 AGND
SDATA1 11
26 VOUTS+
BCLK1 12
NC
AGND
AVDD
RESETB
CLATCH
CCLK
CDATA
LRCLK0
BCLK0
SDATA0
DGND
LRCLK1
NC = NO CONNECT
25 VOUTS–
13 14 15 16 17 18 19 20 21 22 23 24
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1953 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–6–
REV. 0
AD1953
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Input/
Output
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
NC
MCLK2
MCLK1
MCLK0
AUXDATA
MUTE
DVDD
SDATA2
BCLK2
LRCLK2
SDATA1
BCLK1
DGND
LRCLK1
SDATA0
BCLK0
LRCLK0
CDATA
CCLK
CLATCH
RESETB
AVDD
AGND
NC
VOUTS–
VOUTS+
AGND
VOUTR–
VOUTR+
AVDD
AGND
AVDD
VOUTL+
VOUTL–
AGND
NC
NC
VREF
FILTCAP
ZEROFLAG
DMUXO/TDMO
BMUXO/TDMBC
LRMUXO/TDMFS
IN
IN
OUT
OUT
OUT
OUT
44
45
ODVDD
DCSOUT
OUT
46
47
48
COUT
MCLKOUT
DGND
REV. 0
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Description
No Connect
Master Clock Input 2 256/512 fS
Master Clock Input 1 256/512 fS
Master Clock Input 0 256/512 fS
Auxiliary Serial Data Input
Mute Signal, Initiates Volume Ramp-Down
Digital Supply for DSP Core, 4.5 V to 5.5 V
Serial Data Input 2
Bit Clock 2
Left/Right Clock 2
Serial Data Input 1
Bit Clock 1
Digital Ground
Left/Right Clock 1
Serial Data Input 0
Bit Clock 0
Left/Right Clock 0
SPI Data Input
SPI Data Bit Clock
SPI Data Framing Signal
Reset Signal, Active Low
Analog 5 V Supply
Analog GND
No Connect
Negative Sub Analog DAC Output
Positive Sub Analog DAC Output
Analog GND
Negative Left Analog DAC Output
Positive Left Analog DAC Output
Analog 5 V Supply
Analog GND
Analog 5 V Supply
Positive Left Analog DAC Output
Negative Left Analog DAC Output
Analog GND
No Connect
No Connect
Connection for Filtered AVDD/2
Connection for Noise Reduction Capacitor
Zero Flag Output. High when both left and right channels are 0 for 1024 frames.
Dual-function Pin: Serial Data MUX Output/TDM Mode Output Data
Dual-function Pin: Bit Clock MUX Output/TDM Mode Bit Clock Output (256 fS)
Dual-function Pin: Left/Right Clock MUX Output/TDM Mode Frame Sync
Clock Output
Digital Supply Pin for Output Drivers, 2.5 V to 5.5 V
Data Capture Serial Output for Data Capture Registers. Use in conjunction
with selected LRCLK and BCLK to form a 3-wire output.
SPI Data Output, Three-Stated when Inactive
Master Clock Output 512/256 fS (Frequency Selected by SPI Register)
Digital Ground
–7–
AD1953–Typical Performance Characteristics
PERFORMANCE PLOTS
The following plots demonstrate the performance achieved on the
actual silicon. TPC 1 shows an FFT of a full-scale 1 kHz signal
with a THD+N of –100 dB, which is dominated by a second
harmonic. TPC 2 shows an FFT of a –60 dB sine wave, demonstrating the lack of low level artifacts. TPC 3 shows a frequency
response plot with the seven equalization biquads set to an alternating pattern of 6 dB boosts and cuts. TPC 4 shows a linearity
plot, where the measurement was taken with the same equalization curve used to make TPC 3. When the biquad filters are not
in use, the signal passes through the filters with no quantization
effects. TPC 4 therefore demonstrates that using double-precision
math in the biquad filters has virtually eliminated any quantization
artifacts. TPC 5 shows a tone-burst applied to the compressor,
with the attack and recovery characteristics plainly visible. The
rms detector was programmed for normal rms time constants;
the hold/decay feature was not used for this plot.
0
–2
–4
–6
dB
–8
–10
–12
–14
–16
–18
–20
20
50
100
200
500
1k
5k
10k
Hz
TPC 3. Frequency Response of EQ Biquad Filters
0
3.0
2.5
–20
2.0
–40
1.5
1.0
–60
dB
dB
0.5
–80
0
–0.5
–100
–1.0
–120
–1.5
–2.0
–140
–2.5
–160
0
2
4
6
8
10
kHz
12
14
16
18
–3.0
–120
20
–20
1.5
–40
1.0
–60
0.5
V
dB
2.0
–80
–0.5
–120
–1.0
–140
–1.5
4
6
8
10
–40
–20
0
0
–100
2
–60
TPC 4. Linearity Plot
0
0
–80
dBFS
TPC 1. FFT of Full-Scale Sine Wave (32k Points)
–160
–100
12
14
16
18
–2.0
–120
20
–100
–80
–60
–20
0
ms
kHz
TPC 5. Tone-Burst Response with Compressor
Threshold Set to –20 dB
TPC 2. FFT of –60 dB Sine Wave (32k Points)
–8–
REV. 0
AD1953
PRODUCT OVERVIEW (continued from page 1)
An extensive SPI port allows click-free parameter updates, along
with readback capability from any point in the algorithm flow.
The AD1953 also includes ADI’s patented multibit Σ-∆ DAC
architecture. This architecture provides 112 dB SNR and dynamic
range and THD+N of –100 dB. These specifications allow the
AD1953 to be used in applications ranging from low end
boom-boxes to high end professional mixing/editing systems.
The AD1953 has a digital output that allows it to be used purely
as a DSP. This digital output can also be used to drive an external DAC to extend the number of channels beyond the three
that are provided on the chip. This chip can be used with either
its default signal processing program or with a custom userdesigned program. Graphical programming tools are available
from ADI for custom programming.
Features
The AD1953 is comprised of a 26-bit DSP (48-bit with doubleprecision) for interpolation and audio processing, three multibit
Σ-∆ modulators, and analog output drive circuitry. Other features
include an on-chip parameter RAM using a “safe-upload” feature
for transparent and simultaneous updates of filter coefficients.
Digital de-emphasis filters are also included. On-chip input
selectors allow up to three sources of serial data and master
clock to be selected. The 3-channel configuration is especially
useful for 2.1 playback systems that include two satellite speakers
and a subwoofer. The default program allows for independent
equalization and compression/limiting for the satellite and
subwoofer outputs. Figure 1 shows the block diagram of the device.
The AD1953 contains a program RAM that is booted from an
internal program ROM on power-up. Signal-processing parameters are stored in a 256-location parameter RAM, which is
initialized on power-up by an internal boot ROM. New values
are written to the parameter RAM using the SPI port. The
values stored in the parameter RAM control the IIR equalization
filters, the dual-band compressor/limiter, the delay values, and
the settings of the stereo spreading algorithm.
The AD1953 has a very sophisticated SPI port that supports
complete read/write capability of both the program RAM and
the parameter RAM. Two control registers are also provided to
control the chip serial modes and various other optional features. Handshaking is included for ease of memory uploads/
downloads.
The AD1953 contains eight independent data-capture circuits
that can be programmed to tap the signal flow of the processor
at any point in the DSP algorithm flow. Two of these datacapture circuits can be read back over the SPI port, and the
other six are fed to a serial output pin operating either in TDM
mode (for all six channels) or 2-channel mode for simple connection to an external DAC. This allows the basic functionality
of the AD1953 to be easily extended.
The processor core in the AD1953 has been designed from the
ground up for straightforward coding of sophisticated compression/limiting algorithms. The AD1953 contains two independent
compressor/limiters with rms based amplitude detection and
attack/hold/release controls, together with an arbitrary compression curve that is loaded by the user into a lookup table that
resides in the parameter RAM. The compressor also features
look-ahead compression, which prevents compressor overshoots.
The AD1953 has a very flexible serial data input port that allows
for glueless interconnection to a variety of ADCs, DSP chips,
AES/EBU receivers, and sample rate converters. The AD1953
can be configured in left-justified, I2S, right-justified, or DSP
serial port compatible modes. It can support 16, 20, and 24 bits
in all modes. The AD1953 accepts serial audio data in MSB
first, twos complement format. The part can also be set up in a
4-channel serial input mode by simultaneously using the serial
input mux and the auxiliary serial input.
The AD1953 operates from a single 5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed
in a 48-lead LQFP package for operation over the temperature
range –40°C to +105°C.
VREF
DVDD AVDD ODVDD
3
ZEROFLAG
RESETB MUTE
VOLTAGE
REFERENCE
DATA MEMORY, 512 26
3
3
3
3
3:1
AUDIO
DATA
MUX1
DAC – L
SERIAL
IN1
26 22
DSP CORE
3:1
MCLK
MUX1
MCLK
GENERATOR1
(256/512 fS IN)
256/512 fS OUT
CONTROL
REGISTERS
3
SPI PORT
DATA FORMAT:
3.23 (SINGLE PRECISION)
3.45 (DOUBLE PRECISION)
TRAP REG.
(I2S, SPI)
BOOT ROM
MASTER
CLOCK I/O
GROUP
SAFELOAD
REGISTERS
PROGRAM
RAM
512 35
PARAMETER
RAM
256 22
MEMORY CONTROLLERS
FILTCAP
NOTES
1CONTROLLED THROUGH SPI CONTROL REGISTERS
2DAC DOES NOT USE DIGITAL INTERPOLATION
Figure 1. Block Diagram
REV. 0
ANALOG
OUTPUTS
DAC –SW2
AUX SERIAL
DATA INPUT
SPI I/O
GROUP
DAC – R
–9–
ANALOG
BIAS
BIAS
BOOT ROM
SERIAL DATA I/O
GROUP
(2-CHANNEL
AND TDM)
DE-EMPHASIS
COEFFICIENT
ROM
64 22
DCSOUT TRAP
AGND
DGND
3
2
DCSOUT
AD1953
Pin Functions
All input pins have a logic threshold compatible with TTL input
levels, and may therefore be used in systems with 3.3 V logic.
All digital output levels are controlled by the ODVDD pin,
which may range from 2.7 V to 5.5 V, for compatibility with a
wide range of external devices. (See Pin Function Descriptions.)
SDATA0, 1, 2—Serial Data Inputs.
One of these three inputs is selected by an internal MUX, set by
writing to Bits <7:6> in Control Register 2. Default is 00, which
selects SDATA0. The serial format is selected by writing to Bits
<3:0> of Control Register 0. See SPI Read/Write Data Formats
section for recommendations on how to change input sources
without causing a click or pop noise.
LRCLK0, 1, 2—Left/Right Clocks for Framing the Input Data.
The active LRCLK input is selected by writing to Bits <7:6>
in Control Register 2. Default is 00, which selects LRCLK0.
The interpretation of the LRCLK changes according to the serial
mode, set by writing to Control Register 0.
MCLKO—Master Clock Output.
The master clock output pin may be programmed to produce
either 256 × fS, 512 × fS, or a copy of the selected MCLK input
pin. This pin is programmed by writing to Bits <1:0> of Control
Register 2. The default is 00, which disables the MCLKO pin.
CDATA—Serial Data In for the SPI Control Port.
See SPI Port section for more information on SPI port timing.
COUT—Serial Data Output.
This is used for reading back registers and memory locations. It
is three-stated when an SPI read is not active. See SPI Port
section for more information on SPI port timing.
CCLK—SPI Bit Rate Clock.
This pin either may run continuously or be gated off between
SPI transactions. See SPI Port section for more information on
SPI port timing.
CLATCH—SPI Latch Signal.
This pin must go LOW at the beginning of an SPI transaction,
and HIGH at the end of a transaction. Each SPI transaction
may take a different number of CCLKs to complete, depending
on the address and read/write bit that are sent at the beginning
of the SPI transaction. Detailed SPI timing information is given
in the SPI Port section.
BCLK0, 1, 2—Serial Bit Clocks for Clocking in the Serial Data.
The active BCLK input is selected by writing to Bits <7:6> in
Control Register 2. Default is 00, which selects BCLK0. The
interpretation of BCLK changes according to the serial mode,
which is set by writing to Control Register 0.
DMUXO/TDMO, LRMUXO/TDMFS, BMUXO/TDMBC
Dual-function pins:
• Function 1: Outputs of 3:1 MUX that selects one of the
three serial input groups.
• Function 2: Used for 6-channel data capture outputs in
TDM Data Capture Mode.
These three pins operate as MUX outputs when Bit <8> of
Control Register 2 is a 1 and Bits <13:12> of Control Register 1
are 00. These pins may be used to send the selected serial input
signals to other external devices. The default is OFF.
In TDM mode, TDMBC provides a 256 × fS clock signal,
TDMFS provides a frame sync signal, and TDMO provides the
TDM data for an external multichannel DAC or CODEC, such
as the AD1833 or AD1836 respectively. These output pins are
enabled by writing a 01 to Bits <13:12> of Control Register 1.
The default mode is 00, or OFF.
In TDM mode, the internal signals that are captured are controlled by writing Program Counter Trap numbers to SPI
addresses 268 to 273. When the internal Program Counter
contents are equal to the Trap values written to the SPI port, the
selected DSP register is transferred to parallel-to-serial registers
and shifted out of the TDMO pin.
MCLK0, 1, 2—Master Clock Inputs.
Active input selected by writing to Bits <5:4> of Control Register 2. The default is 00, which selects MCLK0. The master clock
frequency must be either 256 × fS or 512 × fS, where fS is the input
sampling rate. The master clock frequency is programmed by
writing to Bit <2> of Control Register 2. The default is 0, (512
× fS). See Initialization section for recommendations concerning
how to change clock sources without causing an audio click or
pop. Note that since the default MCLK source pin is MCLK0,
there must be a clock signal present on this pin on power-up so
that the AD1953 can complete its initialization routine.
RESETB—Active-Low Reset Signal.
After RESETB goes HIGH, the AD1953 goes through an initialization sequence where the program and parameter RAMs
are initialized with the contents of the on-board boot ROMs. All
SPI registers are set to 0, and the data RAMs are also zeroed.
The initialization is complete after 1024 MCLK cycles. Since
the MCLK IN FREQ SELECT (Bit <2> in Control Register 2)
defaults to 512 × fS at power-up, this initialization will proceed
at the external MCLK rate and will take 1024 MCLK cycles to
complete, regardless of the absolute frequency of the external
MCLK. New values should not be written to the SPI port until
the initialization is complete.
ZEROFLAG—Zero-Input Indicator.
This pin will go HIGH if both serial inputs have been inactive
(zero data) for 1024 LRCLK cycles. This pin may be used to
drive an external mute FET for reduced noise during digital
silence. This pin also functions as a test out pin, controlled by
the test register at SPI address 511. While most test modes are
not useful to the end user, one may be of some use. If the test
register is programmed with the number 7 (decimal), the
ZEROFLAG output will be switched to the output of the internal pseudo-random noise generator. This noise generator
operates at a bit rate of 128 × fS, and has a repeat time of once
per 224 cycles. This mode may be used to generate white noise
(or, with appropriate filtering, pink noise) to be used as a test
signal for measuring speakers or room acoustics.
DCSOUT—Data Capture Serial Out.
This pin will output the DSP’s internal signals, which can be
used by external DACs or other signal-processing devices. The
signals that are captured and output on the DCSOUT pin are
controlled by writing Program Counter Trap numbers to SPI
addresses 263 (for the left output) and 264 (for the right output).
When the internal Program Counter contents are equal to the
Trap values written to the SPI port, the selected DSP register is
transferred to the DCSOUT parallel-to-serial registers and
–10–
REV. 0
AD1953
shifted out on the DCSOUT pin. Table XXI shows the Program Counter Trap values and register-select values that should
be used to tap various internal points of the algorithm flow.
The DCSOUT pin is meant to be used in conjunction with the
LRCLK and BCLK signals that are provided to the serial input
port. The format of DCSOUT is the same as the format used
for the serial port. In other words, if the serial port is running in
I2S mode, then the DCSOUT pin, together with the LRCLK0
and BCLK0 pins (assuming input 0 is selected), will form a
valid 3-wire I2S output.
The DCSOUT pin can be used for a variety of purposes. If the
DCSOUT pin is used to drive another external DAC, then a 4.1
system is possible using a new program downloaded into the
program RAM.
AUXDATA—Auxiliary Serial Data Input.
The AUXDATA pin may be used in conjunction with a custom
program to access two extra channels of serial input data, allowing for a total of four input channels. The serial format is identical
to the selected format of SDATA0, 1, 2. The AUXDATA pin is
synchronous to the selected LRCLK and BCLK signal, and therefore should have the same timing as the main serial input signal.
MUTE—Mute Output Signal.
When this pin is asserted HIGH, a ramp sequence is started that
gradually reduces the volume to zero. When deasserted, the
volume ramps from zero back to the original volume setting.
The ramp speed is timed so that it takes 10 ms to reach zero
volume when starting from the default 0 dB volume setting.
VOUTS+, VOUTS– —Sub Channel Differential Outputs.
These outputs are designed to drive loads of 10 kΩ or greater,
with a peak current capability of 250 µA. This output does not
use digital interpolation, as it is intended for low frequency
application. An external third-order filter with a cutoff frequency
< 2 kHz is recommended.
VREF—Analog Reference Voltage Input.
The nominal VREF input voltage is 2.5 V; the analog gain
scales directly with the voltage on this pin. When using the
AD1953 to drive a power amplifier, it is recommended that the
VREF voltage be derived by dividing down and heavily filtering
the supply to the power amplifier. This provides a benefit if the
compressor/limiter in the AD1953 is used to prevent amplifier
clipping. In this case, if the DAC output voltage is scaled to the
amplifier power supply, a fixed compressor threshold can be
used to protect an amplifier whose supply may vary over a wide
range. Any ac signal on this pin will cause distortion, and a large
decoupling capacitor may therefore be necessary to ensure that
the voltage on VREF is clean. The input impedance of VREF is
greater than 1 MΩ.
FILTCAP—Filter Capacitor Point.
This pin is used to reduce the noise on an internal biasing point
in order to provide the highest performance. It may not be necessary to connect this pin, depending on the quality of the layout
and grounding used in the application circuit.
DVDD—Digital VDD for Core.
5 V nominal.
VOUTL+, VOUTL– —Left-Channel Differential Analog Outputs. Full-scale outputs correspond to 1 V rms on each output pin,
or 2 V rms differential, assuming a VREF input voltage of 2.5 V. The
full-scale swing scales directly with VREF. These outputs are
capable of driving a load of > 5 kΩ, with a maximum peak current
of 1 mA from each pin. An external third-order filter is recommended for filtering out-of-band noise.
ODVDD—Digital VDD for All Digital Outputs.
Variable from 2.7 V to 5.5 V.
VOUTR+, VOUTR– —Right Channel Differential Outputs.
Output characteristics are the same as for VOUTL+ and VOUTL–.
AGND (3)—Analog Ground.
For best performance, separate nonoverlapping analog and
digital ground planes should be used.
REV. 0
DGND (2)—Digital Ground.
AVDD (3)—Analog VDD.
5 V nominal. For best results, use a separate regulator for AVDD.
Bypass capacitors should be placed close to the pins and connected directly to the analog ground plane.
–11–
AD1953
L/R DYNAMICS PROCESSOR
IN
RIGHT
HPF/
DE-EMPHASIS
7 BIQUAD
FILTERS
CROSSOVER
(2 FILTERS)
CROSSOVER
(2 FILTERS)
PHAT STEREO
7 BIQUAD
FILTERS
VOLUME
HPF/
DE-EMPHASIS
DELAY
(0ms–3.7ms)
CROSSOVER
(3 FILTERS)
DELAY
(0ms–2.3ms)
8
INTERPOLATION
DAC
OUT
LEFT
8
INTERPOLATION
DAC
OUT
RIGHT
LEVEL DETECT,
LOOK-UP TABLE
DELAY
(0ms–3.7ms)
1 BIQUAD
FILTER
SUB CHANNEL
L/R MIX
VOLUME
IN
LEFT
VOLUME
EQ AND CROSSOVER FILTERS
DELAY
(0ms–2.3ms)
L/R REINJECTION
LEVEL
LEVEL DETECT,
LOOK-UP TABLE
DELAY
(0ms–3.7ms)
MONO DAC
SUBWOOFER
OUTPUT
SUB DYNAMICS PROCESSOR
Figure 2. Signal Processing Flow
Figure 3. Graphical User Interface
SIGNAL PROCESSING
Signal Processing Overview
Figure 2 shows the signal processing flow diagram of the AD1953.
The AD1953 is designed to provide all common signal-processing
functions commonly used in 2.0 or 2.1 playback systems. A
7-biquad equalizer operates on the stereo input signal. The
output of this equalizer is fed to a 2-biquad crossover filter for
the main channels, and the mono sum of the left and right equalizer
outputs is fed to a 3-biquad crossover filter for the Sub channel.
Each of the three channels has independent delay compensation. There are two high quality compressor/limiters available:
one operating on the left/right outputs and one operating on the
subwoofer channel. The subwoofer output may be blended back
into the left/right outputs for 2.0 playback systems. In this
configuration, the two independent compressor/limiters provide
2-band compression, which significantly improves the sound
quality of compressed audio. In addition, the main channels
have a stereo widening algorithm that increases the perceived
spread of the stereo image.
Most of the signal processing functions are coded using full 48-bit
double-precision arithmetic. The input word length is 24 bits,
with two extra headroom bits added in the processor to allow
internal gains up to 12 dB without clipping (additional gains can
be accommodated by scaling down the input signal in the first
biquad filter section).
A graphical user interface (GUI) is available for evaluation of
the AD1953 (Figure 3). This GUI controls all of the functions
of the chip in a very straightforward and user-friendly interface.
No code needs to be written to use the GUI to control the chip.
For more information on AD1953 software tools, send an email to
[email protected]
–12–
REV. 0
AD1953
2-BIT SIGN EXTENTION
DATA IN
0.75
DAC INTERPOLATION
FILTERS (3.23 FORMAT)
SIGNAL PROCESSING
(3.23 FORMAT)
SERIAL PORT
1.23
DIGITAL
CLIPPER
3.23
DIGITAL -
MODULATORS
(1.23 FORMAT)
Figure 4. Numeric Precision and Clipping Structure
It is common in DSP systems to use a standardized method of
specifying numeric formats. To better comprehend issues relating to precision and overflow, it is helpful to think in terms of
fractional twos complement number systems. Fractional
number systems are specified by an A.B format, where A is the
number of bits to the left of the decimal point and B is the
number of bits to the right of the decimal point. In a twos
complement system, there is also an implied offset of one-half of
the binary range; for example, in a twos complement 1.23 system, the legal signal range is –1.0 to (+1.0 – 1 LSB).
A digital clipper circuit is used between the output of the DSP
core and the input to the DAC Σ-∆ modulators to prevent overloading the DAC circuitry (see Figure 4). Note that there is a
gain factor of 0.75 used in the DAC interpolation filters, and
therefore signal values of up to 1/0.75 will pass through the DSP
without clipping. Since the DAC is designed to produce an
analog output of 2 V rms (differential) with a 0 dB digital input,
signals between 0 dB and 1/0.75 (approximately 3 dB) will produce
larger analog outputs and result in slightly degraded analog performance. This extra analog range is necessary in order to pass 0
dBFS square waves through the system, as these square waves
cause overshoots in the interpolation filters that would otherwise
briefly clip the digital DAC circuitry.
The AD1953 uses two different numeric formats; one for the
coefficient values (stored in the parameter RAM) and one for
the signal data values. The coefficient format is as follows:
A separate digital clipper circuit is used in the DSP core to
ensure that any accumulator values that exceed the numeric
3.23 format range are clipped when taken from the accumulator.
Coefficient Format
High-Pass Filter
Each section of this flow diagram will be explained in detail on
the following pages.
Numeric Formats
The high-pass filter is a first-order double-precision design. The
purpose of the high-pass filter is to remove digital dc from the
input. If this dc were allowed to pass, the detectors used in the
compressor/limiter would give an incorrect reading for low
signal levels.
Coefficient format: 2.20
Range: –2.0 to (+2.0 – 1 LSB)
Examples:
1000000000000000000000 = –2.0
1100000000000000000000 = –1.0
1111111111111111111111 = (1 LSB below 0.0)
0000000000000000000000 = 0.0
0100000000000000000000 = 1.0
0111111111111111111111 = (2.0 – 1 LSB)
The high-pass filter is controlled by a single parameter
(alpha_HPF), which is programmed by writing to SPI location
180 in 2.20 twos complement format. The following equation
can be used to calculate the parameter Alpha_HPF from the –3 dB
point of the filter:
This format is used because standard biquad filters require
coefficients that range between +2.0 and –2.0. It also allows
gain to be inserted at various places in the signal path.
 –2.0 × π × HPF _ CUTOFF 
Alpha _ HPF = 1.0 – EXP 

fS


Internal DSP Signal Data Format
Input data format: 1.23
This is sign-extended when written to the data memory of the
AD1953.
where EXP is the exponential operator, HPF_CUTOFF is the
high-pass cutoff in Hz, and fS is the audio sampling rate.
The default value for the –3 dB cutoff of the high-pass filter is
2.75 Hz at a sampling rate of 44.1 kHz.
Internal DSP signal data format: 3.23
Range: –4.0 to (+4.0 – 1 LSB)
Examples:
10000000000000000000000000 = –4.0
11000000000000000000000000 = –2.0
11100000000000000000000000 = –1.0
11111111111111111111111111 = (1 LSB below 0.0)
00000000000000000000000000 = 0.0
00100000000000000000000000 = 1.0
01000000000000000000000000 = 2.0
01111111111111111111111111 = (4.0 – 1 LSB).
b0
b1
a1
Z–1
Z–1
b2
a2
Z–1
Z–1
The sign-extension between the serial port and the DSP core
allows for up to 12 dB of gain in the signal path without internal
clipping. Gains greater than 12 dB can be accommodated by
scaling the input down in the first biquad filter, and scaling the
signal back up at the end of the biquad filter section.
REV. 0
OUT
IN
Figure 5. Biquad Filter
Biquad Filters
Each of the two input channels has seven second-order biquad
sections in the signal path. In addition, the left and right channels have two additional biquad filters that may be used either
as crossover filters or as additional equalization filters. The sub
channel has three additional biquad filters, also to be used as
equalization and/or crossover filters. In a typical scenario, the
–13–
AD1953
first seven biquads would be used for speaker equalization and/
or tone controls, and the remaining filters would be programmed
to function as crossover filters. Note that there is a common
equalization section used for both the main and sub channels,
followed by crossover filters. This arrangement prevents any
interaction from occurring between the crossover filters and the
equalization filters. One section of the biquad IIR filter is shown
in Figure 5.
If gains larger than 12 dB cannot be avoided, then the coefficients b0 through b2 of the first biquad section may be scaled
down to fit the signal into the 12 dB maximum signal range, and
then scaled back up at the end of the filter chain.
Volume
This section implements the transfer function:
H (Z ) =
(b0 + b1 × Z
(1 − a1 × Z
–1
–1
)
)
+ b2 × Z –2
– a2 × Z
–2
The coefficients a1, a2, b0, b1, and b2 are all in twos complement 2.20 format with a range from –2 to (+2 – 1 LSB). The
negative sign on the a1 and a2 coefficients is the result of adding
both the feed-forward “b” terms as well as the feedback “a” terms.
Some digital filter packages automatically produce the correct
a1 and a2 coefficients for the topology of Figure 5, while others
assume a denominator of the form 1 + a1 × Z–1 + a2 × Z–1. In this
case, it may be necessary to invert the a1 and a2 terms for
proper operation.
The biquad structure shown in Figure 5 is coded using doubleprecision math to avoid limit cycles from occurring when low
frequency filters are used. The coefficients are programmed by
writing to the appropriate location in the parameter RAM through
the SPI port (see Table VI). There are two possible scenarios
for controlling the biquad filters:
1. Dynamic Adjustment (for example, Bass/Treble control or Parametric Equalizer)
When using dynamic filter adjustment, it is highly recommended
that the user employ the safeload mechanism to avoid temporary
instability when the filters are dynamically updated. This can
occur if some, but not all, of the coefficients are updated to new
values when the DSP calculates the filter output. The operation
of the Safeload registers is detailed in the Options for Parameter
Updates section.
Eight separate SPI registers are available to control the volume.
Three registers are used by the on-board program—one each for
the Left, Right, and Sub channels. These registers are special in
that they include automatic digital ramp circuitry for clickless
volume adjustment. The volume control word is in 2.20 format,
and gains from +2.0 to –2.0 are possible. The default value is
1.0. It takes 1024 audio frames to adjust the volume from 2.0
down to 0; in the normal case where the max volume is set to
1.0, it will take 512 audio frames for this ramp to reach zero.
Note that a Mute command is the same as setting the volume to
zero, except that when the part is unmuted, the volume returns to
its original value. These volume ramp times assume that the
AD1953 is set for the fast volume ramp speed. If the slow
setting is selected, it will take 8192 audio frames to reach zero
from a setting of 2.0. Correspondingly, it will take 4096 frames
to reach 0 volume from the normal setting of 1.0.
The volume blocks are placed after the biquad filter sections to
maximize the level of the signal that is passed through the filter
sections. In a typical situation, the nominal volume setting might be
–15 dB, allowing a substantial increase in volume when the user
increases the volume. The AD1953 was designed with an analog
dynamic range of > 112 dB, so that in the typical situation with
the volume set to –15 dB, the signal-to-noise ratio at the output
will still exceed 97 dB. Greater output dynamic ranges are possible
if the compressor/limiter is used, as the post-compression gain
parameter can boost the signal back up to a higher level. In this
case, the compressor will prevent the output from clipping when
the volume is turned up and the input signal is large.
Stereo Image Expander
The image-enhancement processing is based on ADI’s patented
Phat Stereo algorithm. The block diagram is shown in Figure 6.
LEFT OUT
LEFT IN
+
2. Setting Static EQ Curve after Power-Up
If many of the biquad filters need to be initialized after powerup (for example, to implement a static speaker-correction
curve), the recommended procedure is to set the processor
shutdown bit, wait for the volume to ramp down (about 20 ms),
and then write directly to the parameter RAM in Burst
Mode. After the RAM is loaded, the shutdown bit can be
deasserted, causing the volume to ramp back up to the initial
value. This entire procedure is click-free and faster than using
the Safeload mechanism.
The datapaths of the AD1953 contain an extra two bits on top
of the 24 bits that are input to the serial port. This allows up to
12 dB of boost without clipping. However, it is important to
remember that it is possible to design a filter that has less than
12 dB of gain at the final filter output, but more than 12 dB of
gain at the output of one or more intermediate biquad filter
sections. For this reason, it is important to cascade the filter
sections in the correct order, putting the sections with the
largest peak gains at the end of the chain rather than at the
beginning. This is standard practice when coding IIR filters and
is covered in basic books on DSP coding.
–
+
1kHz
FIRST-ORDER LPF
–
LEVEL
–
RIGHT IN
RIGHT OUT
Figure 6. Stereo Image Expander
The algorithm works by increasing the phase shift for low
frequency signals that are panned left or right in the stereo mix.
Since the ear is responsive to interaural phase shifts below 1 kHz,
this increase in phase shifts results in a widening of the stereo
image. Note that signals panned to the center are not processed,
resulting in a more natural sound. There are two parameters
that control the Phat Stereo algorithm: the Level variable,
which controls how much out-of-phase information is added to
the left and right channels, and the cutoff frequency of the
first-order low-pass filter, which determines the frequency range
of the added out-of-phase signals. For best results, the cutoff
frequency should be in the range of 500 Hz to 2 kHz. These
parameters are controlled by altering the parameter RAM locations
that store the parameters spread_level and alpha_spread.
–14–
REV. 0
AD1953
The spread_level is a linear number in 2.20 format that multiplies
the processed left-right signal before it is added to or subtracted
from the main channels. The parameter alpha_spread is related to
the cutoff frequency of the first-order low-pass filter by the equation
For example, if the input to a 2:1 compressor is increased by
2 dB, the output will rise by 1 dB for signals above the threshold.
A single “hard” threshold results in more audible behavior than
a so-called “soft-knee” compressor, where the compression is
introduced more gradually. In an analog compressor, the soft-knee
characteristic is usually made by using diodes in their exponential
turn-on region.
 –2.0 × π × spread _ freq 
Alpha _ spread = 1.0 – EXP 

fS


where EXP is the exponential operator, spread_freq is the low-pass
cutoff in Hz, and fS is the audio sampling rate.
VCA WITH EXP OUT
CONTROL
THRESHOLD
Note that the stereo spreading algorithm assumes that frequencies
below 1 kHz are present in the main satellite speakers. In some
systems, the crossover frequency between the satellite and
subwoofer speakers is quite high (> 500 Hz). In this case, the
stereo spreading algorithm will not be effective, as the frequencies
that contribute to the spreading effect will be coming mostly from
the subwoofer, which is a mono source.
FILTER
RMS DETECTOR
WITH dB OUT
SLOPE
COMPRESSION
CURVE NONLINEAR CIRCUITS
Figure 7. Analog Compressor
The best analog compressors use rms detection as the signal
amplitude detector. RMS detectors are the only class of detectors that are not sensitive to the phase of the harmonics in a
complex signal. The ear also bases its loudness judgment on the
overall signal power. Using an rms detector therefore results in
the best audible performance. Compressors that are based on
peak detection, while good for preventing clipping, are generally
quite poor when it comes to audible performance.
Delay
Each of the three DAC channels has a delay block that allows
the user to introduce a delay of up to 165 audio samples. The
delay values are programmed by entering the delay (in samples)
into the appropriate location of the parameter RAM. With a
44.1 kHz sample rate, a delay of 165 samples corresponds to a
time delay of 3.74 ms. Since sound travels at approximately
1 foot/ms, this can be used to compensate for speaker placements that are off by as much as 3.74 feet.
RMS detectors have a certain time constant that determines
how rapidly they can respond to transient signals. There is always
a trade-off between speed of response and distortion. Figure 8
shows this trade-off.
An additional 100 samples of delay are used in the look-ahead
portion of the compressor/limiter, but only for the main two
channels. This can be used to increase the total delay for the left
and right channels to 265 samples, or 6 ms at 44.1 kHz.
INPUT WAVEFORM
Main Compressor/Limiter
The compressor used in the AD1953 is quite sophisticated and
is comparable in many ways to professional compressor/limiters
used in the professional audio and broadcast fields. It uses rms/
peak detection with adjustable attack/hold/release, look-ahead
compression, and table-based entry of the input/output curve for
complete flexibility.
The AD1953 uses two compressor/limiters, one in the subwoofer
DAC and one in the main left/right DAC. It is well known that
having independent compressors operating over different frequency
ranges results in a superior perceived sound. With a single-band
compressor, loud bass information will modulate the gain of the
entire audio signal, resulting in suboptimal maximum perceived
loudness as well as gain pumping or modulation effects. With
independent compressors operating separately on the low and
high frequencies, this problem is dramatically reduced. If the
AD1953 is being operated in 2-channel mode, an extra path is
added so that the subwoofer channel can be added back into the
main channel. This maintains the advantage of using a 2-band
compressor, even in a 2.0 system configuration.
Figure 7 shows the traditional basic analog compressor/limiter.
It uses a voltage controlled amplifier to adjust gain and a feedforward detector path using an rms detector with adjustable
time constants, followed by a nonlinear circuit to implement the
desired input/output relationship. A simple compressor will have
a single threshold above which the gain is reduced. The amount
of compression above the threshold is called the compression
ratio and is defined as dB change in input/dB change in output.
REV. 0
COMPRESSOR ENVELOPE –
FAST TIME CONSTANT
COMPRESSOR ENVELOPE –
SLOW TIME CONSTANT
Figure 8. Effect of RMS Time Constant on Distortion
In the case of a fast-responding rms detector, the detector envelope will have a signal component in addition to the desired dc
component. This signal component (which, for an rms detector,
is at twice the input frequency) will result in harmonic distortion
when multiplied by this detector signal.
The AD1953 uses a modified rms algorithm to improve the
relationship between acquisition time and distortion. It uses a
peak-riding circuit together with a hold circuit to modify the rms
signal, as shown in Figure 9. Figure 8 shows two envelopes—one
with the harmonic distortion and another, flatter envelope,
which is produced by the AD1953.
–15–
AD1953
OUTPUT LEVEL – dB
INPUT WAVEFORM
HOLD TIME, SPIPROGRAMMABLE
DESIRED
COMPRESSION
CURVE
RELEASE TIME, SPIPROGRAMMABLE
INPUT LEVEL – 3dB/TABLE ENTRY
1.0
Figure 9. Using the Hold and Release Time Feature
The detector path of the AD1953 is shown in Figure 10. The rms
detector is controlled by three parameters stored in parameter
RAM: the rms time constant, the hold time, and the release rate.
The log output of the rms detector is applied to a look-up table
with interpolation. The higher bits of the rms output form an
offset into this table, and the lower bits are used to interpolate
between the table entries to form a high precision gain word.
The look-up table resides in the parameter RAM and is loaded
by the user to give the desired curve. The look-up table contains
33 data locations, and the LSB of the address into the look-up
table corresponds to a 3 dB change in the amplitude of the detector signal. This gives the user the ability to program an input/
output curve over a 99 dB range. For the main compressor, the
table resides in locations 110 to 142 in the SPI parameter RAM.
HIGH BITS (1LSB = 3dB)
MODIFIED RMS
DETECTOR WITH
LOG OUTPUT
LOOK-UP TABLE
LINEAR
INTERPOLATION
OUTPUT TO
GAIN STAGE
LOW BITS
TIME
HOLD RELEASE
CONSTANT
LINEAR GAIN
Using this idea of a modified rms algorithm, the true rms value
is still obtained for all but the lowest frequency signals, while the
distortion due to rms ripple is reduced. It also allows the user to
set the hold and release times of the compressor independently.
INPUT LEVEL – 3dB/TABLE ENTRY
Figure 11. Example of Table Entry for a Given
Compression Curve
Note that the maximum gain that can be entered in the table is 2.0
(minus 1 LSB). If more gain is required, the entire compression
curve may be shifted upward by using the post-compression gain
block following the compressor/limiter.
The AD1953 compressor/limiter also includes a look-ahead
compression feature. The idea behind look-ahead compression
is to prevent compressor overshoots by applying some digital
delay to the signal before the gain-control multiplier, but not to
the detector path. In this way, the detector can acquire the new
amplitude of the input signal before the signal actually reaches
the multiplier. A comparison of a tone burst fed to a conventional
compressor versus a look-ahead compressor is shown in Figure 12.
CONVENTIONAL COMPRESSOR GAIN
Figure 10. Gain Derived from Interpolated Look-Up Table
One subtlety of the table look-up involves the difference between
the rms value of a sine wave and that of a square wave. If a
full-scale square wave is applied to the AD1953, the rms value of
this signal will be 3 dB higher than the rms value of a 0 dBFS sine
wave. Therefore, the table will range from +9 dB (location 142)
to –87 dB (location 110).
The entries in the table are linear gain words in 2.20 format.
Figure 11 shows an example of the table entries for a simple
above-threshold compressor.
LOOK-AHEAD COMPRESSOR GAIN
HOLD TIME
Figure 12. Conventional Compression vs. Look-Ahead
Compression
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REV. 0
AD1953
In the look-ahead compressor, the gain has already been reduced
by the time the tone-burst signal arrives at the multiplier input.
Note that when using a look-ahead compressor, it is important to set the detector hold time to a value that is at least the
same as the look-ahead delay time, or else the compressor
release will start too soon, resulting in an expanded “tail” of a
tone burst signal. The complete flow of the left/right dynamics
processor is shown in Figure 13.
fS = audio sample rate
Hold_time = absolute time to wait before starting the release
ramp-down of the detector output
int() = integer part of expression
RMS Release Rate
rms _ decay _ parameter = int(rms _ decay / 1 .096)
Where rms_decay_parameter = decimal integer number to enter
into the SPI RAM
DELAY
SPI-PROGRAMMABLE
LOOK-AHEAD DELAY
POST-COMPRESSION
GAIN, SPIPROGRAMMABLE
UP TO 30dB
DELAY
rms_decay = decay rate in dB/sec
int() = integer part of expression
Look-Ahead Delay
(L+R)
2
Lookahead _ delay _ parameter = Lookahead _ delay × fS
HIGH BITS (1LSB = 3dB)
MODIFIED RMS
DETECTOR WITH
LOG OUTPUT
LOOK-UP
TABLE
LINEAR
INTERPOLATION
Where Lookahead_delay = predictive compressor delay in absolute time
fS = audio sample rate
LOW BITS
TIME
HOLD RELEASE
CONSTANT
The maximum Lookahead_delay_parameter value is 100.
Figure 13. Complete Dynamics Flow, Main Channels
The detector path works from a sum of left and right channels
((L+R)/2). This is the normal way that compressors are built,
and it counts on the fact that the main instruments in any stereo
mix are seldom recorded deliberately out of phase, especially in
the lower frequencies, which tend to dominate the energy spectrum
of real music.
The compressor is followed by a block known as post-compression
gain. Most compressors are used to reduce the dynamic range of
music by lowering the gain during loud signal passages. This
results in an overall loss of volume. This loss can be made up by
introducing gain after the compressor. In the AD1953, the
coefficient format used is 2.20, which has a maximum floatingpoint representation of slightly less than 2.0. This means the
maximum gain that can be achieved in a single instruction is 6 dB.
To get more gain, the program in the AD1953 uses a cascade
of five multipliers to achieve up to 30 dB of post-compression gain.
To program the compressor/limiter, the following formulas may
be used to determine the 22-bit numbers (in 2.20 format) to be
entered into the parameter RAM.
Post-Compression Gain
Post _ compression _ gain _ parameter =
Post _ compression _ gain _ linear ∧ (1 5)
Where Post_compression gain_linear is the linear post-compression
gain
^ = raise to the power
Subwoofer Compressor/Limiter
The subwoofer compressor/limiter differs from the left/right
compressor in the following ways:
1. The subwoofer compressor operates on a weighted sum of left
and right inputs (aa × Left + bb × Right), where aa and bb are
both programmable.
2. The detector input has a biquad filter in series with the input
in order to implement frequency-dependent compression
thresholds.
3. There is no predictive compression, as presumably the input
signals are filtered to pass only low frequencies, and therefore
transient overshoots are not a problem.
The subwoofer compressor signal flow is shown in Figure 14.
RMS Time Constant
This can be best expressed by entering the time constant in
terms of dB/sec “raw” release rate (without the peak-riding circuit).
The attack rate is a rather complicated formula that depends on
the change in amplitude of the input sine wave.
VIN_SUB = K1 LEFT_IN + K2 RIGHT_IN
HIGH BITS (1LSB = 3dB)
 release rate 
 10.0 × f 
S 
rms _ tconst _ parameter = 1.0 – 10
BIQUAD
FILTER
where
rms_tconst_parameter = fractional number to enter into the
SPI RAM (after converting to 22-bit 2.20 format)
release_rate = release rate of the raw rms detector in dB/sec. This
must be negative. fS = audio sampling rate.
RMS Hold Time
rms _ holdtime _ parameter = int( fS × hold _ time)
where
rms_holdtime_parameter = integer number to enter into the SPI RAM
REV. 0
MODIFIED RMS
DETECTOR WITH
LOG OUTPUT
LOOK-UP
TABLE
POST-COMPRESSION
GAIN, SPIPROGRAMMABLE
UP TO 30dB
LINEAR
INTERPOLATION
LOW BITS
TIME
HOLD RELEASE
CONSTANT
Figure 14. Signal Flow for Subwoofer Compressor
The biquad filter before the detector can be used to implement
a frequency-dependent compression threshold. For example,
assume that the overload point of the woofer is strongly frequency-dependent. In this case, one would have to set the
compressor threshold to a value that corresponded to the most
sensitive overload frequency of the woofer. If the input signal
happened to be mostly in a frequency range where the woofer
–17–
AD1953
BIQUAD RESPONSE
WOOFER EXCURSION
was not so sensitive to overload, then the compressor would be
too pessimistic and the volume of the woofer would be reduced.
If, on the other hand, the biquad filter were designed to follow
the woofer excursion curve of the speaker, then the volume of
the woofer could be maximized under all conditions. This is
illustrated in Figure 15.
20Hz
FREQ
200Hz
20Hz
200Hz
FREQ
Figure 15. Optimizing Woofer Loudness Using the
Subwoofer RMS Biquad Filter
When using a filter in front of the detector, a confusing sideeffect occurs. If one measures the frequency response by using a
swept sine wave with an amplitude large enough to be above the
compressor threshold, the resulting frequency response will not
look flat. However, this is not real in the sense that, as the sine
wave is swept through the system, the gain is being slowly
modulated up and down according to the response of the biquad
filter in front of the detector. If one measures the response using a
pink-noise generator, the result will look much better, as the
detector will settle on only one gain value. The perceptual effect
of the swept-sine-wave test is not at all what would be predicted by simply looking at the frequency response curve; it is
only the signal-path filters that will affect the perception of frequency response, not the detector-path filters.
De-emphasis Filtering
The standard for encoding CDs allows the use of a pre-emphasis
curve during encoding, which must be compensated for by a
de-emphasis curve during playback. The de-emphasis curve is
defined as a first-order shelving filter with a single pole at
(1/(2 × π × 50 µs)) followed by a single zero at (1/(2 × π × 15 µs)).
This curve may be accurately modeled using a first-order digital
filter. This filter is included in the AD1953; it is not part of the
bank of biquad filters, and so does not take away from the number of available filters.
Since the specification of the de-emphasis filter is based on an
analog filter, the response of the filter should not depend on the
incoming sampling rate. However, when the de-emphasis filter is
implemented digitally, the response will scale with the sampling rate
unless the filter coefficients are altered to suit each possible input
sampling rate. For this reason, the AD1953 includes three separate
de-emphasis curves; one each for sampling rates of 32 kHz, 44.1 kHz,
and 48 kHz. These curves are selected by writing to Bits <5:4> of
Control Register 1 over the SPI port.
Using the Sub Reinjection Paths for Systems with No Subwoofer
Many systems will not use a subwoofer, but would still benefit
from 2-band compression/limiting. This can be accommodated
by using sub reinjection paths in the program flow. These
parameters are programmed by entering two numbers (in 2.20
format) into the parameter RAM. Note that if the biquad filters
are not properly designed, the frequency response at the crossover point may not be flat. Many crossover filters are designed to
be flat in the sense of adding the powers together, but nonflat if
the sum is done in voltage mode. The user must take care to
design an appropriate set of crossover filters.
Interpolation Filters
The left and right channels have a 128:1 interpolation filter
with 70 dB stop-band attenuation that precedes the digital Σ-∆
modulator. This filter has a group delay of approximately 24.185/fS,
where fS is the sampling rate. The sub channel does not use an
interpolation filter. The reason for this (besides saving valuable
MIPS) is that it is expected that the bandwidth of the sub output
will be limited to less than 1 kHz. With no interpolation filter, the
first “image” will therefore be at 43.1 kHz (which is fS – 1 kHz,
for CD audio). The standard external filter used for both the
main and sub channels is a third-order, single op amp filter. If
the cutoff frequency of the external subwoofer filter is 2 kHz,
then there are more than four octaves between 2 kHz and the
first image at 43.1 kHz. A third-order filter will roll off by
approximately 18 dB/oct × 4 octaves = 72 dB attenuation. This is
approximately the same as the digital attenuation used in the main
channel filters, so no internal interpolation filter is required to remove
the out-of-band images.
Note that by having interpolation filters in the main channels but
not the subwoofer channel, there is a potential time-delay mismatch between the main and sub channels. The group delay of
the digital interpolation filters used in the main left/right channels
is about 0.5 ms. This must be compared to the group delay of
the external analog filter used in the subwoofer path. If the
group delay mismatch causes a frequency response error (when the
two signals are “acoustically added”), the programmable delay
feature can be used to put extra delay in either the subwoofer path
or the main left/right path.
SPI PORT
Overview
The AD1953 has many different control options. Most signalprocessing parameters are controlled by writing new values to
the parameter RAM using the SPI port. Other functions such as
volume and de-emphasis filtering are programmed by writing to
SPI control registers.
The SPI port uses a 4-wire interface, consisting of CLATCH,
CCLK, CDATA, and COUT signals. The CLATCH signal
goes LOW at the beginning of a transaction and HIGH at the
end of a transaction. The CCLK signal latches the serial input
data on a low-to-high transition. The CDATA signal carries the
serial input data, and the COUT signal is the serial output data.
The COUT signal remains three-stated until a read operation is
requested. This allows other SPI compatible peripherals to
share the same readback line.
The SPI port is capable of full read/write operation for all of the
memories (parameter and program) and some of the SPI registers
(Control Register 1 and data capture registers). The memories
may be accessed in both a single-address mode or in burst mode.
All SPI transactions follow the same basic format, shown in Table I.
The Wb/R bit is low for a write, and high for a read operation.
The 10-bit address word is decoded into a location in one of the
two memories (parameter or program) or one of the SPI registers. The number of data bytes varies according to the register
or memory being accessed. In burst-write mode (available for
loading the RAMs only), an initial address is given followed by a
continuous sequence of data for consecutive RAM locations.
–18–
REV. 0
AD1953
The detailed data format diagram for continuous-mode operation is given in SPI Read/Write data formats.
A sample timing diagram for a single SPI WRITE operation to
the parameter RAM is shown in Figure 16.
Table I. SPI Word Format
Byte 0
Byte 1
Byte 2 Byte 3 Byte 4
00000, R/Wb, adr[9:8] Adr[7:0]
Data
Data
Data
A sample timing diagram of a single SPI READ operation is
shown in Figure 17. The COUT pin goes from three-state to
driven at the beginning of Byte 2. Bytes 0 and 1 contain the
address and R/W bit, and Bytes 2 to 4 carry the data. The exact
format is shown in Tables VIII to XIX.
The AD1953 has several mechanisms for updating signalprocessing parameters in real time without causing loud pops or
clicks. In cases where large blocks of data need to be downloaded,
the DSP core can be shut down and new data loaded, and the
core can then be restarted. The shutdown and restart mechanisms employ a gradual volume ramp to prevent clicks and pops.
In cases where only a few parameters need to be changed (for
example, a single biquad filter), a safeload mechanism is used
that allows a block of SPI registers to be transferred to the
parameter RAM within a single audio frame while the core is
running. The safeload mode uses internal logic to prevent contention between the DSP core and the SPI port.
SPI Address Decoding
Table II shows the address decoding used in the SPI port. The
SPI address space encompasses a set of registers and two RAMs,
one for holding signal-processing parameters and one for holding
the program instructions. Both of the RAMs are loaded on
power-up from on-board boot ROMs.
CLATCH
CCLK
BYTE 4
BYTE 1
BYTE 0
CDATA
Figure 16. Sample of SPI WRITE Format (Single-Write Mode)
CLATCH
CCLK
CDATA
COUT
XXX
BYTE 1
BYTE 0
HI-Z
DATA
DATA
Figure 17. Sample of SPI READ Format (Single-Read Mode)
REV. 0
–19–
DATA
HI-Z
AD1953
Table II. SPI Port Address Decoding
SPI Address
Register Name
Read/Write Word Length
0–255
Parameter RAM
256
SPI Control Register 1
257
SPI Control Register 2
258
Volume 0
259
Volume 1
260
Volume 2
261
Volume 3
262
Volume 4
263
Volume 5
264
Volume 6
265
Volume 7
266
Data Capture (SPI Out) #1
267
Data Capture (SPI Out) #2
268
Data Capture (Serial Out) Slot 0
269
Data Capture (Serial Out) Slot 1
270
Data Capture (Serial Out) Slot 2
271
Data Capture (Serial Out) Slot 3
272
Data Capture (Serial Out) Slot 4
273
Data Capture (Serial Out) Slot 5
274
Parameter RAM Safeload Register 0
275
Parameter RAM Safeload Register 1
276
Parameter RAM Safeload Register 2
277
Parameter RAM Safeload Register 3
278
Parameter RAM Safeload Register 4
Write: 22 Bits
Read: 22 Bits
Write: 14 Bits
Read: 2 Bits
Write: 10 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: 24 Bits
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: 24 Bits
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
279–510
511
Unused
Test Register
512–1024
Program RAM
Write: 8 Bits
Read: N/A
Write: 35 Bits
Read: 35 Bits
–20–
REV. 0
AD1953
Control Register 1
Table III. Control Register 1 Write Definition
Control Register 1 is a 14-bit register that controls data capture
modes, serial modes, de-emphasis, mute, power-down, and
SPI-to-memory transfers. Table III documents the contents of
this register. Table IV details the two bits in the register’s
read operation.
Bits <1:0> set the wordlength, which is used in right-justified
serial modes to determine where the MSB is located relative to
the start of the audio frame.
Register Bits
Function
13:12
Data Capture Serial Out Mode Control
00 = none
01 = TDM 6-channel out, uses Pins 41–43
10 = 2-channel out, uses Pin 45
11 = Unused
Unused
Halt Program (1 = Halt)
Initiate Safe Transfer (1 = Transfer)
Unused
Soft Mute (1 = Start Mute Sequence)
Soft Power-Down (1 = Power Down)
De-emphasis Curve Select
00 = none
01 = 44.1 kHz
10 = 32 kHz
11 = 48 kHz
Serial In Mode
00 = I2S
01 = Right-Justified
10 = DSP
11 = Left-Justified
Word Length
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
11
10
9
8
7
6
5:4
Bits <3:2> select one of four serial modes, which are discussed
in the Serial Data Input Port section.
The de-emphasis curve selection Bits <5:4> turn on the internal
de-emphasis filter for one of three possible sample rates.
Bit <6>, the soft power-down bit, stops the internal clocks to
the DSP core, but does not reset the part. The digital power
consumption is reduced to a low level when this bit is asserted.
Reset can only be asserted using the external reset pin.
Soft mute (Bit <7>) is used to initiate a volume ramp-down
sequence. If the initial volume was set to 1.0, this operation will
take 512 audio frames to complete. When this bit is deasserted,
a ramp-up sequence is initiated until the volume returns to its
original setting.
3:2
The initiate-safe-transfer Bit <9> will request a data transfer
from the SPI safeload registers to the parameter RAM. The
safeload registers contain address-data pairs, and only those
registers that have been written to since the last transfer operation will be uploaded. The user may poll for this operation being
complete by reading Bit <0> of Control Register 1. The Safeload
Mechanism section goes into more detail on this feature.
1:0
Bit <10>, the halt program bit, is used to initiate a volume
ramp-down followed by a shutdown of the DSP core. The user
may poll for this operation being complete by reading Bit <1>
of Control Register 1.
The Data Capture Serial Out mode is controlled with Bits
<13:12>. This function can be used to send data that is captured using the data-capture feature to external devices such as
an external stereo DAC or multichannel codec. The Data Capture Registers and Outputs section gives more information about
the TDM and data capture features.
REV. 0
–21–
AD1953
Table IV. Control Register 1 READ Definition
Register Bits
Function
1
DSP Core Shutdown Complete
1 = Shutdown Complete
0 = Not Shut Down
Safe Memory Load Complete
1 = Complete (Note: Cleared after Read)
0 = Not Complete
0
Bit 0 is asserted when all requested safeload registers have been
transferred to the parameter RAM. It is cleared after the read
operation is complete.
Bit 1 is asserted after the requested shutdown of the DSP is
completed. When this bit is set, the user is free to write or read
any RAM location without causing an audio pop or click.
Table V. Control Register 2 WRITE Definition
Register Bits
Function
9
Volume Ramp Speed
1 = 160 ms Full-Ramp Time
0 = 20 ms Full-Ramp Time
Serial Port Output Enable
1 = Enabled
0 = Disabled
Serial Port Input Select
00 = IN0
01 = IN1
10 = IN2
11 = NA
MCLK Input Select
00 = MCLK0
01 = MCLK1
10 = MCLK2
11 = NA
Reserved
MCLK In Frequency Select
0 = 512 × fS
1 = 256 × fS
MCLK Out Frequency Select
00 Disabled
01 512 × fS
10 256 × fS
11 MCLKO = MCLK_In (Feedthrough)
8
7:6
5:4
3
2
1:0
Control Register 2
Table V documents the contents of Control Register 2. Bits
<1:0> set the frequency of the MCLKO pin. If these bits are set
to 00, the MCLKO pin is disabled (default). When set to 01,
the MCLKO pin is set to 512 × fS, which is the same as the
internal master clock used by the DSP core. When set to 10,
this pin is set to 256 × fS, derived by dividing the internal DSP
clock by 2. In this mode, the output 256 × fS clock will be inverted
with respect to the input 256 × fS clock. This is not the case with
the feedthrough mode. When set to 11, the MCLKO pin mirrors
the selected MCLK input pin (it’s the output of the MCLK
MUX selector). Note that the internal DSP master clock may
either be the same as the selected MCLK pin (when MCLK
frequency select is set to 512 × fS mode) or may be derived from
the MCLK pin using internal clock doubler (when MCLK frequency select is set to 256 × fS).
Bit <2> selects one of two possible MCLK input frequencies. When
set to 0 (default), the MCLK frequency is set to 512 × fS. In this mode,
the internal DSP clock and the external MCLK are at the same
frequency. When set to 1, the MCLK frequency is set to 256 × fS, and
an internal clock doubler is used to generate the DSP clock.
Bits <5:4> select one of three clock input sources using an internal MUX. To avoid click and pop noises when switching MCLK
sources, it is recommended that the user put the DSP core in
shutdown before switching MCLK sources.
Bits <7:6> select one of three serial input sources using an internal MUX. Each source selection includes a separate SDATA,
LRCLK, and BCLK input. To avoid click and pop noises when
switching serial sources, it is recommended that the user put the
DSP core in shutdown before writing to these bits.
Bit <8> is used to enable the three serial output pins. These pins
are connected to the output of the serial input MUX, which is set
by Bits <7:6>. The default is 0 (disabled).
Bit <9> changes the default setting of the volume ramp speed.
When set to 0, it will take 1024 LRCLK periods to go from full
volume (6 dB) to infinite attention. When set to 1, the same
operation will take 8192 LRCLK periods.
–22–
REV. 0
AD1953
Volume Registers
The AD1953 contains eight 22-bit volume registers, one each
for the left, right, and subwoofer channels and an additional five
registers to be used by custom programs used in multichannel
applications. These registers are special because when the volume
is changed from an initial value to a new value, a linear ramp is
used to interpolate between the two values. This feature prevents
audible clicks and pops when changing volume. The ramp is
set so that it takes 512 audio frames to decrement from a volume of
1.0 (default) down to 0 (muted). The volume registers are formatted in 2.20 twos complement, meaning that 010000000
0000000000000 is interpreted as 1.0. Negative values can also be
written to the volume register, causing an inversion of the signal.
Negative values work as expected with the ramp feature; to go
from +1.0 to –1.0 will take 1024 LRCLKs, and the volume will
pass through 0 on the way.
Parameter RAM Contents
Table VI shows the contents of the parameter RAM. The
parameter RAM is 22 bits wide and occupies SPI addresses
0–255. The low addresses of the RAM are used to control the
biquad filters. There are 22 biquad filters in all, and each
biquad has five coefficients, resulting in a total memory usage
of 110 coefficients. There are also two tables of 33 coefficients
each that define the main and sub compressor input/output
characteristics. These are loaded with 1.0 on power-up, resulting
in no compression. Other RAM entries control other compressor
characteristics, as well as delay and spatialization settings.
The parameter RAM is initialized on power-up by an on-board
boot ROM. The default values (shown in the table) yield no
equalization, no compression, no spatialization, no delay, and
“normal” detector time constants in the compressor sections.
The functionality of the AD1953 on power-up is basically that
of a normal audio DAC with no signal-processing capability.
The data format of the Parameter RAM is twos complement
2.20 format. This means that the coefficients may range from
+2.0 (–1 LSB) to –2.0, with 1.0 represented by the binary word
0100000000000000000000.
Table VI. Parameter RAM Contents
Address
Function
Default Value
in Fractional
2.20 Format
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
IIR0 Left b0
IIR0 Left b1
IIR0 Left b2
IIR0 Left a1
IIR0 Left a2
IIR1 Left b0
IIR1 Left b1
IIR1 Left b2
IIR1 Left a1
IIR1 Left a2
IIR2 Left b0
IIR2 Left b1
IIR2 Left b2
IIR2 Left a1
IIR2 Left a2
IIR3 Left b0
IIR3 Left b1
IIR3 Left b2
IIR3 Left a1
IIR3 Left a2
IIR4 Left b0
IIR4 Left b1
IIR4 Left b2
IIR4 Left a1
IIR4 Left a2
IIR5 Left b0
IIR5 Left b1
IIR5 Left b2
IIR5 Left a1
IIR5 Left a2
IIR6 Left b0
IIR6 Left b1
IIR6 Left b2
IIR6 Left a1
IIR6 Left a2
IIR0 Right b0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
REV. 0
Table VI. Parameter RAM Contents (continued)
Address
Function
Default Value
in Fractional
2.20 Format
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
IIR0 Right b1
IIR0 Right b2
IIR0 Right a1
IIR0 Right a2
IIR1 Right b0
IIR1 Right b1
IIR1 Right b2
IIR1 Right a1
IIR1 Right a2
IIR2 Right b0
IIR2 Right b1
IIR2 Right b2
IIR2 Right a1
IIR2 Right a2
IIR3 Right b0
IIR3 Right b1
IIR3 Right b2
IIR3 Right a1
IIR3 Right a2
IIR4 Right b0
IIR4 Right b1
IIR4 Right b2
IIR4 Right a1
IIR4 Right a2
IIR5 Right b0
IIR5 Right b1
IIR5 Right b2
IIR5 Right a1
IIR5 Right a2
IIR6 Right b0
IIR6 Right b1
IIR6 Right b2
IIR6 Right a1
IIR6 Right a2
IIR0 Xover Left b0
IIR0 Xover Left b1
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
–23–
AD1953
Table VI. Parameter RAM Contents (continued)
Table VI. Parameter RAM Contents (continued)
Default Value
in Fractional
2.20 Format
Address
Function
Default Value
in Fractional
2.20 Format
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
IIR0 Xover Left b2
IIR0 Xover Left a1
IIR0 Xover Left a2
IIR1 Xover Left b0
IIR1 Xover Left b1
IIR1 Xover Left b2
IIR1 Xover Left a1
IIR1 Xover Left a2
IIR0 Xover Right b0
IIR0 Xover Right b1
IIR0 Xover Right b2
IIR0 Xover Right a1
IIR0 Xover Right a2
IIR1 Xover Right b0
IIR1 Xover Right b1
IIR1 Xover Right b2
IIR1 Xover Right a1
IIR1 Xover Right a2
IIR0 Xover Sub b0
IIR0 Xover Sub b1
IIR0 Xover Sub b2
IIR0 Xover Sub a1
IIR0 Xover Sub a2
IIR1 Xover Sub b0
IIR1 Xover Sub b1
IIR1 Xover Sub b2
IIR1 Xover Sub a1
IIR1 Xover Sub a2
IIR2 Xover Sub b0
IIR2 Xover Sub b1
IIR2 Xover Sub b2
IIR2 Xover Sub a1
IIR2 Xover Sub a2
IIR Sub rms b0
IIR Sub rms b1
IIR Sub rms b2
IIR Sub rms a1
IIR Sub rms a2
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
1.0
0
0
0
0
Address
Function
110–142
193
Main Compressor
Look-Up Table Base
Main Compressor
Attack/rms Time
Constant
Main Post-Compressor
Gain
Subwoofer Compressor
Look-Up Table Base
Sub Compressor
Attack/RMS Time
Constant
Post-Compressor
Gain (SUB)
High-Pass Filter
Cutoff Frequency
Main Compressor
Look-Ahead Delay
Delay Left
Delay Right
Delay Sub
Stereo Spreading
Coefficient
Stereo Spreading
Frequency Control
Subwoofer Reinjection
to Main Left
Subwoofer Reinjection
to Main Right
Subwoofer Channel
Input Gain from Left IN
Subwoofer Channel
Input Gain from Right IN
Main Detector Hold Time,
Samples (4095 MAX)
Sub Detector Hold Time,
Samples (4095 MAX)
Main Detector Decay Time
194
Sub Detector Decay Time
143
144
145–177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
1.0 (all)
5.75 ⫻ 10–4
(120 dB/sec)
1.0
1.0 (all)
5.75 ⫻ 10–4
(120 dB/sec)
1.0
3.92 ⫻ 10–4
0
0
0
0
0
0.112694
0.0
0.0
0.5
0.5
01
01
0x3FFFFF
(4.597 ⫻ 106 dB/sec)1, 2
0x3FFFFF
(4.597 ⫻ 106 dB/sec)1, 2
NOTES
1
The detector hold and decay times are integer values, while the rest of the parameters are fractional twos complement values.
2
The default decay time of the hold/release circuit is set fast enough that the decay is dominated by the time constant of the rms detector.
Options for Parameter Updates
The parameter and program RAMs can be written and read
using one of several methods.
1. Direct Read/Write. This method allows direct access to the
RAMs. Since the RAMs are also being used during real-time
DSP operation, a glitch will likely occur at the output. This
method is not recommended.
2. Direct Read/Write after Core Shutdown. This method avoids
the glitch while accessing the internal RAMs by first shutting
down the core. This is recommended for transferring large
amounts of data, such as initializing the parameter RAM at
power-up or downloading a completely new program. These
transfers can be sped up by using burst mode, where an
initial address followed by blocks of data are sent to the RAM.
3. Safeload Writes Up to five SPI registers are loaded with
address/data intended for the parameter RAM. The data is then
transferred to the requested address when the RAM is not busy.
This method can be used for dynamic updates while live
program material is playing through the AD1953. For example,
a complete update of one biquad section can occur in one
audio frame while the RAM is not busy. This method is not
available for writing to the program RAM or control registers.
The next section discusses these options in more detail.
–24–
REV. 0
AD1953
otherwise, the filter could execute for one or two audio frames
with a mixture of old and new coefficients. This mix of old and
new could cause temporary instability, leading to transients that
could take a long time to decay.
Soft Shutdown Mechanism
When writing large amounts of data to the program or parameter
RAM, the processor core should be halted to prevent unpleasant
noises from appearing at the audio output. Figure 18 shows a
graphical representation of this mechanism’s volume envelope.
Points A to D are referenced in the following description. Bit
<10> in serial Control Register 0 (processor shutdown bit) will
shut down the processor core. When the processor shutdown bit
is asserted (A), an automatic volume ramp-down sequence (B)
lasting from 10 ms to 20 ms will occur, followed by a shutdown
of the core. This method of shutting down the core prevents pops
or clicks from occurring. After the shutdown is complete, Bit
<1> in Control Register 1 will be set. The user can either poll
for this bit to be set, or just wait for a period longer than 20 ms.
The method used in the AD1953 to eliminate this problem is to
load a set of five registers in the SPI port with the desired parameter RAM address and data. Five registers are used because each
biquad filter has five coefficients. Once these registers are loaded,
the initiate safe transfer bit in SPI Control Register 1 is set.
Once this bit is set, the processor waits for a period of time in
the program sequence when the parameter RAM is not being
accessed for at least five consecutive instruction cycles. When
the program counter reaches this point, the parameter RAM is
written with five new data values at addresses corresponding to
those entered in the safeload registers. When the operation is
complete, Bit 0 of Control Register 1 is set. This bit may be
polled by the external microprocessor until a 1 is read. This bit
will be reset on a read operation. The polling operation is not
required; the safeload mechanism guarantees that the transfer
will be complete within one audio frame.
Once the core is shut down (C), the parameter or program RAMs
may be written or read freely. To ease the transfer of large blocks
of sequential data, a block transfer mode is supported where a
starting address followed by a stream of data is sent to the memory.
The address into the memory will be automatically incremented
for each new write. This mode is documented in the SPI Data
Format section of this data sheet.
The safeload logic automatically sends only those safeload registers that have been written to since the last safeload operation.
For example, if only two parameters are to be sent, it is only
necessary to write to two of the five safeload registers. When the
request safe transfer bit is asserted, only those two registers will
be sent; the other three registers are not sent, and can still hold
old or invalid data.
Once the data has been written, the shutdown bit can be cleared
(D). The processor then will initiate a volume ramp-up sequence
lasting 10 ms to 20 ms. Again, this reduces the chance that any
pop or click noise will occur.
Note that this shutdown sequence assumes the part is set to the
fast volume ramp speed (Control Register 2, Bit <9>). If the
slow ramp speed is set, the volume may not reach zero before
the part enters shutdown, and a click or pop may be heard.
The safeload mechanism is not limited to uploading biquad
coefficients; any set of five values in the parameter RAM may be
updated in the same way. This allows real-time adjustment of
the compressor/limiter, delay, or stereo spreading blocks.
Safeload Mechanism
Many applications require real-time control of filter characteristics,
such as bass/treble controls and parametric or graphic equalization. To prevent instability from occurring, all of the parameters
of a particular biquad filter must be updated at the same time;
A
Summary of RAM Modes
Table VII shows the sizes and available modes of the parameter
RAM and the program RAM.
C
B
D
Figure 18. Recommended Sequences for Complete Parameter or Program RAM Upload Using Shutdown Mechanism
Table VII. Read/Write Modes
Memory
Size
SPI Address Range
Read
Write
Burst Mode Available
Write Modes
Parameter RAM
256 × 22
0–255
Yes
Yes
Yes
Direct Write, Write after core
shutdown, safeload write
Program RAM
512 × 35
512–1023
Yes
Yes
Yes
Direct Write, Write after core
shutdown
REV. 0
–25–
AD1953
SPI READ/WRITE DATA FORMATS
(five bytes). These zero-extended data fields are appended to
a 2-byte field consisting of a read/write bit and a 10-bit address.
The SPI port knows how many data bytes to expect based on
the address that is received in the first two bytes.
The read/write formats of the SPI port are designed to be byteoriented. This allows for easy programming of common
microcontroller chips to fit into a byte-oriented format; 0s are
appended to the data fields to extend the data-word to the next
multiple of eight bits. For example, 22-bit words written to the
SPI parameter RAM are appended with two leading zeros to
reach 24 bits (three bytes), and 35-bit words written to the
program RAM are appended with five zeros to reach 40 bits
The total number of bytes for a single-location SPI write command
can vary from four bytes (for a control register write), to seven
bytes (for a program RAM write). Block writes may be used to
fill contiguous locations in program RAM or parameter RAM.
Table VIII. Parameter RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
00000, R/Wb, Adr[9:8]
Adr[7:0]
00, Param[21:16]
Param[15:8]
Param[7:0]
Table IX. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
00000, R/Wb, Adr[9:8]
Adr[7:0]
00, Param[21:16]
Param[15:8]
Param[7:0]
ADR
Byte 5 Byte 8
Byte 6 Byte 9
Byte 7 Byte 10
ADR + 1 ADR + 2
Table X. Program RAM Read/Write Format (Single Address)
Byte 0
Byte 1
00000, R/Wb, Adr[9:8] Adr[7:0]
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
00000, Prog[34:32]
Prog[31:24]
Prog[23:16]
Prog[15:8]
Prog[7:0]
Table XI. Program RAM Block Read/Write Format (Burst Mode)
Byte 7 Byte 12
Byte 8 Byte 13
Byte 0
Byte 1 Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 9 Byte 14
00000, R/Wb, Adr[9:8]Adr[7:0] 00000, Prog[34:32] Prog[31:24] Prog[23:16] Prog[15:8] Prog[7:0] Byte 10 Byte 15
Byte 11 Byte 16
ADR
ADR + 1 ADR + 2
Table XII. SPI Control Register 1 Write Format
Byte 0
Byte 1
Byte 2
Byte 3
00000, R/Wb, Adr[9:8]
Adr[7:0]
00, Bit[13:8]
Bit[7:0]
Table XIII. SPI Control Register 1 Read Format
Byte 0
Byte 1
Byte 2
00000, R/Wb, Adr[9:8]
Adr[7:0]
000000, Bit[1:0]
Table XIV. SPI Control Register 2 Write Format
Byte 0
Byte 1
Byte 2
Byte 3
00000, R/Wb, Adr[9:8]
Adr[7:0]
000000, Bit[9:8]
Bit[7:0]
Table XV. SPI Volume Register Write Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
000000, Adr[9:8]
Adr[7:0]
00, Volume[21:16]
Volume[15:8]
Volume[7:0]
–26–
REV. 0
AD1953
Table XVI. Data Capture Register Write Format
Byte 0
Byte 1
00000, R/Wb, Adr[9:8]
Byte 2
Adr[7:0]
Byte 3
1
ProgCount[5:0], RegSel[1:0]1, 2
00000, ProgCount[8:6]
NOTES
1. ProgCount[8:0] = value of program counter where trap occurs (see Table XXI).
2. RegSel[1:0] selects one of four registers (see Data Capture Register section).
Table XVII. Data_Capture_Serial Out Register (Address and Register Select) Write Format
Byte 0
Byte 1
00000, R/Wb, Adr[9:8]
Byte 2
Adr[7:0]
Byte 3
1
ProgCount[5:0], RegSel[1:0]1, 2
00000, ProgCount[8:6]
NOTES
1. ProgCount[8:0] = value of program counter where trap occurs (see Table XXI).
2. RegSel[1:0] selects one of four registers (see Data Capture Registers section).
Table XVIII. Data Capture Read Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
00000, R/Wb, Adr[9:8]
Adr[7:0]
00000000
Data[23:16]
Data[15:8]
Data[7:0]
Table XIX. Safeload Register Write Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
00000, R/Wb, Adr[9:8]
Adr[7:0]
ParamAdr[7:0]
00, Param[21:16]
Param[15:8]
Param[7:0]
INITIALIZATION
Power-Up Sequence
The AD1953 has a built-in power-up sequence that initializes
the contents of all internal RAMs. During this time, the contents
of the internal program boot ROM are copied to the internal
program RAM, and likewise the SPI parameter RAM is filled
with values from its associated boot ROM. The data memories
are also cleared during this time.
The boot sequence lasts for 1024 MCLK cycles and starts on
the rising edge of the RESETB pin. Since the boot sequence
requires a stable master clock, the user should avoid writing to
or reading from the SPI registers during this period of time.
Note that the default power-on state of the internal clock mode
circuitry is 512 × fS, or about 24 MHz for normal audio sample
rates. This mode bypasses all the internal clock doublers and
allows the external master clock to directly operate the DSP
core. If the external master clock is 256 × fS, the boot sequence will
operate at this reduced clock rate and take slightly longer to
complete. After the boot sequence has finished, the clock modes
may be set via the SPI port. For example, if the external master
clock frequency is 256 × fS clock, the boot sequence would
take 1024 256 × fS clock cycles to complete, after which an
SPI write could occur to put the AD1953 in 256 × fS mode.
The default state of the MCLK input selector is MCLK0. Since
this input selector is controlled using the SPI port, and the SPI
port cannot be written to until the boot sequence is complete,
there must be a stable master clock signal present on the MCLK0
pin at startup.
REV. 0
Setting the Clock Mode
The AD1953 contains a clock doubler circuit that is used to
generate an internal 512 × fS clock when the external clock is
256 × fS. The clock mode is set by writing to Bit <2> of Control
Register 2.
When the clock mode is changed, it is possible that a glitch will
occur on the internal MCLK signal. This may cause the processor to inadvertently write an incorrect value into the data RAM,
which could cause an audio pop or click sound. To prevent this,
it is recommended that the following procedure be followed:
1. Assert the soft power-down bit (Bit <6> in Control Register 1)
to stop the internal MCLK.
2. Write the desired clock mode into Bit <2> of Control Register 2.
3. Wait at least 1 ms while the clock doublers settle.
4. Deassert the soft power-down bit.
An alternative procedure is to initiate a soft shutdown of the
processor core by writing a 1 to the halt program bit in Control
Register 1. This initiates a volume ramp-down sequence followed
by a shutdown of the DSP core. Once the core is shut down
(which can be verified by reading Bit <1> from Control Register 1,
or by waiting at least 20 ms), the new clock mode can be
programmed by writing to Bit <2> of Control Register 2. The
DSP core can then be restarted by clearing the halt program bit
in Control Register 1.
–27–
AD1953
Setting the Data and MCLK Input Selectors
The AD1953 contains input selectors for both the serial data
inputs as well as the MCLK input. This allows the AD1953 to
select a variety of input and clock sources with no external hardware required. These input selectors are controlled by writing to
SPI Control Register 2.
When the DATA source or MCLK source is changed by writing
to the SPI port, it is possible that a pop or click will occur in the
audio. To prevent this noise, the core should be shut down by
writing a 1 to the “halt program” bit in Control Register 1. This
initiates a volume ramp-down sequence followed by a shutdown
of the DSP core. Once the core is shut down (which can be
verified by reading Bit <1> from Control Register 1, or by waiting at least 20 ms after the halt program command is issued),
the new DATA or MCLK source can be programmed by writing to Control Register 2. The DSP core can then be restarted
by clearing the “halt-program” bit in Control Register 1.
DATA CAPTURE REGISTERS AND OUTPUTS
The AD1953 incorporates a feature called “data capture.” Using
this feature, any node in the signal processing flow may be sent
either to an SPI-readable register, to a dedicated serial output
pin (2-channel output), or to a set of dual-function pins (6-channel
TDM mode). This allows the basic functionality of the AD1953
to be extended to a larger number of channels, or alternatively it
can be used to monitor and display information about signal
levels or compressor/limiter activity.
The AD1953 contains eight independent data capture registers.
The Data Capture SPI Out registers are used for reading back
internal DSP signals over the SPI port. These registers can be
used for a variety of purposes. One example might be to access
the dB output of the internal rms detector, to run a front-panel
signal level display.
The remaining data capture registers are used to output internal
DSP signals to external DACs, CODECs, or DSP chips. There
are two possible output modes, detailed in the following table.
Table XX. Data Capture/TDM Mode Settings
Control
Reg 1, Bits Control Reg
<13:12>
2, Bit <8>
DCSOUT
Pin (45)
Functions
00
00
01
OFF
OFF
OFF
10
10
0
1
Don’t care
0
1
ON, 2channel
output.
ON, 2channel
output.
DMUXO/TDMO,
LRMUXO/TDMFS,
BMUXO/TDMBC
Pin Functions
OFF
Serial MUX Output
TDM Data Capture
Outputs and Clocks,
6-channel Output
OFF
be formatted in the same way as the input data. The data capture feature is primarily intended to feed signals to external
DACs, DSPs, or CODECs, such as the AD1836, in order to
extend the number of channels that the internal DSP can access.
For each of the data capture registers, a capture count and a
register select must be set. The capture count is a number between
0 and 511 that corresponds to the program step number where
the capture will occur. The register-select field programs one of
four registers in the DSP core that will be transferred to the data
capture register when the program counter equals the capture
count. The register select field is decoded as follows:
00: Multiplier Output (Mult_Out)
01: Output of dB conversion block (DB_OUT)
10: Multiplier Data Input (MDI)
11: Multiplier Coefficient Input (MCI)
The capture count and register select bits are set by writing to
one of the four data capture registers at the following SPI addresses:
266: SPI data capture setup register 1
267: SPI data capture setup register 2
268: Data Capture serial out setup register 0
269: Data Capture serial out setup register 1
270: Data Capture serial out setup register 2
271: Data Capture serial out setup register 3
272: Data Capture serial out setup register 4
273: Data Capture serial out setup register 5
The format of the captured data varies according to the register
select fields. Data captured from the Mult_Out setting is in 1.23
twos complement format, so that a full-scale input signal will
produce a full-scale digital output (assuming no processing). If
the parameters are set such that the input-to-output gain is
more than 0 dB, then the digital output will be clipped.
Data captured from the DB_OUT setting is in 5.19 format,
where the actual rms dB level is equal to –87 + (3 × DB_OUT).
In this equation, DB_OUT is the value that is captured. It
follows that in this data format, the actual output readings will
range from –87 dB to +9 dB. The AD1953 uses the convention
that 0 dB is the rms value of the full-scale digital signal.
Data captured using the MDI setting is in 3.21 format. A 0 dB
digital input will produce a –12 dB digital output, assuming the
AD1953 is set for no processing.
Data captured using the MCI setting is in 2.20 format. This data
is generally a signal gain or filter coefficient, and therefore it does
not make sense to talk about the input-to-output gain. A coefficient of 0100000000000000000000 corresponds to a gain of 1.0.
The data that must be written to set up the data capture is a
concatenation of the 9-bit program count index with the 2-bit
register select field.
Serial MUX Output
In TDM output mode, the Serial Mux Out multifunction pins
(41–43) are used to output 6-channel TDM data, BCLK, and
frame sync signals. In 2-channel output mode, the data appears
on Pin 45, and can be used with the BCLK and LRCLK signals
that are already present on the serial input pins. The data will
The SPI capture registers can be accessed by reading from SPI
locations 266 (for SPI capture register 1) or 267 (for SPI capture
register 2). The other six data capture registers (data capture
serial-out) automatically transfer their data to either the Data
Capture Serial Out (DCSOUT) pin in 2-channel mode or the
DMUXO/TDMO pin in TDM mode. In 2-channel mode,
DCSOUT capture register 1 is present in the left data slot (as
defined by the serial input format) and DCSOUT capture register 2 is present in the right data slot.
–28–
REV. 0
AD1953
Table XXI. Data Capture Trap Indexes and Register Select
Signal Description
Program Count
Index (9 Bits)
Register Select (2 Bits)
Numeric Format
HPF Out Left
HPF Out Right
De-emphasis Out Left
De-emphasis Out Right
Left Biquad 0 Output
Left Biquad 1 Output
Left Biquad 2 Output
Left Biquad 3 Output
Left Biquad 4 Output
Left Biquad 5 Output
Left Biquad 6 Output
Right Biquad 0 Output
Right Biquad 1 Output
Right Biquad 2 Output
Right Biquad 3 Output
Right Biquad 4 Output
Right Biquad 5 Output
Right Biquad 6 Output
Volume Out Left
Volume Out Right
Volume Out Sub
Phat Stereo Out Left
Phat Stereo Out Right
Delay Output Left
Delay Output Right
Main Compressor rms Out (dB)
15
259
19
263
34
43
52
61
70
79
88
284
293
302
311
320
329
338
114
111
459
115
112
190
361
154
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
DB_Out
Main Compressor Gain Reduction
(Linear)
Look-Ahead Delay Output Left
Look-Ahead Delay Output Right
Main Compressor Out Left
Main Compressor Out Right
Interpolator Input Left
(includes SUB Reinject)
Interpolator Input Right
(includes SUB Reinject)
Sub Channel Filter Input
Sub XOVER Biquad 0 Output
Sub XOVER Biquad 1 Output
Sub XOVER Biquad 2 Output
Left XOVER Biquad 0 Output
Left XOVER Biquad 1 Output
Right XOVER Biquad 0 Output
Right XOVER Biquad 1 Output
Sub Delay Output
Sub rms Biquad Output
Sub rms Output (dB)
165
MCI
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
24-Bit Positive Binary, Bit <19>
Corresponds to a 3 dB Change
2.22, 2 LSB = 0
165
178
175
188
191
MDI
MDI
Mult_Out
Mult_Out
Mult_Out
3.21, 2 LSBs truncated
3.21, 2 LSBs truncated
1.23, Clipped
1.23, Clipped
1.23, Clipped
362
Mult_Out
1.23, Clipped
430
438
447
456
99
108
349
358
511
467
489
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
Mult_Out
DB_Out
495
511
MCI
Mult_Out
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
1.23, Clipped
24-Bit Positive Binary, Bit <19>
Corresponds to a 3 dB Change
2.22, 2 LSB = 0
1.23, Clipped
Sub Compressor Gain (Linear)
Sub Channel Output
REV. 0
–29–
AD1953
SERIAL DATA INPUT/OUTPUT PORTS
The AD1953’s flexible serial data input port accepts data in twos
complement, MSB first format. The left channel data field always
precedes the right channel data field. The serial mode is set by
using mode select bits in the SPI control register. In all modes
except for the right-justified mode, the serial port will accept an
arbitrary number of bits up to a limit of 24 (extra bits will not
cause an error, but they will be truncated internally). In the rightjustified mode, SPI control register bits are used to set the word
length to 16, 20, or 24 bits. The default on power-up is 24-bit mode.
Proper operation of the right-justified mode requires that there
be exactly 64 BCLK per audio frame.
Serial Data Input/Output Modes
Figure 19 shows the serial input modes. For the left-justified
mode, LRCLK is HIGH for the left channel, and LOW for the
right channel. Data is sampled on the rising edge of BCLK. The
LRCLK
MSB is left-justified to an LRCLK transition, with no MSB delay.
The left-justified mode can accept any word length up to 24 bits.
In I2S mode, LRCLK is low for the left channel and high for the
right channel. Data is valid on the rising edge of BCLK. The MSB
is left-justified to an LRCLK transition but with a single BCLK
period delay. The I2S mode can be used to accept any number
of bits up to 24.
In right-justified mode, LRCLK is high for the left channel and
low for the right channel. Data is sampled on the rising edge
of BCLK. The start of data is delayed from the LRCLK edge
by 16, 12, or 8 BCLK intervals, depending on the selected
word length. The default word length is 24 bits; other word
lengths are set by writing to Bits <1:0> of Control Register 1.
In right-justified mode, it is assumed that there are 64 BCLKs
per frame.
RIGHT CHANNEL
LEFT CHANNEL
BCLK
SDATA
MSB
MSB
LSB
LSB
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDATA
LSB
MSB
LSB
MSB
I2S MODE – 16 BITS TO 24 BITS PER CHANNEL
LRCLK
RIGHT CHANNEL
LEFT CHANNEL
BCLK
SDATA
LSB
MSB
MSB
LSB
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE – 16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOESN’T IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT fS EXCEPT DSP MODE, WHICH IS 2 fS
3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE
Figure 19. Serial Input Modes
–30–
REV. 0
AD1953
For the DSP serial port mode, LRCLK must pulse high for at
least one bit clock period before the MSB of the left channel is
valid, and LRCLK must pulse HIGH again for at least one bit
clock period before the MSB of the right channel is valid. Data
is sampled on the falling edge of BCLK. The DSP serial port
mode can be used with any word length up to 24 bits. In this
mode, it is the responsibility of the DSP to ensure that the left
data is transmitted with the first LRCLK pulse, and that synchronism is maintained from that point forward.
All current sources are derived from the VREF input pin. The
gain of the AD1953 is directly proportional to the magnitude of
the current sources, and therefore the gain of the AD1953 is
proportional to the voltage on the VREF pin. With VREF set to
2.5 V, the gain of the AD1953 is set to provide signal swings of
2 V rms differential (1 V rms from each pin). This is the recommended operating condition.
The TDM data capture output mode is shown in Figure 20.
Using this mode allows six channels of serial data to be sent to
an external DAC, allowing the potential for nine total audio
channels. The frame clock is low for the first 128 BCLKs (the
first three data channels), and is then high for the final 128
BCLKs. Each data slot, which is 32 BCLK periods wide, contains one data-word in an I2S-like format, with the MSB delayed
by one BCLK period. In this format, data is valid on the rising
edge of the BCLK.
IREF
OUT+
OUT–
VREF
IN
IREF + DIG_IN
FROM DIGITAL
- MODULATOR (DIG_IN)
SLOT 0
SLOT 1
SLOT 2
32BCLKs 32BCLKs 32BCLKs
SLOT 3
SLOT 4
SLOT 5
LRCLK
BCLK
MSB
MSB-1
MSB-2
DATA
Figure 20. TDM Data Capture Output Format
DIGITAL CONTROL PIN
Mute
The AD1953 offers two methods of muting the analog output.
By asserting the MUTE signal high, the left, right, and sub
channels are muted. As an alternative, the user can assert the
mute bit in the serial control register high. The AD1953 has
been designed to minimize pops and clicks when muting and
unmuting the device by automatically ramping the gain up or
down. When the device is unmuted, the volume returns to the
value set in the volume register.
ANALOG OUTPUT SECTION
Figure 21 shows the block diagram of the analog output section.
A series of current sources is controlled by a digital Σ-∆ modulator.
Depending on the digital code from the modulator, each current
source is connected to the summing junction of either a positive
I-to-V converter or a negative I-to-V converter. Two extra current
sources that push instead of pull are added to set the midscale
common-mode voltage.
REV. 0
SWITCHED CURRENT
SOURCES
Figure 21. Internal DAC Analog Architecture
256BCLKs
BMUXO/
TDMBC
DMUXO/
TDMO
IREF – DIG_IN
BIAS
LRMUXO/
TDMFS
32BCLKs 32BCLKs 32BCLKs
IREF
When the AD1953 is used to drive an audio power amplifier
and the compression feature is being used, the VREF voltage
should be derived by dividing down the supply of the amplifier.
This sets a fixed relationship between the digital signal level
(which is the only information available to the digital compressor)
and the full-scale output of the amplifier (just prior to the onset
of clipping). For example, if the amplifier power supply drops
by 10%, the VREF input to the amplifier will also drop by 10%,
which will reduce the analog output signal swing by 10%. The
compressor will therefore be effective in preventing clipping
regardless of any variation in amplifier supply voltage.
Since the VREF input effectively multiplies the signal, care must
be taken to ensure that no ac signals appear on this pin. This
can be accomplished by using a large decoupling capacitor in
the VREF external resistive divider circuit. If the VREF signal is
derived by dividing the 5 V analog supply, the time constant of
the divider must effectively filter any noise on the supply. If the
VREF signal is derived from an unregulated power-amplifier
supply, the time constant must be longer, as the ripple on the
amplifier supply voltage will presumably be greater than in the
case of the 5 V supply.
The AD1953 should be used with an external third-order filter
on each output channel. The circuits shown in Figures 22, 23,
and 24 combine a third-order filter and a single-ended-todifferential converter in the same circuit. The values used in the
main channel (Figure 22) are for a 100 kHz Bessel filter, and
those used in the subwoofer channel (Figure 23) result in a
10 kHz Bessel filter. The lower frequency filter is used on the
subwoofer output because there is no digital interpolation filter
used in the subwoofer signal path. When calculating the resistor
values for the filter, it is important to take into account the
output resistance of the AD1953, which is nominally 60 Ω.
For best distortion performance, 1% resistors should be used.
The reason for this is that the single-ended performance of the
AD1953 is about 80 dB. The degree to which the single-ended
distortion cancels in the final output is determined by the common-mode rejection of the external analog filter, which in turn
depends on the tolerance of the components used in the filter.
–31–
AD1953
The sub output of the AD1953 has a lower drive strength than
the left and right output pins (± 0.25 mA peak versus ± 0.5 mA
peak for the left and right outputs). For this reason, it is best to
use higher resistor values in the external sub filter. Figure 24
shows a recommended filter design for the subwoofer output
pins used as a full-bandwidth channel in a custom-designed
program. This design is also a 100 kHz Bessel filter.
For best performance, a large (> 10 µF) capacitor should be
connected between the FILTCAP pin and analog ground. This
pin is connected to an internal node in the bias generator, and
by adding an external capacitance to this pin, the thermal noise
of the left/right channels is minimized. The sub channel is not
affected by this connection.
GRAPHICAL CUSTOM PROGRAMMING TOOLS
Custom programming tools are available for the AD1953 from
ADI. These graphical tools allow the user to modify the default
signal processing flow by individually placing each block (e.g.,
biquad filter, Phat Stereo, dynamics processor) and connecting
them in any desired fashion. The program then creates a file
that is loaded into the AD1953’s program RAM. All of the
contents of the parameter RAM can also be set using these
tools. For more information on these programming tools, email
[email protected]
11k
3.01k
270nF
27nF
560nF
56nF
– INPUT
3.01k
2.80k
– INPUT
549
2.7nF
220nF
2.2nF
+ INPUT
5.62k
OUT
5.62k
1.5k
15nF
150pF
2.2nF
499
1.00k
604
OUT
1.50k
806
68pF
270pF
1nF
+ INPUT
6.8nF
11k
820pF
Figure 23. Recommended External Analog Filter for
Sub Channel
Figure 22. Recommended External Analog Filter for
Main Channels
11k
11k
– INPUT
68pF
3.01k
27nF
604
OUT
56nF
2.2nF
+ INPUT
5.62k
5.62k
1.5k
150pF
Figure 24. Recommended External Analog Filter for Full
Bandwidth Signals on the Sub Channel Output
–32–
REV. 0
AD1953
APPENDIX
Cookbook Formulae for Audio EQ Biquad Coefficients
(adapted from Robert Bristow-Johnson’s Internet posting)
For designing a Parametric EQ, follow the steps below.
1. Given:
Frequency
Q
dB_Gain
sample_rate
2. Compute Intermediate Variables
A = 10^(dB_Gain/40)
omega = 2 × π × Frequency/Sample_Rate
sn = sin(omega)
cs = cos(omega)
alpha = sn/(2 × Q)
3. Compute Coefficients
b0 = (1 + A × alpha)/(1 + (alpha/A))
b1 = –2 × cs/(1 + (alpha/A))
b2 = (1 – (alpha/A))/(1 + (alpha/A))
a1 = 2 × cs/(1 + (alpha/A)) = –b1
a2 = –(1 – (alpha/A))/(1 + (alpha/A))
4. The transfer function implemented by the AD1953 is given by:
H(Z) = (b0 + b1 × Z–1 + b2 × Z–2)/(1 – a1 × Z–1 – a2 × Z–2)
Note the inversion in sign of a1 and a2 relative to the more standard form. This form is used in this document because the AD1953
implements the difference equation using the formula below.
Y(n) = a1 × y(n – 1) + a2 × y(n – 2) + b0 × x(n) + b1 × x(n – 1) + b2 × x(n – 2)
REV. 0
–33–
AD1953
OUTLINE DIMENSIONS
48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
1.45
1.40
1.35
0.15
0.05
10ⴗ
6ⴗ
2ⴗ
SEATING
PLANE
PIN 1
SEATING
PLANE
7.00
BSC SQ
TOP VIEW
0.20
0.09
(PINS DOWN)
VIEW A
7ⴗ
3.5ⴗ
0ⴗ
0.10 MAX
COPLANARITY
25
12
13
0.50
BSC
VIEW A
24
0.27
0.22
0.17
ROTATED 90ⴗ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
–34–
REV. 0
–35–
–36–
C02909–0–4/03(0)