TM FQA18N50V2 500V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficient switched mode power supplies, active power factor correction, electronic lamp ballast based on half bridge topology. • • • • • • 20A, 500V, RDS(on) = 0.265Ω @VGS = 10 V Low gate charge ( typical 42 nC) Low Crss ( typical 11 pF) Fast switching 100% avalanche tested Improved dv/dt capability D ! " ! " " " G! ! TO-3P G DS Absolute Maximum Ratings Symbol VDSS ID S FQA Series TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current FQA18N50V2 500 Units V 20 A - Continuous (TC = 100°C) IDM Drain Current - Pulsed (Note 1) 12.7 A 80 A ± 30 V 330 mJ VGSS Gate-Source Voltage EAS Single Pulsed Avalanche Energy (Note 2) IAR Avalanche Current (Note 1) 20 A EAR Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) (Note 1) 27.7 4.5 277 2.22 -55 to +150 mJ V/ns W W/°C °C 300 °C dv/dt PD TJ, TSTG TL (Note 3) - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RθJC Parameter Thermal Resistance, Junction-to-Case Typ -- RθCS Thermal Resistance, Case-to-Sink RθJA Thermal Resistance, Junction-to-Ambient ©2002 Fairchild Semiconductor Corporation Max 0.45 Units °C/W 0.24 -- °C/W -- 40 °C/W Rev. B, August 2002 FQA18N50V2 QFET Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 500 -- -- V -- 0.5 -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C IDSS IGSSF IGSSR VDS = 500 V, VGS = 0 V -- -- 1 µA VDS = 400 V, TC = 125°C -- -- 10 µA Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA 3.0 -- 5.0 V -- 0.225 0.265 Ω -- 16 -- S -- 2530 3290 pF -- 300 390 pF -- 11 14.3 pF -- 76 -- pF -- 150 -- pF ns Zero Gate Voltage Drain Current On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 10 A gFS Forward Transconductance VDS = 40 V, ID = 10 A (Note 4) Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Coss Output Capacitance Coss eff. Effective Output Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz VDS = 400 V, VGS = 0 V, f = 1.0 MHz VDS = 0V to 400 V, VGS = 0 V Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 250 V, ID = 18 A, RG = 25 Ω (Note 4, 5) VDS = 400 V, ID = 18 A, VGS = 10 V (Note 4, 5) -- 40 90 -- 150 310 ns -- 95 200 ns -- 110 230 ns -- 42 55 nC -- 12 -- nC -- 14 -- nC A Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 20 ISM -- -- 80 A VSD Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 20 A Drain-Source Diode Forward Voltage -- -- 1.4 V trr Reverse Recovery Time -- 420 -- ns Qrr Reverse Recovery Charge -- 5.4 -- µC VGS = 0 V, IS = 18 A, dIF / dt = 100 A/µs (Note 4) Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 1.83mH, IAS = 18A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 18A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature ©2002 Fairchild Semiconductor Corporation Rev. B, August 2002 FQA18N50V2 Electrical Characteristics FQA18N50V2 Typical Characteristics VGS Top : 15.0 V 10.0 V 8.0 V 1 1 7.0 V ID , Drain Current [A] ID, Drain Current [A] 10 6.5 V 6.0 V Bottom : 10 5.5 V 0 ※ Notes : 10 150℃ 25℃ -55℃ 0 10 ※ Notes : 1. 250μ s Pulse Test 1. VDS = 40V 2. TC = 25℃ 10 2. 250μ s Pulse Test -1 -1 10 -1 10 0 10 10 1 2 4 VDS, Drain-Source Voltage [V] 6 8 10 VGS , Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics IDR , Reverse Drain Current [A] R DS(ON) [Ω ], Drain-Source On-Resistance 1.0 0.8 0.6 VGS = 10V 0.4 V GS = 20V 0.2 1 10 0 10 150℃ 25℃ ※ Notes : 1. VGS = 0V ※ Note : TJ = 25℃ 2. 250μ s Pulse Test -1 0.0 0 10 20 30 40 50 60 10 70 0.2 0.4 0.6 1.0 1.2 1.4 1.6 VSD , Source-Drain Voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 7000 12 C iss = C gs + Cgd (Cds = shorted) VDS = 100V C oss = Cds + Cgd 6000 10 4000 3000 Ciss Coss 2000 ※ Notes : 1. VGS = 0 V 2. f = 1 MHz 1000 Crss 0 -1 10 V GS , Gate-Source Voltage [V] C rss = C gd 5000 Capacitance [pF] 0.8 ID, Drain Current [A] VDS = 250V VDS = 400V 8 6 4 2 ※ Note : ID = 18A 0 10 0 10 1 VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics ©2002 Fairchild Semiconductor Corporation 0 5 10 15 20 25 30 35 40 45 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. B, August 2002 (Continued) 3.0 R DS(ON) , (Normalized) 1.1 1.0 ※ Notes : 0.9 1. VGS = 0 V 2. ID = 250 μ A Drain-Source On-Resistance 1.2 BV DSS , (Normalized) Drain-Source Breakdown Voltage FQA18N50V2 Typical Characteristics 2.5 2.0 1.5 1.0 ※ Notes : 0.5 1. VGS = 10 V 2. ID = 10 A 0.8 -100 -50 0 50 100 150 0.0 -100 200 -50 o 0 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 20 Operation in This Area is Limited by R 10 DS(on) 2 ID, Drain Current [A] ID , Drain Current [A] 15 100 us 1 ms 10 1 10 ms DC 10 ※ Notes : 0 o 10 5 1. TC = 25 C o 2. TJ = 150 C 3. Single Pulse 10 -1 10 0 10 1 10 2 10 0 25 3 50 75 Figure 9.. Maximum Safe Operating Area Zθ 125 150 Figure 10. Maximum Drain Current vs. Case Temperature 0 D = 0 .5 10 -1 ※ N o te s : 0 .2 1. Zθ JC ( t ) = 0 .4 5 ℃ /W M a x . 2 . D u t y F a c to r , D = t 1 /t 2 0 .1 3 . T JM - T C = P DM * Z θ JC (t) 0 .0 5 JC ( t) , T h e r m a l R e s p o n s e 10 100 TC, Case Temperature [℃] VDS , Drain-Source Voltage [V] 10 PDM 0 .0 2 0 .0 1 -2 t1 t2 s in g le p u ls e 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u l s e D u r a t io n [ s e c ] Figure 11. Transient Thermal Response Curve ©2002 Fairchild Semiconductor Corporation Rev. B, August 2002 FQA18N50V2 Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL VDS 90% VDD VGS RG VGS DUT 10V 10% td(on) tr td(off) t on tf t off Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG VDD DUT 10V tp ©2002 Fairchild Semiconductor Corporation ID (t) VDS (t) VDD tp Time Rev. B, August 2002 FQA18N50V2 Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2002 Fairchild Semiconductor Corporation Rev. B, August 2002 FQA18N50V2 Package Dimensions TO-3P 15.60 ±0.20 3.00 ±0.20 3.80 ±0.20 +0.15 1.00 ±0.20 18.70 ±0.20 23.40 ±0.20 19.90 ±0.20 1.50 –0.05 16.50 ±0.30 2.00 ±0.20 9.60 ±0.20 4.80 ±0.20 3.50 ±0.20 13.90 ±0.20 ø3.20 ±0.10 12.76 ±0.20 13.60 ±0.20 1.40 ±0.20 +0.15 5.45TYP [5.45 ±0.30] 5.45TYP [5.45 ±0.30] 0.60 –0.05 Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation Rev. B, August 2002 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet series™ Bottomless™ FAST® CoolFET™ FASTr™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOS™ HiSeC™ EnSigna™ I2C™ Across the board. Around the world™ The Power Franchise™ Programmable Active Droop™ ImpliedDisconnect™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SLIENT SWITCHER® SMART START™ SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET® VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness. provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. ©2002 Fairchild Semiconductor Corporation Rev. I1