a FEATURES Low-Cost 3.3 V CMOS Analog Front End Converter for MCNS-DOCSIS, DVB, DAVIC-Compliant Set-Top Box, Cable Modem Applications 232 MHz Quadrature Digital Upconverter DC to 65 MHz Output Bandwidth 12-Bit Direct IF D/A Converter (TxDAC+ ®) Programmable Reference Clock Multiplier (PLL) Direct Digital Synthesis Interpolator SIN(x)/x Compensation Filter Four Programmable, Pin-Selectable Modulator Profiles Single-Tone Mode for Frequency Synthesis Applications 12-Bit, 33 MSPS Sampling Direct IF A/D Converter with Auxiliary Automatic Clamp Video Input Multiplexer 10-Bit, 33 MSPS Sampling Direct IF A/D Converter Dual 8-Bit, 16.5 MSPS Sampling IQ A/D Converter Two Independently Programmable Sigma-Delta Converters Direct Interface to AD8321/AD8323 PGA Cable Driver Programmable Frequency Output Power-Down Modes Analog Front End Converter for Set-Top Box, Cable Modem AD9873 FUNCTIONAL BLOCK DIAGRAM AD9873 COS Tx IQ Tx Tx SYNC INTERPOLATOR FILTER INV SINC 12 DAC Tx SIN 3 PLL SERIAL ITF PROFILE CA DDS 12 4 CONTROL FUNCTIONS 2 SDELTA0 12 SDELTA1 REF CLK 8 Rx IQ Rx IF Rx SYNC 8 ADC IIN ADC QIN ADC IF10 Rx 10 12 IF12 ADC MUX VIDEO APPLICATIONS Cable and Satellite Systems PC Multimedia Digital Communications Data and Video Modems Cable Modem Set-Top Boxes Powerline Modem Broadband Wireless Communication GENERAL DESCRIPTION The AD9873 integrates a complete 232 MHz quadrature digital transmitter and a multichannel receiver with four highperformance analog-to-digital converters (ADC) for various video and digital data signals. The AD9873 is designed for cable modem set-top box applications, where cost, size, power dissipation, and dynamic performance are critical attributes. A single external crystal is used to control all internal conversion and data processing cycles. The transmit section of the AD9873 includes a high-speed direct digital synthesizer (DDS), a high-performance, high-speed 12-bit digital-to-analog converter (DAC), programmable clock multiplier circuitry, digital filters, and other digital signal processing functions, to form a complete quadrature digital up-converter device. On the receiver side, two 8-bit ADCs are optimized for IQ demodulated “out-of band” signals. An on-chip 10-bit ADC is typically used as a direct IF input of 256 QAM modulated signals in cable modem applications. A second direct IF input and an auxiliary video input with automatic programmable clamp function are multiplexed to a high-performance 12-bit video ADC. The chip’s programmable sigma-delta modulated outputs and an output clock may be used to control external components such as programmable gain amplifiers (PGA) and mixer stages. Three pins provide a direct interface to the AD8321/AD8323 programmable gain amplifier (PGA) cable driver. The AD9873 is available in a space-saving 100-lead MQFP package. TxDAC+ is a registered trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD9873 TABLE OF CONTENTS Page Page FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 7 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 7 EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 7 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DEFINITIONS OF TERMS . . . . . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 9 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . 10 REGISTER BIT DEFINITIONS . . . . . . . . . . . . . . . . . . . 12 TYPICAL PERFORMANCE CHARACTERISTICS . . . 14 Typical Power Consumption Characteristics . . . . . . . . . 14 Dual Sideband Transmit Spectrum . . . . . . . . . . . . . . . . 14 Single Sideband Transmit Spectrum . . . . . . . . . . . . . . . 15 Typical QAM Transmit Performance Characteristics . . 16 Typical ADC Performance Characteristics . . . . . . . . . . . 18 THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . 20 Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 OSC IN Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . 21 Receive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CLOCK AND OSCILLATOR CIRCUITRY . . . . . . . . . . 22 PROGRAMMABLE CLOCK OUTPUT REF CLK . . . . 23 SIGMA-DELTA OUTPUTS . . . . . . . . . . . . . . . . . . . . . . 23 SERIAL INTERFACE FOR REGISTER CONTROL . . . 23 General Operation of the Serial Interface . . . . . . . . . . . . 23 Instruction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial Interface Port Pin Description . . . . . . . . . . . . . . . 24 MSB/LSB Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Notes on Serial Port Operation . . . . . . . . . . . . . . . . . . . 24 TRANSMIT PATH (Tx) . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Half-Band Filters (HBFs) . . . . . . . . . . . . . . . . . . . . . . . Cascaded Integrator—COMB (CIC) Filter . . . . . . . . . . Combined Filter Response . . . . . . . . . . . . . . . . . . . . . . . Inverse SINC Filter (ISF) . . . . . . . . . . . . . . . . . . . . . . . Tx Signal Level Considerations . . . . . . . . . . . . . . . . . . . Tx Throughput and Latency . . . . . . . . . . . . . . . . . . . . . D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROGRAMMING/WRITING THE AD8321/AD8323 CABLE DRIVER AMPLIFIER GAIN CONTROL . . . RECEIVE PATH (Rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driving the Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . Op Amp Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . ADC Differential Inputs . . . . . . . . . . . . . . . . . . . . . . . . ADC Voltage References . . . . . . . . . . . . . . . . . . . . . . . . Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER AND GROUNDING CONSIDERATIONS . . . EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . –2– 24 24 24 25 25 25 27 28 28 28 29 30 30 30 30 31 31 31 31 32 33 33 33 39 REV. 0 SPECIFICATIONS (VAS = 3.3 V ⴞ 5%, VDS = 3.3 V ⴞ 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8, N = 4), ADC Sample Rate derived from PLL fMCLK , RSET = 10 k⍀, 75 ⍀ DAC Load) AD9873 Parameter Temp Test Level SYSTEM CLOCK, DAC SAMPLING fSYSCLK Frequency Range Full III OSC IN and XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Capacitance Input Resistance Full 25C 25C 25C III III IV IV MCLK OUT JITTER (fMCLK Derived from PLL) 25C IV N/A Full 25C 25C 25°C 25C 25C 25C 25C Full N/A III I I I IV IV IV IV III 25C 25C IV IV 59 54 dBc dBc 25C IV 79 dBc Full Full Full Full III III III III N/A Full N/A N/A III N/A 8 25C 25C 25C 25C Full Full Min 3 35 Typ 50 3 100 Max Unit 232 MHz 33 65 MHz % pF MΩ 6 ps rms 1 TxDAC CHARACTERISTICS Resolution Full-Scale Output Current Gain Error (Using Internal Reference) Output Offset Reference Voltage (REFIO Level) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Output Capacitance Phase Noise @ 1 kHz Offset, 42 MHz Output Voltage Compliance Range Wideband SFDR 5 MHz Analog Out, IOUT = 4 mA 65 MHz Analog Out, IOUT = 4 mA Narrowband SFDR (100 kHz Window) 65 MHz Analog Out, IOUT = 4 mA Tx MODULATOR CHARACTERISTICS I/Q Offset Pass Band Amplitude Ripple (f < fIQCLK/8) Pass Band Amplitude Ripple (f < fIQCLK/4) Stop Band Response (f > fIQCLK × 3/4) 8-BIT ADC CHARACTERISTICS Resolution Conversion Rate Pipeline Delay DC Accuracy Differential Nonlinearity Integral Nonlinearity Offset Error for Each 8-Bit ADC Gain Error for Each 8-Bit ADC Offset Matching Between 8-Bit ADCs Gain Matching Between 8-Bit ADCs Analog Input Input Voltage Range Input Capacitance Differential Input Resistance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (–3 dB) Input Referred Noise Reference Voltage Error REFT8–REFB8 (0.5 V) Dynamic Performance (AIN = –0.5 dB FS, f = 5 MHz) Signal-to-Noise and Distortion Ratio (SINAD) REV. 0 2 –3 –1 1.18 12 4 0.14 1.23 ± 2.5 ±8 5 –113 –0.5 +1.5 dB dB dB dB 16.5 3.5 Bits MHz ADC Cycles IV IV IV IV IV IV 0.5 0.5 0.75 4 3 4.5 LSB LSB % FSR % FSR LSB LSB Full 25C 25C 25C 25C 25C 25C IV IV IV IV IV IV IV 1 1.4 4 2.0 1.2 90 600 V p-p pF kΩ ns ps rms MHz µV 25C I ±4 Full II 43.5 55 Bits mA % FS % FS V LSB LSB pF dBc/Hz V 0.1 0.5 –63 –3– 50 20 +3 +1 1.28 48 ± 92 mV dB AD9873–SPECIFICATIONS Parameter Temp Test Level 8-BIT ADC CHARACTERISTICS (Continued) Dynamic Performance (AIN = –0.5 dB FS, f = 5 MHz) Effective Number of Bits (ENOB) Effective Number of Bits (ENOB)2 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Differential Phase Differential Gain Full Full Full Full Full 25C 25C II IV II II II IV IV N/A Full N/A N/A III N/A 10 25C 25C 25C 25C 10-BIT ADC CHARACTERISTICS Resolution Conversion Rate Pipeline Delay DC Accuracy Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Analog Input Input Voltage Range Input Capacitance Differential Input Resistance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (–3 dB) Input Referred Noise Reference Voltage REFT10–REFB10 (1 V) Dynamic Performance (AIN = –0.5 dB FS, f = 5 MHz) Signal-to-Noise and Distortion Ratio (SINAD) Effective Number of Bits (ENOB) Effective Number of Bits (ENOB)3 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Differential Phase Differential Gain 12-BIT ADC CHARACTERISTICS Resolution Conversion Rate Pipeline Delay DC Accuracy Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Analog Input Input Voltage Range Input Capacitance Differential Input Resistance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (–3 dB) Input Referred Noise Reference Voltage REFT12–REFB12 (1 V) –4– Min Typ Max Unit 6.9 7.68 7.68 48 –66 64 <0.1 1 –57 Bits Bits dB dB dB Degree LSB 33 5.5 Bits MHz ADC Cycles IV IV IV IV 0.75 0.5 0.5 3 LSB LSB % FSR % FSR Full 25C 25C 25C 25C 25C 25C IV IV IV IV IV IV IV 2 1.4 4 2.0 1.2 95 350 V p-p pF kΩ ns ps rms MHz µV 25C I ±6 Full Full Full Full Full Full 25C 25C II II IV II II II IV IV N/A Full N/A N/A III N/A 12 5.5 Bits MHz ADC Cycles 25C 25C 25C 25C IV IV IV IV 0.75 1.5 1 2 LSB LSB % FSR % FSR Full 25C 25C 25C 25C 25C 25C IV IV IV IV IV IV IV 2 1.4 4 2.0 1.2 85 75 V p-p pF kΩ ns ps rms MHz µV 25C I ±6 43.5 58 57.9 9.3 58.2 65.7 60.1 9.7 9.8 60.1 –75.8 80 <0.1 <1 ± 200 –63.9 33 ± 200 mV dB Bits Bits dB dB dB Degree LSB mV REV. 0 AD9873 Parameter Temp Test Level 12-BIT ADC CHARACTERISTICS (Continued) Dynamic Performance (AIN = –0.5 dB FS, f = 5 MHz) Signal-to-Noise and Distortion Ratio (SINAD) Signal-to-Noise and Distortion Ratio (SINAD)3 Effective Number of Bits (ENOB) Effective Number of Bits (ENOB)3 Signal-to-Noise Ratio (SNR) Signal-to-Noise Ratio (SNR)3 Total Harmonic Distortion (THD) Total Harmonic Distortion (THD)3 Spurious Free Dynamic Range (SFDR) Spurious Free Dynamic Range (SFDR)3 Differential Phase Differential Gain Full Full Full Full Full Full Full Full Full Full 25C 25C III IV III IV III IV III IV III IV IV IV Full 25C 25C 25C 25C 25C IV IV IV III IV IV Full Full Full Full Full 25°C 25°C IV IV IV IV IV IV IV 52 8.34 61.0 –53.0 55.0 <0.1 <8 dB Bits dB dB dB Degree LSB 25C 25C 25C IV IV IV >80 >85 >90 dB dB dB 25C 25C 25C 25C III IV IV IV >70 >80 >80 >70 dB dB dB dB N/A N/A 25C N/A N/A III 25C 25C 25C 25C 25C III III III III III Full Full Full Full Full Full Full III III III III III III III VIDEO CLAMP INPUT Input Voltage Range Clamp Current Positive Clamp Droop Current Clamp Level Offset Programming Range Clamp Level Resolution Carrier Rejection Filter Bandwidth (–3 dB) Dynamic Performance (AIN = –0.5 dB FS, f = 5 MHz) Signal-to-Noise and Distortion Ratio (SINAD) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Differential Phase Differential Gain CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation (5 MHz Analog Output) Isolation Between Tx and 8-Bit ADCs Isolation Between Tx and 10-Bit ADC Isolation Between Tx and 12-Bit ADC ADC-to-ADC Isolation (AIN = –0.5 dB FS, f = 5 MHz) Isolation Between IF12 and Video Isolation Between IF10 and IF12 Isolation Between Q in and IF10 Isolation Between Q in and I Inputs TIMING CHARACTERISTICS (20 pF Load) Wake-Up Time Minimum RESET Pulsewidth Low (tRL) Digital Output Rise/Fall Time Tx/Rx Interface MCLK Frequency (fMCLK) TxSYNC/TxIQ Set Up Time (tSU) TxSYNC/TxIQ Hold Time (tHD) RxSYNC/RxIQ/IF to Valid Time (tTV) RxSYNC/RxIQ/IF Hold Time (tHT) Serial Control Bus SCLK Frequency (fSCLK) Clock Pulsewidth High (tPWH) Clock Pulsewidth Low (tPWL) Clock Rise/Fall Time Data/Chip-Select Setup Time (tDS) Data Hold Time (tDH) Data Valid Time (tDV) REV. 0 –5– Min Typ 62.3 65 67.4 10.5 10.8 65.3 67.4 –77.6 –77.6 80 80 <0.1 <1 10.0 63.3 65.7 256 70 2 1.3 2 512 16 0.6 Max –65.4 2032 200 5 2.8 4 66 3 3 5.2 0.2 15 30 30 1 25 0 30 Unit dB dB Bits Bits dB dB dB dB dB dB Degree LSB V mA A LSB LSB MHz tMCLK Cycles tMCLK Cycles ns MHz ns ns ns ns MHz ns ns ms ns ns ns AD9873–SPECIFICATIONS Parameter Temp Test Level CMOS LOGIC INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance 25C 25C 25C 25C 25C III III III III IV 2.0 CMOS LOGIC OUTPUTS (1 mA Load) Logic “1” Voltage Logic “0” Voltage 25C 25C III III 2.4 25C II 91 25C 25C 25C 25°C IV II IV II 250 175 210 42 25C 25C 25C 25C IV IV IV IV <0.25 <0.004 <0.002 <0.0004 POWER SUPPLY Analog Supply Current IAS Digital Supply Current IDS Full Operating Conditions4 (Register 02h = 00h) Zero Input Tx4 (Register 02h = 00h) 25% Tx Burst Duty Cycle4 (Register 02h = 00h) Power-Down Digital Tx (Register 02h = 20h) Power Supply Rejection (Differential Signal) Tx DAC 8-Bit ADC 10-Bit ADC 12-Bit ADC Min Typ Max Unit 0.8 12 12 V V A A pF 3 0.4 V V 115 mA 205 55 mA mA mA mA % FS % FS % FS % FS NOTES 1 Single tone generated by applying a 1.6875 MHz sine signal to the Q Channel and the 90 degree phase shifted (cosine) signal to the I Channel. 2 Sampling directly with f OSCCIN/2. No degradation due to Clock Multiplier PLL. ADC Clock Select Register 08h, Bits 5 and 7 set to “1.” 3 Sampling directly with f OSCCIN. No degradation due to Clock Multiplier PLL. ADC Clock Select Register 08h, Bits 5 and 7 set to “1.” 4 See performance graph TPC 2 for power saving in burst mode operation. –6– REV. 0 AD9873 ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS Power Supply (VAS, VDS) . . . . . . . . . . . . . . . . . . . . . . 3.9 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Digital Inputs . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V Analog Inputs . . . . . . . . . . . . . –0.3 V to AVDD (IQ) +0.3 V Operating Temperature . . . . . . . . . . . . . . . . . . . . 0C to 70C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . –65C to +150C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300C I II III IV – 100% production tested. – Devices are 100% production tested at 25C and guaranteed by design and characterization testing for commercial operating temperature range (0C to 70C). – Parameter is guaranteed by design and/or characterization testing. – Parameter is a typical value only. N/A – Test level definition is not applicable. *Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 100-Lead MQFP JA = 40.5C/W ORDERING GUIDE Model AD9873JS AD9873-EB Temperature Range Package Description Package Option 0C to 70C Metric Quad Flatpack (MQFP) Evaluation Board S-100C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9873 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –7– WARNING! ESD SENSITIVE DEVICE AD9873 DEFINITIONS OF TERMS APERTURE DELAY DIFFERENTIAL NONLINEARITY ERROR (DNL, NO MISSING CODES) Aperture delay is a measure of the Sample-and-Hold Amplifier (SHA) performance and specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion. An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes respectively, must be present over all operating ranges. APERTURE UNCERTAINTY (JITTER) Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the ADC. INTEGRAL NONLINEARITY ERROR (INL) Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. SIGNAL-TO-NOISE + DISTORTION (SINAD) RATIO SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, PHASE NOISE Single-sideband phase noise power density is specified relative to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier. Phase noise can be measured directly in single tone transmit mode with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log (rbw). It also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display and detector characteristic. N = (SINAD – 1.76) dB/6.02 it is possible to obtain a measure of performance expressed as N, the effective number of bits. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. OUTPUT COMPLIANCE RANGE The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation, resulting in nonlinear performance or breakdown. TOTAL HARMONIC DISTORTION (THD) SPURIOUS-FREE DYNAMIC RANGE (SFDR) POWER SUPPLY REJECTION THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. The difference, in dB, between the rms amplitude of the DACs output signal (or ADC’s input signal) and the peak spurious signal over the specified bandwidth (Nyquist bandwidth unless otherwise noted). Power supply rejection specifies the converters maximum full-scale change when the supplies are varied from nominal to minimum and maximum specified voltages. PIPELINE DELAY (LATENCY) In an ideal multichannel system, the signal in one channel will not influence the signal level of another channel. The channelto-channel isolation specification is a measure of the change that occurs to a grounded channel as a full-scale signal is applied to another channel. CHANNEL-TO-CHANNEL ISOLATION (CROSSTALK) The number of clock cycles between conversion initiation and the associated output data being made available. OFFSET ERROR First transition should occur for an analog value 1/2 LSB above negative full scale. Offset error is defined as the deviation of the actual transition from that point. GAIN ERROR The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. –8– REV. 0 AD9873 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Pin Function Pin No. Mnemonic Pin Function 1, 84, 87 92, 95 2, 21, 70 3, 22, 72 4–15 AVDD Analog Supply Voltage 10-/12-Bit ADC Pin Driver Digital Ground Pin Driver Digital Supply Voltage Multiplexed Output of IF10and IF12-Bit ADCs Multiplexed Output of I and Q 8-Bit ADCs Demultiplexer Synchronization Output for IF and IQ ADCs Master Clock Output Demultiplexer Digital Supply Voltage Digital Ground 64 CA DATA 65 CA ENABLE 66 67 68 69 71 DVDD SD SDELTA1 SDELTA0 DGND SD REF CLK Cable Amplifier Control Data Output Cable Amplifier Control Enable Output Supply Voltage Sigma Delta Sigma Delta Output Stream 1 Sigma Delta Output Stream 0 Ground Sigma Delta Programmable Reference Clock Output Derived from MCLK Analog Supply 8-Bit ADCs Analog Ground 8-Bit ADCs Bottom Reference Decoupling IQ 8-Bit ADC’s Reference Top Reference Decoupling IQ 8-Bit ADC’s Reference Inverting I Analog Input Noninverting I Analog Input Inverting Q Analog Input Noninverting Q Analog Input Analog Ground 10-/12-Bit ADC 16–19 DRGND DRVDD IF11–IF0 20 Rx IQ 3 –Rx IQ 0 Rx SYNC 23 MCLK 24, 33, 38 DVDD 25, 34, DGND 39, 40 26 Tx SYNC 27–32 Tx IQ 5 –Tx IQ 0 35, 36 37 PROFILE[1:0] RESET 41 42 43 44 45 46 47 SCLK CS SDIO SDO DGND Tx DVDD Tx PWR DOWN 48 REFIO 49 FSADJ 50 51 52 53 54 55 56 57 58 59 60 61 62 63 AGND Tx Tx– Tx+ AVDD Tx DGND PLL DVDD PLL AVDD PLL PLL FILTER AGND PLL DGND OSC XTAL OSC IN DVDD OSC CA CLK REV. 0 Synchronization Input for Transmitter Multiplexed I and Q Input Data for Transmitter (Two’s Complement) Profile Selection Inputs Master Reset Input, Reset applies for all Interfaces and Registers Serial Interface Input Clock Serial Interface Chip Select Serial Interface Data I/O Serial Interface Data Output Digital Ground Tx Section Digital Supply Voltage Tx Transmit Power-Down Control Input DAC Bandgap requires 0.1 µF Capacitor to Ground Full-Scale DAC Current Output Adjust with External Resistor Analog Ground Tx Section Transmitter DAC Output– Transmitter DAC Output+ Analog Supply Voltage Tx PLL Digital Ground PLL Digital Supply Voltage PLL Analog Supply Voltage PLL Loop Filter Connection PLL Analog Ground Digital Ground Oscillator Crystal Oscillator Inv. Output Oscillator Clock Input Digital Supply Oscillator Cable Amplifier Control Clock Output 73 AVDD IQ 74, 77, 80 AGND IQ 75 REFB8 76 REFT8 78 79 81 82 83, 88, 91, 96, 99 85 I IN– I IN+ Q IN– Q IN+ AGND 86 REFT10 89 90 93 IF10– IF10+ REFB12 94 REFT12 97 98 100 IF12– IF12+ VIDEO IN –9– REFB10 Bottom Reference Decoupling IF 10-Bit ADC’s Reference Top Reference Decoupling IF 10-Bit ADC’s Reference Noninverting IF10 Analog Input Inverting IF10 Analog Input Bottom Reference Decoupling IF 12-Bit ADC’s Reference Top Reference Decoupling IF 12-Bit ADC’s Reference Inverting IF12 Analog Input Noninverting IF12 Analog Input Single-Ended Video Input AD9873 AVDD 1 DRGND 2 81 Q IN– 82 Q IN+ 83 AGND 84 AVDD 85 REFB10 86 REFT10 88 AGND 87 AVDD 89 IF10– 90 IF10+ 91 AGND 93 REFB12 92 AVDD 94 REFT12 95 AVDD 96 AGND 97 IF12– 98 IF12+ 99 AGND 100 VIDEO IN PIN CONFIGURATION 80 AGND IQ PIN 1 IDENTIFIER DRVDD 3 79 I IN+ 78 I IN– (MSB) IF(11) 4 77 AGND IQ IF(10) 5 76 REFT8 IF(9) 6 75 REFB8 IF(8) 7 74 AGND IQ IF(7) 8 73 AVDD IQ IF(6) 9 72 DRVDD IF(5) 10 71 REF CLK IF(4) 11 70 DRGND IF(3) 12 IF(2) 13 69 DGND SD IF(1) 14 67 SDELTA 1 68 SDELTA 0 AD9873 IF(0) 15 66 DVDD SD TOP VIEW (Pins Down) (MSB) RxIQ(3) 16 RxIQ(2) 17 65 CA ENABLE 64 CA DATA RxIQ(1) 18 63 CA CLK RxIQ(0) 19 62 DVDD OSC RxSYNC 20 61 OSC IN DRGND 21 60 XTAL DRVDD 22 59 DGND OSC MLCK 23 58 AGND PLL DVDD 24 57 PLL FILTER DGND 25 56 AVDD PLL TxSYNC 26 55 DVDD PLL (MSB) TxIQ(5) 27 54 DGND PLL –10– AGND Tx 50 FSADJ 49 REFIO 48 PWR DOWN 47 DVDD Tx 46 DGND Tx 45 SDO 44 SDIO 43 CS 42 DGND 40 SCLK 41 DGND 39 RESET 37 DVDD 38 PROFILE(0) 36 51 Tx– DGND 34 PROFILE(1) 35 52 Tx+ TxIQ(2) 30 TxIQ(0) 32 DVDD 33 53 AVDD Tx TxIQ(3) 29 TxIQ(1) 31 TxIQ(4) 28 REV. 0 AD9873 Table I. Register Map Address (Hex) Default (Hex) Type OSC IN Multiplier M <0> 10 rw MCLK Divider R <0> 09 rw Power-Down Power-Down Power-Down Power-Down Power-Down 00 12-Bit ADC Reference 10-Bit ADC Reference 8-Bit ADC 12-Bit ADC 10-Bit ADC rw Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 SDIO Bidirectional LSB/MSB First RESET OSC IN Multiplier M <4> OSC IN Multiplier M <3> OSC IN Multiplier M <2> OSC IN Multiplier M <1> 01 PLL Lock Detect OSC IN Divider N = 3 (4) MCLK Divider R <5> MCLK Divider R <4> MCLK Divider R <3> MCLK Divider R <2> MCLK Divider R <1> 02 Power-Down PLL Power-Down DAC Tx Power-Down Digital Tx 03 Sigma-Delta Output 0 Control Word <3:0> LSB 04 05 00 rw 00 rw 00 rw Sigma-Delta Output 1 Control Word <11:4> MSB 00 rw Clamp Level Control for Video Input <6:0> 20 rw ADC 0 0 0 0 Sigma-Delta Output 0 Control Word <11:4> MSB Sigma-Delta Output 1 Control Word <3:0> LSB 06 0 0 0 0 07 Video Input Enable 08 ADC Clock Select 0 ADC Clock Select 0 0 0 Test 12-Bit ADC Test 10-Bit ADC 00 rw ADC 09 0 0 0 0 0 0 0 0 00 rw 0A 0 0 0 0 0 0 0 0 00 rw 0B 0 0 0 0 0 0 0 0 00 rw 0C 0 0 0 0 0X r 0D 0 0 0 0 0 0 0 0 00 r 0E 0 0 0 0 0 0 0 0 00 r 0F 0 0 Profile Select <1> Profile Select <0> 0 Bypass Inv. Sinc Tx Filter Spectral Inversion Tx Single-Tone Tx Mode 00 rw Tx Version <3:0> 10 Tx Frequency Turning Word Profile 0 <7:0> 00 rw Tx 11 Tx Frequency Turning Word Profile 0 <15:8> 00 rw Tx 12 Tx Frequency Turning Word Profile 0 <23:16> 00 rw Tx 13 Cable Driver Amplifier Gain Control Profile 0 <7:0> 00 rw Tx 14 Tx Frequency Turning Word Profile 1 <7:0> 00 rw Tx 15 Tx Frequency Turning Word Profile 1 <15:8> 00 rw Tx 16 Tx Frequency Turning Word Profile 1 <23:16> 00 rw Tx 17 Cable Driver Amplifier Gain Control Profile 1 <7:0> 00 rw Tx 18 Tx Frequency Turning Word Profile 2 <7:0> 00 rw Tx 19 Tx Frequency Turning Word Profile 2 <15:8> 00 rw Tx 1A Tx Frequency Turning Word Profile 2 <23:16> 00 rw Tx 1B Cable Driver Amplifier Gain Control Profile 2 <7:0> 00 rw Tx 1C Tx Frequency Turning Word Profile 3 <7:0> 00 rw Tx 1D Tx Frequency Turning Word Profile 3 <15:8> 00 rw Tx 1E Tx Frequency Turning Word Profile 3 <23:16> 00 rw Tx 1F Cable Driver Amplifier Gain Control Profile 3 <7:0> 00 rw Tx “0” register bits should not be programmed with 1. REV. 0 –11– AD9873 REGISTER BIT DEFINITIONS 00h, Bits 0–4: OSC IN Multiplier–Register Address 03h to 06h: Sigma-Delta Output Control Words This register field is used to program the on-chip multiplier (PLL) that generates the chip’s high-frequency system clock, fSYSCLK. For example, to multiply the external crystal clock fOSCIN by 19 decimal, program register address 00h, Bits 5–1 as 13h. Default value is M = 16 = 10h. Valid entries range from M = 1 to 31. M = 1 (no PLL) requires a very stable, high-frequency clock at OSC IN. A changed fSYSCLK frequency is stable (PLL locked) after a maximum of 200 fMCLK cycles (= Wake-Up Time). 00h, Bit 5: RESET The Sigma-Delta Output Control Words –0 and –1 are 12 bits wide and split in MSB bits <11:4> and LSB bits <3:0>. Changes to the sigma-delta outputs take effect immediately for every MSB or LSB register write. Sigma-delta output control words have a default value of 0. The smaller the programmed values in these registers, the lower are the integrated (low-pass filtered) sigma delta output levels (straight binary format). 07h, Bits 0–6: Clamp Level Control for Video Input A 7-bit clamp level offset can be set for the internal automatic clamp level control loop of the Video Input. Writing a one to this bit resets the registers to their default values and restarts the chip. The RESET bit always reads back 0. Register address 00h bits are not cleared by this software reset. However, a low level at the RESET pin would force all registers, including all bits in address 00h, to their default state. Clamp level offset = Clamp level control × 16. 00h, Bit 6: LSB/MSB First 07h, Bit 7: Video Input Enable This register defaults to 32 = 20h, which amounts to a clamp level offset of 512 LSB = 200h. Valid clamp level control values are 16 to 127. Active high indicates SPI serial port access of instruction byte and data registers is least significant bit (LSB) first. Default low indicates most significant bit (MSB) first format. This bit controls the multiplexer to the 12-bit ADC and determines if IF12 input or Video input is used. The bit is default set to 0 for the IF12 input. 00h, Bit 7: SDIO Bidirectional 08h, Bit 0: Test 10-Bit ADC Default low indicates SPI serial port uses dedicated input/output lines (SDIO and SDO pin). High configures serial port as single line I/O (SDIO pin is used bidirectional). Active high allows nonmultiplexed 10-bit ADC data only to be read at IF outputs. Output data changes at half MCLK clock rate. This bit defaults to 0. 01h, Bits 0–5: MCLK Divider 08h, Bit 1: Test 12-Bit ADC This register is used to divide the chip’s master clock by R, where R is an integer between 2 and 63. The generated reference clock, REF CLK, can be used for external frequency-controlled devices. Default value is R = 9. Active high allows nonmultiplexed 12-bit ADC data only to be read at IF outputs. Output data changes at half MCLK clock rate. This bit defaults to 0. 08h, Bit 5 and Bit 7: ADC Clock Select 01h, Bit 6: OSC IN Divider Active high indicates that the frequency at OSC IN is directly used to sample the on chip ADCs. Default low indicates that the on chip ADCs generate their sampling frequencies from the internally generated master clock MCLK. Both Bit 5 and Bit 7 need to be programmed with the same values. The OSC IN multiplier output clock can be divided by 4 or 3 to generate the chip’s master clock. Active high indicates a divide ratio of N = 3. Default low configures a divide ratio of N = 4. 01h, Bit 7: PLL Lock Detect If this bit is set to 1, REF CLK pin is disabled from the normal usage. In this mode REF CLK high signals that the internal phase lock loop (PLL) is in lock with CLK IN. 0Ch, Bits 0–3: Version 02h Bits 0–7: Power-Down Active high configures the AD9873 for single-tone applications. The AD9873 will supply a single frequency output as determined by the frequency tuning word (FTW) selected by the active profile. In this mode, the Tx IQ input data pins are ignored but should be tied high or low. Default value of single-tone Tx mode is 0 (inactive). This register stores the die version of the chip. It can only be read. 0Fh, Bit 0: Single-Tone Tx Mode Sections of the chip that are not used can be put in a power saving mode when the corresponding bits are set to 1. This register has a default value of 00h with all sections active. Bit 0: Power-Down 8-bit ADC powers down the 8-bit ADC and stops RxSYNC framing signal. Bit 1: Power-Down 10-bit ADC reference powers down the internal 10-bit ADC reference. Bit 2: Power-Down 10-bit ADC powers down the 10-bit ADC. Bit 3: Power-Down 12-bit ADC reference powers down the internal 12-bit ADC reference. Bit 4: Power-Down 12-bit ADC powers down the 12-bit ADC. Bit 5: Power-Down Tx powers down the transmit section of the chip. 0Fh, Bit 1: Spectral Inversion Tx When set to 1, inverted modulation is performed (I cos (ωt) + Q sin (ωt)). Default is logic zero, noninverted modulation (I cos (ωt) – Q sin (ωt)). 0Fh, Bit 2: Bypass Inv Sinc Tx Filter Active high, configures the AD9873 to bypass the SIN(X)/X compensation filter. Default value is 0 (inverse sinc filter enabled). Bit 6: Power-Down DAC Tx powers down the DAC. Bit 7: Power-Down PLL powers down the CLK IN Multiplier. –12– REV. 0 AD9873 0Fh, Bit 4, Bit 5: Profile Select The AD9873 quadrature digital upconverter is capable of storing four preconfigured modulation modes called profiles that define a transmit frequency tuning word and cable driver amplifier control. Profile Select bits <1:0> or PROFILE [1:0] pins program the current register profile to be used. Profile Select bits should always be 0 if PROFILE pins are used to switch between profiles. Using the Profile Select bits as a means of switching between different profiles requires the PROFILE pins to be tied low. 10h–1Fh: Burst Parameter Tx Frequency Tuning Words The frequency tuning word (FTW) determines the DDSgenerated carrier frequency (fC) and is formed via a concatenation of register addresses. Bit 7 of register address 1Ah is the most significant bit of the profile 2-frequency tuning word. Bit 0 of register address 18h is the least significant bit of the profile 2-frequency tuning word. REV. 0 The output frequency equation is given as: fC = (FTW × fSYSCLK)/224. Where fSYSCLK = Mx fOSCIN and FTW < 80 00 00 h Changes to FTW bytes immediately take effect on active profiles. Cable Driver Gain Control The AD9873 dedicates three output pins that directly interface to the AD832x-family of gain programmable cable driver amplifier. This allows direct control of the cable driver’s gain via the AD9873. New data is automatically sent to the cable driver amplifier whenever a new burst profile with different gain setting becomes active or when the gain contents of an active AD8321/ AD8323 gain control register changes. Default value is 00h (lowest gain). –13– AD9873 Typical Performance Characteristics (VAS = 3.3 V, VDS = 3.3 V, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz [M = 8, N = 4], ADC Sample Rate derived directly from fOSCIN, RSET = 10 k⍀ [IOUT = 4 mA], 75 ⍀ DAC Load, unless otherwise noted) TYPICAL POWER CONSUMPTION CHARACTERISTICS (20 MHz Single Tone, unless otherwise noted) 380 340 SINGLE-TONE 360 330 SUPPLY CURRENT – mA SUPPLY CURRENT – mA 340 320 300 280 260 16-QAM 320 310 300 240 290 220 200 120 140 160 200 180 220 0 240 10 20 30 fSYSCLK – MHz 40 50 60 70 80 90 100 DUTY CYCLE – % TPC 1. Power Consumption vs. Clock Speed, fSYSCLK TPC 2. Power Consumption vs. Transmit Burst Duty Cycle 0 0 –10 –10 –20 –20 –30 –30 MAGNITUDE – dB MAGNITUDE – dB DUAL SIDEBAND TRANSMIT SPECTRUM (See Table IV for Dual-Tone Generation.) –40 –50 –60 –70 –40 –50 –60 –70 –80 –80 –90 –90 –100 –100 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 FREQUENCY – MHz 0 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –80 –90 –90 –100 55 –100 55 65 67 16 18 20 –60 –80 63 14 –50 –70 61 12 –40 –70 59 10 TPC 3b. Dual Sideband Spectral Plot, fC = 5 MHz f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz MAGNITUDE – dB MAGNITUDE – dB TPC 3a. Dual Sideband Spectral Plot, fC = 5 MHz f = 1 MHz, RSET =10 kΩ (IOUT = 4 mA), RBW = 1 kHz 57 8 FREQUENCY – MHz 69 71 73 75 57 59 61 63 65 67 69 71 73 75 FREQUENCY – MHz FREQUENCY – MHz TPC 4a. Dual Sideband Spectral Plot, fC = 65 MHz f = 1 MHz, RSET =10 kΩ (IOUT = 4 mA), RBW = 1 kHz TPC 4b. Dual Sideband Spectral Plot, fC = 65 MHz f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz –14– REV. 0 AD9873 0 0 –10 –10 –20 –20 –30 –30 MAGNITUDE – dB MAGNITUDE – dB SINGLE SIDEBAND TRANSMIT SPECTRUM –40 –50 –60 –70 –40 –50 –60 –70 –80 –80 –90 –90 –100 –100 0 20 40 60 80 100 0 20 FREQUENCY – MHz 0 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –70 80 100 –40 –50 –60 –70 –80 –80 –90 –90 –100 –100 0 20 40 60 80 100 0 20 FREQUENCY – MHz 40 60 80 100 FREQUENCY – MHz TPC 6a. Single Sideband @ 42 MHz, RBW = 2 kHz fC = 43 MHz, f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA) TPC 6b. Single Sideband @ 42 MHz, RBW = 2 kHz fC = 43 MHz, f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA) 0 0 –10 –10 –20 –20 –30 –30 MAGNITUDE – dB MAGNITUDE – dB 60 TPC 5b. Single Sideband @ 65 MHz, RBW = 2 kHz fC = 66 MHz, f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA) MAGNITUDE – dB MAGNITUDE – dB TPC 5a. Single Sideband @ 65 MHz, RBW = 2 kHz fC = 66 MHz, f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA) –40 –50 –60 –70 –40 –50 –60 –70 –80 –80 –90 –90 –100 –100 0 20 40 60 80 100 0 FREQUENCY – MHz 20 40 60 80 100 FREQUENCY – MHz TPC 7a. Single Sideband @ 5 MHz, RBW = 2 kHz fC = 6 MHz, f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA) REV. 0 40 FREQUENCY – MHz TPC 7b. Single Sideband @ 5 MHz, RBW = 2 kHz fC = 6 MHz, f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA) –15– 0 0 –10 –10 –20 –20 MAGNITUDE – dB MAGNITUDE – dB AD9873 –30 –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 –80 –90 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 –90 –2.5 2.5 –2.0 –1.5 FREQUENCY OFFSET – MHz –10 –20 –20 –30 –30 MAGNITUDE – dB MAGNITUDE – dB 0 –10 –40 –50 –60 –80 –90 –90 0 10 20 1.5 2.0 2.5 –60 –80 –10 1.0 –50 –70 –20 0.5 –40 –70 –30 0 TPC 8b. Single Sideband @ 65 MHz, RBW = 500 Hz fC = 66 MHz, f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA) 0 –40 –0.5 FREQUENCY OFFSET – MHz TPC 8a. Single Sideband @ 65 MHz, RBW = 500 Hz fC = 66 MHz, f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA) –100 –50 –1.0 30 40 –100 –2.5 50 –2.0 –1.5 FREQUENCY OFFSET – kHz –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY OFFSET – kHz TPC 9. Single Sideband @ 65 MHz, RBW = 50 Hz fC = 66 MHz, f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA) TPC 10. Single Sideband @ 65 MHz, RBW = 10 Hz fC = 66 MHz, f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA) 0 0 –10 –10 –20 –20 MAGNITUDE – dB MAGNITUDE – dB TYPICAL QAM TRANSMIT PERFORMANCE CHARACTERISTICS (16-QAM, 2.56 Mbit/s SINC Filter Enabled, Square Root Raised Cosine Filter with Alpha = 0.25, RSET = 4 k⍀ [IOUT = 10 mA], fSYSCLK = 163.84 MHz, fOSCIN = 20.48 MHz [M = 8, N = 4].) –30 –40 –50 –30 –40 –50 –60 –60 –70 –70 –80 –80 0 5 10 15 20 25 30 35 40 45 50 0 FREQUENCY – MHz 5 10 15 20 25 30 35 40 45 50 FREQUENCY – MHz TPC 11. 16-QAM @ 42 MHz Spectral Plot, RBW = 1 kHz TPC 12. 16-QAM @ 5 MHz Spectral Plot, RBW = 1 kHz –16– REV. 0 AD9873 TPC 13. Tx Output 16-QAM Analysis TPC 14. Tx Output 64-QAM Analysis REV. 0 –17– AD9873 TYPICAL ADC PERFORMANCE CHARACTERISTICS (ADC Sample Rate derived directly from fOSCIN = 27 MHz [13.5 MSPS for 8-bit ADCs], Single-Tone 5 MHz Input Signal, unless otherwise noted.) 70 85 12-BIT ADC 80 65 12-BIT ADC 75 SFDR – dB SNR – dB 10-BIT ADC 60 55 70 10-BIT ADC 65 8-BIT ADC 50 8-BIT ADC 60 45 55 0 10 20 30 40 50 60 70 80 90 0 100 10 20 INPUT SIGNAL FREQUENCY – MHz 30 40 50 60 70 80 90 100 INPUT SIGNAL FREQUENCY – MHz TPC 15. SNR vs. Input Frequency TPC 18. SFDR vs. Input Frequency 70 –60 11.34 –62 12-BIT ADC 65 –64 10.51 8-BIT ADC –66 55 8.84 THD – dB 9.67 ENOB – Bit SINAD – dB 10-BIT ADC 60 –68 –70 –72 10-BIT ADC –74 50 –76 8.01 8-BIT ADC –78 12-BIT ADC 45 0 10 20 30 40 50 60 70 80 90 –80 7.18 100 0 20 10 TPC 16. SINAD vs. Input Frequency 40 50 60 70 80 90 100 TPC 19. THD vs. Input Frequency 0 65 –5 SNR 60 –25 MAGNITUDE – dB MAGNITUDE – dB 30 INPUT SIGNAL FREQUENCY – MHz INPUT SIGNAL FREQUENCY – MHz 55 SFDR 50 SINAD –45 –65 –85 45 –105 40 –125 2 4 6 8 10 12 14 16 18 20 0 INPUT SIGNAL FREQUENCY – MHz 1 2 3 4 5 6 FREQUENCY – MHz TPC 17. Video Input Characteristics vs. Input Frequency TPC 20. 8-Bit ADC Single-Tone Spectral Plot Using PLL (Input Frequency = 5 MHz, 2048 Point FFT) –18– REV. 0 0 0 –5 –5 –25 –25 MAGNITUDE – dB MAGNITUDE – dB AD9873 –45 –65 –85 –105 –45 –65 –85 –105 –125 –125 0 2 4 6 8 10 12 0 13.5 2 4 FREQUENCY – MHz 0 0 –5 –5 –25 –25 –45 –65 –85 –105 12 13.5 –45 –65 –85 –105 –125 –125 0 2 4 6 8 10 12 13.5 0 2 4 FREQUENCY – MHz 6 8 10 12 13.5 FREQUENCY – MHz TPC 22. 10-Bit ADC Single-Tone Spectral Plot Using PLL (Input Frequency = 10 MHz, 4096 Point FFT) TPC 25. 10-Bit ADC Single-Tone Spectral Plot Without PLL (Input Frequency = 10 MHz, 4096 Point FFT) 0 0 –5 –5 –25 –25 MAGNITUDE – dB MAGNITUDE – dB 10 TPC 24. 12-Bit ADC Single-Tone Spectral Plot Without PLL (Input Frequency = 10 MHz, 4096 Point FFT) MAGNITUDE – dB MAGNITUDE – dB TPC 21. 12-Bit ADC Single-Tone Spectral Plot Using PLL (Input Frequency = 10 MHz, 4096 Point FFT) –45 –65 –85 –45 –65 –85 –105 –105 –125 –125 0 2 4 6 8 10 12 0 13.5 TPC 23. Video Input Single-Tone Spectral Plot Using PLL (Input Frequency = 5 MHz, 4096 Point FFT) 2 4 6 8 10 12 13.5 FREQUENCY – MHz FREQUENCY – MHz REV. 0 8 6 FREQUENCY – MHz TPC 26. Video Input Single-Tone Spectral Plot Without PLL (Input Frequency = 5 MHz, 4096 Point FFT) –19– AD9873 THEORY OF OPERATION To gain a general understanding of the AD9873 it is helpful to refer to Figure 1, which displays a block diagram of the device QUADRATURE MODULATOR DATA ASSEMBLER Tx IQ I 6 architecture. The following is a general description of the device functionality. Later sections will detail each of the data path building blocks. HALF-BAND FILTER #1 12 12 HALF-BAND FILTER #2 12 CIC FILTER COS AD9873 FSADJ INV SINC BYPASS 12 MUX DAC INV SINC Tx SYNC Q (fMCLK) 12 12 Tx 12 SIN DDS (fIQCLK) ⴜ2 (fSYSCLK) ⴜ2 OSC IN MULTIPLIER ⴛM MCLK R = 2,3,.......,63 REF CLK N = 3,4 ⴜR (fOSCIN) XTAL M = 1,2,.......,31 ⴜN OSC IN CONTROL WORD 0 3 AD832x CTRL 2 - SDELTA0 - SDELTA1 ⴜ8 BURST PROFILE CTRL 4 12 CONTROL WORD 1 SERIAL INTERFACE ⴜ2 12 ⴜ2 (fOSCIN) 8 Rx IQ 4 REF-8 MUX 8 Rx SYNC I INPUT ADC Q INPUT ADC ⴜ2 Rx - ITF REF-10 (fOSCIN) 10 Rx IF 12 IF10 INPUT ADC MUX 12 IF12 INPUT MUX ADC VIDEO INPUT CLAMP LEVEL DAC REF-12 Figure 1. Block Diagram –20– REV. 0 AD9873 Transmit Section Modulation Mode Operation The AD9873 accepts 6-bit words, which are strobed synchronous to the master clock MCLK into the Data Assembler. Tx SYNC signals the start of a transmit symbol. Two successive 6-bit words form a 12-bit symbol component. The incoming data is assumed to be complex, in that alternating 12-bit words are regarded as the inphase (I) and quadrature (Q) components of a symbol. Symbol components are assumed to be in two’s complement format. The rate at which the 6-bit words are presented to the AD9873 will be referred to as the master clock rate (fMCLK). The Data Assembler splits the incoming data words into separate I/Q data streams. The rate at which the I/Q data word pairs appear at the output of the Data Assembler will be referred to as the I/Q Sample Rate (fIQCLK). Since two 6-bit input data words are used to construct each individual I and Q data paths, it should be apparent that the input 6-bit data rate fMCLK is four times the I/Q sample rate (fMCLK = 4 fIQCLK). Once through the Data Assembler, the I/Q data streams are fed through two half-band filters (half-band filters #1 and #2). The combination of these two filters results in a factor of four (4) increase of the sample rate. Thus, at the output of half-band filter #2, the sample rate is 4 fIQCLK. In addition to the sample rate increase, the half-band filters provide the low-pass filtering characteristic necessary to suppress the spectral images produced by the upsampling process. After passing through the half-band filter stages, the I/Q data streams are fed to a Cascaded Integrator-Comb (CIC) filter. This filter is configured as an interpolating filter, which allows further upsampling rates of 3 or 4. The CIC filter, like the half-bands, has a built-in low-pass characteristic. Again, this provides for suppression of the spectral images produced by the upsampling process. The digital quadrature modulator stage following the CIC filters is used to frequency-shift the baseband spectrum of the incoming data stream up to the desired carrier frequency (this process is known as upconversion). The carrier frequency is numerically controlled by a Direct Digital Synthesizer (DDS). The DDS uses its internal reference clock (fSYSCLK) to generate the desired carrier frequency with a high degree of precision. The carrier is applied to the I and Q multipliers in quadrature fashion (90 phase offset) and summed to yield a data stream that is at the modulated carrier. It should be noted at this point that the incoming symbols have been converted from an input sample rate of fIQCLK to an output sample rate of fSYSCLK (see Figure 1). The modulated carrier is ultimately destined to serve as the input to the digital-to-analog converter (DAC) integrated on the AD9873. The DAC output spectrum is distorted due to the intrinsic zeroorder hold effect associated with DAC-generated signals. This distortion is deterministic and follows the familiar SIN(X)/X (or SINC) envelope. Since the SINC distortion is predictable, it is also correctable. Hence, the presence of the optional Inverse SINC Filter preceding the DAC. This is a FIR filter, which has a transfer function conforming to the inverse of the SINC response. Thus, when selected, it modifies the incoming data stream so that the SINC distortion, which would otherwise appear in the DAC output spectrum, is virtually eliminated. REV. 0 Single-Tone Output Transmit Operation The AD9873 can be configured for frequency synthesis applications by writing the single-tone bit true, and applying a clock signal (e.g., Rx SYNC) to the Tx SYNC pin. In single-tone mode, the AD9873 disengages the modulator and preceding data path logic to output a spectrally pure single frequency sine wave. The AD9873 provides for a 24-bit frequency tuning word, which results in a tuning resolution of 12.9 Hz at a fSYSCLK rate of 216 MHz. A good rule of thumb when using the AD9873 as a frequency synthesizer is to limit the fundamental output frequency to 30% of fSYSCLK. This avoids generating aliases too close to the desired fundamental output frequency, thus minimizing the cost of filtering the aliases. All applicable programming features of the AD9873 apply when configured in single-tone mode. These features include: 1. Frequency hopping via the PROFILE inputs and associated tuning word, which allows Frequency Shift Keying (FSK) modulation. 2. Ability to bypass the SIN(x)/x compensation filter. 3. Power-down modes. OSC IN Clock Multiplier As mentioned earlier, the output data is sampled at the rate of fSYSCLK. Since the AD9873 is designed to operate at fSYSCLK frequencies up to 232 MHz, there is the potential difficulty of trying to provide a stable input clock fOSCIN. Although stable, high-frequency oscillators are available commercially, they tend to be cost prohibitive and create noise coupling issues on the printed circuit board. To alleviate this problem, the AD9873 has a built-in programmable clock multiplier and an oscillator circuit. This allows the use of a relatively low frequency (thus, less expensive) crystal or oscillator to generate the OSC IN signal. The low frequency OSC IN signal can then be multiplied in frequency by an integer factor of between 1 and 31, inclusive, to become the fSYSCLK clock. For DDS applications, the carrier is typically limited to about 30% of fSYSCLK. For a 65 MHz carrier, the recommended system clock is above 216 MHz. The OSC IN Multiplier function maintains clock integrity as evidenced by the AD9873’s system phase noise characteristics of –113 dBc/Hz. External loop filter components consisting of a series resistor (1.3 kΩ) and capacitor (0.01 F) provide the compensation zero for the CLK IN Multiplier PLL loop. The overall loop performance has been optimized for these component values. Receive Section The AD9873 includes four high-speed, high-performance ADCs. Two matched 8-bit ADCs are optimized for analog IQ demodulated signals and can be sampled with up to 16.5 MSPS. A direct IF 10-bit ADC and a 12-bit ADC can digitize signals at a maximum sampling frequency of 33 MSPS. Input signal selection to the 12-bit ADC can be programmed to either direct IF or video (NTSC/PAL). A programmable automatic clamp control provides black level offset correction for video signals. The ADC sampling frequency can either be derived directly from the OSC IN crystal or from the on-chip OSC IN Multiplier. For highest dynamic performance it is recommended to choose a OSC IN frequency that can be used to directly sample the ADCs. –21– AD9873 Digital 8-bit ADC outputs are multiplexed to one 4-bit bus, clocked by a frequency (fMCLK) of four times the sampling rate whereas the 10- and 12-bit ADCs are multiplexed together to one 12-bit bus clocked by fMCLK, which is two times their sampling frequency. (register address 00h). The MCLK signal (Pin 23) fMCLK is derived by dividing this PLL output frequency with the interpolation rate N of the CIC filter stages (register address 01h). CLOCK AND OSCILLATOR CIRCUITRY An external PLL loop filter (Pin 57) consisting of a series resistor and ceramic capacitor (Figure 15, R1 = 1.3 kΩ, C12 = 0.01 µF) is required for stability of the PLL. Also, a shield surrounding these components is recommended to minimize external noise coupling into the PLL’s voltage controlled oscillator input (guard trace connected to AVDD PLL). fSYSCLK = fOSC IN × M fMCLK = fOSC IN × M/N The AD9873’s internal oscillator generates all sampling clocks from a simple, low-cost, series resonance, fundamental frequency quartz crystal. Figure 2 shows how the quartz crystal is connected between OSC IN (Pin 61) and XTAL (Pin 60) with parallel resonant load capacitors as specified by the crystal manufacturer. The internal oscillator circuitry can also be overdriven by a TTL level clock applied to OSC IN with XTAL left unconnected. AVDD 1 DRGND 2 83 AGND 84 AVDD 85 REFB10 86 REFT10 87 AVDD 90 IF10+ 89 IF10– 88 AGND C4 C5 C6 0.1F 0.1F 0.1F 91 AGND C1 C2 C3 0.1F 0.1F 0.1F 93 REFB12 92 AVDD CP2 10F 95 AVDD 94 REFT12 CP1 10F 96 AGND 97 IF12– 99 AGND 98 IF12+ 100 VIDEO IN An internal phase locked loop (PLL) generates the DAC sampling frequency fSYSCLK by multiplying OSC IN frequency M times 81 Q IN– fOSC IN = fMCLK × N/M 82 Q IN+ Figure 1 shows that ADCs are either directly sampled by a lowjitter clock at OSC IN or by a clock that is derived from the PLL output. Operating modes can be selected in register address 08. Sampling the ADCs directly with the OSC IN clock requires MCLK to be programmed to be twice the OSC IN frequency. 80 AGND IQ PIN 1 IDENTIFIER DRVDD 3 (MSB) IF(11) 4 79 I IN+ 78 I IN– 77 AGND IQ IF(10) 5 76 REFT8 IF(9) 6 75 REFB8 IF(8) 7 74 AGND IQ IF(7) 8 73 AVDD IQ IF(6) 9 72 DRVDD IF(5) 10 70 DRGND IF(3) 12 IF(2) 13 69 DGND SO 68 SDELTA0 CP3 10F C9 0.1F 67 SDELTA1 IF(1) 14 AD9873 IF(0) 15 66 DVDD SD TOP VIEW (Pins Down) (MSB) Rx IQ(3) 16 Rx IQ(2) 17 Rx IQ(1) 18 65 CA ENABLE 64 CA DATA 63 CA CLK 62 DVDD OSC Rx IQ(0) 19 20 61 OS IN DRGND 21 60 XTAL DRVDD 22 MLCK 23 59 DGND OSC 58 AGND PLL DVDD 24 57 PLL FILTER DGND 25 56 AVDD PLL 26 55 DVDD PLL (MSB) Tx IQ(5) 27 54 DGND PLL Tx SYNC C8 0.1F 71 REF CLK IF(4) 11 Rx SYNC C7 0.1F C13 0.1F C11 20pF GUARD TRACE R1 C12 1.3k⍀ 0.01F AGND Tx 50 FSADJ 49 PWRDOWN 47 REFIO 48 DVDD Tx 46 DGND Tx 45 SDO 44 CS 42 SDIO 43 SCLK 41 DGND 40 DVDD 38 DGND 39 RESET 37 PROFILE(0) 36 DGND 34 PROFILE(1) 35 51 Tx– DVDD 33 52 Tx+ Tx IQ(2) 30 Tx IQ(0) 32 53 AVDD Tx Tx IQ(3) 29 Tx IQ(1) 31 Tx IQ(4) 28 C10 20pF RSET 10k⍀ Figure 2. Basic Connections Diagram –22– REV. 0 AD9873 PROGRAMMABLE CLOCK OUTPUT REF CLK SERIAL INTERFACE FOR REGISTER CONTROL The AD9873 provides a frequency programmable clock output REF CLK (Pin 71). MCLK (fMCLK) and the master clock divider ratio R stored in register address 01h determine its frequency: The AD9873 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/ write access to all registers that configure the AD9873. Single or multiple byte transfers are supported as well as MSB first or LSB first transfer formats. The AD9873’s serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO). fREF CLK = fMCLK/R SIGMA-DELTA OUTPUTS The AD9873 contains two independent sigma-delta outputs that when low-pass filtered generate level programmable DC voltages of: VSD = (Sigma-Delta Code)/4096)(VLOGIC1) +VLOGIC0 (Influenced by CMOS logic output levels.) There are two phases to a communication cycle with the AD9873. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9873, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9873 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9873. 4096 ⴛ 8 tMCLK 8 tMCLK 000h 001h 002h 800h FFFh 8 tMCLK 4096 ⴛ 8 tMCLK Figure 3. Sigma-Delta Output Signals In cable modem set-top box applications the outputs can be used to control external variable gain amplifiers and RF tuners. A simple single-pole R-C low-pass filter provides sufficient filtering (see Figure 4). AD9873 SIGMA-DELTA 0 12 CONTROL WORD 0 R DC (0.4 TO DRVDD-0.6V) C MCLK ⴜ8 CONTROL WORD 1 R 12 SIGMA-DELTA 1 General Operation of the Serial Interface The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9873 and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. Instruction Byte The instruction byte contains the following information as shown in Table II: DC (0.4 TO DRVDD-0.6V) Table II. Instruction Byte Information C MSB TYPICAL: R = 50k⍀ C = 0.01F f–3dB = 1/(2RC) = 318Hz Figure 4. Sigma-Delta RC Filter In more demanding applications where additional gain, level-shift or drive capability is required, a first or second order active filter might be considered for each sigma-delta output (see Figure 5). C AD9873 SIGMA-DELTA R1 I6 I5 I4 I3 I2 I1 I0 R/W N1 N0 A4 A3 A2 A1 A0 R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic zero indicates a write operation. N1, N0, Bits 6 and 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in the Table III. R Table III. Decode Bits R C R VOFFSETREF OP250 VDC = (VSD /2 + VOFFSETREF) (1 + R/R1) GAIN = (1 + R/R1)/ 2 VOFFSET = VOFFSETREF (1 + R/R1) TYPICAL: R = 50k⍀ C = 0.01F f–3dB = 1/(2RC) = 318Hz Figure 5. Sigma-Delta Active Filter With Gain and Offset REV. 0 LSB I7 N1 N0 Description 0 0 1 1 0 1 0 1 Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes A4, A3, A2, A1, A0, Bits 4, 3, 2, 1, 0, of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9873. –23– AD9873 Serial Interface Port Pin Description SCLK—Serial Clock. The serial clock pin is used to synchronize data to and from the AD9873 and to run the internal state machines. SCLK maximum frequency is 15 MHz. All data input to the AD9873 is registered on the rising edge of SCLK. All data is driven out of the AD9873 on the falling edge of SCLK. CS—Chip Select. Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins will go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. A write to Bits 1, 2, and 3 of address 00h with the same logic levels as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary), allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to address 00h with RESET bit low and serial port configuration as specified above (XY) reprograms the OSC IN Multiplier setting. A changed fSYSCLK frequency is stable after a maximum of 200 fMCLK cycles (= Wake–Up Time). INSTRUCTION CYCLE CS DATA TRANSFER CYCLE SCLK SDIO—Serial Data I/O. Data is always written into the AD9873 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of register address 0h. The default is logic zero, which configures the SDIO pin as unidirectional. SDIO R/W I6(n) I5(n) I4 I3 I2 I1 I0 D7n D6n D20 D10 D00 D7n D6n D20 D10 D00 SDO Figure 6a. Serial Register Interface Timing MSB-First SDO—Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9873 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. SCLK MSB/LSB Transfers SDIO INSTRUCTION CYCLE CS The AD9873 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by register address, 0h, Bit 6. The default is MSB first. When this bit is set active high, the AD9873 serial port is in LSB first format. That is, if the AD9873 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the most significant byte. In MSB first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. Multibyte data transfers in LSB first format can be completed by writing an instruction byte that includes the register address of the least significant byte. In LSB first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. I0 I1 I2 I3 DATA TRANSFER CYCLE I4 I5(n) I6(n) R/W D00 D10 D20 D6n D7n D00 D10 D20 D6n D7n SDO Figure 6b. Serial Register Interface Timing LSB-First CS t SCLK t DS t PWH t PWL SCLK t DS SDIO t DH INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 7. Timing Diagram for Register Write to AD9873 CS The AD9873 serial port controller address will increment from 1Fh to 00h for multibyte I/O operations if the MSB first mode is active. The serial port controller address will decrement from 00h to 1Fh for multibyte I/O operations if the LSB first mode is active. SCLK t DV SDIO SDO DATA BIT n DATA BIT n–1 Figure 8. Timing Diagram for Register Read from AD9873 Notes on Serial Port Operation The AD9873 serial port configuration bits reside in Bits 6 and 7 of register address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of a communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply to setting the reset bit in register address 00h. All other registers are set to their default values, but the software reset does not affect the bits in register address 00h. TRANSMIT PATH (Tx) Transmit Timing The AD9873 provides a master clock MCLK and expects 6-bit multiplexed Tx IQ data on each rising edge. Transmit symbols are framed with the Tx SYNC input. Tx SYNC high indicates the start of a transmit symbol. Four consecutive 6-bit data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB). Data Assembler It is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset. The input data stream is representative complex data. Two 6-bit words form a 12-bit symbol component (two’s complement format). Four input samples are required to produce one I/Q data pair. The I/Q sample rate fIQCLK at the input to the first half-band filter is a quarter of the input data rate fMCLK. –24– REV. 0 AD9873 t SU MCLK t HD Tx SYNC Tx IQ TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6]' TxI[5:0]' TxQ[11:6]' TxQ[5:0]' TxI[11:6]" TxI[5:0]" Figure 9. Transmit Timing Diagram The I/Q sample rate fIQCLK puts a bandwidth limit on the maximum transmit spectrum. This is the familiar Nyquist limit and is equal to one-half fIQCLK which hereafter will be referred to as fNYQ. 3 1 R −1 1 1 − z−R = ∑ z−k H(z ) = −1 R − z R 1 k = 0 Half-Band Filters (HBFs) 3 The transfer function is given by: HBF 1 is a 15-tap filter that provides a factor-of-two increase in sampling rate. HBF 2 is an 11-tap filter offering an additional factor-of-two increase in sampling rate. Together, HBF 1 and 2 provide a factor-of-four increase in the sampling rate (4 fIQCLK or 8 fNYQ). 3 1 sin( π f R ) 1 1 − e − j (2 π f R ) = H( f ) = − j 2πf R sin( π f ) R 1− e 3 In relation to phase response, both HBFs are linear phase filters. As such, virtually no phase distortion is introduced within the passband of the filters. This is an important feature as phase distortion is generally intolerable in a data transmission system. The frequency response in this form is such that “f ” is scaled to the output sample rate of the CIC filter. That is, f = 1 corresponds to the frequency of the output sample rate of the CIC filter. H(f/R) will yield the frequency response with respect to the input sample of the CIC filter. Cascaded Integrator—COMB (CIC) Filter Combined Filter Response A CIC filter is unlike a typical FIR filter in that it offers the flexibility to handle differing input and output sample rates (only in integer ratios, however). In the purest sense, a CIC filter can provide either an increase or a decrease in sample rate at the output relative to the input, depending on the architecture. If the integration stage precedes the comb stage, the CIC filter provides sample rate reduction (decimation). When the comb stage precedes the integrator stage, the CIC filter provides an increase in sample rate (interpolation). In the AD9873, the CIC filter is configured as a programmable interpolator and provides a sample rate increase by a factor of R = 3 or R = 4. In addition to the ability to provide a change in sample rate between input and output, a CIC filter also has an intrinsic low-pass frequency response characteristic. The frequency response of a CIC filter is dependent on three factors: 1. The rate change ratio, R. 2. The order of the filter, n. 3. The number of unit delays per stage, m. It can be shown that the system function H(z), of a CIC filter is given by: n 1 Rm −1 1 1 − z − Rm = ∑ z−k H(z ) = −1 R k = 0 R 1− z n The form on the far right has the advantage of providing a result for z = 1 (corresponding to zero frequency or dc). The alternate form yields an indeterminate form (0/0) for z = 1, but is otherwise identical. The only variable parameter for the AD9873’s CIC filter is R; m and n are fixed at 1 and 3, respectively. Thus, the CIC system function for the AD9873 simplifies to: The combined frequency response of HBF 1, HBF 2 and CIC is shown in Figure 10a to 10c and Figure 11a to 11c. The usable bandwidth of the filter chain puts a limit on the maximum data rate that can be propagated through the AD9873. A look at the passband detail of the combined filter response (Figure 10d and Figure 11d) indicates that in order to maintain an amplitude error of no more than 1 dB, we are restricted to signals having a bandwidth of no more than about 60% of fNYQ. Thus, in order to keep the bandwidth of the data in the flat portion of the filter passband, the user must oversample the baseband data by at least a factor of two prior to presenting it to the AD9873. Note that without oversampling, the Nyquist bandwidth of the baseband data corresponds to the fNYQ. As such, the upper end of the data bandwidth will suffer 6 dB or more of attenuation due to the frequency response of the digital filters. Furthermore, if the baseband data applied to the AD9873 has been pulse-shaped, there is an additional concern. Typically, pulse-shaping is applied to the baseband data via a filter having a raised cosine response. In such cases, an α value is used to modify the bandwidth of the data where the value of α is such that 0 ≤ α ≤ 1. A value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth. A value of 1 causes the data bandwidth to be extended to twice the Nyquist bandwidth. Thus, with 2× oversampling of the baseband data and α = 1, the Nyquist bandwidth of the data will correspond with the I/Q Nyquist bandwidth. As stated earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of the filters. The maximum value of α that can be implemented is 0.45. This is because the data bandwidth becomes: 1/2(1+ α) fNYQ = 0.725 fNYQ, which puts the data bandwidth at the extreme edge of the flat portion of the filter response. REV. 0 –25– AD9873 The combined HB1, HB2, and CIC filter introduces, over the frequency range of the data to be transmitted, a worst-case droop of less than 0.2 dB. 10 10 0 0 –10 –10 –20 –20 MAGNITUDE – dB MAGNITUDE – dB If a particular application requires an α value between 0.45 and 1, the user must oversample the baseband data by at least a factor of four. –30 –40 –50 –50 –60 –70 –70 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY – FS/2 0.8 0.9 –80 0 1.0 Figure 10a. Cascaded Filter 12 × Interpolator (N = 3) 10 10 0 0 –10 –10 –20 –20 –30 –40 –50 –70 0.3 0.4 0.5 0.6 0.7 FREQUENCY – FS/2 0.8 0.9 –80 0 1.0 Figure 10b. Input Signal Spectrum (N = 3), α = 0.25 0 0 –10 –10 –20 –20 MAGNITUDE – dB 10 –30 –40 –50 –70 0.4 0.5 0.6 0.7 FREQUENCY – FS/2 0.8 0.9 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY – FS/2 0.8 0.9 1.0 –50 –70 0.3 1.0 –40 –60 0.2 0.9 –30 –60 0.1 0.8 Figure 11b. Input Signal Spectrum (N = 4), α = 0.25 10 –80 0 0.4 0.5 0.6 0.7 FREQUENCY – FS/2 –50 –70 0.2 0.3 –40 –60 0.1 0.2 –30 –60 –80 0 0.1 Figure 11a. Cascaded Filter 16 × Interpolator (N = 4) MAGNITUDE – dB MAGNITUDE – dB –40 –60 –80 0 MAGNITUDE – dB –30 –80 0 1.0 Figure 10c. Response to Input Signal Spectrum (N = 3) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY – FS/2 0.8 0.9 1.0 Figure 11c. Response to Input Signal Spectrum (N = 4) –26– REV. 0 1 1 0 0 –1 –1 MAGNITUDE – dB MAGNITUDE – dB AD9873 –2 –3 –2 –3 –4 –4 –5 –5 –6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 FREQUENCY RELATIVE TO I/Q NYQ. BW 0.9 –6 0 1.0 Figure 10d. Cascaded Filter Passband Detail (N = 3) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 FREQUENCY RELATIVE TO I/Q NYQ. BW 0.9 1.0 Figure 11d. Cascaded Filter Passband Detail (N = 4) Inverse SINC Filter (ISF) The AD9873 transmit section is almost entirely digital. The input “signal” is made up of a time series of digital data words. These data words propagate through the device as numbers. Ultimately, this number stream must be converted to an analog signal. To this end, the AD9873 incorporates an integrated DAC. The output waveform of the DAC is the familiar “staircase” pattern typical of a signal that is sampled and quantized. The staircase pattern is a result of the finite time that the DAC holds a quantized level until the next sampling instant. This is known as a zero-order hold function. The spectrum of the zero-order hold function is the familiar SIN(x)/x, or SINC, envelope. The series of digital data words presented at the input of the DAC represent an impulse stream. It is the spectrum of this impulse stream, which is the characteristic of the desired output signal. Due to the zero-order hold effect of the DAC, however, the output spectrum is the product of the zero-order hold spectrum (the SINC envelope) and the Fourier transform of the impulse stream. Thus, there is an intrinsic distortion in the output spectrum, which follows the SINC response. 0.1 The SINC response is deterministic and totally predictable. Thus, it is possible to predistort the input data stream in a manner, which compensates for the SINC envelope distortion. This can be accomplished by means of an ISF. The ISF incorporated on the AD9873 is a 5-tap, linear phase FIR filter. Its frequency response characteristic is the inverse of the SINC envelope and it equalizes the SINC droop up to 0.6 times the Nyquist frequency. Figure 12a and Figure 12b show the effectiveness of the ISF in correcting for the SINC distortion. Figure 12a includes a graph of the SINC envelope and ISF response while Figure 12b shows the SYSTEM response (which is the product of the SINC and ISF responses). It should be mentioned at this point that the ISF exhibits an insertion loss of 1.4 dB. Thus, signal levels at the output of the AD9873 with the ISF bypassed are 1.4 dB higher than with the ISF engaged. However, for modulated output signals, which have a relatively wide bandwidth, the benefits of the SINC compensation usually outweighed the 1.4 dB loss in output level. The decision of whether or not to use the ISF is an application specific system design issue. 1.0 1.35 0.5 1.36 1.37 –0.5 1.38 MAGNITUDE – dB MAGNITUDE – dB ISF 0 –1.0 –1.5 –2.0 SINC 1.39 1.40 1.41 –2.5 1.42 –3.0 1.43 –3.5 1.44 –4.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY – FS/2 0.8 0.9 1.45 0 1.0 Figure 12a. SINC and ISF Filter Response REV. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY – FS/2 0.8 0.9 Figure 12b. SINC Compensated Response –27– 1.0 AD9873 If INV SINC filter is enabled, an insertion loss of ~1.4 dB (for low frequencies) occurs at the DAC output (see Figure 12a, 12b). Q Programming the AD9873 to single-tone transmit mode while disabling the INV SINC filter (address 0Fh) generates a maximum (FS) amplitude single tone with a frequency (fc) determined by the associated frequency tuning word. Z X I X Table IV shows typical I–Q input test signals with amplitude levels related to 12-bit full scale (FS). Tx Throughput and Latency Figure 13. 16-Quadrature Modulation Data inputs effect the output fairly quickly but remain effective due to AD9873’s filter characteristics. Data transmit latency through the AD9873 is easiest to describe in terms of fSYSCLK clock cycles (4 fMCLK). The numbers quoted are when an effect is first seen after an input value change. Tx Signal Level Considerations The quadrature modulator itself introduces a maximum gain of 3 dB in signal level. To visualize this, assume that both the I data and Q data are fixed at the maximum possible digital value, x. Then the output of the modulator, z, is: Latency of I/Q data entering the data assembler (AD9873 input) to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK cycles). DC values applied to the data assembler input will take up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to propagate and settle at the DAC output. Enabling the Inverse SINC Filter adds only 2 fSYSCLK clock cycles latency. z = [x cos(ωt) – x sin(ωt)] It can be shown that z assumes a maximum value of z = (x 2 ) + x 2 = x 2 (a gain of +3 dB). However, if the same Frequency hopping is accomplished via changing the PROFILE input pins. The time required to switch from one frequency to another is less than 234 fSYSCLK cycles with the Inverse SINC Filter engaged. With the Inverse SINC Filter bypassed, the latency drops to less than 232 fSYSCLK cycles (58.5 fMCLK cycles). number of bits were used to represent the z values, as is used to represent the x values, an overflow would occur. To prevent this possibility, an effective –3 dB attenuation is internally implemented on the I and Q data path. z = (1 / 2 + 1 / 2) = x D/A Converter A 12-bit digital-to-analog converter (DAC) is used to convert the digitally processed waveform into an analog signal. The worstcase spurious signals due to the DAC are the harmonics of the fundamental signal and their aliases. (Please see the AD9851 data sheet for a detailed explanation of aliased images.) The wideband 12-bit DAC in the AD9873 maintains spurious-free dynamic range (SFDR) performance of 59 dBc up to fOUT = 42 MHz and 54 dBc up to fOUT = 65 MHz. The conversion process will produce aliased components of the fundamental signal at n fSYSCLK fCARRIER (n = 1, 2, 3). These are typically filtered with an external RLC filter at the DAC output. It is important for The following example assumes a Pk/rms level of 10 dB: Maximum Symbol Component Input Value = (2047 LSBs – 0.2 dB) = 2000 LSBs Maximum Complex Input rms Value = 2000 LSBs + 6 dB – Pk/rms(dB) = 1265 LSBs rms Maximum Complex Input rms Value calculation uses both I and Q symbol components which adds a factor of 2 (= 6 dB) to the formula. +0.2dB 12 I COMPLEX DATA INPUT 12 O 0dB –3dB HBF + CIC INTERPOLATOR I I ATTENUATOR +0.2dB 1.4dB –3dB HBF + CIC INTERPOLATOR O 12 MODULATOR 3dB MAX ATTENUATOR INV SINC FILTER DAC O TWO'S COMPLEMENT FORMAT Figure 14. Signal Level Contribution Table IV. I–Q Input Test Signals Single-Tone (fc – f) Single-Tone (fc + f) Dual-Tone (fc f) I = cos(f) Q = cos(f + 90) = –sin(f) I = cos(f) Q = cos(f + 270) = sin(f) I = cos(f) Q = cos(f + 180) = –cos(f) or Q = cos(f) –28– Input Level Modulator Output Level FS – 0.2 dB FS – 0.2 dB FS – 0.2 dB FS – 0.2 dB FS – 0.2 dB FS – 0.2 dB FS – 3.0 dB FS – 3.0 dB FS REV. 0 AD9873 this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest to avoid modulation impairments. A relatively inexpensive fifth order elliptical low-pass filter is sufficient to suppress the aliased components for HFC network applications. AD832x DAC AD9873 CA The AD9873 provides true and complement current outputs. The full-scale output current is set by the RSET resistor at Pin 49. The value of RSET for a particular IOUT is determined using the following equation: The full-scale output current range of the AD9873 is 2 mA to 20 mA. Full-scale output currents outside of this range will degrade SFDR performance. SFDR is also slightly affected by output matching, that is, the two outputs should be terminated equally for best SFDR performance. The output load should be located as close as possible to the AD9873 package to minimize stray capacitance and inductance. The load may be a simple resistor to ground, an op amp current-to-voltage converter, or a transformer-coupled circuit. It is best not to attempt to directly drive highly reactive loads (such as an LC filter). Driving an LC filter without a transformer requires that the filter be doubly terminated for best performance, that is, the filter input and output should both be resistively terminated with the appropriate values. The parallel combination of the two terminations will determine the load that the AD9873 will see for signals within the filter passband. For example, a 50 Ω terminated input/output low-pass filter will look like a 25 Ω load to the AD9873. The output compliance voltage of the AD9873 is –0.5 V to +1.5 V. Any signal developed at the DAC output should not exceed +1.5 V, otherwise, signal distortion will result. Furthermore, the signal may extend below ground as much as 0.5 V without damage or signal distortion. The AD9873 true and complement outputs can be differentially combined for common mode rejection using a broadband 1:1 transformer. Using a grounded center-tap results in signals at the AD9873 DAC output pins that are symmetrical about ground. As previously mentioned, by differentially combining the two signals the user can provide some degree of common mode signal rejection. A differential combiner might consist of a transformer or an operational amplifier. The object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such as 60 Hz hum or “clock feedthrough” that is equally present on both individual signals. Connecting the AD9873 true and complement outputs to the differential inputs of the gain programmable cable drivers AD8321 or AD8323 provides an optimized solution for the standard compliant cable modem upstream channel. The cable driver’s gain can be programmed through a direct 3-wire interface using the AD9873’s profile registers. REV. 0 75⍀ 3 CA_ENABLE CA_DATA CA_CLK VARIABLE GAIN CABLE DRIVER AMPLIFIER Figure 15. Cable Amplifier Connection RSET = 32 VDACRSET/IOUT = ~ 39.4/IOUT For example, if a full-scale output current of 20 mA is desired, then RSET = (39.4/0.02) Ω, or approximately 2 kΩ. Every doubling of the RSET value will halve the output current. Maximum output current is specified as 20 mA. LOW-PASS FILTER Tx 8 t MCLK 8 t MCLK 8 t MCLK 4 t MCLK 4 t MCLK CA ENABLE CA_CLK CA_DATA MSB LSB Figure 16. Cable Amplifier Interface Timing PROGRAMMING/WRITING THE AD8321/AD8323 CABLE DRIVER AMPLIFIER GAIN CONTROL Programming the gain of the AD832x-family cable driver amplifier can be accomplished via the AD9873 cable amplifier control interface. Four 8-bit registers within the AD9873 (one per profile) store the gain value to be written to the serial 3-wire port. Data transfers to the gain programmable cable driver amplifier are initiated by four conditions. Each is described below: 1. Power-up and Hardware Reset—Upon initial power-up and every hardware reset, the AD9873 clears the contents of the gain control registers to 0, which defines the lowest gain setting of the AD832x. Thus, the AD9873 writes all 0s out of the 3-wire cable amplifier control interface. 2. Software Reset—Writing a one to Bit 5 of address 00h initiates a software reset. On a software reset the AD9873 clears the contents of the gain control registers to 0 for the lowest gain and sets the profile select to 0. The AD9873 writes all 0s out of the 3-wire cable amplifier control interface if the gain was on a different setting (different from 0) before. 3. Change in Profile Selection—The AD9873 samples the PROFILE[0], PROFILE[1] input pins together with the two profile select bits and writes to the AD832x gain control registers when a change in profile and gain is determined. The data written to the cable driver amplifier comes from the AD9873 gain control register associated with the current profile. 4. Write to AD9873 Cable Driver Amplifier Control Registers – The AD9873 will write gain control data associated with the current profile to the AD832x whenever the selected AD9873 cable driver amplifier gain setting is changed. Once a new stable gain value has been detected (48 to 64 MCLK cycles after initiation) data write starts with CA_ENABLE going low. The AD9873 will always finish a write sequence to the cable driver amplifier once it is started. The logic controlling data transfers to the cable driver amplifier uses up to 200 MCLK cycles and has been designed to prevent erroneous write cycles from occurring. –29– AD9873 RECEIVE PATH (Rx) ADC Theory of Operation every second 10-bit ADC data (if 8-bit ADC is not in powerdown mode). The AD9873’s analog-to-digital converters implement pipelined multistage architectures to achieve high sample rates while consuming low power. Each ADC distributes the conversion over several smaller ADC subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, ADCs require a small fraction of the 2N comparators used in a traditional n-bit flash-type ADC. A sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. Driving the Analog Inputs AINP AINN A/D SHA A/D SHA D/A A/D GAIN D/A AD9873 CORRECTION LOGIC Figure 17. ADC Architecture The analog inputs of the AD9873 incorporate a novel structure that merges the input sample and hold amplifiers (SHA), and the first pipeline residue amplifiers into single, compact switchedcapacitor circuits. This structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline. By matching the sampling network of the input SHA with the first stage flash ADC, the ADCs can sample inputs well beyond the Nyquist frequency with no degradation in performance. Figure 19 illustrates the equivalent analog inputs of the AD9873, (a switched capacitor input). Bringing CLK to a logic high, opens Switch 3 and closes Switches S1 and S2. The input source is connected to AIN and must charge capacitor CH during this time. Bringing CLK to a logic low opens S2, and then Switch 1 opens followed by closing S3. This puts the input in the hold mode. AD9873 AINP CH S1 2k⍀ VBIAS CP CH S3 2k⍀ S2 CP AINN Figure 19. Differential Input Architecture The structure of the input SHA places certain requirements on the input drive source. The combination of the pin capacitance, and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to its n-bit accuracy in one-half of a clock cycle. When the SHA goes into track mode, the input source must charge or discharge capacitor CH from the voltage already stored on CH to the new voltage. In the worst case, a full-scale voltage step on the input source must provide the charging current through the RON (100 Ω) of Switch 1 and quickly (within 1/2 CLK period) settle. This situation corresponds to driving a low input impedance. On the other hand, when the source voltage equals the value previously stored on CH, the hold capacitor requires no input current and the equivalent input impedance is extremely high. Adding series resistance between the output of the signal source and the AIN pin reduces the drive requirements placed on the signal source. Figure 20 shows this configuration. < 50⍀ VS AINP SHUNT < 50⍀ The digital data outputs of the ADCs are represented in straight binary format. They saturate to full scale or zero when the input signal exceeds the input voltage range. AINN Figure 20. Simple ADC Drive Configuration Receive Timing The AD9873 sends multiplexed data to the Rx IQ and IF outputs on every rising edge of MCLK. Rx SYNC frames the start of each Rx IQ data Symbol. Both 8-bit ADCs transfer their data within four MCLK cycles using 4-bit data packages (I MSB, I LSB, Q MSB and Q LSB). 10-bit and 12-bit ADCs are completely read on every second MCLK cycle. Rx SYNC is high for The bandwidth of the particular application limits the size of this resistor. To maintain the performance outlined in the data sheet specifications, the resistor should be limited to 50 Ω or less. For applications with signal bandwidths less than 10 MHz, the user may proportionally increase the size of the series resistor. Alternatively, adding a shunt capacitance between the AIN pins can t HT MCLK t TV Rx SYNC Rx IQ IF RxI[7:4] RxI[3:0] RxQ[7:4] RxQ[3:0] RxI[7:4]' RxI[3:0]' RxQ[7:4]' RxQ[3:0]' RxI[7:4]" RxI[3:0]" IF-10 [11:2] IF-12 [11:0] IF-10 [11:2]' IF-12 [11:0]' IF-10 [11:2]" IF-12 [11:0]" IF-10 [11:2]''' IF-12 [11:0]''' IF-10 [11:2]"" IF-12 [11:0]"" Figure 18. Receive Timing Diagram –30– REV. 0 AD9873 lower the ac load impedance. The value of this capacitance will depend on the source resistance and the required signal bandwidth. In systems that must use dc coupling, use an op amp to comply with the input requirements of the AD9873. AD9873 R AINP C R1 AINN Op Amp Selection Guide Op amp selection for the AD9873 is highly application-dependent. In general, the performance requirements of any given application can be characterized by either time domain or frequency domain constraints. In either case, one should carefully select an op amp that preserves the performance of the ADC. This task becomes challenging when one considers the AD9873’s high-performance capabilities, coupled with other system-level requirements such as power consumption and cost. The ability to select the optimal op amp may be further complicated either by limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer high-performance op amps typically have input and output range limitations in accordance with their lower supply voltages. As a result, some op amps will be more appropriate in systems where ac-coupling is allowed. When dc-coupling is required, op amps’ headroom constraints (such as rail-to-rail op amps) or ones where larger supplies can be used, should be considered. Analog Devices offers differential output operational amplifiers like the AD8131 or AD8132. They can be used for differential or single-ended-to-differential signal conditioning with 8-bit performance to directly drive ADC inputs. The AD8138 is a higher performance version of the AD8132. It provides 12-bit performance and allows different gain settings. Please contact the factory or local sales office for updates on Analog Devices’ latest amplifier product offerings. ADC Differential Inputs The AD9873 uses 1 V p-p input span for the 8-bit ADC inputs and 2 V p-p for the 10- and 12-bit ADCs. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. In systems that do not need a dc input, an RF transformer with a center tap is the best method to generate differential inputs beyond 20 MHz for the AD9873. This provides all the benefits of operating the ADC in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the ADC. An improvement in THD and SFDR performance can be realized by operating the AD9873 in differential mode. The performance enhancement between the differential and single-ended mode is most considerable as the input frequency approaches and goes beyond the Nyquist frequency (i.e., fIN > FS/2). SINGLE-ENDED ANALOG INPUT R1 R2 AD9873 Figure 22. Transformer-Coupled Input Figure 22 shows the schematic of a suggested transformer circuit. Transformers with turns ratios (n2/n1) other than one may be selected to optimize the performance of a given application. For example, selecting a transformer with a higher impedance ratio (e.g., Mini-Circuits T16–6T with an impedance ratio of (z2/z1) = 16 = (n2/n1)2) effectively “steps up” the signal amplitude, thus further reducing the driving requirements of the signal source. In Figure 22, a resistor, R1, is added between the analog inputs to match the source impedance R as in the formula R1储4 kV = (z2/z1) R. ADC Voltage References The AD9873 has three independent internal references for its 8-bit, 10-bit, and 12-bit ADCs. Both 8-bit ADCs have a 1 V p-p input and share one internal reference source. The 10-bit and 12-bit ADCs, however, are designed for 2 V p-p input voltages with each of them having their own internal reference. Figure 15 shows the proper connections of the reference pins REFT and REFB. External references may be necessary for systems that require high accuracy gain matching between ADCs or improvements in temperature drift and noise characteristics. External references REFT and RFB need to be centered at AVDD/2 with offset voltages as specified: REFT-8: AVDDIQ/2 + 0.25 V REFB-8: AVDDIQ/2 – 0.25 V REFT-10, -12: AVDD/2 + 0.5 V REFB-10, -12: AVDD/2 – 0.5 V A differential level of 0.5 V between the reference pins results in a 1 V p-p ADC input level AIN. A differential level of 1 V between the reference pins results in a 2 V p-p ADC input level AIN. Internal reference sources can be powered down when external references are used (Register Address 02h). Video Input For sampling video-type waveforms, such as NTSC and PAL signals, the Video Input channel provides black level clamping. Figure 23 shows the circuit configuration for using the video channel input (Pin 100). An external blocking capacitor is used with the on-chip video clamp circuit, to level-shift the input signal to a desired reference level. The clamp circuit automatically senses the most negative portion of the input signal, and adjusts the voltage across the input capacitor. This forces the black level of the input signal to be equal to the value programmed into the clamp level register (register address 07h). AINP AD8131 R1 R2 CLAMP LEVEL + FS/2 AINN AD9873 CLAMP LEVEL VIDEO INPUT Figure 21. Single-Ended-to-Differential Input Drive BUFFER 12 The AD8131 provides a convenient method of converting a singleended signal to a differential signal. This is an ideal method for generating a direct coupled signal to the AD9873. The AD8131 will accept a signal swinging below 0 V and shift it to an externally provided common-mode voltage. The AD8131 configuration is shown in Figure 21. REV. 0 CLAMP LEVEL 0.1F ADC 2A LPF DAC OFFSET Figure 23. Video Clamp Circuit Input –31– AD9873 81 Q IN– 82 Q IN+ 83 AGND 84 AVDD 85 REFB10 86 REFT10 87 AVDD 88 AGND 90 IF10+ 89 IF10– 91 AGND 93 REFB12 92 AVDD 95 AVDD 94 REFT12 96 AGND 97 IF12– 99 AGND 98 IF12+ 100 VIDEO IN AGND AVDD 1 80 AGND IQ 0.1F DRGND 2 DRVDD 3 (MSB) IF(11) 4 0.1F 10F 0.1F 0.1F 79 I IN+ 78 I IN– 0.1F 77 AGND IQ IF(10) 5 AD9873 IF(9) 6 MQFP TOP VIEW (Pins Down) IF(8) 7 76 REFT8 75 REFB8 74 AGND IQ 0.1F 10F IF(7) 8 73 AVDD IQ IF(6) 9 72 DRVDD IF(5) 10 10F 71 REF CLK 0.1F IF(4) 11 70 DRGND IF(3) 12 69 DGND SD IF(2) 13 10F 68 SDELTA0 67 SDELTA1 0.1F IF(1) 14 IF(0) 15 (MSB) Rx IQ(3) 16 66 DVDD SD Rx IQ(2) 17 64 CA DATA 63 CA CLK 65 CA_ENABLE Rx IQ(1) 18 Rx SYNC 20 DRGND 21 0.1F EXTERNAL POWER SUPPLY DECOUPLING Rx IQ(0) 19 VDR VAS 62 DVDD OSC 61 OSCIN 10F 0.1F OSC GND 60 XTAL DRVDD 22 59 DGND OSC 58 AGND PLL MLCK 23 VDS AGND IQ 0.1F DVDD 24 0.01F 57 PLL FILTER DGND 25 56 AVDD PLL Tx SYNC 26 (MSB) Tx IQ(5) 27 55 DVDD PLL 0.01F 0.1F 54 DGND PLL 10F Tx IQ(4) 28 53 AVDD Tx 0.1F Tx IQ(3) 29 Tx IQ(2) 30 10F 0.1F 0.1F 0.1F 0.01F 52 Tx+ 51 Tx– AGND Tx 50 FSADJ 49 PWR DOWN 47 REF IO 48 DVDD Tx 46 DGND Tx 45 SDO 44 CS 42 SDIO 43 SCLK 41 DGND 40 DVDD 38 DGND 39 RESET 37 PROFILE(0) 36 DGND 34 PROFILE(1) 35 DVDD 33 Tx IQ(0) 32 DGND Tx IQ(1) 31 0.01F Tx GND Figure 24. Power Supply Decoupling POWER AND GROUNDING CONSIDERATIONS In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection, placement, routing, supply bypassing, and grounding. Figure 24 illustrates proper power supply decoupling. Split-ground technique can be used to isolate digital and high-speed clock generation noise from the analog front ends. The analog front end may be further split to minimize crosstalk between the transmit and receive sections. Noise-sensitive video-IF signals can also be separated from the more robust IQ-ADC signal path. One common ground underneath the chip connects all ground splits and assures short distances for ground pin connections. Figure 24 uses two separate power supplies. VAS powers the analog and clock generation section of the chip while VDS is used for the digital signals of the chip. An extra power supply VDR is only needed in applications that require lower level digital outputs. D RVDD and DVDD pins should be connected together for normal mode. VDS (and VDR) should not be directly connected to the power supply of noisy digital signal processing chips. It might even be considered as an analog supply. Ferrite beads and 10 F decoupling capacitors isolate power supplies between functional blocks. Each supply pin is further decoupled with a 0.1 F multilayer ceramic capacitor that is mounted as close as possible to the pin. In the high-speed PLL and DAC sections additional 0.01 F capacitors may be required as shown in Figure 24. –32– REV. 0 AD9873 Software EVALUATION BOARD Hardware The AD9873-EB is an evaluation board for the AD9873 analog front end converter. Careful attention to layout and circuit design allow the user to easily and effectively evaluate the AD9873 in any application where high-resolution, and high-speed conversion is required. This board allows the user flexibility to operate the AD9873 in various configurations. Several jumper or solder bridge settings are available. The ADC inputs can be differentially driven by transformers or by an AD8138 when using connector J8 as the only input. Differential to single-ended transmit output options include direct transformer coupled or filtered (75 MHz) and variable gain amplified by the AD8323. Digital transmit (Tx) inputs are designed to be driven from various word generators and allow for proper load termination. The AD9873-EB software provides a graphical user interface that allows easy programming and read back of AD9873 register settings. Three programming windows are available. The Direct register access window allows AD9873 register write and readback in decimal, binary or hexadecimal data format. The register map window provides a very easy, function orientated programming of AD9873 bits and registers. Programming hints appear when the cursor is moved over an input field. Registers are updated on every WRITE button click. The advanced register access window allows programming of register access sequences. Figure 25. Evaluation Board Software REV. 0 –33– AD9873 Figure 26. Evaluation Board Schematic First Page, AD9873 and Analog Circuitry –34– REV. 0 –35– A B C D JP1 JUMPER 3 1 2 4 5 6 7 8 +5VACON 1 +3.3VACON + C2 C11 10uF - 10V + 10uF - 10V GND + 10uF - 10V C1 C5 GND + 10uF - 10V VccFIFO POWER CONN. J1 3VDriver 1 2 +3.3VDCON 3 3 C16 10uF - 10V Ferrite Bead L11 Ferrite Bead L10 Ferrite Bead L13 + +C15 10uF - 10V +C14 10uF - 10V +C13 10uF - 10V Ferrite Bead L12 +C12 10uF - 10V +C10 10uF - 10V +C9 10uF - 10V Ferrite Bead L9 Ferrite Bead L8 Ferrite Bead L6 Ferrite Bead L7 +C8 10uF - 10V +C7 10uF - 10V Ferrite Bead L5 +C6 10uF - 10V +C4 10uF - 10V +C3 10uF - 10V +C17 10uF - 10V Ferrite Bead L1 Ferrite Bead L4 Ferrite Bead L3 Ferrite Bead L2 2 GND GND GND +5VRX +5VTX DVDDTX AVDDTX DVDDPLL DVDDOSC AVDDPLL DVDDSD AVDDIQ AVDD DRVDD DVDD 3VD C41 0.1uF C82 0.01uF C81 0.01uF C80 0.01uF C35 0.1uF C79 0.01uF C34 0.1uF C33 0.1uF C32 0.1uF C23 0.1uF C22 0.1uF C21 0.1uF C45 0.1uF C44 0.1uF C43 0.1uF C42 0.1uF C37 0.1uF C36 0.1uF C26 0.1uF C25 0.1uF C24 0.1uF 3 x 74LCX541 deoupling C46 0.1uF C38 0.1uF C29 0.1uF C28 0.1uF C27 0.1uF C47 0.1uF C39 0.1uF C30 0.1uF 3 C48 0.1uF C40 0.1uF C31 0.1uF 2 x NC75Z04 decoupling 3 DVDD DRVDD AVDD AVDDIQ DVDDSD AVDDPLL DVDDOSC DVDDPLL AVDDTX DVDDTX AD8323 decoupling TP-LOOP TP10 TP-LOOP TP9 TP-LOOP TP8 TP-LOOP TP7 TP-LOOP TP6 TP-LOOP TP5 TP-LOOP TP4 TP-LOOP TP3 TP-LOOP TP2 TP-LOOP TP1 GND 3VD J2 4 DB25 J7 HEADER, RT ANG, 50 PIN D15 2 1 D14 4 3 D13 6 5 D12 8 7 D11 10 9 D10 12 11 D9 14 13 D8 16 15 D7 18 17 D6 20 19 D5 22 21 D4 24 23 D3 26 25 D2 28 27 D1 30 29 D0 32 31 CLK 34 33 SYNC 36 35 38 37 40 39 SDOut 42 41 SDIn 44 43 CSL 46 45 SCK 48 47 50 49 DIGITAL RECEIVE 4 R10 R11 CA_PD CA_SLEEP 3 Delay CLK CLK SYNC GND 22 R13 74LCX541 O8 GND O7 I8 O6 I7 O5 I6 O4 I5 O3 I4 O2 I3 O1 I2 OE2 I1 Vcc OE1 U2 74LCX541 O8 GND O7 I8 O6 I7 O5 I6 O4 I5 O3 I4 O2 I3 O1 I2 OE2 I1 Vcc OE1 U1 5 3VD 11 12 13 14 15 16 17 18 19 20 74LCX541 Parallel Printer Port Connector to PC (Male) 5 2 GND 10 9 8 7 6 5 4 3 2 1 GND GND GND GND GND GND 3VD 8 7 6 5 4 3 2 1 5 6 7 8 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 GND 1k RP7 22 OHM RES NET RP6 4 3 2 1 SDO 33 R1 RXSYNC MCLK RXSYNC MCLK RXIQ[3..0] IF[11..0] DUT_CONTROL GND J4 22 OHM RES NET RP4 IF3 8 IF2 7 IF1 6 5 IF0 RXIQ3 4 RXIQ2 3 RXIQ1 2 RXIQ0 1 22 OHM RES NET RP3 IF11 8 IF10 7 IF9 6 IF8 5 IF7 4 IF6 3 IF5 2 IF4 1 6 Figure 27. Evaluation Board Schematic Second Page, Power and Digital Circuitry Date: File: B Size 6 Revision A Sheet 2 of 2 Drawn By: Martin Kessler Analog Devices 14-Jul-2000 D:\AD9873\evalboard3\AD9873 Rev A.ddb Number AD9873 Evaluation Board - Power, Digital Title 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 NC7SZ04 U4 O8 GND O7 I8 O6 I7 O5 I6 O4 I5 O3 I4 O2 I3 O1 I2 OE2 I1 Vcc OE1 U3 4 Invert CLK 3VD 11 12 13 14 15 16 17 18 19 20 3VD 11 12 13 14 15 16 17 18 19 20 SJP2 1 22 OHM RES NET RP5 8 7 6 5 4 3 2 1 SDIO CS SCLK 9 10 11 12 13 14 15 16 3 GND 22 OHM RES NET RP2 8 7 6 5 4 3 2 1 GND 22 OHM RES NET RP1 8 7 6 5 4 3 2 1 SJP1 1 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 2 2 2 REV. 0 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 1 A B C D AD9873 AD9873 Figure 28. Evaluation Board PCB, Assembly Top Side Figure 29. Evaluation Board PCB, Top Layer –36– REV. 0 AD9873 Figure 30 Evaluation Board PCB, Ground Plane Figure 31. Evaluation Board PCB, Power Plane REV. 0 –37– AD9873 Figure 32. Evaluation Board PCB, Bottom Layer Figure 33. Evaluation Board PCB, Assembly Bottom Side –38– REV. 0 AD9873 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.921 (23.4) 0.906 (23.0) 0.791 (20.10) 0.787 (20.00) 0.783 (19.90) 0.134 (4.30) MAX 0.742 (18.85) TYP 80 51 81 50 0.486 (12.35) TYP 0.555 (14.10) 0.551 (14.00) 0.547 (13.90) TOP VIEW C01584–4.5–7/00 (rev. 0) 100-Lead Metric Quad Flatpack (MQFP) (S-100C) (PINS DOWN) 0.685 (17.4) 0.669 (17.0) PIN 1 31 100 30 1 0.029 (0.73) 0.023 (0.57) 0.015 (0.35) 0.009 (0.25) 0.110 (2.80) 0.102 (2.60) 0.041 (1.03) 0.031 (0.78) SEATING PLANE PRINTED IN U.S.A. 0.004 0.010 (0.10) (0.25) MAX MIN CONTROLLING DIMENSIONS ARE IN MILLIMETERS REV. 0 –39–