TC58V64BDC TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 TM 64-MBIT (8M ´ 8 BITS) CMOS NAND E PROM (8M BYTE SmartMedia ) DESCRIPTION The TC58V64B is a single 3.3-V 64-Mbit (69,206,016) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes ´ 16 pages ´ 1024 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (8 Kbytes + 256 bytes: 528 bytes ´ 16 pages). The TC58V64B is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. The data stored in the TC58V64BDC needs to comply with the data format standardized by the SSFDC Forum in order to maintain compatibility with other SmartMediaTM systems. FEATURES · · · · Organization Memory cell array 528 ´ 16K ´ 8 Register 528 ´ 8 Page size 528 bytes Block size (8K + 256) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read Mode control Serial input/output, Command control Complies with the SmartMediaTM Electrical Specification and Data Format Specification issued by the SSFDC Forum PIN ASSIGNMENT (TOP VIEW) WE VSS CLE ALE 1 2 3 WP 4 I/O1 I/O2 I/O3 I/O4 VSS VSS 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 · · · · · Power supply VCC = 3.3 V ± 0.3 V Program/Erase Cycles 1E5 cycle (with ECC) Access time Cell array-register 25 ms max Serial Read cycle 50 ns min Operating current Read (50-ns cycle) 10 mA typ. Program (avg.) 10 mA typ. Erase (avg.) 10 mA typ. Standby 100 mA max Package FDC-22A (Weight: 1.8 g typ.) PIN NAMES I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect RY/BY Ready/Busy GND Ground Input LVD Low Voltage Detect VCC Power supply VSS Ground TM VCC CE RE RY/BY GND LVD I/O8 I/O7 I/O6 I/O5 VCC is a trademark of Toshiba Corporation. 000707EBA2 · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 2001-10-24 1/33 TC58V64BDC BLOCK DIAGRAM VCC VSS Status register Address register I/O1 Column buffer ~ I/O control circuit Column decoder I/O8 Command register Data register ROW Row address address buffer buffer decoder CE CLE ALE Logic control Control circuit WE RE WP ROW Row address address decoder decoder Sense amp Memory cell array Extended area (embedded ID) RY/BY HV generator RY/BY ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT VCC Power Supply Voltage -0.6~4.6 V VIN Input Voltage -0.6~4.6 V VI/O Input/Output Voltage -0.6 V~VCC + 0.3 V (£ 4.6 V) V PD Power Dissipation 0.3 W Tstg Storage Temperature -20~65 °C Topr Operating Temperature 0~55 °C CAPACITANCE *(Ta = 25°C, f = 1 MHz) SYMBOL PARAMETER CONDITION MIN MAX UNIT CIN Input VIN = 0 V ¾ 10 pF COUT Output VOUT = 0 V ¾ 12 pF * This parameter is periodically sampled and is not tested for every device. 000707EBA2 · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 2001-10-24 2/33 TC58V64BDC VALID BLOCKS (1) SYMBOL NVB PARAMETER Number of Valid Blocks MIN TYP. MAX UNIT 1014 ¾ 1024 Blocks (1) The TC58V64B occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 3.0 3.3 3.6 V VIH High Level input Voltage 2.0 ¾ VCC + 0.3 V VIL Low Level Input Voltage -0.3* ¾ 0.8 V -2 V (pulse width lower than 20 ns) * DC CHARACTERISTICS (Ta = 0°~55°C, VCC = 3.3 V ± 0.3 V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT IIL Input Leakage Current VIN = 0 V to VCC ¾ ¾ ±10 mA ILO Output Leakage Current VOUT = 0.4 V to VCC ¾ ¾ ±10 mA ICCO1 Operating Current (Serial Read) CE = VIL, IOUT = 0 mA, tcycle = 50 ns ¾ 10 30 mA ICCO3 Operating Current (Command Input) tcycle = 50 ns ¾ 10 30 mA ICCO4 Operating Current (Data Input) tcycle = 50 ns ¾ 10 30 mA ICCO5 Operating Current (Address Input) tcycle = 50 ns ¾ 10 30 mA ICCO7 Programming Current ¾ ¾ 10 30 mA ICCO8 Erasing Current ¾ ¾ 10 30 mA ICCS1 Standby Current CE = VIH ¾ ¾ 1 mA ICCS2 Standby Current CE = VCC - 0.2 V ¾ ¾ 100 mA VOH High Level Output Voltage IOH = -400 mA 2.4 ¾ ¾ V VOL Low Level Output Voltage IOL = 2.1 mA ¾ ¾ 0.4 V IOL ( RY/BY ) Output Current of RY/BY pin VOL = 0.4 V ¾ 8 ¾ mA 2001-10-24 3/33 TC58V64BDC AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta = 0°~55°C, VCC = 3.3 V ± 0.3 V) SYMBOL PARAMETER MIN MAX UNIT tCLS CLE Setup Time 0 ¾ ns tCLH CLE Hold Time 10 ¾ ns tCS CE Setup Time 0 ¾ ns tCH CE Hold Time 10 ¾ ns tWP Write Pulse Width 25 ¾ ns tALS ALE Setup Time 0 ¾ ns tALH ALE Hold Time 10 ¾ ns tDS Data Setup Time 20 ¾ ns tDH Data Hold Time 10 ¾ ns tWC Write Cycle Time 50 ¾ ns tWH WE High Hold Time 15 ¾ ns tWW WP High to WE Low 100 ¾ ns tRR Ready to RE Falling Edge 20 ¾ ns tRP Read Pulse Width 35 ¾ ns tRC Read Cycle Time 50 ¾ ns tREA RE Access Time (Serial Data Access) tCEH CE High Time for Last Address in Serial Read Cycle ¾ 35 ns 100 ¾ ns RE Access Time (ID Read) ¾ 35 ns tOH Data Output Hold Time 10 ¾ ns tRHZ RE High to Output High Impedance ¾ 30 ns tREAID tCHZ CE High to Output High Impedance ¾ 20 ns tREH RE High Hold Time 15 ¾ ns Output-High-impedance-to- RE Rising Edge 0 ¾ ns RE Access Time (Status Read) ¾ 35 ns tCSTO CE Access Time (Status Read) ¾ 45 ns tRHW RE High to WE Low 0 ¾ ns tWHC WE High to CE Low 30 ¾ ns tIR tRSTO tWHR WE High to RE Low 30 ¾ ns tAR1 ALE Low to RE Low (ID Read) 100 ¾ ns CE Low to RE Low (ID Read) 100 ¾ ns ¾ 25 ms tCR tR Memory Cell Array to Starting Address tWB WE High to Busy ¾ 200 ns tAR2 ALE Low to RE Low (Read Cycle) 50 ¾ ns tRB RE Last Clock Rising Edge to Busy (in Sequential Read) ¾ 200 ns tCRY CE High to Ready (When interrupted by CE in Read Mode) ¾ tRST Device Reset Time (Read/Program/Erase) ¾ 1+ ms tr ( RY/BY ) NOTES (2) (1) (2) ms 6/10/500 AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load CONDITION 2.4 V, 0.4 V 3 ns 1.5 V, 1.5 V 1.5 V, 1.5 V CL (100 pF) + 1 TTL 2001-10-24 4/33 TC58V64BDC Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/ BY pin. (Refer to Application Note (8) toward the end of this document.) (2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay is less than 30 ns, RY/ BY signal stays Ready. tCEH ³ 100 ns * *: VIH or VIL CE RE 525 526 527 A : 0 to 30 ns ® Busy signal is not output. A RY/BY Busy tCRY PROGRAMMING AND ERASING CHARACTERISTICS (Ta = 0°~55°C, VCC = 3.3 V ± 0.3 V) SYMBOL PARAMETER MIN TYP. MAX UNIT ms tPROG Programming Time ¾ 200 to 300 1000 N Number of Programming Cycles on Same Page ¾ ¾ 5 tBERASE Block Erasing Time ¾ 2 10 NOTES (1) ms (1): Refer to Application Note (11) toward the end of this document. 2001-10-24 5/33 TC58V64BDC TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE CE RE Setup Time Hold Time WE tDS tDH I/O1 to I/O8 : VIH or VIL Command Input Cycle Timing Diagram CLE tCLS tCS tCLH tCH CE tWP WE tALS tALH ALE tDS tDH I/O1 to I/O8 : VIH or VIL 2001-10-24 6/33 TC58V64BDC Address Input Cycle Timing Diagram tCLS CLE tCS tWC tWC CE tWP tWH tWP tWH tWP WE tALS tALH ALE tDS I/O1 to I/O8 tDH A0 to A7 tDS tDH A9 to A16 tDS tDH A17 to A22 : VIH or VIL Data Input Cycle Timing Diagram tCLH CLE tCH CE tALS tWC ALE tWP tWH tWP tWP WE tDS I/O1 to I/O8 tDH DIN0 tDS tDH DIN1 tDS tDH DIN 527 : VIH or VIL 2001-10-24 7/33 TC58V64BDC Serial Read Cycle Timing Diagram tRC CE tRP tREH RE tOH tRHZ tREA tRP tREA tRP tOH tRHZ tCHZ tOH tRHZ tREA I/O1 to I/O8 tRR RY/BY Status Read Cycle Timing Diagram tCLS CLE tCLS tCLH tCS CE tWP tCH WE tWHC tCSTO tCHZ tWHR RE tOH tDS I/O1 to I/O8 tDH 70H* tIR tRSTO tRHZ Status output RY/BY * 70H represents the hexadecimal number : VIH or VIL 2001-10-24 8/33 TC58V64BDC Read Cycle (1) Timing Diagram CLE tCLS tCLH tCS tCH tCEH CE tWC tCRY WE tALH tALS tALH tAR2 ALE tR tRR tRC tWB RE I/O1 to I/O8 tDS tDH tDS tDH tDS tDH tDS tDH 00H A0 to A7 A9 to A16 A17toA22 tREA DOUT N DOUT N+1 DOUT 527 tRB DOUT N+2 Column address N* RY/BY * Read Operation using 00H Command N: 0 to 255 : VIH or VIL Read Cycle (1) Timing Diagram: When Interrupted by CE CLE tCLS tCLH tCS tCH CE tWC tCHZ WE tALH tALS tALH tAR2 ALE tR tRC tWB RE I/O1 to I/O8 tRR tDS tDH tDS tDH tDS tDH tDS tDH 00H A0 to A7 A9 to A16 A17toA22 tOH tRHZ tREA DOUT N DOUT N+1 DOUT N+2 Column address N* RY/BY * Read Operation using 00H Command N: 0 to 255 : VIH or VIL 2001-10-24 9/33 TC58V64BDC Read Cycle (2) Timing Diagram CLE tCLS tCLH tCS tCH CE WE tALH tALS tALH tAR2 ALE tR tRR tRC tWB RE tDS tDH I/O1 to I/O8 tDS tDH 01H tREA A0 to A7 A9 to A16 A17toA22 DOUT DOUT 256 + M 256 + M + 1 Column address N* DOUT 527 RY/BY : VIH or VIL * Read Operation using 01H Command N: 0 to 255 Read Cycle (3) Timing Diagram CLE tCLS tCLH tCS tCH CE WE tALH tALS tALH tAR2 ALE tR tRC tWB RE tDS tDH I/O1 to I/O8 tRR 50H tDS tDH A0 to A7 A9 to A16 A17toA22 Column address N* tREA DOUT DOUT 512 + M 512 + M + 1 DOUT 527 RY/BY * Read Operation using 50H Command N: 0 to15 : VIH or VIL 2001-10-24 10/33 TC58V64BDC Sequential Read (1) Timing Diagram CLE CE WE ALE RE I/O1 to I/O8 00H A0 to A7 A9 to A16 A17toA22 Column Page address address N M N N+1 N+2 527 tR 0 1 2 527 2 527 tR RY/BY Page M + 1 access Page M access : VIH or VIL Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 to I/O8 01H A0 to A7 A9 to A16 A17toA22 Column Page address address N M 527 tR 256 + 256 + 256 + N N+1 N+2 0 1 tR RY/BY Page M access Page M + 1 access : VIH or VIL 2001-10-24 11/33 TC58V64BDC Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 to I/O8 50H A0 to A7 A9 to A16 A17toA22 Column Page address address N M 527 tR 512 + 512 + 512 + N N+1 N+2 512 513 514 527 tR RY/BY Page M access Page M + 1 access : VIH or VIL 2001-10-24 12/33 TC58V64BDC Auto-Program Operation Timing Diagram tCLS CLE tCLS tCLH tCS CE tCS tCH WE tALH tALS tALH tALS tPROG tWB ALE RE tDS tDS tDH I/O1 to I/O8 tDS tDH 80H tDS tDH tDH A0 to A7 A9 to A16 A17toA22 DIN0 DIN1 DIN 527 10H 70H Status output RY/BY : VIH or VIL : Do not input data while data is being output. Auto Block Erase Timing Diagram CLE tCLS tCLH tCLS tCS CE WE tALS tALH tWB tBERASE ALE RE tDS tDH I/O1 to I/O8 60H RY/BY Auto Block Erase Setup command A9 to A16 A17toA22 D0H Erase Start command : VIH or VIL 70H Busy Status output Status Read command : Do not input data while data is being output. 2001-10-24 13/33 TC58V64BDC ID Read Operation Timing Diagram CLE tCLS tCS tCH tCLS tCS CE tCH WE tALH tALS tALH tCR tAR1 ALE RE tDS tDH I/O1 to I/O8 90H tREAID tREAID 00 98H E6H Address input Maker code Device code : VIH or VIL 2001-10-24 14/33 TC58V64BDC PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. 1 2 3 4 5 6 7 8 9 10 11 VSS CLE ALE WE WP I/O1 I/O2 I/O3 I/O4 VSS VSS Address Latch Enable: ALE The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is latched if ALE is Low. Chip Enable: CE 22 21 20 19 18 17 16 15 14 13 12 VCC CE RE RY/BY GND LVD I/O8 I/O7 I/O6 I/O5 VCC The device goes into a low-power Standby mode when CE Figure 1. Pinout goes High during a Read operation. The CE signal is ignored when device is in Busy state ( RY/ BY = L), such as during a Program or Erase operation, and will not enter Standby mode even if the CE input goes High. The CE signal must stay Low during the Read mode Busy state to ensure that memory array data is correctly transferred to the data register. Write Enable: WE The WE signal is used to control the acquisition of data from the I/O port. Read Enable: RE The RE signal controls serial data output. Data is available tREA after the falling edge of RE . The internal column address counter is also incremented (Address = Address + 1) on this falling edge. I/O Port: I/O1~I/O8 The I/O1 to I/O8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: RY / BY The RY/ BY output signal is used to indicate the operating condition of the device. The RY/ BY signal is in Busy state ( RY/ BY = L) during the Program, Erase and Read operations and will return to Ready state ( RY/ BY = H) after completion of the operation. The output buffer for this signal is an open drain. Low Voltage Detect: LVD The LVD signal is used to detect the power supply voltage level. 2001-10-24 15/33 TC58V64BDC chematic Cell Layout and Address Assignment The Program operation works on page units while the Erase operation works on block units. I/O1 512 A page consists of 528 bytes in which 512 bytes are used for main memory storage and 16 bytes are for redundancy or for other uses. I/O8 16 1 page = 528 bytes 1 block = 528 bytes ´ 16 pages = (8K + 256) bytes Capacity = 528 bytes ´ 16 pages ´ 1024 blocks 16 pages = 16384 pages = 1 block An address is read in via the I/O port over three consecutive clock cycles, as shown in Table 1. 1024 blocks 8I/O 528 Figure 2. Schematic Cell Layout Table 1. Addressing I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 First cycle A7 A6 A5 A4 A3 A2 A1 A0 Second cycle A16 A15 A14 A13 A12 A11 A10 A9 *L *L A22 A21 A20 A19 A18 A17 Third cycle *: A8 is automatically set to Low or High by a 00H command or a 01H command. *: I/O7 and I/O8 must be set to Low in the third cycle. A0~A7: A9~A22: A13~A22: A9~A12: Column address Page address Block address NAND address in block Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2. Table 2. Logic table CLE ALE CE Command Input H L Data Input L Address Input RE WP L H * L L H * L H L H * Serial Data Output L L L H During Programming (Busy) * * * * * H During Erasing (Busy) * * * * * H Program, Erase Inhibit * * * * * L * * H * * 0V/VCC Standby *2 WE * H: VIH, L: VIL, *: VIH or VIL *1: Refer to Application Note (9) toward the end of this document regarding the WP signal when Program or Erase Inhibit *2: The device does not go into a low-power Standby mode when CE goes High during Busy state of a Program or Erase operation. 2001-10-24 16/33 TC58V64BDC Table 3. Command table (HEX) First Cycle Second Cycle Serial Data Input 80 ¾ Read Mode (1) 00 ¾ Read Mode (2) 01 ¾ Read Mode (3) 50 ¾ Reset FF ¾ Auto Program 10 ¾ Auto Block Erase 60 D0 Status Read 70 ¾ ID Read 90 ¾ Acceptable while Busy HEX data bit assignment (Example) Serial data input: 80H 1 Q 0 0 0 0 0 0 0 I/O8 7 6 5 4 3 2 I/O1 Q Once the device has been set to Read mode by a 00H, 01H or 50H command, additional Read commands are not needed for sequential page Read operations. Table 4 shows the operation states for Read mode. Table 4. Read mode operation states CLE ALE CE WE RE I/O1~I/O8 Power Output Select L L L H L Data output Active Output Deselect L L L H H High impedance Active H: VIH, L: VIL, *: VIH or VIL 2001-10-24 17/33 TC58V64BDC DEVICE OPERATION Read Mode (1) Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for timing details and the block diagram. CLE CE WE ALE RE RY/BY I/O Busy N M 00H Start-address input M 527 Select page N Cell array Figure 3. Read mode (1) operation A data transfer operation from the cell array to the register starts on the rising edge of WE in the third cycle (after the address information has been latched). The device will be in Busy state during this transfer period. The CE signal must stay Low after the third address input and during Busy state. After the transfer period the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start pointer designated in the address input cycle. Read Mode (2) CLE CE WE ALE RE RY/BY I/O Busy N M 01H Start-address input 256 M 527 Select page N Cell array The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer is to be set after column address 256, use Read mode (2). However, for a Sequential Read, output of the next page starts from column address 0. Figure 4. Read mode (2) operation 2001-10-24 18/33 TC58V64BDC Read Mode (3) Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra 16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527. CLE CE WE ALE RE RY/BY Busy I/O 50H Addresses bits A0~A3 are used to set the start pointer for the redundant memory cells, while A4~A7 are ignored. Once a 50H command has been issued, the pointer moves to the redundant cell locations and only those 16 cells can be addressed, regardless of the value of the A4-to-A7 address. (An 00H command is necessary to move the pointer back to the 0-to-511 main memory cell location.) A0~A3 512 527 Figure 5. Read mode (3) operation Sequential Read (1) (2) (3) This mode allows the sequential reading of pages without additional address input. 00H 01H Address input 50H Data output Data output tR tR tR Busy Busy Busy RY/BY (00H) 0 527 (01H) (50H) 512 527 A A Sequential Read (1) A Sequential Read (2) Sequential Read (3) Sequential Read modes (1) and (2) output the contents of addresses 0~527 as shown above, while Sequential Read mode (3) outputs the contents of the redundant address locations only. When the pointer reaches the last address, the device continues to output the data from this address ** on each RE clock signal. ** Column address 527 on the last page. 2001-10-24 19/33 TC58V64BDC Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the I/O port on the RE clock after a 70H command input. The resulting information is outlined in Table 5. Table 5. Status output table STATUS OUTPUT I/O1 Pass/Fail Pass: 0 Fail: 1 I/O2 Not Used 0 I/O3 Not Used 0 I/O4 Not Used 0 I/O5 Not Used 0 I/O6 Not Used 0 I/O7 Ready/Busy Ready: 1 Busy: 0 I/O8 Write Protect Protect: 0 Not Protected: 1 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state. An application example with multiple devices is shown in Figure 6. CLE ALE WE RE CE1 CE2 CE3 CEN CEN + 1 Device 1 Device 2 Device 3 Device N Device N+1 I/O1 ~I/O8 RY/BY Busy RY/BY CLE ALE WE CE1 CEN RE I/O 70H 70H Status on Device 1 Status on Device N Figure 6. Status Read timing application example System Design Note: If the RY/ BY pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. 2001-10-24 20/33 TC58V64BDC Auto Page Program The device carries out an Automatic Page Program operation when it receives a “10H” Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) 80 10 70 Data input Address Data input Program command input 0 to 527 command Status Read command I/O Pass Fail RY/BY automatically returns to Ready after completion of the operation. RY/BY Data input Program Reading & verification Selected page Figure 7. Auto Page Program operation The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the “10H” command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0H” which follows the Erase Setup command “60H”. This two-cycle process for Erase operations acts as an ertra layer of protection from aceidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. 60 D0 70 Block Address Erase Start input: 2 cycles command RY/BY Status Read command I/O Pass Fail Busy 2001-10-24 21/33 TC58V64BDC Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an “FFH” Reset command input during the various device operations is as follows: When a Reset (FFH) command is input during programming Figure 8. 80 10 FF 00 Internal VPP RY/BY tRST (max 10 ms) When a Reset (FFH) command is input during erasing Figure 9. D0 FF 00 Internal erase voltage RY/BY tRST (max 500 ms) When a Reset (FFH) command is input during Read operation Figure 10. 00 FF 00 RY/BY tRST (max 6 ms) When a Status Read command (70H) is input after a Reset Figure 11. FF 70 I/O status: Pass/Fail ® Pass Ready/Busy ® Ready RY/BY FF 70 I/O status: Ready/Busy ® Busy RY/BY When two or more Reset commands are input in succession Figure 12. (1) (2) (3) FF FF FF RY/BY The second FF command is invalid, but the thirdFF command is 2001-10-24 22/33 TC58V64BDC ID Read The TC58V64B contains ID codes which identify the device type and the manufacturer. The ID codes can be read out under the following timing conditions: CLE tCR CE WE tAR1 ALE RE tREAID I/O 90H 00 98H E6H ID Read command Address 00 Maker code Device code For the specifications of the access times tREAID, tCR and tAR1 refer to the AC Characteristics. Figure13. ID Read timing Table 6. Code table I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data Maker code 1 0 0 1 1 0 0 0 98H Device code 1 1 1 0 0 1 1 0 E6H 2001-10-24 23/33 TC58V64BDC APPLICATION NOTES AND COMMENTS (1) Power-on/off sequence: The WP signal is useful for protecting against data corruption at power-on/off. The following timing sequence is necessary. The WP signal may be negated any time after the VCC reaches 2.7 V and CE signal is kept high in power up sequence. 3.0 V 2.7 V 0V VCC Don’t care Don’t care CE , WE , RE CLE, ALE WP VIH VIL VIL Operation Figure 15. Power-on/off Sequence In order to operate this device stably, after VCC becomes 2.7 V, it recommends starting access after about 200 ms. (2) Status after power-on The following sequence is necessary because some input signals may not be stable at power-on. Power on FF Reset Figure 16. (3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of command while Busy state During Busy state, do not input any command except 70H and FFH. (5) Acceptable commands after Serial Input command “80H” Once the Serial Input command “80H” has been input, do not input any command other than the Program Execution command “10H” or the Reset command “FFH”. If a command other than “10H” or “FFH” is input, the Program operation is not performed. 80 XX 10 For this operation the “FFH” command is Command other than “10H” or “FFH” Programming cannot be 2001-10-24 24/33 TC58V64BDC (6) Status Read during a Read operation 00 command 00 70 [A] CE WE RY/BY RE Status Read command input Address N Status Read Status output Figure 18. The device status can be read out by inputting the Status Read command “70H” in Read mode. Once the device has been set to Status Read mode by a “70H” command, the device will not return to Read mode. Therefore, a Status Read during a Read operation is prohibited. However, when the Read command “00H” is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary 2001-10-24 25/33 TC58V64BDC (7) Pointer control for “00H”, “01H” and “50H” The device has three Read modes which set the destination of the pointer. Table 7 shows the destination of the pointer, and Figure 14 is a block diagram of their operations. Table 8. Pointer Destination 0 Read Mode Command Pointer (1) 00H 0 to 255 (2) 01H 256 to 511 (3) 50H 512 to 527 255 256 511 512 527 A B (1) 00H (2) 01H (3) 50H C Pointer control Figure 19. Pointer control The pointer is set to region A by the “00H” command, to region B by the “01H” command, and to region C by the “50H” command. (Example) The “00H” command must be input to set the pointer back to region A when the pointer is pointing to region C. 00H 50H Add Start point A area Add Start point A area Add Start point C area Add Start point C area Add Start point B area Add Start point A area 50H Add Start point C area Add Start point A area 00H 01H To program region C only, set the start point to region C using the 50H command. 50H 01H 80H 10H Add DIN Start point C Area Add DIN Start point B Area 80H Programming region C only 10H Programming region B and C Figure 20. Example of How to Set the Pointer 2001-10-24 26/33 TC58V64BDC (8) RY/ BY : termination for the Ready/Busy pin ( RY/ BY ) A pull-up resistor needs to be used for termination because the RY/ BY buffer consists of an open drain circuit. VCC VCC Ready 3.0 V R Device VCC 3.0 V 1.0 V RY/BY CL Busy 1.0 V tr tf VSS 1.5 ms Figure 21. tr This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. tf 1.0 ms 15 ns 10 ns tf tr 0.5 ms 0 VCC = 3.3 V Ta = 25°C CL = 100 pF 5 ns 1 KW 2 KW 3 KW 4 KW R 2001-10-24 27/33 TC58V64BDC (9) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN 80 10 WP RY/BY tWW (100 ns min) Disable Programming WE DIN 80 10 WP RY/BY tWW (100 ns min) Enable Erasing WE DIN 60 D0 WP RY/BY tWW (100 ns min) Disable Erasing WE DIN 60 D0 WP RY/BY tWW (100 ns min) 2001-10-24 28/33 TC58V64BDC (10) When four address cycles are input Although the device may read in a fourth address, it is ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Address input Ignored RY/BY Internal read operation starts when WE goes High in the third cycle. Figure 22. Program operation CLE CE WE ALE I/O 80H Address input Data input Ignored Figure 23. 2001-10-24 29/33 TC58V64BDC (11) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 5 segments. Each segment can be programmed individually as follows: 1st programming Data Pattern 1 2nd programming All 1s All 1s Data Pattern 2 All 1s 5th programming Result All 1s Data Pattern 1 Data Pattern 5 Data Pattern 2 Data Pattern 5 Figure 24. Note: The input data for unprogrammed or previously programmed page segments must be “1” (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all “1”). (12) Note regarding the RE signal RE The internal column address counter is incremented synchronously with the RE clock in Read mode. Therefore, once the device has been set to Read mode by a “00H”, “01H” or “50H” command, the internal column address counter is incremented by the RE clock independently of the address input timing, If the RE clock input pulses start before the address input, and the pointer reaches the last column address, an internal read operation (array to register) will occur and the device will enter Busy state. (Refer to Figure 25.) Address input I/O 00H/01H/50H WE RE RY/BY Figure 25. Hence the RE clock input must start after the address input. 2001-10-24 30/33 TC58V64BDC (13) Invalid blocks (bad blocks) The device contains unusable blocks. Therefore, the following issues must be recognized: Bad Block Bad Block Referring to the Block status area in the redundant area allows the system to detect bad blocks in the accordance with the physical data format issued by the SSFDC Forum. Detect the bad blocks by checking the Block Status Area at the system power-on, and do not access the bad blocks in the following routine. The number of valid blocks at the time of shipment is as follows: Valid (Good) Block Number MIN TYP. MAX UNIT 1014 ¾ 1024 Block Figure 26. (14) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Block Erase Failure Status Read after Erase ® Block Replacement Page Programming Failure Status Read after Program ® Block Replacement Single Bit Programming Failure 1®0 · · (1) Block Verify after Program ® Retry (2) ECC ECC: Error Correction Code Block Replacement Program Error occurs Buffer memory Block A When an error happens in Block A, try to reprogram the data into another (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 27. Erase When an error occurs for an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) Chattering of Connector There may be contact chattering when the device is inserted or removed from a connector. This chattering may cause damage to the data in the device. Therefore, sufficient time must be allowed for contact bouncing to subside when a system is designed with SmartMediaTM. (16) The device is formatted to comply with the Physical and Logical Data Format of the SSFDC Forum at the time of shipping. 2001-10-24 31/33 TC58V64BDC Handling Precaution (1) Avoid bending or subjecting the card to sudden impact. (2) Avoid touching the connectors so as to avoid damage from static electricity. This card should be kept in the antistatic film case when not in use. (3) Toshiba cannot accept, and hereby disclaims liability for, any damage to the card including data corruption that may occur because of mishandling. How to read out unique ID number The 128 bit unique ID number is embedded in the device. The procedure to read out the ID number is available using special command which is provided under a non-disclosure agreement. SSFDC Forum The SSFDC Forum is a voluntary organization intended to promote the SmartMediaTM, a small removable NAND flash memory card. The SSFDC Forum standardized the following specifications in order to keep the compatibility of SmartMediaTM in systems. The latest specifications issued by the Forum must be referenced when a system is designed with SmartMediaTM, especially with large capacity SmartMediaTM. SmartMediaTM SmartMediaTM SmartMediaTM Electrical Specifications Physical Format Specification Logical Format Specification Some electrical specifications in this data sheet show differences from the Forum’s electrical specification. Complying with the Forum’s electrical specification maintains compatibility with other SmartMedias. Please refer following SSFDC Forum’s URL to get the detailed information of each specification. URL http://www.ssfdc.or.jp 2001-10-24 32/33 TC58V64BDC PACKAGE DIMENSIONS Weight: 1.8 g (typ.) 2001-10-24 33/33