INTEGRATED CIRCUITS DATA SHEET TDA9870A Digital TV Sound Processor (DTVSP) Product specification File under Integrated Circuits, IC02 1998 Aug 10 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) CONTENTS 1 FEATURES 1.1 1.2 1.3 Demodulator and decoder section DSP section Analog audio section 2 GENERAL DESCRIPTION 2.1 Supported standards 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 6.2 6.3 Description of the demodulator and decoder section Description of the DSP Description of the analog audio section 7 LIMITING VALUES 8 THERMAL CHARACTERISTICS 9 CHARACTERISTICS 10 I2C-BUS CONTROL 10.1 10.2 10.3 10.4 10.5 Introduction Power-up state Slave receiver mode Slave transmitter mode Expert mode 11 I2S-BUS DESCRIPTION 12 EXTERNAL COMPONENTS 13 APPLICATION CIRCUITRY 14 PACKAGE OUTLINE 15 SOLDERING 15.1 15.2 15.3 Introduction Soldering by dipping or by wave Repairing soldered joints 16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS 18 PURCHASE OF PHILIPS I2C COMPONENTS 1998 Aug 10 2 TDA9870A Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 1 1.1 TDA9870A FEATURES Demodulator and decoder section • Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF sources • SIF AGC with 24 dB control range • SIF 8-bit Analog-to-Digital Converter (ADC) 2 • Two-carrier multistandard FM demodulation (B/G, D/K and M standard) The TDA9870A is a single-chip Digital TV Sound Processor (DTVSP) for analog multi-channel sound systems in TV sets and satellite receivers. • Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound 2.1 • Programmable identification (B/G, D/K and M standard) and different identification times. 1.2 GENERAL DESCRIPTION Supported standards The multistandard/multi-stereo capability of the TDA9870A is mainly of interest in Europe, but also in Hong Kong/Peoples Republic of China and South East Asia. This includes B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those standard combinations otherwise only single standards are transmitted. DSP section • Digital crossbar switch for all digital signal sources and destinations • Control of volume, balance, contour, bass, treble, pseudo stereo, spatial, bass boost and soft-mute M standard is transmitted in Europe by the American Forces Network (AFN) with European channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. • Plop-free volume control • Automatic Volume Level (AVL) control • Adaptive de-emphasis for satellite • Monitor selection for FM/AM DC values and signals, with peak detection option Korea has a stereo sound system similar to Europe and is supported by the TDA9870A. Differences include deviation, modulation contents and identification. It is based on M standard. • I2S-bus interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and mute. An overview of the supported standards and sound systems and their key parameters is given in Table 1. 1.3 The analog multi-channel sound systems (A2, A2+ and A2*) are sometimes also named 2CS (2-Carrier Systems). • Programmable beeper Analog audio section • Analog crossbar switch with inputs for mono and stereo (also applicable as SCART 3 input), SCART 1 input/output, SCART 2 input/output and line output • User defined full-level/−3 dB scaling for SCART outputs • Output selection of mono, stereo, dual A/B, dual A or dual B • 20 kHz bandwidth for SCART-to-SCART copies • Standby mode with functionality for SCART copies • Dual audio Digital-to-Analog Converter (DAC) from DSP to analog crossbar switch, bandwidth of 15 kHz • Dual audio ADC from analog inputs to DSP • Two dual audio DACs for loudspeaker (Main) and headphone (Auxiliary) outputs; also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension. 1998 Aug 10 3 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 2.1.1 TDA9870A ANALOG 2-CARRIER SYSTEMS Table 1 Frequency modulation STANDARD M SOUND SYSTEM CARRIER FREQUENCY (MHz) FM DEVIATION (kHz) MODULATION NOM. MAX. OVER mono 4.5 15 25 50 SC1 mono M A2+ 4.5/4.724 15 25 50 1⁄ B/G A2 5.5/5.742 27 50 80 1⁄ I mono 6.0 27 50 80 D/K A2 6.5/6.742 27 50 80 1⁄ D/K A2* 6.5/6.258 27 50 80 1⁄ Table 2 + R) 1⁄ SC2 BANDWIDTH/ DE-EMPHASIS (kHz/µs) − 15/75 2(L − R) 2(L 2(L + R) R 15/75 (Korea) 15/50 mono − 15/50 2(L + R) R 15/50 2(L + R) R 15/50 Identification for A2 systems PARAMETER A2/A2* A2+ (KOREA) Pilot frequency 54.6875 kHz = 3.5 × line frequency 55.0699 kHz = 3.5 × line frequency Stereo identification frequency line frequency 117.5 Hz = --------------------------------------133 line frequency 149.9 Hz = --------------------------------------105 Dual identification frequency line frequency 274.1 Hz = --------------------------------------57 line frequency 276.0 Hz = --------------------------------------57 AM modulation depth 50% 50% 1998 Aug 10 4 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 2.1.2 TDA9870A SATELLITE SYSTEMS An important specification for satellite TV reception is the “Astra specification”. The TDA9870A is suited for the reception of Astra and other satellite signals. Table 3 FM satellite sound CARRIER TYPE CARRIER FREQUENCY (MHz) MODULATION INDEX MAXIMUM FM DEVIATION (kHz) MODULATION BANDWIDTH/ DE-EMPHASIS (kHz/µs) Main 6.50(1) 0.26 85 mono 15/50(1) Sub 7.02/7.20 0.15 50 m/st/d(2) 15/adaptive(3) 15/adaptive(3) Sub 7.38/7.56 0.15 50 m/st/d(2) Sub 7.74/7.92 0.15 50 m/st/d(2) 15/adaptive(3) Sub 8.10/8.28 0.15 50 m/st/d(2) 15/adaptive(3) Notes 1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis of 60 µs, or in accordance with J17, is available. 2. m/st/d = mono or stereo or dual language sound. 3. Adaptive de-emphasis is compatible to transmitter specification. 3 ORDERING INFORMATION TYPE NUMBER TDA9870A 1998 Aug 10 PACKAGE NAME SDIP64 DESCRIPTION plastic shrink dual in-line package; 64 leads (750 mil) 5 VERSION SOT274-1 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 4 TDA9870A BLOCK DIAGRAM SIF2 handbook, full pagewidth SIF1 10 P1 P2 ADDR1 ADDR2 SCL SDA 12 9 7 20 3 13 I2C-BUS INTERFACE SUPPLY SOUND IF (SIF) INPUT SWITCH AGC, ADC 4 6 11 8 5 33 XTALO SYSCLK 34 18 19 36 A2/SATELLITE DECODER CLOCK 21 37 31 32 ANALOG CROSSBAR SWITCH 29 47 48 PEAK DETECTION 51 LEVEL ADJUST 52 63 62 SDI1 SDI2 SDO1 SDO2 SCK WS 1 26 25 24 22 VDDD2 64 VSSD1 14 VSSD2 49 VSSD3 35 VSSD4 17 2 ADC (2) 41 I2S-BUS INTERFACE 42 44 DIGITAL SELECT 23 VDDD1 45 DAC (2) 54 55 59 16 38 AUDIO PROCESSING 40 TDA9870A SUPPLY SCART, DAC, ADC DAC (2) DAC (2) TEST2 46 53 28 30 43 TEST 56 50 61 60 58 57 MHB110 MOL MOR AUXOL AUXOR Fig.1 Block diagram. 1998 Aug 10 Iref SCIR1 SCIL1 SCIR2 SCIL2 EXTIR EXTIL MONOIN SCOR1 SCOL1 SCOR2 SCOL2 LOR LOL i.c. i.c. i.c. i.c. i.c. i.c. PCAPR PCAPL DIGITAL SUPPLY 39 TEST1 Vref1 27 15 CRESET VSSA1 FM (AM) DEMODULATION IDENTIFICATION XTALI VDEC1 6 VDDA2 VDEC2 Vref(p) Vref(n) Vref2 Vref3 VSSA2 VSSA3 VSSA4 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 5 TDA9870A PINNING SYMBOL PIN I/O DESCRIPTION i.c. 1 − internally connected; note 1 i.c. 2 − internally connected; note 1 ADDR1 3 I first I2C-bus slave address modifier SCL 4 I I2C-bus clock input SDA 5 I/O VSSA1 6 supply VDEC1 7 − positive power supply voltage 1 decoupling; analog front-end circuitry Iref 8 − resistor for reference current generator; analog front-end circuitry P1 9 I/O SIF2 10 I sound IF input 2 I2C-bus data input/output supply ground 1; analog front-end circuitry first general purpose I/O pin Vref1 11 − reference voltage; analog front-end circuitry SIF1 12 I sound IF input 1 ADDR2 13 I second I2C-bus slave address modifier VSSD1 14 supply supply ground 1; digital circuitry VDDD1 15 supply digital supply voltage 1; digital circuitry CRESET 16 − VSSD4 17 supply XTALI 18 I crystal oscillator input XTALO 19 O crystal oscillator output P2 20 I/O second general purpose I/O pin SYSCLK 21 O system clock output SCK 22 I/O I2S-bus clock input/output WS 23 I/O I2S-bus word select input/output SDO2 24 O I2S-bus data output 2 SDO1 25 O I2S-bus data output 1 SDI2 26 I I2S-bus data input 2 SDI1 27 I I2S-bus data input 1 TEST1 28 I first test pin; connected to VSSD1 for normal operation MONOIN 29 I audio mono input capacitor for power-on reset supply ground 4; digital circuitry TEST2 30 I second test pin; connected to VSSD1 for normal operation EXTIR 31 I external audio input right channel EXTIL 32 I external audio input left channel SCIR1 33 I SCART 1 input right channel SCIL1 34 I SCART 1 input left channel VSSD3 35 supply SCIR2 36 I SCART 2 input right channel SCIL2 37 I SCART 2 input left channel VDEC2 38 − positive power supply voltage 2 decoupling; audio analog-to-digital converter circuitry Vref(p) 39 − positive reference voltage; audio analog-to-digital converter circuitry 1998 Aug 10 supply ground 3; digital circuitry 7 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL TDA9870A PIN I/O DESCRIPTION Vref(n) 40 − reference voltage ground; audio analog-to-digital converter circuitry i.c. 41 − internally connected; note 2 i.c. 42 − internally connected; note 3 VSSA2 43 supply i.c. 44 − internally connected; note 3 i.c. 45 − internally connected; note 2 Vref2 46 − reference voltage; audio analog-to-digital converter circuitry SCOR1 47 O SCART 1 right channel output SCOL1 48 O SCART 1 left channel output VSSD2 49 supply supply ground 2; digital circuitry VSSA4 50 supply supply ground 4; audio operational amplifier circuitry SCOR2 51 O SCART 2 right channel output SCOL2 52 O SCART 2 left channel output Vref3 53 − reference voltage; audio digital-to-analog converter and operational amplifier circuitry PCAPR 54 − post-filter capacitor pin right channel, audio digital-to-analog converter PCAPL 55 − post-filter capacitor pin left channel, audio digital-to-analog converter VSSA3 56 supply supply ground 2; audio analog-to-digital converter circuitry supply ground 3; audio digital-to-analog converter circuitry AUXOR 57 O headphone (Auxiliary) right channel output AUXOL 58 O headphone (Auxiliary) left channel output VDDA 59 supply MOR 60 O loudspeaker (Main) right channel output MOL 61 O loudspeaker (Main) left channel output LOL 62 O line output left channel LOR 63 O line output right channel VDDD2 64 supply positive analog power supply voltage; analog circuitry digital supply voltage 2; digital circuitry Notes 1. Test pin, CMOS 3-state stage, pull-up resistor, can be connected to VSS. 2. Test pin, CMOS level input, pull-up resistor, can be connected to VSS. 3. Test pin, CMOS 3-state stage, can be connected to VSS. 1998 Aug 10 8 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A handbook, halfpage i.c. 1 64 VDDD2 i.c. 2 63 LOR ADDR1 3 62 LOL SCL 4 61 MOL SDA 5 60 MOR VSSA1 6 59 VDDA VDEC1 7 58 AUXOL Iref 8 57 AUXOR P1 9 56 VSSA3 SIF2 10 55 PCAPL Vref1 11 54 PCAPR SIF1 12 53 Vref3 ADDR2 13 52 SCOL2 VSSD1 14 51 SCOR2 VDDD1 15 50 VSSA4 CRESET 16 VSSD4 17 49 VSSD2 TDA9870A XTALI 18 48 SCOL1 47 SCOR1 XTALO 19 46 Vref2 P2 20 45 i.c. SYSCLK 21 44 i.c. SCK 22 43 VSSA2 WS 23 42 i.c. SDO2 24 41 i.c. SDO1 25 40 Vref(n) SDI2 26 39 Vref(p) SDI1 27 38 VDEC2 TEST1 28 37 SCIL2 MONOIN 29 36 SCIR2 TEST2 30 35 VSSD3 EXTIR 31 34 SCIL1 EXTIL 32 33 SCIR1 MHB111 Fig.2 Pin configuration. 1998 Aug 10 9 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6 6.1.5 FUNCTIONAL DESCRIPTION 6.1 6.1.1 SIF INPUT 6.1.6 AGC 6.1.7 6.1.8 POWER FAIL DETECTOR The power fail detector monitors the internal power supply for the digital part of the device. If the supply has temporarily been lower than the specified lower limit, the power-on reset bit POR, transmitter register subaddress 0 (see Section 10.4.1), will be set to HIGH. The CLRPOR bit, slave register subaddress 1 (see Section 10.3.2), resets the power-on reset flip-flop to LOW. If this is detected, an initialization of the TDA9870A has to be performed to ensure reliable operation. found in the I2C-bus register definitions (see Chapter 10). MIXER The digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I2C-bus. FM AND AM DEMODULATION An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. A stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported. 1998 Aug 10 TEST PINS Both test pins are active HIGH, in normal operation of the device they are connected to VSSD1. Test functions are for manufacturing tests only and are not available to customers. Without external circuitry these pads are pulled down to LOW level with internal resistors. The AGC can be controlled via the I2C-bus. Details can be 6.1.4 CRYSTAL OSCILLATOR The crystal oscillator (XO) is illustrated in Fig.8 (see Chapter 12). The circuitry of the XO is fully integrated, only the external 24.576 MHz crystal is needed. The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen (see Table 14; subaddress 0). 6.1.3 FM IDENTIFICATION The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot signal and narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection can be made via the I2C-bus for B/G, D/K and M standard and for three different modes that represent different trade-offs between speed and reliability of identification. Description of the demodulator and decoder section Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner. For higher SIF signal levels the SIF input can be attenuated with an internally switchable −10 dB resistor divider. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz. 6.1.2 TDA9870A 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2 DC FILTER 2 2 2 MATRIX AUTOMATIC VOLUME LEVEL MATRIX VOLUME SOFT-MUTE BASS/TREBLE BEEPER 4 LEVEL ADJUST I2S1 2 2 6 LEVEL ADJUST I2S2 2 DIGITAL CROSSBAR SELECT SPATIAL PSEUDO VOLUME BASS/TREBLE BASS BOOST CONTOUR SOFT-MUTE BEEPER LEVEL ADJUST AND MUTE 2 MATRIX 2 2 2 LS HP I2S1 8 11 LEVEL ADJUST AND MUTE 2 2 I2S2 LEVEL ADJUST FM 2 MATRIX Philips Semiconductors from ADC 2 Digital TV Sound Processor (DTVSP) LEVEL ADJUST Description of the DSP 2 6.2 , full pagewidth 1998 Aug 10 2 DC FILTER ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS LEVEL ADJUST 2 MATRIX MATRIX 2 DAC 10 2 4 14 MONITOR SELECT PEAK DETECTION 1 I2C-bus MHB112 Product specification TDA9870A Fig.3 DSP data flow diagram. Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6.2.1 Pseudo stereo is based on a phase shift in one channel via a 2nd-order all-pass filter. There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150, 200 and 300 Hz. LEVEL SCALING All input channels to the digital crossbar switch (except for the loudspeaker feedback path) are equipped with a level adjust facility to change the signal level in a range of ±15 dB. It is recommended to scale all input channels to be 15 dB below full scale (−15 dB full scale) under nominal conditions. 6.2.2 Volume is controlled individually for each channel ranging from +24 to −83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dBs (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). FM (AM) PATH A high-pass filter suppresses DC offsets from the FM demodulator, due to carrier frequency offsets, and supplies the monitor/peak function with DC values and an unfiltered signal, e.g. for the purpose of carrier detection. Balance can be realized by independent control of the left and right channel volume settings. Contour is adjustable between 0 and +18 dB with 1 dB resolution. This function is linked to the volume setting by means of microcontroller software. The de-emphasis function offers fixed settings for the supported standards (50 µs, 60 µs and 75 µs). An adaptive de-emphasis is available for Wegener-Panda 1 encoded programs. Bass is adjustable between +15 and −12 dB with 1 dB resolution and treble is adjustable between ±12 dB with 1 dB resolution. A matrix performs the dematrixing of the A2 stereo, dual and mono signals. 6.2.3 For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for contour, bass or treble is identical to the new contour, bass or treble setting in dBs (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). MONITOR This function provides data words from a number of locations of the signal processing paths to the I2C-bus interface (2 data bytes). Signal sources include the FM demodulator outputs, most inputs to the digital crossbar switch and the outputs of the ADC. Source selection and data read-out is performed via the I2C-bus. Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented coefficient set serves merely as an example on how to use this filter. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full scale between 0 and −93 dB with 3 dB resolution. The beeper is not effected by mute. Optionally, the peak value can be measured instead of simply taking samples. The internally stored peak value is reset to zero when the data is read via the I2C-bus. The monitor function may be used, for example, for signal level measurements or carrier detection. 6.2.4 TDA9870A LOUDSPEAKER (MAIN) CHANNEL Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking. The matrix provides the following functions; forced mono, stereo, channel swap, channel 1, channel 2 and spatial effects. There are fixed coefficient sets for spatial settings of 30%, 40% and 52%. 6.2.5 The Automatic Volume Level (AVL) function provides a constant output level of −23 dB full scale for input levels between 0 and −29 dB full scale. There are some fixed decay time constants to choose from, i.e. 2, 4 and 8 s. HEADPHONE (AUXILIARY) CHANNEL The matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled individually for each channel in a range from +24 to −83 dB with 1 dB resolution. There is also a mute position. 1998 Aug 10 12 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dB (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). 6.2.7 6.2.8 CHANNEL TO THE ANALOG CROSSBAR PATH Level adjust with control positions 0 dB, +3 dB, +6 dB and +9 dB. Bass is adjustable between +15 and −12 dB with 1 dB resolution and treble is adjustable between ±12 dB with 1 dB resolution. 6.2.9 For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for bass or treble is identical to the new bass or treble setting in dB (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). DIGITAL CROSSBAR SWITCH (see Fig.6) Input channels to the crossbar switch are from the audio ADC, I2S1, I2S2, FM path and from the loudspeaker channel path after matrix and AVL. Output channels comprise loudspeaker, headphone, I2S1, I2S2 and the audio DACs for line output and SCART. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full scale between 0 and −93 dB with 3 dB resolution. The beeper is not effected by mute. The I2S1 and I2S2 outputs also provide digital outputs from the loudspeaker and headphone channels, but without the beeper signals. 6.2.10 GENERAL There are a number of functions that can provide signal gain, e.g. volume, bass and treble control. Great care has to be taken when using gain with large input signals in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital crossbar switch should be 15 dB below digital full scale (−15 dB full scale). This means that a volume setting of, say, +15 dB would just produce a full scale output signal and not cause clipping, if the signal level is nominal. Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking. FEATURE INTERFACE The feature interface comprises two I2S-bus input/output ports and a system clock output. Each I2S-bus port is equipped with level adjust facilities that can change the signal level in a range of ±15 dB with 1 dB resolution. Outputs can be disabled to improve EMC performance. Sending illegal data patterns via the I2C-bus will not cause any changes of the current setting for the volume, bass, treble, bass boost and level adjust functions. The I2S-bus output matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2. 6.2.11 EXPERT MODE The TDA9870A provides a special expert mode that gives direct write access to the internal Coefficient RAM (CRAM) of the DSP. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses by means of the bass boost filter. However, this mode must be used with great care. One example of how the feature interface can be used in a TV set is to connect an external Dolby Surround Pro Logic DSP, such as the SAA7710, to the I2S-bus ports. Outputs must be enabled and a suitable master clock signal for the DSP can be taken from pin SYSCLK. A stereo signal from any source will be output on one of the I2S-bus serial data outputs and the four processed signal channels will be entered at both I2S-bus serial data inputs. Left and right could then be output to the power amplifiers via the Main channel, centre and surround via the Auxiliary channel. 1998 Aug 10 CHANNEL FROM THE AUDIO ADC The signal level at the output of the ADC can be adjusted in a range of ±15 dB with 1 dB resolution. The audio ADC itself is scaled to a gain of −6 dB. Balance can be realized by independent control of the left and right channel volume settings. 6.2.6 TDA9870A More information on the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be made available on request. 13 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6.2.12 OVERVIEW OF DSP FUNCTIONS Table 4 Overview of DSP functions EXPERT MODE FUNCTION Bass control for loudspeaker and headphone output Treble control for loudspeaker and headphone output yes yes Contour for loudspeaker output yes Bass boost for loudspeaker output yes TDA9870A PARAMETER VALUE UNIT control range −12 to +15 dB resolution 1 dB resolution at frequency 40 Hz control range −12 to +12 dB resolution 1 dB resolution at frequency 14 kHz control range 0 to +18 dB resolution 1 dB resolution at frequency 40 Hz control range 0 to +20 dB resolution 2 dB resolution at frequency 20 Hz corner frequency 350 Hz control range −83 to +24 dB resolution 1 dB mute position at step 10101100 processing time 32 ms Volume control for each separate channel in loudspeaker and headphone output no Soft-mute for loudspeaker and headphone output no Spatial effects yes anti-phase crosstalk positions 30, 40 and 52 % Pseudo stereo yes 90 degree phase shift at frequency 150, 200 and 300 Hz beep frequencies see Section 10.3.38 Beeper additional to the signal in the loudspeaker and headphone channel yes Automatic Volume Level (AVL) yes General Level adjust Level adjust outputs no I2S1 I2S1 and and I2S2 inputs I2S2 Level adjust analog crossbar path 1998 Aug 10 yes yes no control range 0 to −93 dB resolution 3 dB mute position at step 00100000 step width quasi continuously AVL output level for an input level between 0 and −29 dB full scale −23 dBFS attack time 10 ms decay time constant 2, 4 and 8 s −3 dB lower corner frequency of DSP 10 Hz −1 dB bandwidth of DSP 14.5 kHz control range −15 to +15 dB resolution 1 dB control range −15 to +15 dB resolution 1 dB mute position at step 00010000 control positions 0, 3, 6 and 9 14 dB Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) EXPERT MODE FUNCTION Level adjust audio ADC outputs yes Level adjust FM path 6.3 yes TDA9870A PARAMETER VALUE UNIT control range +15 to −15 resolution 1 dB control range +15 to −15 dB resolution 1 dB dB Description of the analog audio section handbook, full pagewidth SCART 1 2 −3 dB 2 −3 dB 2 2 2 SCART 2 external 2 2 ANALOG CROSSBAR SWITCH 2 ANALOG MATRIX 2 ANALOG MATRIX 2 ANALOG MATRIX 2 2 D 2 FM 2 2 I2S2 2 I2S1 2 I2S2 2 3 dB 2 0 dB 3 dB 2 0 dB SCART 1 SCART 2 Line output 2 A D A I2S1 2 0 dB mono 2 3 dB DSP AND DIGITAL CROSSBAR SWITCH 2 2 D A 2 2 D A Main Auxiliary MHB113 Fig.4 Block diagram for the audio section. 1998 Aug 10 15 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6.3.1 ANALOG CROSSBAR SWITCH AND ANALOG MATRIX (see also Fig.6) 6.3.2 SCART INPUTS The SCART specification allows for a signal level of up to 2 V (RMS). Because of signal handling limitations, due to the 5 V supply voltage of the TDA9870A, it is necessary to have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input. This results in a −3 dB SCART-to-SCART copy gain. If 0 dB copy gain is preferred (with maximum 1.4 V input), there are 3 dB and 0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. There are a number of analog input and output ports with the TDA9870A. Analog source selector switches are employed to provide the desired analog signal routing capability. The analog signal routing is performed by the analog crossbar switch section. A dual audio ADC provides the connection to the DSP section and a dual audio DAC provides the connection from the DSP section to the analog crossbar switch. The digital signal routing is performed by a digital crossbar switch. The input attenuator is realized by an external series resistor in combination with the input impedance, both of which form a voltage divider. With this voltage divider the maximum SCART signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. The basic signal routing philosophy of the TDA9870A is that each switch handles two signal channels at the same time, e.g. left and right, language A and B, directly at the source. 6.3.3 Each source selector switch is followed by an analog matrix to perform further selection tasks, such as putting a signal from one input channel, say language A, to both output channels or for swapping left and right channels. The analog matrix provides the functions given in Table 5 (see also Fig.5). Table 5 TDA9870A EXTERNAL AND MONO INPUTS The 3 dB input attenuators are not required for the external and mono inputs, because those signal levels are under control of the TV designer. The maximum allowed input level is 1.4 V (RMS). By adding external series resistors, the external inputs can be used as an additional SCART input. Analog matrix functions 6.3.4 MATRIX OUTPUT MODE LEFT OUTPUT RIGHT OUTPUT 1 left input right input 2 right input left input 3 left input left input 4 right input right input handbook, halfpage left input right input ANALOG MATRIX The SCART outputs employ amplifiers with two gain settings. The gain can be set to 3 dB or to 0 dB via the I2C-bus. The 3 dB position is needed to compensate for the 3 dB attenuation at the SCART inputs should SCART-to-SCART copies with 0 dB gain be preferred [under the condition of 1.4 V (RMS) maximum input level]. The 0 dB position is needed, for example, for an external-to-SCART copy with 0 dB gain. left output right output MGK110 Fig.5 Analog matrix. All switches and matrices are controlled via the I2C-bus. 1998 Aug 10 SCART OUTPUTS 16 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6.3.5 LINE OUTPUT 6.3.8 The line output can provide an unprocessed copy of the audio signal in the loudspeaker channels. This can be either an external signal that comes from the dual audio ADC, or a signal from an internal digital audio source that comes from the dual audio DAC. The line output employs amplifiers with two gain settings. The 3 dB position is needed to compensate for the attenuation at the SCART inputs, while the 0 dB position is needed, for example, for non-attenuated external or internal digital signals (see Section 6.3.4). 6.3.6 6.3.9 STANDBY MODE The standby mode (subaddress 1, bit 5) disables most functions and reduces power dissipation. The analog crossbar switch and the SCART section remains operational and can be controlled by the I2C-bus to support copying of analog signals from SCART-to-SCART. LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) Signals from any audio source can be applied to the loudspeaker and to the headphone output channels via the digital crossbar switch and the DSP. Unused internal registers may lose their information in standby mode. Therefore, the device needs to be initialized on returning to normal operation. This can be accomplished in the same way as after a power-on reset. DUAL AUDIO DAC 6.3.10 The TDA9870A contains three dual audio DACs, one for the connection from the DSP to the analog crossbar switch section and two for the loudspeaker and headphone outputs. Each of the three dual low-noise high-dynamic range DACs consists of two 15-bit DACs with current outputs, followed by a buffer operational amplifier. The audio DACs operate with four-fold oversampling and noise shaping. 1998 Aug 10 DUAL AUDIO ADC There is one dual audio ADC in the TDA9870A for the connection of the analog crossbar switch section to the DSP. The dual audio ADC consists of two bitstream 3rd-order sigma-delta audio ADCs and a high-order decimation filter. OUTPUTS 6.3.7 TDA9870A SUPPLY GROUND The different supply grounds VSSX are internally connected via substrate. It is therefore recommended to connect all ground pins externally close to the pins by a copper plane. 17 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... DIGITAL MATRIX SCART 2 ADC −6 dB AUTOMATIC VOLUME LEVEL DIGITAL MATRIX mono DIGITAL MATRIX part FM/AM DEMODULATOR ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS STEREO DECODER DAC HEADPHONE CHANNEL PROCESSING DAC Main ADC LEVEL ADJUST external FM/AM LOUDSPEAKER CHANNEL PROCESSING FM LEVEL ADJUST Auxiliary I2S1 OUTPUT LEVEL ADJUST I2S1 I2S2 18 DIGITAL MATRIX I2S1 I2S2 I2S1 INPUT LEVEL ADJUST DIGITAL MATRIX BUFFER 0/+3 dB ANALOG MATRIX BUFFER 0/+3 dB ANALOG MATRIX BUFFER 0/+3 dB Line SCART 1 DAC SCART 2 MHB114 TDA9870A Fig.6 Audio signal flow diagram. DAC GAIN ANALOG MATRIX Product specification I2S2 INPUT LEVEL ADJUST I2S2 OUTPUT LEVEL ADJUST Philips Semiconductors Digital TV Sound Processor (DTVSP) ok, full pagewidth 1998 Aug 10 SCART 1 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD DC supply voltage −0.5 +6.0 V ∆VDD voltage differences between two VDD pins − 550 mV II/O(max) maximum input/output voltage −0.5 VDD + 0.5 V IDDD, ISSD DC VDD or VSS current per digital supply pin − ±180 mA Ilu(prot) latch-up protection current 100 − mA Ptot total power dissipation − 1.2 W Tstg storage temperature −55 +125 °C Tamb operating ambient temperature Ves electrostatic handling −20 +70 °C note 1 2000 − V note 2 200 − V Notes 1. Human body model: C = 100 pF; R = 1.5 kΩ. 2. Machine model: C = 200 pF; L = 0.75 µH; R = 0 Ω. 8 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1998 Aug 10 PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 19 VALUE UNIT 40 K/W Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 9 CHARACTERISTICS VSIF(p-p) = 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain setting in accordance with note 3; VDD = 5 V; Tamb = 25 °C; settings in accordance with B/G standard; FM deviation ±50 kHz; fmod = 1 kHz; FM sound parameters in accordance with system A2; 1 kΩ measurement source resistance for AF inputs; unless otherwise specified; with external components of Fig.8. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD1 digital supply voltage 1 4.75 5.0 5.5 V VSSD1 digital supply ground 1 note 1 − 0.0 − V IDDD1 digital supply current 1 VDDD1 = 5.0 V 53 68 83 mA VDDD2 digital supply voltage 2 4.75 5.0 5.5 V VSSD2 digital supply ground 2 note 1 − 0.0 − V IDDD2 digital supply current 2 VDDD2 = 5.0 V; SYSCLOCK off 0.1 0.4 2 mA VSSD3 digital supply ground 3 note 1 − 0.0 − V VSSD4 digital supply ground 4 note 1 − 0.0 − V VDDA analog supply voltage 4.75 5.0 5.5 V IDDA analog supply current for DAC part VDDA = 5.0 V; digital silence 44 56 68 mA VSSA1 analog ground for analog front-end note 1 − 0.0 − V VSSA2 analog ground for audio ADC part note 1 − 0.0 − V VSSA3 analog ground for audio DAC part note 1 − 0.0 − V VSSA4 analog ground for SCART − 0.0 − V Demodulator supply decoupling and references VDEC1 analog supply decoupling voltage for demodulator part 3.0 3.3 3.6 V Vref1 analog reference voltage for demodulator part − 2 − V Iref1(sink) Vref1 sink current − 200 − µA 3.0 3.3 3.6 V − 50 − % Audio supply decoupling and references VDEC2 analog supply decoupling voltage for audio ADC part Vref2 reference voltage for audio ADCs ZVref2-VDEC2 impedance Vref2 to VDEC2 − 20 − kΩ ZVref2-VSSA2 impedance Vref2 to VSSA2 − 20 − kΩ Vref3 reference voltage for audio DAC and operational amplifier − 50 − % ZVref3-VDDA impedance Vref3 to VDDA − 20 − kΩ ZVref3-VSSA3 impedance Vref3 to VSSA3 − 20 − kΩ 1998 Aug 10 referenced to VDEC2/VSSA2 referenced to VDDA/VSSA3 20 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9870A CONDITIONS MIN. TYP. MAX. UNIT Power fail detector Vth(pf) power fail threshold level − 3.9 − − 0.3VDDD V V Digital inputs and outputs INPUTS CMOS level input, pull-down (pins TEST1 and TEST2) VIL LOW-level input voltage − VIH HIGH-level input voltage 0.7VDDD − − V Ci input capacitance − − 10 pF Zi input impedance − 50 − kΩ − 0.3VDDD V CMOS level input, hysteresis, pull-up (pin CRESET) VIL LOW-level input voltage − VIH HIGH-level input voltage 0.7VDDD − − V Vhys hysteresis voltage − 1.3 − V Ci input capacitance − − 10 pF Zi input impedance − 50 − kΩ INPUTS/OUTPUTS I2C-bus level input with Schmitt trigger, open-drain output stage, 400 kHz I2C operation and level (pins SCL and SDA) VIL LOW-level input voltage − VIH HIGH-level input voltage 0.7VDDD − − − V Vhys hysteresis voltage − 0.05VDDD − V 0.3VDDD V ILI input leakage current − − ±10 µA Ci input capacitance − − 10 pF VOL LOW-level output voltage − − 0.6 V CL load capacitance − − 400 pF TTL/CMOS level, 4 mA 3-state output stage, pull-up (pins ADDR1, ADDR2, P1, P2, SCK, WS, SDO1, SDO2, SDI1 and SDI2) VIL LOW-level input voltage − − VIH HIGH-level input voltage 2.0 Ci input capacitance − VOL LOW-level output voltage VOH CL Zi 1998 Aug 10 0.8 V − − V − 10 pF − − 0.4 V HIGH-level output voltage 2.4 − − V load capacitance − − 100 pF input impedance − 50 − kΩ 21 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9870A CONDITIONS MIN. TYP. MAX. UNIT OUTPUTS CMOS level output, 4 mA 3-state output stage, slew rate controlled (pin SYSCLK) VOL LOW-level output voltage − − 0.3VDDD V VOH HIGH-level output voltage 0.7VDDD − − V CL load capacitance − − 100 pF ILIZ 3-state leakage current Vi = 0 to VDDD − − ±10 µA maximum composite SIF input voltage for clipping (peak-to-peak value) SIF input level adjust 0 dB − 941 − mV SIF input level adjust −10 dB − 2976 − mV minimum composite SIF input voltage for lower limit of AGC (peak-to-peak value) SIF input level adjust 0 dB − 59 − mV SIF input level adjust −10 dB − 188 − mV − 24 − dB 4 − 9.2 MHz 10 − − kΩ − 7.5 11 pF SIF1 and SIF2 analog inputs VSIF(max)(p-p) VSIF(min)(p-p) AGC AGC range fi input frequency Ri input resistance Ci input capacitance ∆fFM FM deviation B/G standard; THD < 1% ±100 − − kHz ∆fFM(FS) FM deviation full-scale level terrestrial FM; level adjust 0 dB ±150 − − kHz C/NFM FM carrier C/Nc ratio NFM bandwidth = 6 MHz; white noise for S/N = 40 dB; “CCIR468”; quasi peak − 77 − αct crosstalk attenuation SIF1 to SIF2 fi = 4 to 9.2 MHz; note 2 50 − − dB − 0.3 0.5 % AGCLEV = 0 dB FM -------------Hz Demodulator performance; note 3 THD + N total harmonic distortion plus noise from FM source to any output; Vo = 1 V (rms) with low-pass filter S/N signal-to-noise ratio SC1 from FM source to any 64 output; Vo = 1 V (rms); “CCIR468”; quasi peak 70 − dB SC2 from FM source to any 60 output; Vo = 1 V (rms); “CCIR468”; quasi peak 66 − dB B−3dB −3 dB bandwidth from FM source to any output 14.5 15 − kHz fres frequency response 20 Hz to 14 kHz from FM to any output; fref = 1 kHz; inclusive pre-emphasis and de-emphasis − ±2 − dB αcs(dual) dual signal channel separation note 4 65 70 − dB 1998 Aug 10 22 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9870A CONDITIONS MIN. TYP. MAX. UNIT αcs(stereo) stereo channel separation note 5 40 45 − dB αAM AM suppression for FM AM: 1 kHz, 30% modulation; reference: 1 kHz, 50 kHz deviation 50 − − dB S/NAM AM demodulation SIF level 100 mV (RMS); 54% AM; 1 kHz AF; “CCIR468”; quasi peak 36 45 − dB IDENTIFICATION FOR FM SYSTEMS modp pilot modulation for identification 25 50 75 % C/Np pilot sideband C/N for identification start − 27 − dB ------Hz fident identification window slow mode 116.85 − 118.12 Hz medium mode 116.11 − 118.89 Hz fast mode 114.65 − 120.46 Hz slow mode 273.44 − 274.81 Hz medium mode 272.07 − 276.20 Hz fast mode 270.73 − 277.60 Hz slow mode − − 2 s medium mode − − 1 s fast mode − − 0.5 s slow mode − − 2 s medium mode − − 1 s fast mode − − 0.5 s B/G stereo B/G dual tident(on) tident(off) total identification time ON total identification time OFF Analog audio inputs MONO INPUT AND EXTERNAL INPUT Vi(nom)(rms) nominal level input voltage (RMS value) note 3 − 500 − mV Vi(clip)(rms) clipping level input voltage (RMS value) THD < 3%; note 6 1250 1400 − mV Ri input resistance note 6 28 35 42 kΩ Vi(nom)(rms) nominal level input voltage at input pin (RMS value) −3 dB divider with external 15 kΩ resistor; notes 3 and 7 − 350 − mV Vi(clip)(rms) clipping level input voltage at input pin (RMS value) −3 dB divider with external 15 kΩ resistor; THD < 3%; notes 6 and 7 1250 1400 − mV Ri input resistance note 6 28 35 42 kΩ SCART INPUTS 1998 Aug 10 23 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9870A CONDITIONS MIN. TYP. MAX. UNIT Analog audio outputs LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS clipping level output voltage (RMS value) Ro output resistance 150 250 375 Ω RL(AC) AC load resistance 10 − − kΩ RL(DC) DC load resistance 10 − − kΩ CoL output load capacitance − 10 12 nF Voffset(DC) static DC offset voltage − 30 70 mV αmute mute suppression nominal input signal from any source; fi = 1 kHz; note 3 80 − − dB Gro(main,aux) roll-off gain at 14.5 kHz for Main and Auxiliary channels from any source −3 −2 − dB fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 µF; signal from I2S-bus 40 45 − dB PSRRmain,aux power supply ripple rejection for Main and Auxiliary channels THD < 3% 1250 1400 − Vo(clip)(rms) mV SCART OUTPUTS AND LINE OUTPUT Vo(nom)(rms) nominal level output voltage (RMS value) 3 dB amplification; note 3 − 500 − mV Vo(clip)(rms) clipping level output voltage (RMS value) THD < 3% 1250 1400 − mV Ro output resistance 150 250 375 Ω RL(AC) AC load resistance 10 − − kΩ RL(DC) DC load resistance 10 − − kΩ CoL output load capacitance − − 2.5 nF Voffset(DC) static DC offset voltage output amplifiers at 3 dB position − 30 50 mV αmute mute suppression nominal input signal from any source; fi = 1 kHz; note 3 80 − − dB B bandwidth from SCART, external and mono sources; −3 dB bandwidth 20 − − kHz from DSP sources; −3 dB bandwidth 14.5 − − kHz fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 µF; signal from I2S-bus 40 45 − dB PSRR 1998 Aug 10 power supply ripple rejection 24 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9870A CONDITIONS MIN. TYP. MAX. UNIT Audio performance THD + N S/N αct αcs GA 1998 Aug 10 total harmonic distortion plus noise Vi = Vo = 1 V (RMS); fi = 1 kHz; bandwidth 20 Hz to 15 kHz; note 8 from any analog audio input to I2S-bus − 0.1 0.3 % from I2S-bus to any analog audio output − 0.1 0.3 % SCART-to-SCART copy − 0.1 0.3 % SCART-to-Main copy − 0.2 0.5 % from any analog audio input to I2S-bus 73 77 − dB from I2S-bus to any analog audio output 78 85 − dB SCART-to-SCART copy 78 85 − dB SCART-to-Main copy 73 77 − dB between any analog input pairs; fi = 1 kHz 70 − − dB between any analog output pairs; fi = 10 kHz 65 − − dB between left and right of any input pair 65 − − dB between left and right of any output pair 60 − − dB gain from SCART-to-SCART output amplifier in 3 dB with −3 dB input voltage divider position; Rext = 15 kΩ ±10% −1.5 0 +1.1 dB output amplifier in 0 dB position; Rext = 15 kΩ ±10% −4.5 −3.0 −1.9 dB signal-to-noise ratio crosstalk attenuation channel separation reference voltage Vo = 1.4 V (RMS); fi = 1 kHz; “CCIR468”; quasi peak; note 8 25 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9870A CONDITIONS MIN. TYP. MAX. UNIT Crystal specification (fundamental mode) fxtal crystal frequency − 24.576 − MHz CL load capacitance − 20 − pF C1 series capacitance − 20 − fF pF C0 parallel capacitance − − 7 Φpull pulling sensitivity CL changed from 18 to 16 pF − 25 − RR equivalent series resistance at nominal frequency − − 30 Ω RN equivalent series resistance of unwanted mode 2RR − − Ω ∆T temperature range −20 +25 +70 °C XJ adjustment tolerance − − ±30 10−6 XD drift − − ±30 10−6 XA ageing − − ±5 across temperature range –6 10 ----------pF –6 10 ----------year Notes 1. All analog and digital supply ground pins are connected internally. 2. Set demodulator to AM mode. Apply an AM carrier (with 1 kHz and 100%) to one channel. Check AGC step. Switch AGC off and set AGC to the gain step found. Measure the 1 kHz signal level of this channel and take it as a reference. Switch to the other SIF input to which no signal is connected and which is terminated with 50 Ω. Measure now the 1 kHz crosstalk signal level. The SIF source resistance should be low (50 Ω). 3. Definitions of levels and level setting: The full-scale level for analog audio signals is VFS = 1.4 V (RMS). The nominal level at the digital crossbar switch is defined at −15 dB (full-scale). Nominal audio input levels: external, mono: 500 mV (RMS); −9 dB (full-scale). See also Tables 6 and 7. 4. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output; Vo = 1 V (RMS) of modulated channel. 5. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output; Vo = 1 V (RMS) of modulated channel. The stereo channel separation may be limited by adjustment tolerances of the transmitter. 6. If the supply voltage for the TDA9870A is switched off, because of the ESD protection circuitry, all audio input pins are short-circuited. To avoid a short-circuit at the SCART inputs a 15 kΩ resistor (−3 dB divider) has to be used. 7. The SCART specification allows a signal level of up to 2 V (RMS). Because of signal handling limitations due to the 5 V supply voltage for the TDA9870A, there is a need for fixed 3 dB attenuators at the SCART inputs. To achieve SCART-to-SCART copies with 0 dB gain, there are 3 dB and 0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. The attenuator is realized by an internal resistor that works together with an external series resistor as a voltage divider. With this voltage divider the maximum SCART input signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. To avoid clipping, the 3 dB gain must not be used if the SCART input signal is larger than 1.4 V (RMS). 8. ADC level adjust = 6 dB, all other level adjusts = 0 dB, if external −3 dB divider is used set output buffer gain to 3 dB, tone control to 0 dB, AVL off and volume control to 0 dB. 1998 Aug 10 26 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... IDENT DE-EMPHASIS OF CARRIER #1 AND CARRIER #2 FM LEVEL ADJUST SETTING OF CARRIER #1 AND CARRIER #2 4.724 MHz on 75 µs 9 dB 5.5 MHz 5.742 MHz on 50 µs 4 dB 6.5 MHz 6.742 MHz on 50 µs 4 dB TRANSMITTER NOMINAL MODULATION DEPTH NOMINAL LEVEL AT DEMODULATOR OUTPUT (FULL-SCALE) M 15 kHz deviation −24 dB; note 2 4.5 MHz B/G 27 kHz deviation −19 dB D/K 27 kHz deviation −19 dB CARRIER #1 FREQUENCY FREQUENCY 27 kHz deviation −19 dB 6.5 MHz 6.25 MHz on 50 µs 4 dB 27 kHz deviation −19 dB 6.5 MHz 5.742 MHz on 50 µs 4 dB Notes 1. Nominal level at digital crossbar is defined at −15 dB (full-scale). DAC gain setting 6 dB. Output buffer setting 0 dB. Nominal SCART output level 500 mV (RMS). 2. For stereo signals the output level is 6 dB lower. The level adjust has to be increased by 6 dB. 27 Table 7 Level setting SAT FM 0 dB (full-scale) = 1.4 V (RMS). SOURCE TRANSMITTER MAXIMUM MODULATION DEPTH NOMINAL LEVEL AT DEMODULATOR OUTPUT (FULL-SCALE) FM LEVEL ADJUST SETTING MAXIMUM LEVEL AT CROSSBAR (FULL-SCALE) DAC GAIN SETTING OUTPUT BUFFER NOMINAL SCART OUTPUT VOLTAGE SAT FM, stereo 50 kHz deviation SAT FM, mono 85 kHz deviation −13 dB 4 dB −9 dB 6 dB 0 dB 1 V (RMS) −9 dB 0 dB Philips Semiconductors CARRIER #2 2 CHANNEL FM STANDARD Digital TV Sound Processor (DTVSP) 1998 Aug 10 Table 6 FM level setting 0 dB (full-scale) = 1.4 V (RMS); note 1. Product specification TDA9870A Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10 I2C-BUS CONTROL 10.2 10.1 At power-up the device is in the following state: Introduction • All outputs muted The TDA9870A is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers. Status information can be read from an array of registers to enable the controlling microcontroller to determine whether any action is required. • No sound carrier frequency loaded • General purpose I/O pins ready for input (HIGH) • Input SIF1 selected with: – AGC on The device has an I2C-bus slave transceiver, in accordance with the fast-mode specification, with a maximum speed of 400 kbits/s. Information concerning the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar or complementary functions, there are four possible slave addresses available which can be selected by pins ADDR1 and ADDR2 (see Table 8). Table 8 – Small hysteresis – SIF input level shift 0 dB. • Demodulators for both sound carriers set to FM with: – Identification for B/G, D/K, response time 1 s – Level adjust set to 0 dB – De-emphasis 50 µs – Matrix set to mono. • Main channel set to FM input with: Possible slave addresses ADDR2 ADDR1 SLAVE ADDRESS A6 TO A0 0 0 1011000 0 1 1011001 1 0 1011010 1 1 1011011 Power-up state – Spatial off – Pseudo off – AVL off – Volume mute – Bass flat – Treble flat – Contour off The I2C-bus interface remains operational in the standby mode of the TDA9870A to allow control of the analog source selectors with regard to SCART-to-SCART copying. – Bass boost flat. • Auxiliary channel set to FM input with: – Volume mute The device will not respond to a ‘general call’ on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master. – Bass flat – Treble flat. • Feature interface all outputs off The data transmission between the microcontroller and the other I2C-bus controlled ICs is not disturbed when the supply voltage of the TDA9870A is not connected. • Beeper off • Monitoring of carrier 1 FM demodulator DC output. After power-up a device initialization has to be performed via the I2C-bus to put the TDA9870A into the proper mode of operation, in accordance with the desired TV standard, audio control settings, etc. 1998 Aug 10 28 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3 TDA9870A Slave receiver mode As a slave receiver, the TDA9870A provides 46 registers for storing commands and data. These registers are accessed via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location. Table 9 S I2C-bus; slave address, subaddress and data format SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA ACK P Table 10 Explanation of Table 9 BIT FUNCTION S START condition SLAVE ADDRESS 7-bit device address 0 data direction bit (write to device) ACK acknowledge by slave SUBADDRESS address of register to write to DATA data byte to be written into register P STOP condition It is allowed to send more than one data byte per transmission to the TDA9870A. In this event, the subaddress is automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with ACK (acknowledge). There is no ‘wrap-around’ of subaddresses. Commands and data are processed as soon as they have been completely received. Functions requiring more than one byte will, thus, be executed only after all bytes for that function have been received. If the transmission is terminated (STOP condition) before all bytes have been received, the incomplete data for that function is ignored. Table 11 Format for a transmission employing auto-increment of subaddresses S SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA BYTE A(1) DATA ACK P Note 1. n data bytes with auto-increment of subaddresses. Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the functions of volume, bass, treble control, bass boost and level adjust. Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will not then be executed. 1998 Aug 10 29 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A Table 12 Overview of the slave receiver registers DATA SUBADDRESS (DECIMAL) MSB 0 0 FUNCTION LSB 0 s g g g g g AGC level shift, AGC gain selection 1 c c c c c c c c general configuration 2 p 0 0 m m s s s monitor select, peak detector on/off 3 f f f f f f f f carrier 1 frequency; MS part 4 f f f f f f f f carrier 1 frequency 5 f f f f f f f f carrier 1 frequency; LS part 6 f f f f f f f f carrier 2 frequency; MS part 7 f f f f f f f f carrier 2 frequency 8 f f f f f f f f carrier 2 frequency; LS part 9 c c c c c c c c demodulator configuration 10 d d d d d d d d FM de-emphasis 11 0 0 0 0 0 m m m FM matrix 12 0 0 0 l l l l l channel 1 output level adjust 13 0 0 0 l l l l l channel 2 output level adjust 14 0 0 0 0 0 0 0 0 set to logic 0; note 1 15 0 0 0 0 0 0 0 0 set to logic 0; note 1 16 0 0 0 0 0 0 0 0 set to logic 0; note 1 17 0 0 0 0 0 0 0 0 set to logic 0; note 1 18 m m m m m m m m audio mute control 19 g m m m g s s s DAC output select 20 0 g m m 0 s s s SCART 1 output select 21 0 g m m 0 s s s SCART 2 output select 22 0 g m m 0 0 0 s line output select 23 s s s l l l l l ADC output select 24 0 m m m 0 s s s Main channel select 25 0 0 s s p p a a audio effects (AVL, pseudo, spatial) 26 v v v v v v v v volume control, Main left 27 v v v v v v v v volume control, Main right 28 0 0 0 c c c c c contour control, Main 29 0 0 0 b b b b b bass control, Main 30 0 0 0 t t t t t treble control, Main 31 0 m m m 0 s s s Auxiliary channel select 32 v v v v v v v v volume control, Auxiliary left 33 v v v v v v v v volume control, Auxiliary right 34 0 0 0 b b b b b bass control, Auxiliary 35 0 0 0 t t t t t treble control, Auxiliary 36 0 0 0 c c c c c feature interface configuration 37 0 m m m 0 s s s I2S1 output select 1998 Aug 10 30 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A DATA SUBADDRESS (DECIMAL) MSB FUNCTION LSB 38 0 0 0 i i i i i I2S1 input level adjust 39 0 0 0 o o o o o I2S1 output level adjust 40 0 m m m 0 s s s I2S2 output select 41 0 0 0 i i i i i I2S2 input level adjust 42 0 0 0 o o o o o I2S2 output level adjust 43 0 0 0 0 0 f f f beeper frequency 44 0 0 v v v v v v beeper volume, Main and Auxiliary 45 b b b b b b b b bass boost, Main left and right Note 1. These bits have not been assigned to a function. The following sub-sections provide a detailed description of the slave receiver registers: 10.3.1 AGC GAIN REGISTER 10.3.1.1 Description If the automatic gain control function is switched off in the general configuration register, the contents of this register will define a fixed gain of the AGC stage. The input voltages given are meant to generate a full scale output from the SIF ADC. If automatic gain control is on, the AGCGAIN setting is ignored. After switching off the automatic gain control function, the latest gain control setting is copied to the AGC gain register. If the AGC input level shift bit AGCLEV is set to HIGH the input signal is scaled with −10 dB. The AGCLEV bit is also active if the automatic gain function is enabled. It should be noted that the input voltages should be considered as approximate target values. Table 13 Description of the AGC gain register BIT NAME 7 (MSB) − set to logic 0 6 − set to logic 0 5 AGCLEV 4 AGCGAIN If the automatic gain control function is switched off in the general configuration register, the contents of this register will define a fixed gain of the AGC stage. 3 DESCRIPTION If the AGC input level shift bit AGCLEV is set to HIGH the input signal is scaled with −10 dB. The AGCLEV bit is also active if the automatic gain function is enabled. 2 1 0 (LSB) 1998 Aug 10 31 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.1.2 TDA9870A Definition Table 14 Subaddress 0 MSB LSB AGC GAIN SIF INPUT VOLTAGE (dB) (mV (p-p)) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0/1 1 1 1 1 1 0.0 941/2976 0 0 0/1 1 1 1 1 0 0.8 861/2723 0 0 0/1 1 1 1 0 1 1.5 788/2490 0 0 0/1 1 1 1 0 0 2.3 720/2278 0 0 0/1 1 1 0 1 1 3.1 659/2084 0 0 0/1 1 1 0 1 0 3.9 603/1906 0 0 0/1 1 1 0 0 1 4.6 551/1744 0 0 0/1 1 1 0 0 0 5.4 504/1595 0 0 0/1 1 0 1 1 1 6.2 461/1459 0 0 0/1 1 0 1 1 0 7.0 422/1334 0 0 0/1 1 0 1 0 1 7.7 386/1221 0 0 0/1 1 0 1 0 0 8.5 353/1117 0 0 0/1 1 0 0 1 1 9.3 323/1021 0 0 0/1 1 0 0 1 0 10.1 295/934 0 0 0/1 1 0 0 0 1 10.8 270/855 0 0 0/1 1 0 0 0 0 11.6 247/782 0 0 0/1 0 1 1 1 1 12.4 226/715 0 0 0/1 0 1 1 1 0 13.2 207/654 0 0 0/1 0 1 1 0 1 13.9 189/598 0 0 0/1 0 1 1 0 0 14.7 173/547 0 0 0/1 0 1 0 1 1 15.5 158/501 0 0 0/1 0 1 0 1 0 16.3 145/458 0 0 0/1 0 1 0 0 1 17.0 132/419 0 0 0/1 0 1 0 0 0 17.8 121/383 0 0 0/1 0 0 1 1 1 18.6 111/350 0 0 0/1 0 0 1 1 0 19.4 101/321 0 0 0/1 0 0 1 0 1 20.1 93/293 0 0 0/1 0 0 1 0 0 20.9 85/268 0 0 0/1 0 0 0 1 1 21.7 78/245 0 0 0/1 0 0 0 1 0 22.5 71/224 0 0 0/1 0 0 0 0 1 23.2 65/205 0 0 0/1 0 0 0 0 0 24.0 59/188 (note 1) Note 1. The default setting at power-up is 00000000. 1998 Aug 10 32 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.2 TDA9870A GENERAL CONFIGURATION REGISTER 10.3.2.1 Description Table 15 Description of Table 16 NAME HIGH/LOW FUNCTION SIFSEL HIGH LOW HIGH LOW Selects pin SIF2 for input (recommended for satellite tuner). Pin SIF1 (terrestrial TV) is selected. Forces the AGC block to a fixed gain as defined in the AGC gain register. The automatic gain control function is enabled and the contents of the AGC gain register is ignored. A longer decay time is selected for input signals with strong video modulation (intercarrier). This bit only has an effect when bit AGCOFF = 0. Selects normal attack and decay times for the AGC. Resets the power fail detector to LOW. This bit is automatically reset to LOW after bit POR in the device status register has been reset. Causes initialization of TDA9870A to its default settings. This has the same effect as a power-on reset. If there is a conflict between the default settings and any bit set HIGH in this register, the bits of this register have priority over the corresponding default setting. This bit is automatically reset to LOW after initialization. When set LOW, the TDA9870A is in its normal mode of operation. Puts the TDA9870A into the standby mode. Most functions are disabled and power dissipation is somewhat reduced, but the analog selectors/matrices remain operational to support analog copying from SCART-to-SCART and vice versa. The TDA9870A is in its normal mode of operation. On return from standby mode, the device is in its power-on reset mode and needs to be re-initialized. These bits control the general purpose input/output pins. The contents of these bits is written directly to the corresponding pins. If input is desired, the bits must be set HIGH to allow the pins to be pulled LOW externally. Input from the pins is reflected in the device status register (see Section 10.4, subaddress 0). P1OUT is recommended to be used for switching an SIF trap for the adjacent picture carrier in designs that employ such a trap. AGCOFF AGCSLOW HIGH CLRPOR LOW HIGH LOW INIT HIGH LOW STDBY HIGH LOW − P1OUT, P2OUT 10.3.2.2 Definition Table 16 Subaddress 1 (note 1) BIT NAME DESCRIPTION 7 (MSB) P2OUT general purpose I/O pin 2 6 P1OUT general purpose I/O pin 1 5 STDBY standby mode on/off 4 INIT initialize to defaults (as reset) 3 CLRPOR clear power-on reset flip-flop 2 AGCSLOW 1 AGCOFF 0 (LSB) SIFSEL AGC decay time AGC on/off SIF input select Note 1. The default setting at power-up is 11000000. 1998 Aug 10 33 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.3 TDA9870A MONITOR SELECT REGISTER 10.3.3.1 Description This register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be monitored. Peak level refers to the magnitude of the maximum excursion of a signal. Data can be read-out in the I2C-bus slave transmitter mode (see Section 10.4, subaddresses 5 and 6). Audio magnitude/phase is related to the FM demodulator output. Phase information is provided, when it operates in FM mode, while magnitude is supplied in AM mode. Table 17 Description of bit PEAKMON NAME HIGH/LOW PEAKMON 10.3.3.2 FUNCTION HIGH selects the peak level of a source to be monitored LOW the last sample will be supplied Definition Table 18 Subaddress 2 (note 1) MSB LSB B7 B6 B5 PEAKMON 0 0 B4 B3 B2 see Table 20 B1 B0 see Table 19 Note 1. The default setting at power-up is 00000000. Table 19 Signal source (note 1) B2 B1 B0 SIGNAL SOURCE 0 0 0 DC output of FM demodulator 0 0 1 audio magnitude/phase, FM demodulator output 0 1 0 crossbar input from FM/AM channel 0 1 1 don’t care 1 0 0 crossbar input from I2S1 channel 1 0 1 crossbar input from I2S2 channel 1 1 0 crossbar input from audio ADC channel 1 1 1 input to Main channel DAC (without beeper) Note 1. The term ‘crossbar’ refers to the digital selector, where level-adjusted signals from various sources are available. 1998 Aug 10 34 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.4.2 Table 20 Monitor output Definition Most significant part at subaddress 3. B4 B3 MONITOR OUTPUT 0 0 L input + R input ------------------------------------------2 0 1 L input (channel 1, respectively) BIT 1 0 R input (channel 2, respectively) 7 (MSB) Table 21 Subaddresses 3 to 5 SUBADDRESSES 6 10.3.3.3 Note 5 4 By reading out level read-out registers (subaddresses 5 and 6, see Section 10.4), the current peak level will be reset. 10.3.4 10.3.4.1 3 2 1 CARRIER 1 FREQUENCY REGISTER 0 Description 7 The three bytes together constitute a 24-bit frequency control word to represent the sound carrier (i.e. mixer) frequency in accordance with the following formula: f mix 24 data = --------- × 2 f clk 6 Where: 1 5 4 3 4 2 data = 24-bit frequency control word. 0 fmix = desired sound carrier frequency. 7 fclk = 12.288 MHz (clock frequency of mixer). 6 224 = 16777216 (number of steps in a 24-bit word size). 5 4 Example: A 5.5 MHz sound carrier frequency will be generated by sending the following sequence of data bytes to the TDA9870A (data = 7509333 in decimal notation or 729555 in HEX): 01110010 10010101 01010101. 3 5 2 1 0 (LSB) As three bytes are required to define a carrier frequency, execution of this command starts only after all bytes have been received. If an error occurs, e.g. a premature STOP condition, partial data for this function is ignored. 10.3.5 10.3.5.1 CARRIER 2 FREQUENCY REGISTER Description Same as for sound carrier 1. The default setting at power-up is 00000000 for all three bytes. 1998 Aug 10 3 If the carrier 2 frequency register is used, it will be for the second FM sound carrier of a terrestrial or satellite FM program. 35 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.5.2 TDA9870A Definition Subaddresses 6 to 8. Same as for sound carrier 1, except for subaddresses used. 10.3.6 DEMODULATOR CONFIGURATION REGISTER 10.3.6.1 Description Table 22 Description of subaddress 9 (notes 1 and 2) NAME HIGH/LOW FUNCTION CH1MODE HIGH selects the hardware for the first sound carrier to operate in AM mode LOW FM mode is assumed. This applies to both terrestrial and satellite FM reception. FILTBW0, FILTBW1 − selects the filter bandwidth for channel 1 and channel 2 in accordance with Table 25 CH2MOD0, CH2MOD1 − These bits control the hardware for the second sound carrier in accordance with the truth Table 24. HIGH selects FM identification frequencies in accordance with the specification for Korea LOW frequencies for Europe are selected (B/G and D/K standard) IDAREA − IDMOD0, IDMOD1 These bits define the response time after which a sound mode identification result may be expected. The longer the time, the more reliable the identification. Notes 1. It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial 2-carrier sound. 2. Switching the identification off will reset the associated hardware to a defined state. 10.3.6.2 Definition Table 23 Subaddress 9 (note 1; see Table 22) BIT NAME 7 (MSB) IDMOD1 6 IDMOD0 5 IDAREA 4 FILTBW1 3 CH2MOD1 2 CH2MOD0 1 FILTBW0 0 (LSB) CH1MODE DESCRIPTION response time for FM sound mode identification application area for FM identification selects filter bandwidth in accordance with Table 25 channel 2 receive mode selects filter bandwidth in accordance with Table 25 channel 1 receive mode Note 1. The default setting at power-up is 00000000. 1998 Aug 10 36 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A Table 24 Channel 2 receive mode (see Table 23) B3 B2 CHANNEL 2 0 0 FM 0 1 AM 1 0 don’t care Table 25 Filter bandwidth Channel 1 and Channel 2 (see Table 23) FILTER BANDWIDTH B4 B1 FILTER MODES CH1 CH2 narrow narrow recommended for nominal terrestrial broadcast conditions and SAT with 2 carriers extra wide narrow recommended only for high-deviation SAT mono carriers (e.g. obsolete main channel on Astra) recommended for moderately overmodulated broadcast conditions 0 0 0 1 1 0 medium medium 1 1 wide wide recommended for strongly overmodulated broadcast conditions Table 26 Identification mode (see Table 23) 10.3.7 10.3.7.1 B7 B6 IDENT MODE 0 0 slow 0 1 medium 1 0 fast 1 1 off/reset FM DE-EMPHASIS REGISTER Description This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2. In the event of A2 reception, both groups must be set to the same characteristics. 10.3.7.2 Definition Table 27 Subaddress 10 (note 1) BIT NAME DESCRIPTION 7 (MSB) 6 5 4 3 2 1 0 (LSB) ADEEM2 adaptive de-emphasis on/off time constant selection for FM de-emphasis ADEEM1 adaptive de-emphasis on/off time constant selection for FM de-emphasis Note 1. The default setting at power-up is 00000000. 1998 Aug 10 37 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A Table 28 De-emphasis B6, B2 B5, B1 B4, B0 DE-EMPHASIS 0 0 0 50 µs (Europe) 0 0 1 60 µs 0 1 0 75 µs (M standard) 0 1 1 J17 1 0 0 off Table 29 Description of bits ADEEM1 and ADEEM2 (note 1) NAME HIGH/LOW ADEEM1, ADEEM2 FUNCTION HIGH Activates the adaptive de-emphasis function, which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 µs. LOW the adaptive de-emphasis is off Note 1. The FM de-emphasis gain is 0 dB at 40 Hz. 10.3.8 FM MATRIX REGISTER 10.3.8.1 Description This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received carrier and the related sound mode identification. 10.3.8.2 Definition Table 30 Subaddress 11 (notes 1) MSB LSB B7 B6 B5 B4 B3 0 0 0 0 0 Note 1. The default setting at power-up is 00000000. 1998 Aug 10 38 B2 B1 see Table 31 B0 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A Table 31 Description of Subaddress 11 (bits B2 to B0) B2 B1 B0 L OUTPUT R OUTPUT 0 0 0 0 CH1 input; note 1 CH1 input; note 1 mono 1 0 1 CH2 input; note 2 CH2 input; note 2 mono 2 0 1 0 CH1 input; note 1 CH2 input; note 2 dual 0 1 1 CH2 input; note 2 CH1 input; note 1 dual swapped 1 0 0 2CH1 input − CH2 input CH2 input; note 2 stereo Europe 1 0 1 CH1 input + CH2 input ----------------------------------------------------------2 stereo Korea; note 3 CH1 input – CH2 input ----------------------------------------------------------2 MODE Notes 1. CH1: audio signal from FM channel 1. 2. CH2: audio signal from FM channel 2. 3. See Table 6. For stereo Korea the dematrix applies 6 dB attenuation. 10.3.9 10.3.9.1 FM CHANNEL 1 LEVEL ADJUST REGISTER Description This register is used to correct for standard and station-dependent differences of signal levels. Table 32 applies to sound carrier 1. 1998 Aug 10 39 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.9.2 TDA9870A Definition Table 32 Subaddress 12 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Note 1. The default setting at power-up is 00000000. 10.3.10 FM CHANNEL 2 LEVEL ADJUST REGISTER 10.3.10.1 Description This register is used to correct for standard and station-dependent differences of signal levels. Table 33 applies to sound carrier 2 in its FM and AM modes. In the event of A2, channels 1 and 2 should be adjusted to the same level. 1998 Aug 10 40 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.10.2 Definition Table 33 Subaddress 13 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 (note 1) 0 0 0 1 1 1 1 1 −1 0 0 0 1 1 1 1 0 −2 0 0 0 1 1 1 0 1 −3 0 0 0 1 1 1 0 0 −4 0 0 0 1 1 0 1 1 −5 0 0 0 1 1 0 1 0 −6 0 0 0 1 1 0 0 1 −7 0 0 0 1 1 0 0 0 −8 0 0 0 1 0 1 1 1 −9 0 0 0 1 0 1 1 0 −10 0 0 0 1 0 1 0 1 −11 0 0 0 1 0 1 0 0 −12 0 0 0 1 0 0 1 1 −13 0 0 0 1 0 0 1 0 −14 0 0 0 1 0 0 0 1 −15 0 0 0 1 0 0 0 0 mute Note 1. The default setting at power-up is 00000000. 1998 Aug 10 41 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.11 REGISTER 14 10.3.14 REGISTER 17 10.3.11.1 Description 10.3.14.1 Description Set to logic 0. This bits have not been assigned to a function. Set to logic 0. This bits have not been assigned to a function. 10.3.12 REGISTER 15 10.3.15 AUDIO MUTE CONTROL REGISTER 10.3.12.1 Description 10.3.15.1 Description Set to logic 0. This bits have not been assigned to a function. When any of these bits are set HIGH, the corresponding pair of output channels will be muted. A LOW bit allows normal signal output. 10.3.13 REGISTER 16 There is a soft-mute facility for the Main and Auxiliary output channels to provide click-free muting independent of the volume control. This is switched on/off by bits MUTMAIN and MUTAUX. 10.3.13.1 Description Set to logic 0. This bits have not been assigned to a function. 10.3.15.2 Definition Table 34 Subaddress 18 (note 1) BIT NAME DESCRIPTION 7 (MSB) MUTI2S2 mute I2S2 outputs 6 MUTI2S1 mute I2S1 outputs 5 MUTDAC mute internal DAC 4 MUTLINE mute line outputs 3 MUTSC2 mute SCART 2 outputs 2 MUTSC1 mute SCART 1 outputs 1 MUTAUX mute Auxiliary outputs 0 (LSB) MUTMAIN mute Main channels Note 1. The default setting at power-up is 11111111. 10.3.16 DAC OUTPUT SELECT REGISTER 10.3.16.1 Description This register is used to define both the signal source to be entered into the DAC and the mode of the digital matrix for signal selection. The DAC is used for signal output from digital sources at analog outputs. The bits DACGAIN1 and DACGAIN2 can introduce some extra gain at the input to the DAC. DACGAIN1 adds 3 dB and DACGAIN2 adds 6 dB of gain, respectively. 1998 Aug 10 42 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.16.2 Definition Table 35 Subaddress 19 (note 1) MSB LSB B7 B6 DACGAIN2(2) B5 B4 B3 B2 B1 DACGAIN1(2) see Table 37 B0 see Table 36 Notes 1. The default setting at power-up is 00000000. 2. See Table 38. Table 36 Signal source left and right SIGNAL SOURCE B2 B1 B0 LEFT RIGHT 0 0 0 0 0 1 FM left FM right 0 1 0 I2S1 left I2S1 right 0 1 1 I2S2 left I2S2 right 1 0 0 ADC left ADC right 1 0 1 AVL left AVL right 1 1 0 don’t care 1 1 1 don’t care B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 don’t care Table 37 Bits B6 to B4 Table 38 Description of bits DACGAIN1 and DACGAIN2 1998 Aug 10 B7 B3 GAIN (dB) 0 0 0 0 1 3 1 0 6 1 1 9 43 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.17 SCART 1 OUTPUT SELECT REGISTER 10.3.17.1 Description This register is used to define both the signal source to be output at SCART 1 and the output channel selector mode. 10.3.17.2 Definition Table 39 Subaddress 20 (note 1) MSB LSB B7 B6 0 SC1GAIN(2) B5 B4 B3 see Table 41 B2 0 B1 B0 see Table 40 Notes 1. The default setting at power-up is 00000001. 2. See Table 42. Table 40 Signal source B2 B1 B0 SIGNAL SOURCE 0 0 0 SCART 1 input 0 0 1 SCART 2 input 0 1 0 external input 0 1 1 mono input 1 0 0 DAC input B5 B4 L OUTPUT R OUTPUT 0 0 L input R input 0 1 L input L input 1 0 R input R input 1 1 R input L input Table 41 Bits B5 and B4 Table 42 Description of bit SC1GAIN NAME SC1GAIN 1998 Aug 10 HIGH/LOW FUNCTION HIGH Activates the 3 dB gain stage at the SCART 1 output buffers. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 2 input to SCART 1 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. LOW The audio signal will be output unchanged (0 dB gain). 44 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.18 SCART 2 OUTPUT SELECT REGISTER 10.3.18.1 Description This register is used to define both the signal source to be output at SCART 2 and the output channel selector mode. 10.3.18.2 Definition Table 43 Subaddress 21 (note 1) MSB LSB B7 B6 0 SC2GAIN(2) B5 B4 B3 see Table 45 B2 0 B1 B0 see Table 44 Notes 1. The default setting at power-up is 00000000. 2. See Table 46. Table 44 Signal source B2 B1 B0 SIGNAL SOURCE 0 0 0 SCART 1 input 0 0 1 SCART 2 input 0 1 0 external input 0 1 1 mono input 1 0 0 DAC input B5 B4 L OUTPUT R OUTPUT 0 0 L input R input 0 1 L input L input 1 0 R input R input 1 1 R input L input Table 45 Bits B5 and B4 Table 46 Description of bit SC2GAIN NAME HIGH/LOW FUNCTION SC2GAIN HIGH Activates the 3 dB gain stage at the SCART 2 output buffers. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 1 input to SCART 2 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. LOW The audio signal will be output unchanged (0 dB gain). 1998 Aug 10 45 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.19 LINE OUTPUT SELECT REGISTER 10.3.19.1 Description By definition, the line output conveys the same signal as the Main (loudspeaker) channel, but in a non-processed form. This register is used to characterize the signal to be output at the line output and define the output channel selector mode. 10.3.19.2 Definition Table 47 Subaddress 22 (note 1) BIT NAME DESCRIPTION 7 (MSB) − set to logic 0 6 LINGAIN line output gain on/off; see Table 49 5 see Table 48 4 3 − set to logic 0 2 − set to logic 0 1 − set to logic 0 0 (LSB) LINSEL select source for line output; see Table 49 Note 1. The default setting at power-up is 00000000. Table 48 Bits B5 and B4 B5 B4 L OUTPUT R OUTPUT 0 0 L input R input 0 1 L input L input 1 0 R input R input 1 1 R input L input Table 49 Description of bits LINSEL and LINGAIN NAME HIGH/LOW LINSEL HIGH Specifies that a signal from an analog source is being processed in the Main channel. Analog signal sources comprise SCART 1 input, SCART 2 input, external input and mono input, i.e. any input to the ADC. LOW Specifies that a signal from a digital source is being processed in the Main channel. Digital signal sources comprise FM, I2S1 input and I2S2 input. HIGH Activates the 3 dB gain stage at the line output buffers. LOW The audio signal will be output unchanged (0 dB gain). LINGAIN 1998 Aug 10 FUNCTION 46 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.20 ADC OUTPUT SELECT REGISTER 10.3.20.1 Description This register is used to define the signal source for the ADC. There is no output channel selector, because all digital signal sinks of the ADC have their own matrix. Instead, a level adjustment facility for the ADC output is provided. 10.3.20.2 Definition Table 50 Subaddress 23 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 see Table 51 B1 B0 see Table 52 Note 1. The default setting at power-up is 00000000. Table 51 Signal source 1998 Aug 10 B7 B6 B5 SIGNAL SOURCE 0 0 0 SCART 1 input 0 0 1 SCART 2 input 0 1 0 external input 0 1 1 mono input 47 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A Table 52 ADC level adjust (note 1) B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 +15 +14 +13 +12 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 +11 +10 +9 +8 +7 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 +6 +5 +4 +3 +2 +1 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 1 1 1 0 0 0 1 1 1 1 0 0 0 1 0 −10 −11 −12 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 −13 −14 −15 1 0 0 0 0 mute Note 1. If the ADC level adjust is set to 0 dB a full-scale input signal to the ADC results into a level of −6 dB full-scale at the digital x-bar. 1998 Aug 10 48 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.21 MAIN CHANNEL SELECT REGISTER 10.3.21.1 Description This register is used to define both the signal source to be processed in the Main (loudspeaker) channel and the mode of the digital matrix for signal selection. 10.3.21.2 Definition Table 53 Subaddress 24 (note 1) MSB LSB B7 B6 0 B5 B4 B3 see Table 55 B2 B1 0 B0 see Table 54 Note 1. The default setting at power-up is 00000000. Table 54 Signal source B2 B1 B0 SIGNAL SOURCE 0 0 0 FM input 0 0 1 don’t care 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC input B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 Table 55 Bits B6 to B4 1998 Aug 10 49 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.22 AUDIO EFFECTS REGISTER 10.3.22.1 Definition Table 56 Subaddress 25 (note 1; see Table 60) MSB LSB B7 B6 B5 0 0 SPATIAL1(2) B4 B3 B2 SPATIAL0(2) PSEUDO1(3) PSEUDO0(3) B1 B0 AVL1(4) AVL0(4) Notes 1. The default setting at power-up is 00000000. 2. See Table 59. 3. See Table 58. 4. See Table 57. Table 57 AVL control mode B1 B0 AVL MODE 0 0 off/reset 0 1 short decay 1 0 medium decay 1 1 long decay B3 B2 PSEUDO SETTING (Hz) 0 0 off 0 1 300 1 0 200 1 1 150 B5 B4 SPATIAL SETTING (%) 0 0 off 0 1 30 1 0 40 1 1 52 Table 58 Pseudo control setting Table 59 Spatial control setting 1998 Aug 10 50 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A Table 60 Description of Table 56 (notes 1, 2 and 3) NAME FUNCTION AVL0, AVL1 these bits set the mode of operation of the automatic volume level control function at the entrance to the Main (loudspeaker) channel PSEUDO0, PSEUDO1 These bits set the amount of the effect function (pseudo stereo) for mono signals in the Main channel. This function should be activated only in accordance with the result of the sound mode identification. SPATIAL0, SPATIAL1 These bits set the amount of the effect function (stereo base width expansion) for stereo signals in the Main channel. This function should be activated only in accordance with the result of the sound mode identification. Notes 1. Switching the AVL off will reset the associated hardware to a defined state. 2. When the signal source for the Main channel is changed while the AVL is on, the AVL needs to be reset in order to avoid excessive settling times. This can be achieved by switching the AVL off and on again. 3. The pseudo stereo function is based on an all-pass filter. A 90 degrees phase shift occurs at the frequencies stated in Table 58. There is a gain of 3 dB in the left audio channel. 10.3.23 VOLUME CONTROL REGISTERS (MAIN) 10.3.23.1 Description These two registers control the volume setting of the Main (loudspeaker) channel. The register at subaddress 26 applies to the left channel signal, while the register at subaddress 27 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings. 10.3.23.2 Definition Table 61 Subaddresses 26 and 27 MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 1 1 0 0 0 +24 0 0 0 1 0 1 1 1 +23 0 0 0 1 0 1 1 0 +22 0 0 0 1 0 1 0 1 +21 0 0 0 1 0 1 0 0 +20 0 0 0 1 0 0 1 1 +19 0 0 0 1 0 0 1 0 +18 0 0 0 1 0 0 0 1 +17 0 0 0 1 0 0 0 0 +16 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 1998 Aug 10 51 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 −1 1 1 1 1 1 1 1 0 −2 1 1 1 1 1 1 0 1 −3 1 1 1 1 1 1 0 0 −4 1 1 1 1 1 0 1 1 −5 1 1 1 1 1 0 1 0 −6 1 1 1 1 1 0 0 1 −7 1 1 1 1 1 0 0 0 −8 1 1 1 1 0 1 1 1 −9 1 1 1 1 0 1 1 0 −10 1 1 1 1 0 1 0 1 −11 1 1 1 1 0 1 0 0 −12 1 1 1 1 0 0 1 1 −13 1 1 1 1 0 0 1 0 −14 1 1 1 1 0 0 0 1 −15 1 1 1 1 0 0 0 0 −16 1 1 1 0 1 1 1 1 −17 1 1 1 0 1 1 1 0 −18 1 1 1 0 1 1 0 1 −19 1 1 1 0 1 1 0 0 −20 1 1 1 0 1 0 1 1 −21 1 1 1 0 1 0 1 0 −22 1 1 1 0 1 0 0 1 −23 1 1 1 0 1 0 0 0 −24 1 1 1 0 0 1 1 1 −25 1 1 1 0 0 1 1 0 −26 1 1 1 0 0 1 0 1 −27 1 1 1 0 0 1 0 0 −28 1 1 1 0 0 0 1 1 −29 1 1 1 0 0 0 1 0 −30 1998 Aug 10 52 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 1 1 1 0 0 0 0 1 −31 1 1 1 0 0 0 0 0 −32 1 1 0 1 1 1 1 1 −33 1 1 0 1 1 1 1 0 −34 1 1 0 1 1 1 0 1 −35 1 1 0 1 1 1 0 0 −36 1 1 0 1 1 0 1 1 −37 1 1 0 1 1 0 1 0 −38 1 1 0 1 1 0 0 1 −39 1 1 0 1 1 0 0 0 −40 1 1 0 1 0 1 1 1 −41 1 1 0 1 0 1 1 0 −42 1 1 0 1 0 1 0 1 −43 1 1 0 1 0 1 0 0 −44 1 1 0 1 0 0 1 1 −45 1 1 0 1 0 0 1 0 −46 1 1 0 1 0 0 0 1 −47 1 1 0 1 0 0 0 0 −48 1 1 0 0 1 1 1 1 −49 1 1 0 0 1 1 1 0 −50 1 1 0 0 1 1 0 1 −51 1 1 0 0 1 1 0 0 −52 1 1 0 0 1 0 1 1 −53 1 1 0 0 1 0 1 0 −54 1 1 0 0 1 0 0 1 −55 1 1 0 0 1 0 0 0 −56 1 1 0 0 0 1 1 1 −57 1 1 0 0 0 1 1 0 −58 1 1 0 0 0 1 0 1 −59 1 1 0 0 0 1 0 0 −60 1 1 0 0 0 0 1 1 −61 1 1 0 0 0 0 1 0 −62 1 1 0 0 0 0 0 1 −63 1 1 0 0 0 0 0 0 −64 1 0 1 1 1 1 1 1 −65 1 0 1 1 1 1 1 0 −66 1 0 1 1 1 1 0 1 −67 1 0 1 1 1 1 0 0 −68 1 0 1 1 1 0 1 1 −69 1998 Aug 10 53 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 1 0 1 1 1 0 1 0 −70 1 0 1 1 1 0 0 1 −71 1 0 1 1 1 0 0 0 −72 1 0 1 1 0 1 1 1 −73 1 0 1 1 0 1 1 0 −74 1 0 1 1 0 1 0 1 −75 1 0 1 1 0 1 0 0 −76 1 0 1 1 0 0 1 1 −77 1 0 1 1 0 0 1 0 −78 1 0 1 1 0 0 0 1 −79 1 0 1 1 0 0 0 0 −80 1 0 1 0 1 1 1 1 −81 1 0 1 0 1 1 1 0 −82 1 0 1 0 1 1 0 1 −83 1 0 1 0 1 1 0 0 mute (note 1) Note 1. The default setting at power-up is 10101100. 1998 Aug 10 54 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.24 CONTOUR CONTROL REGISTER 10.3.24.1 Description This register is used to apply the contour or loudness function (physiological volume control) to the left and right signal channels of the Main channel by means of an extra bass boost. The gain setting must be chosen in accordance with the volume control setting for the Main channel. For example, the contour gain could be incremented for every 5 dB, or so, of decrease of the volume setting. This needs to be done by the microcontroller. The 0 dB contour setting is equal to contour off. 10.3.24.2 Definition Table 62 Subaddress 28 MSB LSB CONTOUR GAIN (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 1 0 0 1 0 18 0 0 0 1 0 0 0 1 17 0 0 0 1 0 0 0 0 16 0 0 0 0 1 1 1 1 15 0 0 0 0 1 1 1 0 14 0 0 0 0 1 1 0 1 13 0 0 0 0 1 1 0 0 12 0 0 0 0 1 0 1 1 11 0 0 0 0 1 0 1 0 10 0 0 0 0 1 0 0 1 9 0 0 0 0 1 0 0 0 8 0 0 0 0 0 1 1 1 7 0 0 0 0 0 1 1 0 6 0 0 0 0 0 1 0 1 5 0 0 0 0 0 1 0 0 4 0 0 0 0 0 0 1 1 3 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 (note 1) Note 1. The default setting at power-up is 00000000. 1998 Aug 10 55 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.25 BASS CONTROL REGISTER (MAIN) 10.3.25.1 Description This register is used to apply bass control to the left and right signal channels of the Main channel. 10.3.25.2 Definition Table 63 Subaddress 29 MSB LSB BASS SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 (note 1) 0 0 0 1 1 1 1 1 −1 0 0 0 1 1 1 1 0 −2 0 0 0 1 1 1 0 1 −3 0 0 0 1 1 1 0 0 −4 0 0 0 1 1 0 1 1 −5 0 0 0 1 1 0 1 0 −6 0 0 0 1 1 0 0 1 −7 0 0 0 1 1 0 0 0 −8 0 0 0 1 0 1 1 1 −9 0 0 0 1 0 1 1 0 −10 0 0 0 1 0 1 0 1 −11 0 0 0 1 0 1 0 0 −12 Note 1. The default setting at power-up is 00000000. 1998 Aug 10 56 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.26 TREBLE CONTROL REGISTER (MAIN) 10.3.26.1 Description This register is used to apply treble control to the left and right signal channels of the Main channel. 10.3.26.2 Definition Table 64 Subaddress 30 MSB LSB TREBLE SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 (note 1) 0 0 0 1 1 1 1 1 −1 0 0 0 1 1 1 1 0 −2 0 0 0 1 1 1 0 1 −3 0 0 0 1 1 1 0 0 −4 0 0 0 1 1 0 1 1 −5 0 0 0 1 1 0 1 0 −6 0 0 0 1 1 0 0 1 −7 0 0 0 1 1 0 0 0 −8 0 0 0 1 0 1 1 1 −9 0 0 0 1 0 1 1 0 −10 0 0 0 1 0 1 0 1 −11 0 0 0 1 0 1 0 0 −12 Note 1. The default setting at power-up is 00000000. 1998 Aug 10 57 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.27 AUXILIARY CHANNEL SELECT REGISTER 10.3.27.1 Description This register is used to define both the signal source to be processed in the Auxiliary (headphone) channel and the mode of the digital matrix for signal selection. 10.3.27.2 Definition Table 65 Subaddress 31 (note 1) MSB LSB B7 B6 0 B5 B4 B3 see Table 67 B2 B1 0 B0 see Table 66 Note 1. The default setting at power-up is 00000000. Table 66 Signal source B2 B1 B0 SIGNAL SOURCE 0 0 0 FM input 0 0 1 don’t care 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC input 1 0 1 AVL input B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 Table 67 Bits B6 to B4 1998 Aug 10 58 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.28 VOLUME CONTROL REGISTERS (AUXILIARY) 10.3.28.1 Description These two registers control the volume setting of the Auxiliary (headphone) channel. The register at subaddress 32 applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings. 10.3.28.2 Definition Table 68 Subaddresses 32 and 33 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 VOLUME SETTING (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 0 1 0 +8 +7 +6 +5 +4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 +3 +2 +1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 −1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 −2 −3 −4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 0 1 −5 −6 −7 1998 Aug 10 59 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 VOLUME SETTING (dB) 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 −8 −9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 −10 −11 −12 −13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 −14 −15 −16 −17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 −18 −19 −20 −21 −22 −23 −24 −25 −26 −27 −28 −29 −30 −31 −32 −33 −34 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 −35 −36 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 1 0 1 −37 −38 −39 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 1 0 −40 −41 −42 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 0 −43 −44 −45 −46 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 −47 −48 1998 Aug 10 60 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 VOLUME SETTING (dB) 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 −49 −50 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 −51 −52 −53 −54 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 −55 −56 −57 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 −58 −59 −60 −61 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 −62 −63 −64 −65 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 −66 −67 −68 −69 −70 −71 −72 −73 −74 −75 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 −76 −77 −78 −79 −80 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 −81 −82 −83 1 0 1 0 1 1 0 0 mute (note 1) Note 1. The default setting at power-up is 10101100. 1998 Aug 10 61 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.29 BASS CONTROL REGISTER (AUXILIARY) 10.3.29.1 Description This register is used to apply bass control to the left and right signal channels of the Auxiliary channel. 10.3.29.2 Definition Table 69 Subaddress 34 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 BASS SETTING (dB) 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 (note 1) 0 0 0 1 1 1 1 1 −1 0 0 0 1 1 1 1 0 −2 0 0 0 1 1 1 0 1 −3 0 0 0 1 1 1 0 0 −4 0 0 0 1 1 0 1 1 −5 0 0 0 1 1 0 1 0 −6 0 0 0 1 1 0 0 1 −7 0 0 0 1 1 0 0 0 −8 0 0 0 1 0 1 1 1 −9 0 0 0 1 0 1 1 0 −10 0 0 0 1 0 1 0 1 −11 0 0 0 1 0 1 0 0 −12 Note 1. The default setting at power-up is 00000000. 1998 Aug 10 62 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.30 TREBLE CONTROL REGISTER (AUXILIARY) 10.3.30.1 Description This register is used to apply treble control to the left and right signal channels of the Auxiliary channel. 10.3.30.2 Definition Table 70 Subaddress 35 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 TREBLE SETTING (dB) X X X 0 1 1 0 0 +12 X X X 0 1 0 1 1 +11 X X X 0 1 0 1 0 +10 X X X 0 1 0 0 1 +9 X X X 0 1 0 0 0 +8 X X X 0 0 1 1 1 +7 X X X 0 0 1 1 0 +6 X X X 0 0 1 0 1 +5 X X X 0 0 1 0 0 +4 X X X 0 0 0 1 1 +3 X X X 0 0 0 1 0 +2 X X X 0 0 0 0 1 +1 X X X 0 0 0 0 0 0 (note 1) X X X 1 1 1 1 1 −1 X X X 1 1 1 1 0 −2 X X X 1 1 1 0 1 −3 X X X 1 1 1 0 0 −4 X X X 1 1 0 1 1 −5 X X X 1 1 0 1 0 −6 X X X 1 1 0 0 1 −7 X X X 1 1 0 0 0 −8 X X X 1 0 1 1 1 −9 X X X 1 0 1 1 0 −10 X X X 1 0 1 0 1 −11 X X X 1 0 1 0 0 −12 Note 1. The default setting at power-up is 00000000. 1998 Aug 10 63 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER 10.3.31.1 Definition Table 71 Subaddress 36 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 SYSCL1(2) SYSCL0(2) SYSOUT(3) I2SFORM(4) I2SOUT(5) Notes 1. The default setting at power-up is 00000000. 2. System clock frequency select; see Table 72. 3. System clock output on/off; see Table 73. 4. Serial output format; see Table 73. 5. I2S-bus outputs on/off; see Table 73. Table 72 System clock frequency select B4 B3 SYSCLK OUTPUT FREQUENCY (MHz) 0 0 256fs 8.192 0 1 384fs 12.288 1 0 512fs 16.384; note 1 1 1 768fs 24.576 Note 1. With 16.384 MHz, the duty cycle is 33% : 67%. Table 73 Description of Table 71 NAME HIGH/LOW FUNCTION I2SOUT HIGH Enables the output of serial audio data (2 pins) plus serial bit clock and word select in a format determined by the I2SFORM bit. The TDA9870A is then an I2S-bus master. LOW the outputs mentioned will be 3-stated, thereby improving the EMC performance I2SFORM HIGH an MSB-aligned, MSB-first output format is selected, i.e. a level change at the word select pin indicates the beginning of a new audio sample LOW the standard I2S-bus output format is selected HIGH enables the output of a system (or master) clock signal at pin SYSCLK LOW the output will be off, thereby improving the EMC performance SYSOUT 1998 Aug 10 64 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.32 I2S1 OUTPUT SELECT REGISTER 10.3.32.1 Description This register is used to define both the signal source to be output at I2S1 and the mode of the digital matrix for signal selection. 10.3.32.2 Definition Table 74 Subaddress 37 (note 1) MSB LSB B7 B6 0 B5 B4 B3 see Table 76 B2 B1 0 B0 see Table 75 Note 1. The default setting at power-up is 00000000. Table 75 Signal source (note 1) B2 B1 B0 SIGNAL SOURCE 0 0 0 FM output 0 0 1 don’t care 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC output 1 0 1 AVL output 1 1 0 Auxiliary output 1 1 1 Main output Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. Table 76 Bits B6 to B4 B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 1998 Aug 10 65 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.33 I2S1 INPUT LEVEL ADJUST REGISTER 10.3.33.1 Description This register is used to adjust the input level at the I2S1 interface. Left and right signal channel are treated identically. 10.3.33.2 Definition Table 77 Subaddress 38 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Note 1. The default setting at power-up is 00000000. 1998 Aug 10 66 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.34 I2S1 OUTPUT LEVEL ADJUST REGISTER 10.3.34.1 Description This register is used to adjust the output level at the I2S1 interface. Left and right signal channel are treated identically. 10.3.34.2 Definition Table 78 Subaddress 39 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Note 1. The default setting at power-up is 00000000. 1998 Aug 10 67 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.35 I2S2 OUTPUT SELECT REGISTER 10.3.35.1 Description This register is used to define both the signal source to be output at I2S2 and the mode of the digital matrix for signal selection. 10.3.35.2 Definition Table 79 Subaddress 40 (note 1) MSB LSB B7 B6 0 B5 B4 B3 see Table 81 B2 B1 0 B0 see Table 80 Note 1. The default setting at power-up is 00000000. Table 80 Signal source (note 1) B2 B1 B0 SIGNAL SOURCE 0 0 0 FM output 0 0 1 don’t care 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC output 1 0 1 AVL output 1 1 0 Auxiliary output 1 1 1 Main output Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. Table 81 Bits B6 to B4 B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 1998 Aug 10 68 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.36 I2S2 INPUT LEVEL ADJUST REGISTER 10.3.36.1 Description This register is used to adjust the input level at the I2S2 interface. Left and right signal channel are treated identically. 10.3.36.2 Definition Table 82 Subaddress 41 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Note 1. The default setting at power-up is 00000000. 1998 Aug 10 69 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.37 I2S2 OUTPUT LEVEL ADJUST REGISTER 10.3.37.1 Description This register is used to adjust the output level at the I2S2 interface. Left and right signal channel are treated identically. 10.3.37.2 Definition Table 83 Subaddress 42 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Note 1. The default setting at power-up is 00000000. 1998 Aug 10 70 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.38 BEEPER FREQUENCY CONTROL REGISTER 10.3.38.1 Description This register is used to select from sample beeper oscillator frequencies. The beeper output signal is added to the Main and Auxiliary channel output DAC. Due to the frequency response of the audio DACs upsampling filters, the 25 kHz beep is approximately 5 dB louder than the 390 Hz beep. 10.3.38.2 Definition Table 84 Subaddress 43 (note 1) MSB LSB GENERATED FREQUENCY (Hz) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 1 1 1 25000 0 0 0 0 0 1 1 0 7040 0 0 0 0 0 1 0 1 3580 0 0 0 0 0 1 0 0 1770 0 0 0 0 0 0 1 1 1270 0 0 0 0 0 0 1 0 900 0 0 0 0 0 0 0 1 640 0 0 0 0 0 0 0 0 390 Note 1. The default setting at power-up is 00000000. 10.3.39 BEEPER VOLUME CONTROL REGISTER 10.3.39.1 Description This register is used to set the beeper volume. The gain setting is relative to digital full scale at the input to the Main and Auxiliary channel output DACs. The beeper volume is independent of any other volume setting. The beeper signal is added to the Main and Auxiliary channel output signals in the 2 × fs domain. The beeper volume should be set with great care, when the audio signals in the Main and Auxiliary channels are close to digital full-scale, to avoid output signal distortion due to overload. 1998 Aug 10 71 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.39.2 Definition Table 85 Subaddress 44 MSB LSB GAIN SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 −3 0 0 1 1 1 1 1 0 −6 0 0 1 1 1 1 0 1 −9 0 0 1 1 1 1 0 0 −12 0 0 1 1 1 0 1 1 −15 0 0 1 1 1 0 1 0 −18 0 0 1 1 1 0 0 1 −21 0 0 1 1 1 0 0 0 −24 0 0 1 1 0 1 1 1 −27 0 0 1 1 0 1 1 0 −30 0 0 1 1 0 1 0 1 −33 0 0 1 1 0 1 0 0 −36 0 0 1 1 0 0 1 1 −39 0 0 1 1 0 0 1 0 −42 0 0 1 1 0 0 0 1 −45 0 0 1 1 0 0 0 0 −48 0 0 1 0 1 1 1 1 −51 0 0 1 0 1 1 1 0 −54 0 0 1 0 1 1 0 1 −57 0 0 1 0 1 1 0 0 −60 0 0 1 0 1 0 1 1 −63 0 0 1 0 1 0 1 0 −66 0 0 1 0 1 0 0 1 −69 0 0 1 0 1 0 0 0 −72 0 0 1 0 0 1 1 1 −75 0 0 1 0 0 1 1 0 −78 0 0 1 0 0 1 0 1 −81 0 0 1 0 0 1 0 0 −84 0 0 1 0 0 0 1 1 −87 0 0 1 0 0 0 1 0 −90 0 0 1 0 0 0 0 1 −93 0 0 1 0 0 0 0 0 mute (note 1) Note 1. The default setting at power-up is 00100000. 1998 Aug 10 72 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 10.3.40 BASS BOOST CONTROL REGISTER 10.3.40.1 Description This register is used to select from a few sample bass boost settings to modify the frequency characteristics of the Main channel (shelving filter). Bits B3 to B0 apply to the left channel, bits B7 to B4 apply to the right channel. This function must be used with care in order to avoid clipping distortion at high volume settings. More sophisticated control of the bass boost filter can be exercised in the expert mode (see Section 10.5). The user then has full control over this 2nd-order filter and can, within limits, realize bass equalizers with arbitrary centre frequencies, Q factors and boost/cut settings. 10.3.40.2 Definition Table 86 Subaddress 45 (note 1; see Table 87) MSB B7 LSB B6 B5 B4 B3 B2 B1 B0 Note 1. The default setting at power-up is 00000000. Table 87 Gain setting B7 AND B3 B6 AND B2 B5 AND B1 B4 AND B0 GAIN SETTING (dB) CORNER FREQUENCY (Hz) 1 0 1 0 20 350 1 0 0 1 18 350 1 0 0 0 16 350 0 1 1 1 14 350 0 1 1 0 12 350 0 1 0 1 10 350 0 1 0 0 8 350 0 0 1 1 6 350 0 0 1 0 4 350 0 0 0 1 2 350 0 0 0 0 0 350 1998 Aug 10 73 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.4 TDA9870A Slave transmitter mode As a slave transmitter, the TDA9870A provides 13 registers with status information and data, a part of which is for Philips internal purposes only. These registers can be accessed by means of subaddresses. Table 88 General format for reading data from the TDA9870A S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA NAm P Table 89 Explanation of Tables 88 and 90 BIT FUNCTION S START condition SLAVE ADDRESS 7-bit device address 0 data direction bit (write to device) ACK acknowledge (by the slave) SUBADDRESS address of register to read from Sr repeated START condition 1 data direction bit (read from device) DATA data byte read from register NAm not acknowledge (by the master) Am acknowledge (by the master) P STOP condition Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the TDA9870A. In this situation, the subaddress is automatically incremented after each data byte, which results in reading the sequence of data bytes from successive register locations, starting at SUBADDRESS. Table 90 Format of a transmission using automatic incrementing of subaddresses S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA BYTE Am(1) DATA NAm P Note 1. n data bytes with auto-increment of subaddresses. Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master). The subaddresses ‘wrap around’ from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF in hexadecimal notation. 1998 Aug 10 74 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A Table 91 Overview of the slave transmitter registers (note 1) DATA SUBADDRESS (DECIMAL) MSB FUNCTION LSB 0 s s X X X s s s device status (power-on, identification, etc.) 1 X X X X X X X X don’t care; note 1 2 X X X X X X X X don’t care; note 1 3 X X X X X X X X don’t care; note 1 4 X X X X X X X X don’t care; note 1 5 l l l l l l l l level read-out (MSB) 6 l l l l l l l l level read-out (LSB) 7 X X X c c c c c SIF level 251 a a a a a a a a test register 3; note 2 252 a a a a a a a a test register 2; note 2 253 a a a a a a a a test register 1; note 2 254 d d d d d d d d device identification code 255 s s s s s s s s software identification code Notes 1. X indicates a bit that has not been assigned to a function. This bit is reserved for future extensions. 2. Registers from subaddress 251 to 255 are for Philips internal purposes only. They are considered as a set of registers for the identification of individual members and some key parameters in a family of devices. A detailed description of the slave transmitter registers is given in below. 10.4.1 DEVICE STATUS REGISTER 10.4.1.1 Description Table 92 Description of Table 93 NAME HIGH/LOW POR − The power supply for the digital part of the device, VDDD2, has temporarily been lower than the specified lower limit. If this is detected an initialization of the TDA9870A has to be carried out to ensure reliable operation. IDSTE − this bit is HIGH if an FM stereo signal has been identified IDDUA − This bit is HIGH if an FM dual-language signal has been identified. When neither IDSTE nor IDDUA are set, the received signal has to be assumed to be FM mono. P1IN, P2IN − these bits reflect the status of the corresponding general purpose port pins, see Section 10.3.2 1998 Aug 10 FUNCTION 75 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.4.1.2 TDA9870A Definition Table 93 Subaddress 0 10.4.2 10.4.2.1 BIT NAME DESCRIPTION 7 (MSB) P2IN input from port 2 6 P1IN input from port 1 5 − don’t care 4 − don’t care 3 − don’t care 2 IDDUA identification of FM dual sound 1 IDSTE identification of FM stereo 0 (LSB) POR power fail bit 10.4.6.2 REGISTER 1 Description Table 94 Subaddress 5 Subaddress 1: These bits have not been assigned to a function. These bits are reserved for future extensions. 10.4.3 10.4.3.1 Definition BIT 7 (most significant bit or sign bit) 6 REGISTER 2 5 Description 4 Subaddress 2: These bits have not been assigned to a function. These bits are reserved for future extensions. 3 10.4.4 1 10.4.4.1 2 REGISTER 3 0 Description Subaddress 3: These bits have not been assigned to a function. These bits are reserved for future extensions. Table 95 Subaddress 6 BIT 10.4.5 10.4.5.1 REGISTER 4 7 6 Description 5 Subaddress 4: These bits have not been assigned to a function. These bits are reserved for future extensions. 4 3 10.4.6 10.4.6.1 LEVEL READ-OUT REGISTERS 2 1 Description 0 (least significant bit) These two bytes constitute a word that provides data from a location that has been specified with the monitor select register. The most significant byte of the data is stored at subaddress 5. 10.4.7 10.4.7.1 If peak-level monitoring has been selected, the peak-level monitoring register is cleared and monitoring resumes after its contents has been transferred to these two bytes. 1998 Aug 10 SIF LEVEL REGISTER Description When the SIF AGC is on, bits B4 to B0 of this register contain a number that gives an indication of the SIF input level. That number corresponds to the AGC gain register setting (see Section 10.3, subaddress 0). 76 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A When the SIF AGC is off, this register returns the contents of the AGC gain register. 10.4.11 DEVICE IDENTIFICATION CODE 10.4.7.2 There will be several devices in the digital TV sound processor family. This byte is used to identify the individual family members. 10.4.11.1 Description Definition Table 96 Subaddress 7 MSB B7 LSB B6 B5 B4 B3 B2 B1 10.4.11.2 Definition B0 Table 100 Subaddress 254 10.4.8 10.4.8.1 TEST REGISTER 3 MSB Description LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 0 0 0 1 0 This register contains, as a binary number, the highest memory address used for the Coefficient RAM (CRAM, expert mode). 10.4.12 SOFTWARE IDENTIFICATION CODE 10.4.8.2 10.4.12.1 Description Definition It is likely that during the life time of this family of devices several versions of the DSP software will be made, e.g., to accommodate new application concepts, respond to customer wishes, etc. This byte is used to identify the different releases. Table 97 Subaddress 251 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 1 1 1 1 1 1 1 10.4.9 10.4.9.1 10.4.12.2 Definition TEST REGISTER 2 Table 101 Subaddress 255 Description MSB This register contains, as a binary number, the highest subaddress used for slave receiver registers. 10.4.9.2 LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 1 0 Definition 10.5 Table 98 Subaddress 252 MSB In addition to the slave receiver and slave transmitter modes previously described, there is a special ‘expert’ mode that gives direct write access to the internal CRAM of the DSP. LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 0 1 1 0 1 In this mode, transferred data contain 12-bit-wide coefficients. As those coefficients bypass on-chip coefficient look-up tables for many functions, they directly influence the processing of signals within the DSP. 10.4.10 TEST REGISTER 1 10.4.10.1 Description This register contains, as a binary number, the highest subaddress used for slave transmitter (status) registers. This mode must be used with great care. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses. 10.4.10.2 Definition Table 99 Subaddress 253 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 1 1 1 1998 Aug 10 Expert mode 77 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A Table 102 General format for entering the expert mode and writing coefficients into the TDA9870A S SLAVE ADDRESS 0 ACK 10000000 ACK CRAM ADDRESS ACK DATA ACK DATA ACK P Table 103 Explanation of Table 102 BIT FUNCTION S START condition SLAVE ADDRESS 7-bit device address 0 data direction bit (write to device) ACK acknowledge 10000000 pattern to enter the expert mode CRAM ADDRESS start address of coefficient RAM to write to DATA data byte containing part of a coefficient P STOP condition As the coefficients do not fit into one data byte, they have to be split and arranged (see Table 104). The most significant bit is transferred first. Table 104 General format (notes 1, 2 and 3) BYTE DATA DESCRIPTION 1. data byte a a a a a a a a 2 MST of 1st coefficient 2. data byte a a a a X X X X 1 LST of 1st coefficient Notes 1. X = don’t care. 2. MST = most significant third. 3. LST = least significant third. The general format described in Table 104 shows the minimum number of data bytes required, i.e. two bytes for the transfer of a single coefficient. Should more than one coefficient be sent, then the CRAM address will be automatically incremented after each coefficient, resulting in writing the sequence of coefficients into successive memory locations, starting at CRAM ADDRESS. A transmission can start with any valid CRAM address. If two coefficients are to be transferred, they are arranged as shown in Table 105. Table 105 Transfer of two coefficients BYTE DATA DESCRIPTION 1 data byte a a a a a a a a 2 MST of 1st coefficient 2 data byte a a a a b b b b 1 LST of 1st coefficient + 1 MST of 2nd coefficient 3 data byte b b b b b b b b 2 LST of 2nd coefficient With any odd number of coefficients to be transferred, the least significant nibble of the last byte is regarded as containing don’t care data. 1998 Aug 10 78 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) is LOW. Data is written at the trailing edge of SCK and read at the leading edge of SCK. The most significant bit is sent first. As the transfer of coefficients cannot be accomplished within one audio sample period, it is necessary that received coefficients be buffered and made active all at the same time to avoid audio signal transients. The receive buffer is designed to store up to 8 coefficients in addition to the CRAM address. Each byte that fits into the buffer is acknowledged with ACK (acknowledge). If an attempt is made to write more coefficients than the buffer can store, the device acknowledges with NACK (not acknowledge) and any further coefficients are ignored. Coefficients that are already in the receive buffer remain intact. At power-up, the outputs of the feature interface are 3-stated to reduce EMC and allow for combinations with other ICs. If output is desired, it has to be activated by means of an I2C-bus command. When the output is enabled, the serial audio data can be taken from pins SDO1 and SDO2. Depending on the signal source, switch and matrix positions, the output can be either mono, stereo or dual language sound on either output. An expert mode transfer ends when the I2C-bus STOP condition or a repeated START condition has been detected. Only those coefficients that have been received during the last transmission will then be copied from the buffer to the CRAM. The word select output is clocked with the audio sample frequency at 32 kHz. The serial clock output (SCK) is clocked at a frequency of 2.048 MHz. This means, that there are 64 clock pulses per pair of stereo output samples, or 32 clock pulses per sample. Depending again on the signal source, the number of significant bits on the serial data outputs, SDO1 and SDO2, is between 14 and 18. To make efficient and correct use of the expert mode, it is recommended to transfer all coefficients for any one function in a single transmission. There is no checking of memory addresses and the automatic incrementing of addresses does not stop at the highest used CRAM address. The user of this expert mode must be fully acquainted with the relevant procedures. Apart from just feeding a digital audio device, such as a DAC or an AES/EBU transmitter, the serial data outputs can be connected directly to the serial inputs (loop-back connection) or first to an external device, e.g. a feature DSP such as the SAA7710 and then back to the serial inputs. In all of these configurations, the SCK and WS clocks will be generated by the TDA9870A, which then is the I2S-bus master. More information concerning the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be supplied on request at a later date. The serial data inputs, SDI1 and SDI2, are active at all times, independent of the serial data outputs being on or off. When the serial data outputs are off (either after power-up or via the appropriate I2C-bus command) serial data and clocks WS and SCK from a separate digital audio source can be fed into the TDA9870A, be processed and output in accordance with internal selector positions, provided that the following criteria are met: 11 I2S-BUS DESCRIPTION The feature interface of the TDA9870A contains two serial audio inputs and outputs and associated clock signals. It can be used to supply, for example, audio signals from received TV programs to a digital audio output device (AES/EBU format), or import serial audio signals from other sources for reproduction through the TV set’s loudspeaker and/or headphone channels. Apart from such simple data input or output, it is also possible to run audio signals through an external DSP, which performs some additional functions, such as room simulation, Dolby Surround Pro Logic etc. and feed those signals back into the loudspeaker and/or headphone channels of the TDA9870A. • 32 kHz audio sample frequency • 32 clock bits per sample • External timing and data synchronized to TDA9870A. In such cases, the external source is the I2S-bus master and the TDA9870A is the I2S-bus slave. To support synchronization of external devices or as a master clock for them, a system clock output, SYSCLK, is available from the TDA9870A. At power-up it is off. It can be enabled and the output frequency set via an I2C-bus command. Available output frequencies are 8.192, 12.288, 16.384 and 24.576 MHz. Two serial audio formats are supported at the feature interface, i.e. the I2S-bus format and a very similar MSB-aligned format. The difference is illustrated in Fig.7. In both formats the left audio channel of a stereo sample pair is output first and is placed on the serial data line (SDI for input, SDO for output) when the word select line (WS) 1998 Aug 10 TDA9870A 79 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A handbook, full pagewidth SCK WS SD LSB MSB LSB MSB MGK112 one sample a. I2S-bus format. handbook, full pagewidth SCK WS SD LSB MSB LSB MSB MGK113 one sample b. MSB-aligned format. Fig.7 Serial audio interface formats. 1998 Aug 10 80 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 12 EXTERNAL COMPONENTS handbook, full pagewidth i.c. 1 64 VDDD2 R19 i.c. ADDR1 SCL SDA VSSA1 VDEC1 C1 4.7 µF Iref R1 2 63 3 62 4 61 5 60 6 59 7 58 8 57 10 kΩ P1 C2 SIF2 SIFSAT 47 pF C3 Vref1 9 56 10 55 11 54 100 nF C4 SIF1 SIFTV 12 53 47 pF ADDR2 VSSD1 +5 V R2 VDDD1 1.5 Ω C5 47 µF C6 1 µF CRESET VSSD4 14 51 15 50 16 49 TDA9870A 48 18 47 XTALO 19 46 P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 MONOIN 29 36 470 nF TEST2 30 35 C8 EXTIR 31 34 C9 EXTIL 33 2.2 µF C32 MOL C31 10 nF C29 10 nF 2.2 µF C28 47 µF C26 10 nF 2.2 µF C24 10 nF MOR VDDA AUXOL AUXOR C27 C25 2.2 µF 10 nF C22 C21 10 nF PCAPR Vref3 47 µF SCOL2 C20 C19 SCOR2 2.2 µF 2.2 µF VSSA4 VSSD2 C18 SCOL1 C17 SCOR1 2.2 µF 2.2 µF C16 Vref2 47 µF i.c. i.c. VSSA2 i.c. i.c. Vref(n) C15 47 µF R7 270 Ω VDEC2 SCIR2 VSSD3 R5 330 nF C12 15 kΩ R4 SCIL1 SCIR1 R3 C14 4.7 µF C13 R6 SCIL2 Fig.8 Schematic for measurements. 81 R8 2.2 Ω C23 PCAPL MHB115 1998 Aug 10 C30 2.2 µF VSSA3 330 nF C11 15 kΩ 330 nF C10 15 kΩ 470 nF 2.2 µF C33 LOL Vref(p) 32 C34 LOR 15 kΩ C7 470 nF 52 17 XTALI 24.576 MHz 13 +5 V 47 µF 1.5 Ω C35 330 nF +5 V Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 13 APPLICATION CIRCUITRY +5 V handbook, full pagewidth POWER i.c. 47 µF C1 i.c. ADDR1 L1 100 Ω R2 SCL L2 SDA 100 Ω VSSA1 VDEC1 C2 470 nF Iref R3 R4 2.2 kΩ P1 SIF2 SIFSAT 47 pF C4 C5 100 nF L4 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 10 kΩ L3 C3 64 Vref1 SIF1 SIFTV 11 54 12 53 13 52 47 pF ADDR2 VSSD1 +5 V L5 R5 1Ω C6 470 nF VDDD1 C7 1 µF CRESET VSSD4 XTALI 24.576 MHz R6 51 15 50 16 49 TDA9870A 17 48 47 XTALO 19 46 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 C38 470 pF 2.2 µF C37 C36 10 nF C34 10 nF 2.2 µF R12 C32 470 nF C31 10 nF 2.2 µF C29 C30 10 nF MOL TEST2 36 29 30 35 VDDA 31 34 L8 EXTIL 33 32 AUXOR 2.2 Ω C28 PCAPL 10 nF C27 C26 10 nF PCAPR Vref3 47 µF SCOL2 C25 C24 470 pF C22 470 pF 2.2 µF C20 470 pF C18 470 pF 2.2 µF C17 SCOR2 VSSA4 2.2 µF 2.2 µF VSSA3 C23 2.2 µF VSSD2 C21 SCOL1 SCOR1 Vref2 C19 2.2 µF 47 µF i.c. i.c. VSSA2 i.c. i.c. Vref(n) C16 47 µF R11 270 Ω VDEC2 SCIR2 VSSD3 R8 Fig.9 Schematic for application. 330 nF C12 15 kΩ 330 nF C11 15 kΩ note: L’s are ferrite beads. R9 330 nF C13 15 kΩ SCIL1 SCIR1 R7 C15 470 nF C14 SCIL2 R10 MHB116 82 C33 AUXOL L7 EXTIR C35 MOR 470 nF 1998 Aug 10 470 pF C39 +5 V 2.2 µF C40 LOL 15 kΩ MONOIN 470 nF C10 R13 470 1 Ω C41 nF LOR Vref(p) L6 470 nF C9 14 18 P2 2.2 kΩ C8 L9 VDDD2 C42 0V R1 1 330 nF +5 V Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9870A 14 PACKAGE OUTLINE seating plane SDIP64: plastic shrink dual in-line package; 64 leads (750 mil) SOT274-1 ME D A2 A L A1 c e Z b1 (e 1) w M MH b 33 64 pin 1 index E 1 32 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.84 0.51 4.57 1.3 0.8 0.53 0.40 0.32 0.23 58.67 57.70 17.2 16.9 1.778 19.05 3.2 2.8 19.61 19.05 20.96 19.71 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-10-13 95-02-04 SOT274-1 1998 Aug 10 EUROPEAN PROJECTION 83 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) time of successive solder waves must not exceed 5 seconds. 15 SOLDERING 15.1 Introduction The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. 15.3 This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 15.2 TDA9870A Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact 16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Aug 10 84 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) NOTES 1998 Aug 10 85 TDA9870A Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) NOTES 1998 Aug 10 86 TDA9870A Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) NOTES 1998 Aug 10 87 TDA9870A Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/1200/01/pp88 Date of release: 1998 Aug 10 Document order number: 9397 750 03839