AD ADSP-BF549BBCZ-ENG

Blackfin®
Embedded Processor
ADSP-BF542/BF544/BF548/BF549
•
a
Preliminary Technical Data
FEATURES
PERIPHERALS
Up to 600 MHz High-Performance Blackfin Processor
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs
RISC-Like Register and Instruction Model
0.9 V to TBD V Core VDD with On-chip Voltage Regulation
2.5 V and 3.3 V-Tolerant I/O with Specific 5V-Tolerant Pins
400-ball Lead-Free mBGA Package
High-Speed USB On-the-Go (OTG) with Integrated PHY
SD/SDIO Controller
ATA/ATAPI-6 Controller
Up to Four Synchronous Serial Ports (SPORTs)
Up to Three Serial Peripheral Interfaces (SPI-Compatible)
Up to Four UARTs, Two with Automatic Hardware Flow
Control
Up to Two CAN (Controller Area Network) 2.0B Interfaces
Up to Two TWI (Two-Wire Interface) Controllers
8- or 16-Bit Asynchronous Host DMA Interface
Multiple Enhanced Parallel Peripheral Interfaces (EPPIs), Supporting ITU-R BT.656 Video Formats and 18/24-bit LCD
Connections
Media Transceiver (MXVR) for connection to a MOST®
Network
Pixel Compositor for overlays, alpha blending, and color
conversion
Up to Eleven 32-Bit Timers/Counters with PWM Support
Real-Time Clock (RTC) and Watchdog Timer
Up/Down Counter With Support for Rotary Encoder
Up to 152 General Purpose I/O (GPIOs)
On-Chip PLL Capable of 1x to 63x Frequency Multiplication
Debug/JTAG Interface
MEMORY
Up to 324K bytes of on-chip memory comprised of:
Instruction SRAM/cache; instruction SRAM;
data SRAM/cache; additional dedicated data SRAM;
scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations
External Sync Memory Controller Supporting
DDR/Mobile DDR SDRAM
External Async Memory Controller Supporting 8/16 bit Async
Memories and Burst Flash Devices
NAND Flash Controller
Four Memory-to-Memory DMA pairs, two with external
requests
Memory Management Unit Providing Memory Protection
Flexible Booting Options
Code Security with LockboxTM Secure Technology
One-Time-Programmable (OTP) Memory
VOLTAGE
REGULATOR
CAN (0-1)
JTAG TEST AND
EMULATION
RTC
WATCHDOG
TIMER
OTP
TWI (0-1)
HOST DMA
PAB 16
B
PORTS
TIMERS(0-10)
INTERRUPTS
UART (0-1)
COUNTER
UART (2-3)
L2
SRAM
KEYPAD
L1
INSTR ROM
L1
INSTR SRAM
L1
DATA SRAM
SPI (2)
32-BIT DMA
MXVR
DCB 32
EAB 64
DAB1
DEB 32
PORTS
SPI (0-1)
32
SPORT (2-3)
USB
16-BIT DMA
DAB0
BOOT
ROM
EXTERNAL PORT
NOR, DDR1 CONTROL
16
SPORT (0-1)
SD / SDIO
ATAPI
DDR1
ASYNC
16
16
EPPI (0-2)
NAND FLASH
CONTRLOLLER
PIXEL
COMPOSITOR
• Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrE
Figure 1. Functional Block Diagram
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/461-3113
© 2007 Analog Devices, Inc. All rights reserved.
ADSP-BF542/4/8/9
Preliminary Technical Data
TABLE OF CONTENTS
Features ................................................................. 1
Keypad Interface ................................................. 15
Memory ................................................................ 1
Secure Digital (SD)/SDIO Controller ....................... 15
Peripherals ............................................................. 1
Code Security ..................................................... 15
Table Of Contents .................................................... 2
Media Transceiver Mac Layer (MXVR) .................... 15
Revision History ...................................................... 2
Voltage Regulation .............................................. 17
General Description ................................................. 3
Clock Signals ...................................................... 17
Low-Power Architecture ......................................... 4
Booting Modes ................................................... 19
System Integration ................................................ 4
Instruction Set Description .................................... 20
ADSP-BF542/4/8/9 Processor Peripherals ................... 4
Development Tools .............................................. 21
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 5
Designing an Emulator-Compatible Processor
Board (Target) ................................................. 21
DMA Controllers ................................................ 10
Related Documents .............................................. 21
Real-Time Clock ................................................. 11
Pin Descriptions .................................................... 22
Watchdog Timer ................................................ 11
Specifications ........................................................ 31
Timers ............................................................. 12
Operating Conditions ........................................... 31
Up/Down Counter and Thumbwheel Interface .......... 12
Electrical Characteristics ....................................... 32
Serial Ports (SPORTs) .......................................... 12
ESD Sensitivity ................................................... 32
Serial Peripheral Interface (SPI) Ports ...................... 12
Absolute Maximum Ratings ................................... 33
UART Ports (UARTs) .......................................... 13
Package Information ............................................ 33
Controller Area Network (CAN) ............................ 13
Timing Specifications ........................................... 34
TWI Controller Interface ...................................... 13
Power Dissipation ............................................... 58
Ports ................................................................ 14
Test Conditions .................................................. 58
Pixel Compositor (PIXC) ...................................... 14
Environmental Conditions .................................... 59
Enhanced Parallel Peripheral Interface (EPPI) ........... 14
400-Ball BGA Pinout ............................................... 60
USB On-The-Go Dual-Role Device Controller ........... 15
Outline Dimensions ................................................ 66
ATA/ATAPI–6 Interface ...................................... 15
Ordering Guide ..................................................... 67
REVISION HISTORY
Revision PrE: Corrections and additions to PrD:
• Many individual line changes throughout datasheet
• Specific Peripherals for Processors table added
• Replace Voltage Regulator Circuit diagram
• Table 10 - processor pin multiplexing reworked
• Table 11 - Pin Descriptions reworded
• Absolute Maximum Rating reworked
• HDMA A/C Timing-Host Read Cycle and Write Cycle
added
• Outline dimensions specified
Rev. PrE |
Page 2 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
The ADSP-BF542/4/8/9 processors are members of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
Specific peripherals for ADSP-BF542/4/8/9 processors are
shown in Table 2.
Specific performance and memory configurations for
ADSP-BF542/4/8/9 processors are shown in Table 1.
Module
ADSP-BF549
ADSP-BF548
ADSP-BF544
ADSP-BF542
GENERAL DESCRIPTION
EBIU (async)
3
3
3
3
NAND Flash Controller
3
3
3
3
ATAPI
3
3
–
3
Host DMA Port (HOSTDP)
3
3
3
–
SD/SDIO Controller
3
3
–
3
1
2
Automotive Only.
This ROM is not customer configurable.
Table 2. ADSP-BF54x Specific Peripherals for Processors
ADSP-BF542
ADSP-BF544
Processor
Features
ADSP-BF548
ADSP-BF549
Table 1. ADSP-BF542/4/8/9 Processor Features
Code Security
1
1
1
1
SD/SDIO Controller
1
1
–
1
Pixel Compositor
1
1
1
1
18- or 24-bit EPPI0 with LCD
1
1
1
–
16-bit EPPI1, 8-bit EPPI2
1
1
1
1
Host DMA Port
1
1
1
–
NAND Flash Controller
1
1
1
1
ATAPI
1
1
–
1
High Speed USB OTG
1
1
–
1
Keypad Interface
1
1
–
1
MXVR
1
–
–
–
CAN ports1
2
2
2
1
TWI ports
2
2
2
1
SPI ports
3
3
2
2
UART ports
4
4
3
3
SPORTs
4
4
3
3
Up / Down Counter
1
1
1
1
Timers
11
11
11
8
General-purpose I/O pins
152 152 152 152
L1 Instruction SRAM/Cache 16
Memory
Configurations L1 Instruction SRAM
48
(K Bytes)
L1 Data SRAM/Cache
32
16
16
16
48
48
48
32
32
32
L1 Data SRAM
32
32
32
32
L1 Scratchpad SRAM
4
4
4
4
L1 ROM2
64
64
64
64
L2
L3 Boot ROM2
128 128 64
4
4
4
Rev. PrE |
3
3
–
3
3
3
EPPI2
3
3
3
3
SPORT0
3
3
–
–
SPORT1
3
3
3
3
SPORT2
3
3
3
3
SPORT3
3
3
3
3
SPI0
3
3
3
3
SPI1
3
3
3
3
SPI2
3
3
–
–
UART0
3
3
3
3
UART1
3
3
3
3
UART2
3
3
–
–
UART3
3
3
3
3
High Speed USB OTG
3
3
–
3
3
–
3
3
1
1
–
4
533 600 533 600
3
3
CAN0
1
Maximum Core Instruction Rate (MHz)
EPPI0
EPPI1
CAN1
3
–
3
–
TWI0
3
3
3
3
TWI1
3
3
3
–
Timer 0-7
3
3
3
3
Timer 8-10
3
3
3
–
Up / Down Counter
3
3
3
3
Keypad Interface
3
3
–
3
MXVR
3
–
–
–
GPIOs
3
3
3
3
Automotive Only.
Page 3 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
The ADSP-BF542/BF544/BF548 processors are completely code
and pin compatible. They differ only with respect to their performance, on-chip memory, and selection of I/O peripherals.
Specific performance, memory, and feature configurations, are
shown in Table 1. The ADSP-BF549 is completely code compatible with the other ADSP-BF542/4/8/9 processors, and this
processor is pin compatible, except for the location of the
HWAIT pin.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like programmability, multimedia support and leading-edge signal
processing in one integrated package.
LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature on-chip
dynamic power management, the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
substantial reduction in power consumption, compared with
just varying the frequency of operation. This translates into
longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF542/4/8/9 processors are highly integrated system-on-a-chip solutions for the next generation of embedded
network connected applications. By combining industry-standard interfaces with a high performance signal processing core,
users can develop cost-effective solutions quickly without the
need for costly external components. The system peripherals
include a high speed USB OTG (On-The-Go) controller with
integrated PHY, CAN 2.0B controllers, TWI controllers, UART
ports, SPI ports, serial ports (SPORTs), ATAPI controller,
SD/SDIO controller, a real-time clock, a watchdog timer, LCD
controller, and multiple enhanced parallel peripheral interfaces.
ADSP-BF542/4/8/9 PROCESSOR PERIPHERALS
The ADSP-BF542/4/8/9 processor contains a rich set of peripherals connected to the core via several high bandwidth buses,
providing flexibility in system configuration as well as excellent
overall system performance (see Figure 1 on Page 1). The general-purpose peripherals include functions such as UARTs, SPI,
TWI, timers with pulse width modulation (PWM) and pulse
measurement capability, general purpose I/O pins, a real-time
clock, and a watchdog timer. This set of functions satisfies a
wide variety of typical system support needs and is augmented
by the system expansion capabilities of the part. The
ADSP-BF542/4/8/9 processor contains dedicated network communication modules and high-speed serial and parallel ports, an
interrupt controller for flexible management of interrupts from
the on-chip peripherals or external sources, and power management control functions to tailor the performance and power
characteristics of the processor and system to many application
scenarios.
Rev. PrE |
All of the peripherals, except for general-purpose I/O, CAN,
TWI, real-time clock, and timers, are supported by a flexible
DMA structure. There are also separate memory DMA channels
dedicated to data transfers between the processor's various
memory spaces, including external DDR and asynchronous
memory. Multiple on-chip buses running at up to 133 MHz
provide enough bandwidth to keep the processor core running
along with activity on all of the on-chip and external
peripherals.
The ADSP-BF542/4/8/9 processor includes an on-chip voltage
regulator in support of the ADSP-BF542/4/8/9 processor
dynamic power management capability. The voltage regulator
provides a range of core voltage levels when supplied from a single 2.70 V to 3.6 V input. The voltage regulator can be bypassed
at the user's discretion.
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 5, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register
file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations, 16bit and 8-bit adds with clipping, 8-bit average operations, and 8bit subtract/absolute value/accumulate (SAA) operations. Also
provided are the compare/select and vector search instructions.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
Page 4 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
ADDRESS ARITHMETIC UNIT
I3
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
DA1 32
DA0 32
P1
TO MEMORY
P0
32
PREG
32
RAB
SD 32
LD1 32
LD0 32
ASTAT
32
32
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
SEQUENCER
ALIGN
16
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
A0
32
40
40
A1
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
MEMORY ARCHITECTURE
The ADSP-BF542/4/8/9 processor views memory as a single
unified 4G byte address space, using 32-bit addresses. All
Rev. PrE |
resources, including internal memory, external memory, and
I/O control registers, occupy separate sections of this common
address space. The memory portions of this address space are
Page 5 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
The memory DMA controllers (DMAC1 and DMAC0) provides high-bandwidth data-movement capability. They can
perform block transfers of code or data between the internal
memory and the external memory spaces.
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit
(EBIU), provides expansion with flash memory, SRAM, and
double-rate SDRAM (DDR1), optionally accessing up to
516M bytes of physical memory.
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
0xFFB0 0000
The ADSP-BF542/4/8/9 processor also includes an L2 SRAM
memory array which provides 128K bytes of high speed SRAM
operating at one half the frequency of the core, and slightly
longer latency than the L1 memory banks. The L2 memory is a
unified instruction and data memory and can hold any mixture
of code and data required by the system design. The Blackfin
cores share a dedicated low latency 64-bit wide data path port
into the L2 SRAM memory.
RESERVED
0xFFA2 4000
L1 ROM (64K BYTE)
0xFFA1 4000
INSTRUCTION SRAM / CACHE (16K BYTE)
0xFFA1 0000
RESERVED
0xFFA0 C000
INSTRUCTION BANK B SRAM (16K BYTE)
0xFFA0 8000
INSTRUCTION BANK A SRAM (32K BYTE)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTE)
0xFF90 4000
DATA BANK B SRAM (16K BYTE)
INTERNAL MEMORY MAP
arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip
memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 3 on Page 6.
0xFF90 0000
RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTE)
0xFF80 4000
DATA BANK A SRAM (16K BYTE)
0xFF80 0000
RESERVED
0xFEB2 0000
L2 SRAM (128K BYTE)
0xFEB0 0000
RESERVED
0xEF00 1000
BOOT ROM (4K BYTE)
0xEF00 0000
ASYNC MEMORY BANK 3 (64M BYTE)
0x2C00 0000
ASYNC MEMORY BANK 2 (64M BYTE)
0x2800 0000
ASYNC MEMORY BANK 1 (64M BYTE)
0x2400 0000
ASYNC MEMORY BANK 0 (64M BYTE)
0x2000 0000
TOP OF LAST
DDR PAGE
RESERVED
DDR1 MEM BANK 1 (8M BYTE - 256M BYTE)
EXTERNAL MEMORY MAP
RESERVED
0x3000 0000
DDR1 MEM BANK 0 (8M BYTE - 256M BYTE)
0x0000 0000
Figure 3. ADSP-BF549 Internal/External Memory Map1
1
This memory map applies to all ADSP-BF542/4/8/9 processors, except for L2
memory population. For details, see Table 1.
Internal (On-Chip) Memory
The ADSP-BF542/4/8/9 processor has several blocks of on-chip
memory providing high-bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
48K bytes SRAM, and also 16K bytes that can be configured as a
four-way set-associative cache or SRAM. This memory is
accessed at full processor speed.
The second on-chip memory block is the L1 data memory, consisting of 64K bytes SRAM, of which 32K bytes can be
configured as a two-way set associative cache. This memory
block is accessed at full processor speed.
Rev. PrE |
Page 6 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
The fourth memory block is the factory programmed L1
instruction ROM, operating at full processor speed. This ROM
is not customer configurable.
system may be used to manage reading and writing of the
NAND flash device. The file system selects memory segments
for storage with the goal of avoiding bad blocks and equally distributing memory accesses across all address locations.
Hardware features of the NFC include:
• Support for page program, page read, and block erase of
NAND flash devices, with accesses aligned to page
boundaries.
The fifth memory block is the L2 SRAM, providing 128K bytes
of unified Instruction and data memory, operating at one half
the frequency of the core.
• Error checking and correction (ECC) hardware that facilitates error detection and correction.
Finally, there is a 4K boot ROM that can be seen as L3 memory.
It operates at full SCLK rate.
• A single 8-bit or 16-bit external bus interface for commands, addresses and data.
External (Off-Chip) Memory
• Support for SLC (single level cell) NAND flash devices
unlimited in size, with page sizes of 256 and 512 bytes.
Larger page sizes can be supported in software.
Through the External Bus Interface Unit (EBIU) the
ADSP-BF542/4/8/9 processors provide glueless connectivity to
external 16-bit wide memories, such as DDR SDRAM, Mobile
DDR, SRAM, NOR flash, NAND flash, and FIFO devices. To
provide the best performance, the bus system of the DDR interface is completely separate from the other parallel interfaces.
The DDR/Mobile DDR memory controller can gluelessly manage up to two banks of double-rate synchronous dynamic
memory (DDR1 SDRAM). The 16-bit wide interface operates at
SCLK frequency enabling maximum throughput of 532
Mbyte/s. The DDR controller is augmented with a queuing
mechanism that performs efficient bursts onto the DDR. The
controller is an industry standard DDR SDRAM controller with
each bank supporting from 64 Mbit to 512 Mbit device sizes and
4-, 8-, or 16-bit widths. The controller supports up to 512
Mbytes in one bank, but the total in two banks is limited to 512
Mbytes. Each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the
different banks or their placement.
Traditional 16-bit asynchronous memories, such as SRAM,
EPROM, and flash devices, can be connected to one of the four
64 MByte asynchronous memory banks, represented by four
memory select strobes. Alternatively, these strobes can function
as bank-specific read or write strobes preventing further glue
logic when connecting to asynchronous FIFO devices.
In addition, the external bus can connect to advanced flash
device technologies, such as:
• Page-mode NOR flash devices
• Capability of releasing external bus interface pins during
long accesses.
• Support for internal bus requests of 16 or 32 bits.
• DMA engine to transfer data between internal memory and
NAND flash device.
I/O Memory Space
The ADSP-BF542/4/8/9 processors do not define a separate I/O
space. All resources are mapped through the flat 32-bit address
space. On-chip I/O devices have their control registers mapped
into memory-mapped registers (MMRs) at addresses near the
top of the 4G byte address space. These are separated into two
smaller blocks, one which contains the control MMRs for all
core functions, and the other which contains the registers
needed for setup and control of the on-chip peripherals outside
of the core. The MMRs are accessible only in supervisor mode
and appear as reserved space to on-chip peripherals.
Booting
The ADSP-BF542/4/8/9 processor contains a small on-chip
boot kernel, which configures the appropriate peripheral for
booting. If the ADSP-BF542/4/8/9 processor is configured to
boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see
Booting Modes on Page 19.
Event Handling
• Synchronous burst-mode NOR flash devices
• NAND flash devices
NAND Flash Controller (NFC)
The ADSP-BF542/4/8/9 provides a NAND Flash Controller
(NFC) as part of the external bus interface. NAND flash devices
provide high-density, low-cost memory. However, NAND flash
devices also have long random access times, invalid blocks, and
lower reliability over device lifetimes. Because of this, NAND
flash is often used for read-only code storage. In this case, all
DSP code can be stored in NAND flash and then transferred to a
faster memory (such as DDR or SRAM) before execution.
Another common use of NAND flash is for storage of multimedia files or other large data segments. In this case, a software file
Rev. PrE |
The event controller on the ADSP-BF542/4/8/9 processor handles all asynchronous and synchronous events to the processor.
The ADSP-BF542/4/8/9 processor provides event handling that
supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously.
Prioritization ensures that servicing of a higher-priority event
takes precedence over servicing of a lower-priority event. The
controller provides support for five different types of events:
Page 7 of 68 |
• Emulation. An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset. This event resets the processor.
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
• Non-Maskable Interrupt (NMI). The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
• Exceptions. Events that occur synchronously to program
flow (that is, the exception is taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts. Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
The ADSP-BF542/4/8/9 processor event controller consists of
two stages, the core event controller (CEC) and the system
interrupt controller (SIC). The core event controller works with
the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter
into the SIC, and are then routed directly into the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF542/4/8/9 processor.
Table 3 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test Control
Reset
Non-Maskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Rev. PrE |
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF542/4/8/9 processor provides a default
mapping, the user can alter the mappings and priorities of
interrupt events by writing the appropriate values into the interrupt assignment registers (IAR). Table 4 describes the inputs
into the SIC and the default mappings into the CEC.
Table 4. System Interrupt Controller (SIC)
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
Table 3. Core Event Controller (CEC)
System Interrupt Controller (SIC)
Peripheral IRQ
(IRQ) Source
IRQ
GP IRQ
ID (at Reset)
Core
IRQ ID
PLL Wakeup IRQ
0
IVG7
0
DMAC0 Status (generic)
1
IVG7
0
EPPI0 Error IRQ
2
IVG7
0
SPORT0 Error IRQ
3
IVG7
0
SPORT1 Error IRQ
4
IVG7
0
SPI0 Status IRQ
5
IVG7
0
UART0 Status IRQ
6
IVG7
0
Real-Time Clock IRQ
7
IVG8
1
DMA12 IRQ (EPPI0)
8
IVG8
1
DMA0 IRQ (SPORT0 RX)
9
IVG9
2
DMA1 IRQ (SPORT0 TX)
10
IVG9
2
DMA2 IRQ (SPORT1 RX)
11
IVG9
2
DMA3 IRQ (SPORT1 TX)
12
IVG9
2
DMA4 IRQ (SPI0)
13
IVG10
3
DMA6 IRQ (UART0 RX)
14
IVG10
3
DMA7 IRQ (UART0 TX)
15
IVG10
3
Timer 8 IRQ
16
IVG11
4
Timer 9 IRQ
17
IVG11
4
Timer 10 IRQ
18
IVG11
4
Pin IRQ 0 (PINT0)
19
IVG12
5
Pin IRQ 1 (PINT1)
20
IVG12
5
MDMA Stream 0 IRQ
21
IVG13
6
MDMA Stream 1 IRQ
22
IVG13
6
Software Watchdog Timer IRQ
23
IVG13
6
DMAC1 Status (generic)
24
IVG7
0
SPORT2 Error IRQ
25
IVG7
0
SPORT3 Error IRQ
26
IVG7
0
MXVR Synchronous Data IRQ
27
IVG7
0
SPI1 Status IRQ
28
IVG7
0
SPI2 Status IRQ
29
IVG7
0
UART1 Status IRQ
30
IVG7
0
UART2 Status IRQ
31
IVG7
0
Page 8 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 4. System Interrupt Controller (SIC) (Continued)
Peripheral IRQ
(IRQ) Source
IRQ
GP IRQ
ID (at Reset)
CAN0 Status IRQ
32
IVG7
DMA18 IRQ (SPORT2 RX)
33
DMA19 IRQ (SPORT2 TX)
34
DMA20 IRQ (SPORT3 RX)
Table 4. System Interrupt Controller (SIC) (Continued)
Core
IRQ ID
Peripheral IRQ
(IRQ) Source
IRQ
GP IRQ
ID (at Reset)
0
Counter (CNT) IRQ
68
IVG9
2
Keypad (KEY) IRQ
IVG9
2
CAN1 RX IRQ
35
IVG9
2
DMA21 IRQ (SPORT3 TX)
36
IVG9
DMA13 IRQ (EPPI1)
37
DMA14 IRQ (EPPI2, Host DMA)
DMA5 IRQ (SPI1)
Core
IRQ ID
IVG8
1
69
IVG8
1
70
IVG11
4
CAN1 TX IRQ
71
IVG11
4
2
SDH Mask 0 IRQ
72
IVG11
4
IVG9
2
SDH Mask 1 IRQ
73
IVG11
4
38
IVG9
2
Reserved
74
IVG11
4
39
IVG10
3
USB_INT0 IRQ
75
IVG11
4
DMA23 IRQ (SPI2)
40
IVG10
3
USB_INT1 IRQ
76
IVG11
4
DMA8 IRQ (UART1 RX)
41
IVG10
3
USB_INT2 IRQ
77
IVG11
4
DMA9 IRQ (UART1 TX)
42
IVG10
3
USB_DMAINT IRQ
78
IVG11
4
DMA10 IRQ (ATAPI RX)
43
IVG10
3
OTPSEC IRQ
79
IVG11
4
DMA11 IRQ (ATAPI TX)
44
IVG10
3
Reserved
80
IVG11
4
TWI0 IRQ
45
IVG11
4
Reserved
81
IVG11
4
TWI1 IRQ
46
IVG11
4
Reserved
82
IVG11
4
CAN0 Receive IRQ
47
IVG11
4
Reserved
83
IVG11
4
CAN0 Transmit IRQ
48
IVG11
4
Reserved
84
IVG11
4
MDMA Stream 2 IRQ
49
IVG13
6
Reserved
85
IVG11
4
MDMA Stream 3 IRQ
50
IVG13
6
Timer 0 IRQ
86
IVG11
4
MXVR Status IRQ
51
IVG11
4
Timer 1 IRQ
87
IVG11
4
MXVR Control Message IRQ
52
IVG11
4
Timer 2 IRQ
88
IVG11
4
MXVR Asynchronous Packet IRQ
53
IVG11
4
Timer 3 IRQ
89
IVG11
4
EPPI1 Error IRQ
54
IVG7
0
Timer 4 IRQ
90
IVG11
4
EPPI2 Error IRQ
55
IVG7
0
Timer 5 IRQ
91
IVG11
4
UART3 Status IRQ
56
IVG7
0
Timer 6 IRQ
92
IVG11
4
Host DMA Status
57
IVG7
0
Timer 7 IRQ
93
IVG11
4
Reserved
58
IVG7
0
Pin IRQ 2 (PINT2)
94
IVG12
5
Pixel Compositor (PIXC) Status IRQ
59
IVG7
0
Pin IRQ 3 (PINT3)
95
IVG12
5
NFC Error IRQ
60
IVG7
0
ATAPI Error IRQ
61
IVG7
0
CAN1 Status IRQ
62
IVG7
0
DMAR0 Block IRQ
63
IVG7
0
DMAR1 Block IRQ
63
IVG7
0
DMAR0 Overflow Error IRQ
63
IVG7
0
DMAR1 Overflow Error IRQ
63
IVG7
0
DMA15 IRQ (PIXC0)
64
IVG8
1
DMA16 IRQ (PIXC1)
65
IVG8
1
DMA17 IRQ (PIXC2)
66
IVG8
1
DMA22 IRQ (SDH/NFC)
67
IVG8
1
Rev. PrE |
Event Control
The ADSP-BF542/4/8/9 processor provides the user with a very
flexible mechanism to control the processing of events. In the
CEC, three registers are used to coordinate and control events.
Each register is 16 bits wide:
• CEC interrupt latch register (ILAT). The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
Page 9 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
• CEC interrupt mask register (IMASK). The IMASK register controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and is processed by the CEC when asserted. A
cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the
event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)
• CEC interrupt pending register (IPEND). The IPEND register keeps track of all nested events. A set bit in the IPEND
register indicates the event is currently active or nested at
some level. This register is updated automatically by the
controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 4 on Page 8.
• SIC interrupt mask register (SIC_IMASK). This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and is processed by the system when asserted. A cleared bit in the register masks the
peripheral event, preventing the processor from servicing
the event.
• SIC interrupt status register (SIC_ISR). As multiple peripherals can be mapped to a single event, this register allows
the software to determine which peripheral event source
triggered the interrupt. A set bit indicates the peripheral is
asserting the interrupt, and a cleared bit indicates the
peripheral is not asserting the event.
• SIC interrupt wakeup enable register (SIC_IWR). By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more information, see Dynamic Power Management on Page 16.)
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
Rev. PrE |
DMA CONTROLLERS
ADSP-BF542/4/8/9 processors have multiple, independent
DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur
between the ADSP-BF542/4/8/9 processor’s internal memories
and any of its DMA-capable peripherals. Additionally, DMA
transfers can be accomplished between any of the DMA-capable
peripherals and external devices connected to the external
memory interfaces, including DDR and asynchronous memory
controllers.
While the USB controller and MXVR have their own dedicated
DMA controllers, the other on-chip peripherals are managed by
two centralized DMA controllers, called DMAC1 (32-bit) and
DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA
controller manages twelve independent DMA channels. The
DMAC1 controller masters high-bandwidth peripherals over a
dedicated 32-bit DMA access bus (DAB32). Similarly, the
DMAC0 controller masters most of serial interfaces over the 16bit DAB16 bus. Individual DMA channels have fixed access priority on the DAB buses. DMA priority of peripherals is
managed by flexible peripheral-to-DMA channel assignment.
All four DMA controllers use the same 32-bit DCB bus to
exchange data with L1 memory. This includes L1 ROM, but
excludes scratchpad memory. Fine granulation of L1 memory
and special DMA buffers minimize potential memory conflicts,
if the L1 memory is accessed by the core contemporaneously.
Similarly, there are dedicated DMA buses between the DMAC1,
DMAC0, and USB DMA controllers and the external bus interface unit (EBIU) that arbitrates DMA accesses to external
memories and boot ROM.
The ADSP-BF542/4/8/9 processor DMA controllers support
both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from
registers or from sets of parameters called descriptor blocks.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be deinterleaved on the fly.
Examples of DMA types supported by the ADSP-BF542/4/8/9
processor DMA controller include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, both the
DMAC1 and the DMAC0 controllers feature two memory
DMA channel pairs for transfers between the various memories
of the ADSP-BF542/4/8/9 processor system. This enables transfers of blocks of data between any of the memories—including
Page 10 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
external DDR, ROM, SRAM, and flash memory—with minimal
processor intervention. Like peripheral DMAs, memory DMA
transfers can be controlled by a very flexible descriptor-based
methodology or by a standard register-based autobuffer
mechanism.
The memory DMA channels of the DMAC1 controller
(MDMA2 and MDMA3) can be optionally controlled by the
external DMA request input pins. When used in conjunction
with the External Bus Interface Unit (EBIU), this so-called
Handshaked Memory DMA (HMDMA) scheme can be used to
efficiently exchange data with block-buffered or FIFO-style
devices connected externally. Users can select whether the DMA
request pins control the source or the destination side of the
memory DMA. It allows control of the number of data transfers
for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow memory
DMA to have an increased priority on the external bus relative
to the core.
Host DMA Port Interface
The Host DMA port (HOSTDP) facilitates a host device external to the ADSP-BF542/4/8/9 to be a DMA master and transfer
data back and forth. The host device always masters the transactions and the processor is always a DMA slave device.
The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60-second counter, a 60-minute
counter, a 24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the
ADSP-BF542/4/8/9 processor from sleep mode upon generation
of any RTC wakeup event. Additionally, an RTC wakeup event
can wake up the ADSP-BF542/4/8/9 processor from deep sleep
mode, and wake up the on-chip internal voltage regulator from
the hibernate operating mode.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 4.
RTXI
RTXO
R1
The HOSTDP port is enabled through the peripheral access bus.
Once the port has been enabled, the transaction are controlled
by the external host. The external host programs standard DMA
configuration words in order to send/receive data to any valid
internal or external memory location. The Host DMA Port controller includes the following features:
X1
C1
• Allows an external master to configure DMA read/write
data transfers and read port status
C2
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10 M ⍀
• Uses a flexible asynchronous memory protocol for its
external interface
• Allows an 8- or 16-bit external data interface to the host
device
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
• Supports half-duplex operation
Figure 4. External Components for RTC
• Supports Little/Big Endian data transfers
• Acknowledge mode allows flow control on host
transactions
WATCHDOG TIMER
• Interrupt mode guarantees a burst of FIFO depth host
transactions
REAL-TIME CLOCK
The ADSP-BF542/4/8/9 processor Real-Time Clock (RTC) provides a robust set of digital watch features, including current
time, stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the ADSP-BF542/4/8/9 processors. The RTC peripheral has dedicated power supply pins so
that it can remain powered up and clocked even when the rest of
the processor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a programmed alarm time.
Rev. PrE |
The ADSP-BF542/4/8/9 processor includes a 32-bit timer that
can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the
processor to a known state through generation of a hardware
reset, non-maskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The
programmer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remaining in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
Page 11 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF542/4/8/9 processor
peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a
status bit in the watchdog timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are up to two timer units in the ADSP-BF542/4/8/9 processors. One unit provides eight general-purpose programmable
timers and the other unit provides three. Each timer has an
external pin that can be configured either as a Pulse Width
Modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an
external clock input on the TMRx pins, an external clock
TMRCLK input pin, or to the internal SCLK.
The timer units can be used in conjunction with the two UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the general-purpose programmable timers,
another timer is also provided by the processor core. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generation of operating system
periodic interrupts.
UP/DOWN COUNTER AND THUMBWHEEL
INTERFACE
SERIAL PORTS (SPORTS)
The ADSP-BF542/4/8/9 processor incorporates up to four dualchannel synchronous serial ports (SPORT0, SPORT1, SPORT2,
SPORT3) for serial and multiprocessor communications. The
SPORTs support the following features:
• I2S capable operation.
• Bidirectional operation. Each SPORT has two sets of independent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports. Each port has
a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking. Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length. Each SPORT supports serial data words from
3 to 32 bits in length, transferred most-significant-bit first
or least-significant-bit first.
• Framing. Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
• Companding in hardware. Each SPORT can perform
A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
• DMA operations with single-cycle overhead. Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
A 32-bit up/down counter is provided that can sense 2-bit
quadrature or binary codes as typically emitted by industrial
drives or manual thumb wheels. The counter can also operate in
general-purpose up/down count modes. Then, count direction
is either controlled by a level-sensitive input pin or by two edge
detectors.
• Interrupts. Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three pins have a programmable debouncing circuit.
• Multichannel capability. Each SPORT supports 128 channels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
An internal signal forwarded to the timer unit enables one timer
to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by
interrupts when programmable count values are exceeded.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF542/4/8/9 processor has up to three SPI-compatible ports that allow the processor to communicate with multiple
SPI-compatible devices.
Each SPI port uses three pins for transferring data: two data pins
(master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip
select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7–1) let the
processor select other SPI devices. The SPI select pins are reconfigured programmable flag pins. Using these pins, the SPI ports
provide a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments.
Rev. PrE |
Page 12 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
f SCLK
SPI Clock Rate = -------------------------------2 × SPI_Baud
UART1 and UART3 feature a pair of RTS (request to send) and
CTS (clear to send) signals for hardware flow purposes. The
transmitter hardware is automatically prevented from sending
further data when the CTS input is de-asserted. The receiver can
automatically de-assert its RTS output when the enhanced
receive FIFO exceeds a certain high-water level. The capabilities
of the UARTs are further extended with support for the Infrared
Data Association (IrDA®) Serial Infrared Physical Layer Link
Specification (SIR) protocol.
CONTROLLER AREA NETWORK (CAN)
Where the 16-bit SPI_BAUD register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
UART PORTS (UARTS)
The ADSP-BF542/4/8/9 processor provides up to four fullduplex Universal Asynchronous Receiver/Transmitter (UART)
ports. Each UART port provides a simplified UART interface to
other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port
includes support for 5 to 8 data bits, 1 or 2 stop bits, and none,
even, or odd parity. Each UART port supports two modes of
operation:
The ADSP-BF542/4/9 processor offers up to two CAN controllers that are communication controllers that implement the
Controller Area Network (CAN) 2.0B (active) protocol. This
protocol is an asynchronous communications protocol used in
both industrial and automotive control systems. The CAN protocol is well suited for control applications due to its capability
to communicate reliably over a network since the protocol
incorporates CRC checking message error tracking, and fault
node confinement.
The ADSP-BF542/4/9 CAN controllers offer the following
features:
• 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit).
• Dedicated acceptance masks for each mailbox.
• PIO (programmed I/O). The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• Additional data filtering on first two bytes.
• DMA (Direct Memory Access). The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates. Flexible interrupt timing options are available on the transmit
side.
• Support for remote frames.
Each UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK) bits per second.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
f SCLK
UART Clock Rate = --------------------------------------------------------------------------( 1 – EBIO )
16
× UART_Divisor
Where the 16-bit UART Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).
In conjunction with the general-purpose timer functions, autobaud detection is supported.
Rev. PrE |
• Support for both the standard (11-bit) and extended (29bit) identifier (ID) message formats.
• Active or passive network support.
• CAN wakeup from hibernation mode (lowest static power
consumption mode).
• Interrupts, including: TX complete, RX complete, error,
global.
The electrical characteristics of each network connection are
very demanding so the CAN interface is typically divided into
two parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF542/4/9 CAN module represents only the controller
part of the interface. The controller interface supports connection to 3.3V high-speed, fault-tolerant, single-wire transceivers.
TWI CONTROLLER INTERFACE
The ADSP-BF542/4/8/9 processor includes up to two Two Wire
Interface (TWI) modules for providing a simple exchange
method of control data between multiple devices. The modules
are compatible with the widely used I2C bus standard. The TWI
modules offer the capabilities of simultaneous Master and Slave
operation, support for both 7-bit addressing and multimedia
data arbitration. Each TWI interface uses two pins for transferring clock (SCL) and data (SDA) and supports the protocol at
speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels.
Page 13 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Additionally, the ADSP-BF542/4/8/9 processor’s TWI modules
are fully compatible with Serial Camera Control Bus (SCCB)
functionality for easier control of various CMOS camera sensor
devices.
PORTS
Because of their rich set of peripherals, the ADSP-BF542/4/8/9
processors group the many peripheral signals to ten ports—
referred to as Port A to Port J. Most ports contain 16 pins, a few
have less. Many of the associated pins are shared by multiple
signals. The ports function as multiplexer controls. Every port
has its own set of memory-mapped registers to control port
muxing and GPIO functionality.
General-Purpose I/O (GPIO)
Every pin in Port A to Port J can function as a GPIO pin resulting in a GPIO pin count of 154. While it is unlikely that all
GPIOs will be used in an application as all pins have multiple
functions, the richness of GPIO functionality guarantees unrestrictive pin usage. Every pin that is not used by any function
can be configured in GPIO mode on an individual basis.
After reset, all pins are in GPIO mode by default. Neither GPIO
output nor input drivers are active by default. Unused pins can
be left unconnected, therefore. GPIO data and direction control
registers provide flexible write-one-to-set and write-one-toclear mechanisms so that independent software threads do not
need to protect against each other because of expensive readmodify-write operations when accessing the same port.
Pin Interrupts
Due to the huge number of port pins, the ADSP-BF542/4/8/9
processors introduce a new scheme to manage pin interrupts.
Every port pin can request interrupts in either an edge-sensitive
or a level-sensitive manner with programmable polarity. Interrupt functionality is decoupled from GPIO operation. Four
system-level interrupt channels (INT0, INT1, INT2 and INT3)
are reserved for this purpose. Each of these interrupt channels
can manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed at a pin by pin level. Rather, groups
of eight pins (half ports) can be flexibly assigned to interrupt
channels.
Every pin interrupt channel features a special set of 32-bit memory-mapped registers, that enable half port assignment and
interrupt management. This not only includes masking, identification, and clearing of requests, it also enables access to the
respective pin states and use of the interrupt latches regardless
of whether the interrupt is masked or not. Most control registers
feature multiple MMR address entries to write-one-to-set or
write-one-to-clear them individually.
both LCD panels and digital video outputs. The main image
buffer provides the basic background image, which is presented
in the data stream. The overlay image buffer allows the user to
add multiple foreground text, graphics, or video on top of the
main image or video data stream.
ENHANCED PARALLEL PERIPHERAL INTERFACE
(EPPI)
The ADSP-BF542/4/8/9 processor provides up to three
Enhanced Parallel Peripheral Interfaces (EPPIs), supporting
data widths up to 24 bits wide. The EPPI supports direct connection to active TFT LCD, parallel A/D and D/A converters,
video encoders and decoders, image sensor modules and other
general purpose peripherals.
The following features are supported in the EPPI module.
• Programmable data length: 8, 10, 12, 14, 16, 18, 24 and 32
bits per clock.
• Bi-directional and half-duplex port.
• Clock can be provided externally or can be generated
internally.
• Various framed and non-framed operating modes. Frame
syncs can be generated internally or can be supplied by an
external device.
• Various general purpose modes with one frame syncs, two
frame syncs, three frame syncs and zero frame sync modes
for both receive and transmit.
• ITU-656 status word error detection and correction for
ITU-656 Receive modes.
• ITU-656 preamble and status word decode.
• Three different modes for ITU-656 receive modes: active
video only, vertical blanking only, and entire field mode.
• Horizontal and vertical windowing for GP 2 and 3 FS
Modes.
• Optional packing and unpacking of data to/from 32 bits
from/to 8, 16 and 24 bits. If packing/unpacking is enabled,
endianness can be changed to change the order of packing/unpacking of bytes/words.
• Optional sign extension or zero fill for receive modes.
• During receive modes, alternate even or odd data samples
can be filtered out.
• Programmable clipping of data values for 8-bit transmit
modes.
• RGB888 can be converted to RGB666 or RGB565 for transmit modes.
• Various de-interleaving/interleaving modes for receiving/transmitting 4:2:2 YCrCb data.
PIXEL COMPOSITOR (PIXC)
The pixel compositor (PIXC) provides image overlay with
transparent-color support, alpha blending, and color space conversion capability for output to TFT-LCDs as well as
NTSC/PAL video encoders. It provides all of the control to
allow two data streams from two separate data buffers to be
combined, blended, and converted into appropriate forms for
Rev. PrE |
• FIFO watermarks and urgent DMA features.
• Clock gating by an external device asserting the clock gating control signal.
Page 14 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER
SECURE DIGITAL (SD)/SDIO CONTROLLER
The USB OTG controller provides a low-cost connectivity solution for consumer mobile devices such as cell phones, digital
still cameras and MP3 players, allowing these devices to transfer
data using a point-to-point USB connection without the need
for a PC host. The USBDRC module can operate in a traditional
USB peripheral-only mode as well as the host mode presented
in the On-The-Go (OTG) supplement [1] to the USB 2.0 Specification [2]. In host mode, the USB module supports transfers at
high-speed (480Mbps), full-speed (12Mbps), and low-speed
(1.5Mbps) rates. Peripheral-only mode supports the high- and
full-speed transfer rates.
The SD/SDIO controller is a serial interface that stores data at a
data rate of up to 10M bytes per second using a 4-bit data line.
The interface runs at 25 MHz.
ATA/ATAPI–6 INTERFACE
An OTP/security system consisting of a blend of hardware and
software provides customers with a flexible and rich set of code
security features with LockboxTM1 secure technology. Key features include:
• Unique chip ID
• Code authentication
• Secure mode of operation
MEDIA TRANSCEIVER MAC LAYER (MXVR)
• Supports PIO modes 0,1,2,3,4
• Supports Multiword DMA modes 0,1,2
• Supports Ultra DMA modes 0,1,2,3,4,5 (up to UDMA 100)
• Programmable timing for ATA interface unit
• Supports CompactFlash Card using True IDE mode
KEYPAD INTERFACE
The keypad interface is a 16 pin interface module that is used to
detect the key pressed in a 8x8 (maximum) keypad matrix. The
size of the input keypad matrix is programmable. The interface
is capable of filtering the bounce on the input pins, which is
common in keypad applications. The width of the filtered
bounce is programmable. The Interface module is capable of
generating an interrupt request to the core once it identifies that
any key has been pressed.
The interface supports a press-release-press mode and infrastructure for a press-hold mode. The former mode identifies a
press, release and press of a key as two consecutive presses of the
same key where as the later mode checks the input key’s state in
periodic intervals to determine the number of times the same
key is meant to be pressed. Simultaneous multiple keys pressed
detection possible and limited key resolution capability. Key
features include:
• Programmable input keypad matrix size
CODE SECURITY
• OTP memory
The ATAPI interface connects to CD/DVD and HDD drives,
and is ATAPI-6 compliant. The controller implements the
peripheral I/O mode, the multi-DMA mode, and the Ultra
DMA mode. The DMA modes enable faster data transfer and
reduced host management. The ATAPI Controller supports
PIO, Multi-DMA, and Ultra DMA ATAPI accesses. Key features include:
• Supports a maximum of 8x8 keypad matrix
The SD/SDIO controller supports the SD memory mode only.
The interface supports all the power modes and performs error
checking by CRC.
The ADSP-BF549 processor provides a Media Transceiver
(MXVR) MAC layer, allowing the processor to be connected
directly to a MOST®2 network through just an FOT or Electrical
PHY.
The MXVR is fully compatible with the industry standard standalone MOST controller devices, supporting 22.579 Mbps or
24.576 Mbps data transfer. It offers faster lock times, greater jitter immunity, a sophisticated DMA scheme for data transfers,
and the high-speed internal interface to the core and L1 memory allows the full bandwidth of the network to be utilized. The
MXVR can operate as either the network master or as a network
slave.
The MXVR supports synchronous data, asynchronous packets,
and control messages using dedicated DMA channels which
operate autonomously from the processor core moving data to
and from L1 and/or L2 memory. Synchronous data is transferred to or from the synchronous data physical channels on the
MOST bus through eight programmable DMA channels. The
synchronous data DMA channels can operate in various modes
including modes which trigger DMA operation when data patterns are detected in the receive data stream. Furthermore two
DMA channels support asynchronous traffic and a further two
support control message traffic.
Interrupts are generated when a user defined amount of synchronous data has been sent or received by the processor or
when asynchronous packets or control messages have been sent
or received.
The MXVR peripheral can wake up the ADSP-BF549 processor
from sleep mode when a wakeup preamble is received over the
network or based on any other MXVR interrupt event. Additionally, detection of network activity by the MXVR can be used
to wake up the ADSP-BF549 processor from sleep mode or
• Debounce filter on input signals
• Programmable debounce filter width
• Press-Release-Press mode supported
• Infrastructure for Press-Hold mode present
• Interrupt on any key pressed capability
• Multiple key pressed detection and limited multiple key
resolution capability
Rev. PrE |
1
2
Lockbox is a trademark of Analog Devices, Inc.
MOST is a registered trademark of Standard Microsystems, Corp.
Page 15 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
hibernate. These features allow the ADSP-BF549 to operate in a
low-power state when there is no network activity or when data
is not currently being received or transmitted by the MXVR.
The MXVR clock is provided through a dedicated external crystal or crystal oscillator. The frequency of external crystal or
crystal oscillator can be 256Fs, 384Fs, 512Fs, or 1024Fs for
Fs = 38kHz, 44.1kHz, or 48kHz. If using a crystal to provide the
MXVR clock, use a parallel-resonant, fundamental mode,
microprocessor-grade crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF542/4/8/9 processor provides five operating
modes, each with a different performance/power profile. In
addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the ADSP-BF542/4/8/9 processor peripherals also reduces
power consumption. See Table 5 for a summary of the power
settings for each mode.
Full-On Operating Mode – Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode – Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.
cally an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the full on mode. If BYPASS is enabled,
the processor will transition to the active mode.
When in the sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode – Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode.
Hibernate State – Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0V to provide the greatest power savings mode.
Any critical information stored internally (memory contents,
register contents, etc.) must be written to a non-volatile storage
device prior to removing power if the processor state is to be
preserved.
Core
Power
Sleep
Deep Sleep
Hibernate
Enabled
Enabled/
Disabled
Enabled
Disabled
Disabled
System
Clock
(SCLK)
Full On
Active
Core
Clock
(CCLK)
The internal supply regulator can be woken up by CAN, by the
MXVR, by the keypad, by the up/down counter, and by some
GPIO pins. It can also be woken up by a real-time clock wakeup
event or by asserting the RESET pin. Waking up from hibernate
state initiates the hardware reset sequence.
PLL
Bypassed
Table 5. Power Settings
PLL
Since VDDEXT is still supplied in this mode, all of the external
pins tri-state, unless otherwise specified. This allows other
devices that may be connected to the processor to have power
still applied without drawing unwanted current.
Mode
In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
No
Yes
Enabled
Enabled
Enabled
Enabled
On
On
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in hibernate
state. State variables may be held in external SRAM or SDRAM.
-
Disabled
Disabled
Disabled
Enabled
Disabled
Disabled
On
On
Off
Power Savings
Sleep Operating Mode – High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
Rev. PrE |
As shown in Table 6, the ADSP-BF542/4/8/9 processor supports
different power domains. The use of multiple power domains
maximizes flexibility, while maintaining compliance with
industry standards and conventions. By isolating the internal
logic of the ADSP-BF542/4/8/9 processor into its own power
domain, separate from the RTC and other I/O, the processor
Page 16 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
can take advantage of dynamic power management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
For additional information, see “Switching Regulator Design
Considerations for the ASDP-BF533 Blackfin Processors” (EE228).
Table 6. Power Domains
Power Domain
All internal logic, except RTC, DDR, and USB
RTC internal logic and crystal I/O
DDR external memory supply
USB internal logic and crystal I/O
MXVR crystal I/O
MXVR I/O
MXVR PLL and logic
All other I/O
VDD Range
VDDINT
VDDRTC
VDDDDR
VDDUSB
VDDMC
VDDMX
VDDMP
VDDEXT
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
VDDEXT
(LOW-INDUCTANCE)
SET OF DECOUPLING
CAPACITORS
+
VDDEXT
100μF
10μH
100nF
+
100μF
+
VDDINT
FDS9431A
100μF
10μF
LOW ESR
ZHCS1000
VROUT
VOLTAGE REGULATION
The ADSP-BF542/4/8/9 processor provides an on-chip voltage
regulator that can generate processor core voltage levels from an
external supply. (Note specifications as indicated in Operating
Conditions on Page 31.) Figure 5 shows the typical external
components required to complete the power management system. The regulator controls the internal logic voltage levels and
is programmable with the voltage regulator control register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
supplied. While in hibernate mode, VDDEXT can still be applied,
eliminating the need for external buffers. The voltage regulator
can be activated from this power down state by assertion of the
RESET pin, which will then initiate a boot sequence. The regulator can also be disabled and bypassed at the user’s discretion.
SHORT AND LOWINDUCTANCE WIRE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
VROUT
GND
Figure 5. Voltage Regulator Circuit
CLOCK SIGNALS
The ADSP-BF542/4/8/9 processor can be clocked by an external
crystal, a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF542/4/8/9 processor
includes an on-chip oscillator circuit, an external crystal may be
used. For fundamental frequency operation, use the circuit
shown in Figure 6. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal is connected across the CLKIN
and XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 kΩ range. Further parallel resistors are
typically not recommended. The two capacitors and the series
resistor shown in Figure 6 fine tune phase and amplitude of the
sine frequency.
The capacitor and resistor values shown in Figure 6 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
Rev. PrE |
Page 17 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
specified by the crystal manufacturer. System designs should
verify the customized values based on careful investigations on
multiple devices over temperature range.
It functions as reference for many timing specifications. While
inactive by default, it can be enabled using the EBIU_SDGCTL
and EBIU_AMGCTL registers.
BLACKFIN
DYNAMIC MODIFICATION
REQUIRES PLL SEQUENCING
CLKOUT
TO PLL CIRCUITRY
DYNAMIC MODIFICATION
ON-THE-FLY
EN
CLKBUF
PLL
0.5x - 64x
CLKIN
EN
CLKIN
ⴜ 1, 2, 4, 8
CCLK
ⴜ 1:15
SCLK
VCO
XTAL
330⍀*
FOR OVERTONE
OPERATION ONLY:
SCLK ⱕ CCLK/2
SCLK ⱕ 133MHz
18 pF*
18 pF*
Figure 7. Frequency Modification Methods
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Figure 6. External Crystal Connections
A third-overtone crystal can be used at frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 6. A design procedure for third-overtone operation is discussed in detail in application note EE-168.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 7 on Page 18, the core clock
(CCLK) and system peripheral clock (SCLK) are derived from
the input clock (CLKIN) signal. An on-chip PLL is capable of
multiplying the CLKIN signal by a programmable
1ⴛ to 63ⴛ multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier
is 10ⴛ, but it can be modified by a software instruction
sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register.
On-the-fly CCLK and SCLK frequency changes can be effected
by simply writing to the PLL_DIV register. Whereas the maximum allowed CCLK and SCLK rates depend on the applied
voltages VDDINT and VDDEXT, the VCO is always permitted to run
up to the frequency specified by the part’s speed grade. The
CLKOUT pin reflects the SCLK frequency to the off-chip world.
Rev. PrE |
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are two
through 15. Table 7 illustrates typical system clock ratios. The
default ratio is 5.
Table 7. Example System Clock Ratios
Signal Name
SSEL3–0
0010
0110
1010
Example Frequency Ratios
Divider Ratio (MHz)
VCO/SCLK
VCO
SCLK
2:1
200
100
6:1
300
50
10:1
500
50
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. The default ratio is 1. This programmable core clock
capability is useful for fast core frequency modifications.
Page 18 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
The maximum CCLK frequency not only depends on the part's
speed grade, it also depends on the applied VDDINT voltage. See
Table 15 through Table 17 for details.
• Idle–no boot mode (BMODE=0x0) — In this mode, the
processor goes into idle. The idle boot mode helps to
recover from illegal operating modes, in the case the user
misconfigured the OTP memory.
Table 8. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Divider Ratio Example Frequency Ratios
VCO/CCLK
(MHz)
VCO
CCLK
1:1
300
300
2:1
300
150
4:1
500
125
8:1
200
25
BOOTING MODES
The ADSP-BF542/4/8/9 processor has many mechanisms (listed
in Table 9) for automatically loading internal and external
memory after a reset. The boot mode is defined by four BMODE
input pins dedicated to this purpose. There are two categories of
boot modes: In master boot modes the processor actively loads
data from parallel or serial memories. In slave boot modes the
processor receives data from an external host devices.
Table 9. Booting Modes
BMODE3–0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Idle–no boot
Boot from 8- or 16-bit external flash memory
Boot from 16-bit asynchronous FIFO
Boot from serial SPI memory (EEPROM or flash)
Boot from SPI host device
Boot from serial TWI memory (EEPROM/flash)
Boot from TWI host
Boot from UART host
Reserved
Reserved
Boot from (DDR) SDRAM
Reserved
Reserved
Reserved
Boot from 16-Bit Host DMA
Boot from 8-Bit Host DMA
• Boot from 8- or 16-bit external flash memory
(BMODE=0x1) — In this mode, the boot kernel loads the
first block header from address 0x2000 0000 and—depending on instructions containing in the header—the boot
kernel performs 8-bit or 16-bit boot or starts program execution at the address provided by the header. By default, all
configuration settings are set for the slowest device possible
(3-cycle hold time; 15-cycle R/W access times; 4-cycle
setup).
• Boot from 16-bit asynchronous FIFO (BMODE=0x2) — In
this mode, the boot kernel starts booting from address
0x2030 0000. Every 16-bit word that boot kernel has to read
from the FIFO must be requested by an low pulse on the
DMAR1 pin.
• Boot from serial SPI memory, EEPROM or flash
(BMODE=0x3) — Eight-, 16-, 24- or 32-bit addressable
devices are supported. (internal note: no special support for
DataFlashes, as they understand now also standard SPI
protocol). The processor uses the PE4 GPIO pin to select a
single SPI EEPROM/flash device, submits a read command
and successive address bytes (0x00) until a valid 8-, 16-,
24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SSEL and MISO pins. By default, a
value of 0x85 is written to the SPI_BAUD register.
• Boot from SPI host device (BMODE=0x4) — The processor operates in SPI slave mode (using SPI0) and is
configured to receive the bytes of the.LDR file from an SPI
host (master) agent. In the host, the HWAIT signal must be
interrogated by the host before every transmitted byte. A
pull-up resistor is required on the SPISS input. A pulldown on the serial clock may improve signal quality and
booting robustness.
The boot modes listed in Table 9 provide a number of mechanisms for automatically loading the processor’s internal and
external memories after a reset. By default all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time or
by proper OTP programming at pre-boot time.The BMODE
Rev. PrE |
pins of the reset configuration register, sampled during poweron resets and software-initiated resets, implement the following
modes:
• Boot from serial TWI memory, EEPROM/flash
(BMODE=0x5) — The processor operates in master mode
(using TWI0) and selects the TWI slave with the unique id
0xA0. The processor submits successive read commands to
the memory device starting at two byte internal address
0x0000 and begins clocking data into the processor. The
TWI memory device should comply with Philips I2C Bus
Specification version 2.1 and have the capability to autoincrement its internal address counter such that the contents of the memory device can be read sequentially. By
default, a prescale value of 0xA and CLKDIV value of
0x0811 is used. Unless, altered by OTP settings an I2C
memory that takes two address bytes is assumed. Development tools ensure that data that is booted to memories that
cannot be accessed by the Blackfin core is written to intermediate storage place and then copied to final destination
via Memory DMA.
Page 19 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Port. The host will receive an interrupt from the
HOST_ACK signal every time it is allowed to send the next
FIFO depth (Sixteen 32-bit words) of information. When
the host sends an HIRQ control command, the boot kernel
issues a CALL instruction to address 0xFFA0 0000. It is the
host's responsibility to ensure valid code has been place at
this address. The routine at 0xFFA0 0000 can be a simple
initialization routine to configure internal resources, such
as the SDRAM controller, then returns using an RTS
instruction. The routine may also by the final application
which will never return to the boot kernel.
• Boot from TWI host (BMODE=0x6) — The TWI host
agent selects the slave with the unique id 0x5F. The processor (using TWI0) replies with an acknowledgement and the
host can then download the boot stream. The TWI host
agent should comply with Philips I2C Bus Specification version 2.1. An I2C multiplexer can be used to select one
processor at a time when booting multiple processors from
a single TWI.
• Boot from UART host (BMODE=0x7) — In this mode, the
processor uses UART1 as booting source. Using an autobaud handshake sequence, a boot-stream-formatted
program is downloaded by the host. The host agent selects
a bit rate within the UART’s clocking capabilities.
When performing the autobaud, the UART expects a [email protected]
(0x40) character (eight bits data, one start bit, one stop bit,
no parity bit) on the RXD pin to determine the bit rate. It
then replies with an acknowledgement which is composed
of 4 bytes: 0xBF, the value of UART_DLL, the value of
UART_DLH, 0x00. The host can then download the boot
stream. The processor deasserts the RTS output to hold off
the host; CTS functionality is not enabled at boot time.
• Boot from (DDR) SDRAM (BMODE=0xA) — In this
mode, the boot kernel starts booting from address 0x0000
0010. This is a warm boot scenery only. The SDRAM is
expected to contain a valid boot stream and the SDRAM
controller must have been configured by the OTP settings.
• Boot from 16-Bit Host DMA (BMODE=0xE) — In this
mode, the host DMA port is configured in 16-bit Acknowledge mode, little endian. Unlike in other modes, here the
host is responsible for interpreting the boot stream. It
writes data block per data block into the Host DMA port.
Before configuring the DMA settings for each block, the
host may either poll the ALLOW_CONFIG bit in
HOST_STATUS or wait to be interrupted by the HWAIT
signal. When using HWAIT, the host must still check
ALLOW_CONFIG at least once before beginning to configure the Host DMA Port. After completing the
configuration the host is required to poll the READY bit in
HOST_STATUS before beginning to transfer data. When
the host sends an HIRQ control command, the boot kernel
issues a CALL instruction to 0xFFA0 0000 address. It is the
host's responsibility to ensure valid code has been placed at
this address. The routine at 0xFFA0 0000 can be a simple
initialization routine to configure internal resources, such
as the SDRAM controller, then returns using an RTS
instruction. The routine may also by the final application
which will never return to the boot kernel.
• Boot from 8-Bit Host DMA (BMODE=0xF) — In this
mode, the Host DMA port is configured in 8-bit interrupt
mode, little endian. Unlike in other modes, here the host is
responsible for interpreting the boot stream. It writes data
block per data block into the Host DMA port. Before configuring the DMA settings for each block, the host may
either poll the ALLOW_CONFIG bit in HOST_STATUS
or wait to be interrupted by the HWAIT signal. When
using HWAIT, the host must still check ALLOW_CONFIG
at least once before beginning to configure the Host DMA
Rev. PrE |
For each of the boot modes, a 16-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the address stored in the EVT1 register.
Prior to booting, the pre-boot routine interrogates the OTP
memory. Individual boot modes can be customized or even disabled based on OTP programming. External hardware,
especially booting hosts may watch the HWAIT signal to determine when the pre-boot has finished and the boot kernel starts
the boot process.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
later case. Bits 6-5 in the system reset configuration (SYSCR)
register can be used to bypass pre-boot routine and/or boot kernel in case of a software reset. They can also be used to simulate
a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to configure
the DDR controller or to speed up booting by managing PLL,
clock frequencies, wait states, or serial bit rates.
The boot ROM also features C-callable function entries that can
be called by the user application at run time. This enables second-stage boot or boot management schemes to be
implemented with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor
resources.
Page 20 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
RELATED DOCUMENTS
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
The following publications that describe the ADSP-BF542/4/8/9
processors (and related processors) can be ordered from any
Analog Devices sales office or accessed electronically on our
Website:
• ADSP-BF54x Blackfin Processor Hardware Reference
• ADSP-BF54x Blackfin Processor Peripheral Reference
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• ADSP-BF54x Blackfin Processor Programming Reference
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
• ADSP-BF542 Blackfin Embedded Processor Silicon Anomaly
List (in preparation)
• ADSP-BF544 Blackfin Embedded Processor Silicon Anomaly
List (in preparation)
• ADSP-BF548 Blackfin Embedded Processor Silicon Anomaly
List (in preparation)
• ADSP-BF549 Blackfin Embedded Processor Silicon Anomaly
List
DEVELOPMENT TOOLS
The ADSP-BF542/4/8/9 processor is supported with a complete
set of CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF542/4/8/9 processor.
EZ-KIT Lite® Evaluation Board
For evaluation of ADSP-BF542/4/8/9 processors, use the ADSPBF548 EZ-KIT Lite board available from Analog Devices. Order
part number ADDS-BF548-EZLITE. The board comes with onchip emulation capabilities and is equipped to enable software
development. Multiple daughter cards are available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD (TARGET)
The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG processor. The emulator
uses the TAP to access the internal features of the processor,
allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see Analog Devices JTAG Emulation Technical Reference
(EE-68) on the Analog Devices web site under
www.analog.com/ee-notes. This document is updated regularly
to keep pace with improvements to emulator support.
Rev. PrE |
Page 21 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
PIN DESCRIPTIONS
ADSP-BF542/4/8/9 processor pin multiplexing scheme is listed
in Table 10 and the pin definitions are listed in Table 11.
Table 10. Pin Multiplexing
Primary Pin
First Peripheral
Function
Function
(Number of Pins)
Port A
GPIO (16 pins)
SPORT2 (8 pins)
SPORT3 (8 pins)
Port B
GPIO (15 pins)
Port C
GPIO (16 pins)
Second Peripheral
Function
Third Peripheral
Function
TMR4 (1 pin)
TMR5 (1 pin)
TMR6 (1 pin)
TMR7 (1 pin)
TACI7 (1 shared pin)
TACLK7-0 (8 pins)
Interrupts (16 pins)
TACI2-3 (2 pins)
Interrupts (15 pins)
TWI1 (2 pins)
HWAITA (1 pin)
UART2 or 3 CTL (2 pins)
UART2 (2 pins)
UART3 (2 pins)
SPI2 SEL (4 pins)
TMR0–2 (3 pins)
SPI2 (3 pins)
TMR3 (1 pin)
SPORT0 (8 pins)
Fourth Peripheral
Function
HWAITA (one pin)
Interrupts (8 pins)1
MXVR MMCLK, MBCLK
(2 pins)
SDH (6 pins)
Port D
GPIO (16 pins)
Port E
GPIO (16 pins)
UART0 TX (1 pin)
UART0 RX (1 pin)
UART0 or 1 CTL (2 pins)
EPPI1 CLK,FS (3 pins)
5V-Tolerant inputs TWI0 (2 pins)
Port F
GPIO (16 pins)
EPPI0 D0–15 (16 pins)
Port G
GPIO (16 pins)
Interrupts (8 pins)
EPPI1 D0–15 (16 pins) Host D0–15 (16 pins)
SPI0 (7 pins)
EPPI0 CLK,FS (3 pins)
DATA 16–17 (2 pins)
SPI1 SEL1–3 (3 pins)
SPI1 (4 pins)
CAN0 (2 pins)
CAN1 (2 pins)
Interrupt Capability
Keypad
Row 4–6
Col 4–7 (7 pins)
Keypad R7 (1 pin)
SPORT1 (8 pins)
EPPI0 D18– 23 (6 pins) Interrupts (8 pins)
EPPI2 D0–7 (8 pins)
Keypad
Row 0–3
Col 0–3 (8 pins)
TACI0 (1 pin)
Interrupts (8 pins)
Interrupts (8 pins)
Interrupts (8 pins)
Interrupts (8 pins)
Interrupts (8 pins)
TMRCLK (1 pin)
Interrupts (8 pins)
Host CTL (3 pins)
MXVR MTXON (1 pin)
Rev. PrE |
EPPI2 CLK,FS (3 pins)
TACI4-5 (2 pins)
Page 22 of 68 |
April 2007
CZM (1 pin)
Interrupts (8 pins)
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 10. Pin Multiplexing
Primary Pin
First Peripheral
Function
Function
(Number of Pins)
Port H
GPIO (14 pins)
UART1 (2 pins)
ATAPI_RST (1 pin)
HOST_ADDR (1 pin)
HOST_ACK (1 pin)
Second Peripheral
Function
Third Peripheral
Function
EPPI1–2_FS3 (2 pins)
TMR8 (1 pin)
TMR9 (1 pin)
TMR10 (1 pin)
TACI1 (1 pin)
EPPI0_FS3 (1 pin)
Counter Up/Dir (1 pin)
Counter Down/Gate
(1 pin)
DMAR 0–1 (2 pins)
TACI8-10 (3 shared
pins)
TACLK8-10 (3 shared
pins)
MXVR MRX, MTX,
MRXON (3 pins)
Fourth Peripheral
Function
AMC Addr 4-9 (6 pins)
Port I
GPIO (16 pins)
Interrupt Capability
Interrupts (8 pins)
Interrupts (6 pins)
Async Addr10–25
(16 pins)
Interrupts (8 pins)
Interrupts (8 pins)
Port J
GPIO (14 pins)
1
Async CTL and MISC
Interrupts (8 pins)
Interrupts (6 pins)
A total of 32 interrupts at once are available from Ports C through J, configurable in byte-wide blocks.
ADSP-BF542/4/8/9 processor pin definitions are listed in
Table 11. To see the pin multiplexing scheme, see Table 10.
Table 11. Pin Descriptions
Pin Name
Port A: GPIO/SPORT2–3/TMR4–7
PA0/TFS2
PA1/DT2SEC/TMR4
PA2/DT2PRI
PA3/TSCLK2
PA4/RFS2
PA5/DR2SEC/TMR5
PA6/DR2PRI
PA7/RSCLK2/TACLK0
PA8/TFS3/TACLK1
PA9/DT3SEC/TMR6
PA10/DT3PRI/TACLK2
PA11/TSCLK3/TACLK3
PA12/RFS3/TACLK4
PA13/DR3SEC/TMR7/TACLK5
PA14/DR3PRI/TACLK6
PA15/RSCLK3/TACLK7 and TACI7
I/O1 Function (First/Second/Third/Fourth)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPORT2 Transmit Frame Sync
GPIO/SPORT2 Transmit Data Secondary/Timer 4
GPIO/SPORT2 Transmit Data Primary
GPIO/SPORT2 Transmit Serial Clock
GPIO/SPORT2 Receive Frame Sync
GPIO/SPORT2 Receive Data Secondary/Timer 5
GPIO/SPORT2 Receive Data Primary
GPIO/SPORT2 Receive Serial Clock/Alternate Input Clock 0
GPIO/SPORT3 Transmit Frame Sync/Alternate Input Clock 1
GPIO/SPORT3 Transmit Data Secondary/Timer 6
GPIO/SPORT3 Transmit Data Primary/Alternate Input Clock 2
GPIO/SPORT3 Transmit Serial Clock/Alternate Input Clock 3
GPIO/SPORT3 Receive Frame Sync/Alternate Input Clock 4
GPIO/SPORT3 Receive Data Secondary/Timer 7/Alternate Input Clock 5
GPIO/SPORT3 Receive Data Primary/Alternate Input Clock 6
GPIO/SPORT3 Receive Serial Clock/Alt Input Clock 7 and Alt Capture Input 7
Rev. PrE |
Page 23 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 11. Pin Descriptions (Continued)
Pin Name
Port B: GPIO/TWI1/UART2–3/SPI2/TMR0–3
PB0/SCL1
PB1/SDA1
PB2/UART3RTS
PB3/UART3CTS
PB4/UART2TX
PB5/UART2RX/TACI2
PB6/UART3TX
PB7/UART3RX/TACI3
PB8/SPI2SS/TMR0
PB9/SPI2SEL1/TMR1
PB10/SPI2SEL2/TMR2
PB11/SPI2SEL3/TMR3/ HWAITA3
PB12/SPI2SCK
PB13/SPI2MOSI
PB14/SPIMISO
Port C: GPIO/SPORT0/SD Controller/MXVR (MOST)
PC0/TFS0
PC1/DT0SEC/MMCLK
PC2/DT0PRI
PC3/TSCLK0
PC4/RFS0
PC5/DR0SEC/MBCLK
PC6/DR0PRI
PC7/RSCLK0
PC8/SD_D0
PC9/SD_D1
PC10/SD_D2
PC11/SD_D3
PC12/SD_CLK
PC13/SD_CMD
I/O1 Function (First/Second/Third/Fourth)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/TWI1 Serial Clock
GPIO/TWI1 Serial Data
GPIO/UART3 Request To Send
GPIO/UART3 Clear To Send
GPIO/UART2 Transmit
GPIO/UART2 Receive/Alternate Capture Input 2
GPIO/UART3 Transmit
GPIO/UART3 Receive/Alternate Capture Input 3
GPIO/SPI2 Slave Select Input/Timer 0
GPIO/SPI2 Slave Select Enable 1/Timer 1
GPIO/SPI2 Slave Select Enable 2/Timer 2
GPIO/SPI2 Slave Select Enable 3/Timer 3/Alternate Boot Host Wait
GPIO/SPI2 Clock
GPIO/SPI2 Master Out Slave In
GPIO/SPI2 Master In Slave Out
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPORT0 Transmit Frame Sync
GPIO/SPORT0 Transmit Data Secondary/MXVR Master Clock
GPIO/SPORT0 Transmit Data Primary
GPIO/SPORT0 Transmit Serial Clock
GPIO/SPORT0 Receive Frame Sync
GPIO/SPORT0 Receive Data Secondary/MXVR Bit Clock
GPIO/SPORT0 Receive Data Primary
GPIO/SPORT0 Receive Serial Clock
GPIO/SD Data Bus
GPIO/SD Data Bus
GPIO/SD Data Bus
GPIO/SD Data Bus
GPIO/SD Clock Output
GPIO/SD Command
Rev. PrE |
Page 24 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 11. Pin Descriptions (Continued)
Pin Name
Port D: GPIO/EPPI0–2/SPORT 1/Keypad/Host DMA
PD0/PPI1_D0/HOST_D8/ TFS1/PPI0_D18
PD1/PPI1_D1/HOST_D9/ DT1SEC/PPI0_D19
PD2/PPI1_D2/HOST_D10/ DT1PRI/PPI0_D20
PD3/PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21
PD4/PPI1_D4 / HOST_D12/RFS1/PPI0_D22
PD5/PPI1_D5/HOST_D13/DR1SEC/PPI0_D23
PD6/PPI1_D6/HOST_D14/DR1PRI
PD7/PPI1_D7/HOST_D15/RSCLK1
PD8/PPI1_D8/HOST_D0/ PPI2_D0/KEY_ROW0
PD9/PPI1_D9/HOST_D1/PPI2_D1/KEY_ROW1
PD10/PPI1_D10/HOST_D2/PPI2_D2/KEY_ROW2
PD11/PPI1_D11/HOST_D3/PPI2_D3/KEY_ROW3
PD12/PPI1_D12/HOST_D4/PPI2_D4/KEY_COL0
PD13/PPI1_D13/HOST_D5/PPI2_D5/KEY_COL1
PD14/PPI1_D14/HOST_D6/PPI2_D6/KEY_COL2
PD15/PPI1_D15/HOST_D7/PPI2_D7/KEY_COL3
Port E: GPIO/SPI0/UART0-1/EPPI1/TWI0/Keypad
PE0/SPI0SCK/KEY_COL7
PE1/SPI0MISO /KEY_ROW6
PE2/SPI0MOSI/KEY_COL6
PE3/SPI0SS/KEY_ROW5
PE4/SPI0SEL1/KEY_COL5
PE5/SPI0SEL2/KEY_ROW4
PE6/SPI0SEL3/KEY_COL4
PE7/UART0TX/KEY_ROW7
PE8/UART0RX/TACI0
PE9/UART1RTS
PE10/UART1CTS
PE11/PPI1_CLK
PE12/PPI1_FS1
PE13/PPI1_FS2
PE14/SCL0
PE15/SDA0
I/O1 Function (First/Second/Third/Fourth)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/EPPI1 Data/Host DMA/SPORT 1 Transmit Frame Sync/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Transmit Data Secondary/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Transmit Data Primary/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Transmit Serial Clock/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Receive Frame Sync/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Receive Data Secondary/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Receive Data Primary
GPIO/EPPI1 Data /Host DMA/SPORT 1 Receive Serial Clock
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Row Input
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Row Input
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Row Input
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Row Input
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Column Output
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Column Output
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Column Output
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Column Output
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPI0 Clock/Keypad Column Output
GPIO/SPI0 Master In Slave Out/Keypad Row Input
GPIO/SPI0 Master Out Slave In/Keypad Column Output
GPIO/SPI0 Slave Select Input/Keypad Row Input
GPIO/SPI0 Slave Select Enable 1/Keypad Column Output
GPIO/SPI0 Slave Select Enable 2/Keypad Row Input
GPIO/SPI0 Slave Select Enable 3/Keypad Column Output
GPIO/UART0 Transmit/Keypad Row Input
GPIO/UART0 Receive/Alternate Capture Input 0
GPIO/UART1 Request To Send
GPIO/UART1 Clear To Send
GPIO / EPPI1Clock
GPIO/EPPI1 Frame Sync 1
GPIO/EPPI1 Frame Sync 2
GPIO/TWI0 Serial Clock
GPIO/TWI0 Serial Data
Rev. PrE |
Page 25 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 11. Pin Descriptions (Continued)
Pin Name
I/O1 Function (First/Second/Third/Fourth)
Port F: GPIO / EPPI0 / Alternate ATAPI Data
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
PF0/PPI0_D0/ATAPI_D0A2
PF1/PPI0_D1/ATAPI_D1A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
PF2/PPI0_D2/ATAPI_D2A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
2
PF3/PPI0_D3/ATAPI_D3A
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
PF4/PPI0_D4/ATAPI_D4A2
PF5/PPI0_D5/ATAPI_D5A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
2
PF6/PPI0_D6/ATAPI_D6A
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
PF7/PPI0_D7/ATAPI_D7A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
PF8/PPI0_D8/ATAPI_D8A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
PF9/PPI0_D9/ATAPI_D9A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
2
PF10/PPI0_D10/ATAPI_D10A
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
PF11/PPI0_D11/ATAPI_D11A2
PF12/PPI0_D12/ATAPI_D12A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
2
PF13/PPI0_D13/ATAPI_D13A
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
PF14/PPI0_D14/ATAPI_D14A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
PF15/PPI0_D15/ATAPI_D15A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Data
Port G: GPIO / EPPI0 / SPI1 / EPPI2 / Up-Down Counter / CAN0–1 / Host DMA/ MXVR (MOST)
PG0/PPI0_CLK/TMRCLK
I/O GPIO/EPPI0 Clock/External Timer Reference
PG1/PPI0_FS1
I/O GPIO/EPPI0 Frame Sync 1
2
PG2/PPI0_FS2/ATAPI_A0A
I/O GPIO/EPPI0 Frame Sync 2/Alternate ATAPI Address
PG3/PPI0_D16/ATAPI_A1A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Address
PG4/PPI0_D17/ATAPI_A2A2
I/O GPIO/EPPI0 Data/Alternate ATAPI Address
PG5/SPI1SEL1/HOST_CE/PPI2_FS2/ CZM
I/O GPIO/SPI1 Slave Select/Host DMA Chip Enable/EPPI2 Frame Sync 2/Counter Zero
Marker
PG6/SPI1SEL2/HOST_RD/ PPI2_FS1
I/O GPIO/SPI1 Slave Select/ Host DMA Read/EPPI2 Frame Sync 1
PG7/SPI1SEL3/HOST_WR/ PPI2_CLK
I/O GPIO/SPI1 Slave Select/Host DMA Write/EPPI2 Clock
PG8/SPI1SCK
I/O GPIO/SPI1 Clock
PG9/SPI1MISO
I/O GPIO/SPI1 Master In Slave Out
PG10/SPI1MOSI
I/O GPIO/SPI1 Master Out Slave In
PG11/SPI1SS/MTXON
I/O GPIO/SPI1 Slave Select Input/MXVR Transmit Phy On
PG12/CAN0TX
I/O GPIO/CAN0 Transmit
PG13/CAN0RX/TACI4
I/O GPIO/CAN0 Receive/Alternate Capture Input 4
PG14/CAN1TX
I/O GPIO/CAN1 Transmit
PG15/CAN1RX/TACI5
I/O GPIO/CAN1 Receive/Alternate Capture Input 5
Rev. PrE |
Page 26 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 11. Pin Descriptions (Continued)
Pin Name
I/O1 Function (First/Second/Third/Fourth)
Port H: GPIO/AMC / EXTDMA / UART1 / EPPI0–2 / ATAPI Interface / Up-Down Counter /TMR8-10/ Host DMA / MXVR (MOST)
PH0/UART1TX/PPI1_FS3
I/O GPIO/UART1 Transmit/EPPI1 Frame Sync 3
PH1/UART1RX/PPI2_FS3/TACI1
I/O GPIO/UART 1 Receive/ EPPI2 Frame Sync 3/Alternate Capture Input 1
PH2/ATAPI_RESET/TMR8/PPI0_FS3
I/O GPIO/ATAPI Interface Hard Reset Signal/Timer 8/EPPI0 Frame Sync 3
PH3/HOST_ADDR/TMR9/CDG
I/O GPIO/HOST Address/Timer 9/Count Down and Gate
PH4/HOST_ACK/TMR10/CUD
I/O GPIO/HOST Acknowledge/Timer 10/Count Up and Direction
PH5/MTX/DMAR0/TACI8 and TACLK8
I/O GPIO/MXVR Transmit Data/Ext. DMA Request/Alt Capt. In. 8 /Alt In. Clk 8
PH6/MRX/DMAR1/TACI9 and TACLK9
I/O GPIO/MXVR Receive Data/Ext. DMA Request/Alt Capt. In. 9 /Alt In. Clk 9
PH7/MRXON/TACI10 and TACLK10/HWAIT 3
I/O GPIO/MXVR Receive Phy On /Alt Capt. In. 10 /Alt In. Clk 10/Boot Host Wait
PH8/A4
I/O GPIO/Address Bus for Async Access
PH9/A5
I/O GPIO/Address Bus for Async Access
PH10/A6
I/O GPIO/Address Bus for Async Access
PH11/A7
I/O GPIO/Address Bus for Async Access
PH12/A8
I/O GPIO/Address Bus for Async Access
PH13/A9
I/O GPIO/Address Bus for Async Access
Port I: GPIO / AMC
PI0/A10
I/O GPIO/Address Bus for Async Access
PI1/A11
I/O GPIO/Address Bus for Async Access
PI2/A12
I/O GPIO/Address Bus for Async Access
PI3/A13
I/O GPIO/Address Bus for Async Access
PI4/A14
I/O GPIO/Address Bus for Async Access
PI5/A15
I/O GPIO/Address Bus for Async Access
PI6/A16
I/O GPIO/Address Bus for Async Access
PI7/A17
I/O GPIO/Address Bus for Async Access
PI8/A18
I/O GPIO/Address Bus for Async Access
PI9/A19
I/O GPIO/Address Bus for Async Access
PI10/A20
I/O GPIO/Address Bus for Async Access
PI11/A21
I/O GPIO/Address Bus for Async Access
PI12/A22
I/O GPIO/Address Bus for Async Access
PI13/A23
I/O GPIO/Address Bus for Async Access
PI14/A24
I/O GPIO/Address Bus for Async Access
PI15/A25/NR_CLK
I/O GPIO/Address Bus for Async Access/ NOR clock
Rev. PrE |
Page 27 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 11. Pin Descriptions (Continued)
Pin Name
Port J: GPIO / AMC / ATAPI Controller
PJ0/ARDY/WAIT
PJ1/ND_CE
PJ2/ND_RB
PJ3/ATAPI_DIOR
PJ4/ATAPI_DIOW
PJ5/ATAPI_CS0
PJ6/ATAPI_CS1
PJ7/ATAPI_DMACK
PJ8/ATAPI_DMARQ
PJ9/ATAPI_INTRQ
PJ10/ATAPI_IORDY
PJ11/BR
PJ12/BG
PJ13/BGH
Memory Interface
DA0–12
DBA0–1
DQ0–15
DQS0–1
DQM0–1
DCLK1–2
DCLK1–2
DCS0–1
DCKE
DRAS
DCAS
DWE
DDR_VREF
DDR_VSSR
Asynchronous Memory Interface
A1-3
D0-15/ND_D0-15/ATAPI_D0-15
AMS0–3
ABE0 /ND_CLE
ABE1/ND_ALE
AOE/NR_ADV
ARE
AWE
ATAPI Controller Pins
ATAPI_PDIAG
I/O1 Function (First/Second/Third/Fourth)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/Async Ready/NOR Wait
GPIO/NAND Chip Enable
GPIO/Ready Busy Signal
GPIO/ATAPI Read
GPIO/ATAPI Write
GPIO/ATAPI Chip Select Signal Command Block
GPIO/ATAPI Chip Select Signal
GPIO/ATAPI DMA Acknowledge Signal
GPIO/ATAPI DMA Request Signal
GPIO/Interrupt Request from the Device
GPIO/ATAPI Ready Handshake Signal
GPIO/Bus Request
GPIO/Bus Grant
GPIO/Bus Grant Hang
O
O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
DDR Address Bus
DDR Bank Active Strobe
DDR Data Bus
DDR Data Strobe
DDR Data Mask for Reads and Writes
DDR Output Clock
DDR Complementary Output Clock
DDR Chip Selects
DDR Clock Enable
DDR Row Address Strobe
DDR Column Address Strobe
DDR Write Enable
DDR Voltage Reference
DDR Voltage Reference Shield (connect to GND)
O
I/O
O
O
O
O
O
O
Address Bus for Async and ATAPI Addresses
Data Bus for Async, NAND and ATAPI Accesses
Bank Selects
Byte Enables:Data Masks for Asynchronous Access/NAND Clock Enable
Byte Enables:Data Masks for Asynchronous Access/NAND Address Latch Enable
Output Enable/NOR Address Data Valid
Read Enable/NOR Output Enable
Write Enable
I
Rev. PrE |
Page 28 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 11. Pin Descriptions (Continued)
Pin Name
High Speed USB OTG Pins
USB_DP
USB_DM
USB_XI
USB_XO
USB_ID
USB_VBUS
USB_VREF
USB_RSET
MXVR (MOST) Interface
MFS
MLF_P
MLF_M
MXI
MXO
Mode Control Pins
BMODE0–3
JTAG Port Pins
TDI
TDO
TRST4
TMS
TCK
EMU
Voltage Regulator
VROUT0, VROUT15
Real Time Clock
RTXO
RTXI
Clock (PLL) Pins
CLKIN
CLKOUT
XTAL
CLKBUF
EXT_WAKE
RESET
NMI6
I/O1 Function (First/Second/Third/Fourth)
I/O
I/O
C
C
I
I/O
O
O
USB D+ pin
USB D- pin
Clock XTAL input 1
Clock XTAL input 2
USB ID pin
USB VBUS pin
USB voltage reference source (Test purposes only)
USB resistance set (Test purposes only)
O
A
A
C
C
MXVR Frame Sync
MXVR Loop Filter Plus
MXVR Loop Filter Minus
MXVR Crystal Input
MXVR Crystal Output
I
Boot Mode Strap 0–3
I
O
I
I
I
O
JTAG Serial Data In
JTAG Serial Data Out
JTAG Reset
JTAG Mode Select
JTAG Clock
Emulation Output
O
External FET/BJT Drivers
C
C
RTC Crystal Output
RTC Crystal Input
C
O
C
O
O
I
I
Clock/Crystal Input
Clock Output
Crystal Output
Buffered Oscillator Output
External Wakeup Output
Reset
Non-maskable Interrupt
Rev. PrE |
Page 29 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 11. Pin Descriptions (Continued)
Pin Name
Supplies
VDDINT
VDDEXT
VDDDDR
VDDUSB
VDDRTC
GND
VDDMC
GNDMC
VDDMX
GNDMX
VDDMP
GNDMP
I/O1 Function (First/Second/Third/Fourth)
P
P
P
P
P
G
P
G
P
G
P
G
Internal Power Supply
External Power Supply
External DDR Power Supply
External USB Power Supply
RTC Clock Supply
Ground
MXVR Crystal Power Supply
MXVR Crystal Ground
MXVR I/O Power Supply
MXVR I/O Ground
MXVR PLL Power Supply
MXVR PLL Ground
1
I = Input, O = Output, P =Power, G = Ground, C = Crystal, A = Analog.
By default the ATAPI bus shares the data pins D0-15 and the address pins A0-2 with the asynchronous memory interface and the NAND controller. When PORTF_MUX[1:0]
= b#01, then the ATAPI data bus is available through Port F and the address line can be found at Port G.
3
The Boot Host Wait (HWAIT) signal on PH7 is a GPIO output that is driven and toggled by the boot kernel at boot time. An external pulling resistor is required for proper
operation. A pull-up resistor instructs the HWAIT signal to behave active high (low when ready for data). A pull-down resistor instructs the HWAIT signal to behave active
low (high when ready for data) After boot it can be used for other purposes. If the PH7 pin is required for other purposes (for example, MXVR operation) the Alternate Boot
Host Wait (HWAITA) on PB11 can be used instead. This is enabled by programming a specific bit in OTP memory page 0x15.
4
This pin should be pulled LOW if the JTAG port will not be used.
5
Always connect VROUT0 and VROUT1 together to reduce signal impedance.
6
This pin should always be pulled HIGH when not used.
2
Rev. PrE |
Page 30 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter1
VDDINT
VDDEXT
VDDUSB
VDDMC
VDDMX
VDDMP
VDDRTC
VDDDDR
VIH
VIHCLKIN
VIHDDR
VIH5V
VIL
VIL5V
VILDDR
VREFDDR
TJ
TJ
Minimum
Nominal
Maximum
Internal Supply Voltage
0.9
TBD2
TBD2
Internal Supply Voltage for Automotive Grade
1.0
TBD2
TBD2
3
External Supply Voltage
2.25
2.5 or 3.3
3.6
External Supply Voltage for Automotive Grade
2.7
3.3
3.6
USB External Supply Voltage
2.7
3.3
3.6
MXVR Crystal Supply Voltage
2.7
3.3
3.6
MXVR I/O Supply Voltage
3.0
3.3
3.6
2
MXVR PLL Supply Voltage
1.0
TBD
TBD2
Real Time Clock Power Supply Voltage
2.25
2.5 or 3.3
3.6
Real Time Clock Power Supply Voltage for Automotive Grade
2.7
3.3
3.6
DDR Memory Supply Voltage
2.3
2.5
2.7
DDR Memory Supply Voltage for Mobile DDR
1.7
1.8
1.9
High Level Input Voltage3,4, @ VDDEXT =maximum
2.0
3.6
High Level Input Voltage5, @ VDDEXT =maximum
2.2
3.6
6
High Level Input Voltage
VREFDDR + 0.15
VDDDDR + 0.3
High Level Input Voltage for Mobile DDR6
0.8 x VDDDDR
VDDDDR + 0.3
High Level Input Voltage7, @ VDDEXT =maximum
2.0
5.5
3, 8
Low Level Input Voltage , @ VDDEXT =minimum
–0.3
0.6
Low Level Input Voltage9, @ VDDEXT =minimum
–0.3
0.8
Low Level Input Voltage6
–0.3
VREFDDR - 0.15
Low Level Input Voltage for Mobile DDR6
-0.3
0.2 x VDDDDR
DDR VREF Pin Input Voltage
0.49 x VDDDDR 0.50 x VDDDDR 0.51 x VDDDDR
–40
+105
Junction Temperature, 400-Ball Chip Scale Ball Grid Array (mini-BGA)
@TAMBIENT = –40ºC to +85ºC
Junction Temperature, 400-Ball Chip Scale Ball Grid Array (mini-BGA)
0
+90
@TAMBIENT = 0ºC to +70ºC
1
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ºC
ºC
Specifications subject to change without notice.
It is recommended that preliminary designs be designed with an adjustable voltage regulator which supports 0.8 V to 1.4 V nominal.
3
The ADSP-BF542/4/8/9 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because
VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bi-directional pins (D15–0, PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0,
PG15–0, PH13–0, PI15–0, PJ14–0) and input only pins (ATAPI_PDIAG, USB_ID, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0).
4
Parameter value applies to all input and bi-directional pins, except CLKIN, PB0, PB1, PE14, PE15, PG15–11, PH6, PH7, and the pins listed in table note 6 of the Operating
Conditions table.
5
Parameter value applies to CLKIN pin only.
6
Parameter value applies to DA0–12, DBA0–1, DQ0–15, DQS0–1, DQM0–1, DCLK1–2, DCLK1–2, DCS0–1, DCKE, DRAS, DCAS, and DWE pins only.
7
Certain ADSP-BF542/4/8/9 processor pins are 5.0 V tolerant (accept up to 5.5 V maximum VIH when power is applied to VDDEXT pins). Voltage compliance on outputs (VOH)
depends on the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). The 5.0 V tolerance feature applies to PB0, PB1, PE14, PE15, PG15–11,
PH6, and PH7 pins only. The 5.0 V tolerance exists only when power is applied to the VDDEXT pins. The PB0, PB1, PE14, and PE15 pins are open drain (regardless of pin
functionality) and therefore require a pullup resistor. Consult the I2C specification version 2.1 for the proper resistor value and other open drain pin electrical parameters.
8
Parameter value applies to all input and bi-directional pins, except PB0, PB1, PE14, PE15, PG15–11, PH6, and PH7.
9
Parameter value applies to the following pins only: PB0, PB1, PE14, PE15, PG15–11, PH6, and PH7.
2
Rev. PrE |
Page 31 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS
Parameter
VOH
High Level Output Voltage1
VOHDDR
High Level Output Voltage2
High Level Output Voltage2
Low Level Output Voltage1
VOL
VOLDDR
Low Level Output Voltage2
Low Level Output Voltage2
IIH
High Level Input Current3
IIHP
High Level Input Current JTAG4
5
IIL
Low Level Input Current3
5
Low Level Input Current JTAG4
IILP
IOZH
Three-State Leakage Current6
5
IOZL
Three-State Leakage Current6
CIN
Input Capacitance7
IDDHIBERNATE
TBD
IDDDEEPSLEEP
TBD
TBD
IDDSLEEP
IDDTYP
TBD
IDDRTC
TBD
Test Conditions
@ VDDEXT = Minimum, IOH = –0.5 mA
@ VDDDDR = 2.3V, IOH = -8.1 mA
@ VDDDDR = 1.7V, IOH = -8.1 mA
@ VDDEXT = Minimum, IOL = 2.0 mA
@ VDDDDR = 2.3V, IOH = 8.1 mA
@ VDDDDR = 1.7V, IOH = 8.1 mA
@ VDDEXT = Maximum, VIN = VIH Maximum
@ VDDEXT = Maximum, VIN = VIH Maximum
@ VDDEXT = Maximum, VIN = 0 V
@ VDDEXT = Maximum, VIN = 0 V
@ VDDEXT = Maximum, VIN = VIH Maximum
@ VDDEXT = Maximum, VIN = 0 V
fIN = TBD MHz, TAMBIENT = TBD°C, VIN = TBD V
TBD
TBD
TBD
TBD
TBD
1
Applies to output and bidirectional pins, except the pins listed in table note 6 of the Operating Conditions table.
Applies to output and bidirectional pins listed in table note 6 of the Operating Conditions table.
3
Applies to input pins except JTAG inputs.
4
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
5
Absolute value.
6
Applies to three-statable pins.
7
Guaranteed, but not tested.
2
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary circuitry, damage may occur
on devices subjected to high energy ESD. Therefore,
proper ESD precautions should be take to avoid
performance degradation or loss of functionality.
Rev. PrE |
Page 32 of 68 |
April 2007
Min
2.4
1.74
TBD
Typical
47
TBD
TBD
TBD
TBD
TBD
Max
0.4
0.56
TBD
10.0
50.0
10.0
TBD
10.0
10.0
87
Unit
V
V
V
V
V
V
μA
μA
μA
μA
μA
μA
pF
μA
mA
mA
mA
μA
ADSP-BF542/4/8/9
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage1 (VDDINT)
External (I/O) Supply Voltage1 (VDDEXT)
Input Voltage1,2
Output Voltage Swing1
Load Capacitance1
Storage Temperature Range1
Junction Temperature Underbias1
–0.3 V to +1.4 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to VDDEXT +0.5 V
200 pF
–65ºC to +150ºC
+125ºC
1
Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Applies to all bidirectional and input only pins except PB0, PB1, PE14, PE15,
PG15–11, PH6, and PH7. Absolute maximum input voltage range on pins PB0,
PB1, PE14, PE15, PG15–11, PH6, and PH7 is –0.5 V to +5.5 V.
Table 12. Maximum Duty Cycle for Input1 Transient Voltage
VIN Max (V)
3.63
3.80
3.90
4.00
4.10
4.20
4.30
1
VIN Min (V)
–0.33
–0.50
–0.60
–0.70
–0.80
–0.90
–1.00
Maximum Duty Cycle
100%
48%
30%
20%
10%
8%
5%
Applies to all signal pins with the exception of CLKIN.
PACKAGE INFORMATION
The information presented in Figure 8 and Table 13 provides
information about how to read the package brand and relate it
to specific product features. For a complete listing of product
offerings, see the Ordering Guide on Page 67.
a
ADSP-BF54x
tppZ-cc
vvvvvv.x n.n
yyww country_of_origin
Table 13. Package Information
Brand Key
t
pp
Z
cc
vvvvvv.x
n.n
yyww
B
Figure 8. Product Information on Package
Rev. PrE |
Page 33 of 68 |
April 2007
Description
Temperature Range
Package Type
RoHS Compliant part
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
ADSP-BF542/4/8/9
Preliminary Technical Data
TIMING SPECIFICATIONS
Table 14, Table 15, Table 16, and Table 17 describe the timing
requirements for the ADSP-BF542/4/8/9 processor clocks. Take
care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock. Table 18
describes phase-locked loop operating conditions. Table 19 and
Figure 9 describe Clock Input and Reset Timing. Table 20
describes Clock Out Timing.
Clock Signals
Table 14. System Clock Requirements
Parameter
fSCLK
fSCLK
fSCLK
fSCLK
tSCLKH
tSCLKL
Condition
VDDEXT = 3.3 V, VDDINT ≥ TBD
VDDEXT = 3.3 V, VDDINT < TBD
VDDEXT = 2.5 V, VDDINT ≥ TBD
VDDEXT = 2.5 V, VDDINT < TBD
CLKOUT Width High
CLKOUT Width Low
Minimum
Maximum
133
100
133
100
Unit
MHz
MHz
MHz
MHz
ns
ns
Maximum
600
TBD
TBD
TBD
TBD
Unit
MHz
MHz
MHz
MHz
MHz
2.5
2.5
Table 15. Core Clock Requirements—600 MHz Speed Grade1
Parameter
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
1
Minimum
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =1.045 V minimum)
Core Clock Frequency (VDDINT =0.95 V minimum)
Core Clock Frequency (VDDINT =0.85 V minimum)
Core Clock Frequency (VDDINT =0.8 V )
The speed grade of a given part may be seen on the Ordering Guide on Page 67. It stands for the maximum allowed CCLK frequency at VDDINT = minimum and the maximum
allowed VCO frequency at any supply voltage.
Table 16. Core Clock Requirements—533 MHz Speed Grade1
Parameter
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
1
Minimum
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =1.045 V minimum)
Core Clock Frequency (VDDINT =0.95 V minimum)
Core Clock Frequency (VDDINT =0.85 V minimum)
Core Clock Frequency (VDDINT =0.8 V )
Maximum
533
TBD
TBD
TBD
TBD
Unit
MHz
MHz
MHz
MHz
MHz
The speed grade of a given part may be seen on the Ordering Guide on Page 67. It stands for the maximum allowed CCLK frequency at VDDINT = minimum and the maximum
allowed VCO frequency at any supply voltage.
Table 17. Core Clock Requirements—400 MHz Speed Grade1
Parameter
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
1
Minimum
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =1.045 V minimum)
Core Clock Frequency (VDDINT = 0.95 V minimum)
Core Clock Frequency (VDDINT =0.85 V minimum)
Core Clock Frequency (VDDINT =0.8 V )
Maximum
400
TBD
TBD
TBD
TBD
Unit
MHz
MHz
MHz
MHz
MHz
The speed grade of a given part may be seen on the Ordering Guide on Page 67. It stands for the maximum allowed CCLK frequency at VDDINT = minimum and the maximum
allowed VCO frequency at any supply voltage.
Rev. PrE |
Page 34 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 18. Phase-Locked Loop Operating Conditions
Parameter
fVCO
1
Minimum
50
Voltage Controlled Oscillator (VCO) Frequency
Maximum
Unit
1
Speed Grade MHz
The speed grade of a given part may be seen on the “Ordering Guide” on page 67. It stands for the Maximum allowed CCLK frequency at VDDINT = minimum and the maximum
allowed VCO frequency at any supply voltage.
Table 19. Clock Input and Reset Timing
Parameter
Timing Requirements
tCKIN
CLKIN Period1,2,3,4
tCKINL
CLKIN Low Pulse2
CLKIN High Pulse2
tCKINH
tBUFDLAY
CLKIN to CLKBUF Delay
tWRST
RESET Asserted Pulsewidth Low5
Minimum
Maximum
Unit
20.0
8.0
8.0
100.0
ns
ns
ns
ns
ns
10
11 tCKIN
1
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in the previous Clock tables.
Applies to PLL bypass mode and PLL nonbypass mode.
3
CLKIN frequency and duty cycle must not change on the fly.
4
If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5
Applies after power-up sequence is complete. At power-up, the processor’s internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
2
tCKIN
CLKIN
tCKINL
tCKINH
tBUFDLAY
tBUFDLAY
CLKBUF
tWRST
RESET
Figure 9. Clock and Reset Timing
Table 20. Clock Out Timing
Parameter
Switching Characteristics
tSCLK
CLKOUT Period1
CLKOUT Width High
tSCLKH
tSCLKL
CLKOUT Width Low
1
Min
TBD
TBD
TBD
The tSCLK value is the inverse of the fSCLK specification. Package type and reduced supply voltages affect the best-case value of 7.5 ns listed here.
tSCLK
t SCLKH
CLKOUT
t SCLKL
Figure 10. SDRAM Interface Timing
Rev. PrE |
Page 35 of 68 |
April 2007
Max
Unit
ns
ns
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
Asynchronous Memory Read Cycle Timing
Table 21 and Table 22 on Page 37 and Figure 11 and Figure 12
on Page 37 describe asynchronous memory read cycle operations for synchronous and for asynchronous ARDY.
Table 21. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
2.1
ns
tHDAT
DATA15–0 Hold After CLKOUT
0.8
ns
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
4.0
ns
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
0.0
ns
tDO
Output Delay After CLKOUT1
tHO
1
Output Hold After CLKOUT
6.0
1
0.8
ns
ns
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
HOLD
1 CYCLE
ACCESS EXTENDED
3 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHARDY
tSARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Rev. PrE |
Page 36 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 22. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
2.1
tHDAT
DATA15–0 Hold After CLKOUT
0.8
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
tDO
Output Delay After CLKOUT2
tHO
Output Hold After CLKOUT2
ns
ns
(S+RA–2)*tSCLK ns
0.0
ns
6.0
0.8
ns
1
S = number of programmed setup cycles, RA = number of programmed read access cycles.
2
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
HOLD
1 CYCLE
ACCESS EXTENDED
CLKOUT
tDO
tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHAA
tDANR
ARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 12. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Rev. PrE |
Page 37 of 68 |
April 2007
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
Asynchronous Memory Write Cycle Timing
Table 23 and Table 24 on Page 39 and Figure 13 and Figure 14
on Page 39 describe asynchronous memory write cycle operations for synchronous and for asynchronous ARDY.
Table 23. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
4.0
ns
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
0.0
ns
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
1.0
1
tDO
Output Delay After CLKOUT
tHO
Output Hold After CLKOUT1
1
6.0
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
ACCESS
EXTENDED
1 CYCLE
PROGRAMMED WRITE
ACCESS 2 CYCLES
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
t SARDY
ARDY
t SARDY
t ENDAT
DATA15–0
ns
6.0
0.8
t HARD Y
t HARDY
t DDAT
WRITE DATA
Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Rev. PrE |
Page 38 of 68 |
April 2007
ns
ns
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 24. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
(S+WA–2)*tSCLK ns
0.0
ns
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT
tHO
Output Hold After CLKOUT2
1
2
6.0
1.0
2
S = number of programmed setup cycles, WA = number of programmed write access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
tDANW
tHAA
ARDY
t ENDAT
DATA15–0
ns
6.0
0.8
WRITE DATA
Figure 14. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Rev. PrE |
Page 39 of 68 |
April 2007
ns
ns
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
Synchronous Memory DDR Read Cycle Timing
Table 25. Synchronous Memory DDR Read Cycle Timing
Parameter
Timing Requirements
TBD
TBD
Switching Characteristic
TBD
TBD
Minimum
Maximum
TBD
M
nous
o
r
h
Sync
Unit
ns
TBD
ns
Maximum
Unit
D
is TB
g
n
i
m
e Ti
Cycl
d
a
e
DR R
D
y
r
emo
Figure 15. Synchronous Memory DDR Read Cycle Timing
Synchronous Memory DDR Write Cycle Timing
Table 26. Synchronous Memory DDR Write Cycle Timing
Parameter
Timing Requirements
TBD
TBD
Switching Characteristic
TBD
TBD
Minimum
TBD
ns
TBD
us M
rono
h
c
n
Sy
em
Cycle
e
t
i
r
DR W
ory D
g is
Timin
Figure 16. Synchronous Memory DDR Write Cycle Timing
Rev. PrE |
Page 40 of 68 |
April 2007
TBD
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
Synchronous Memory Mobile DDR Read Cycle Timing
Table 27. Synchronous Memory DDR Read Cycle Timing
Parameter
Timing Requirements
TBD
TBD
Switching Characteristic
TBD
TBD
Minimum
Maximum
TBD
D
obile
M
y
or
Mem
s
u
o
hron
Sync
yc
ad C
e
R
DR
ing
le Tim
Unit
ns
TBD
ns
Maximum
Unit
D
is TB
Figure 17. Synchronous Memory DDR Read Cycle Timing
Synchronous Memory Mobile DDR Write Cycle Timing
Table 28. Synchronous Memory DDR Write Cycle Timing
Parameter
Timing Requirements
TBD
TBD
Switching Characteristic
TBD
TBD
Minimum
TBD
ns
TBD
o
ory M
m
e
M
nous
o
r
h
c
Syn
ycle
rite C
W
DR
bile D
g is T
Timin
Figure 18. Synchronous Memory DDR Write Cycle Timing
Rev. PrE |
Page 41 of 68 |
April 2007
BD
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
External Port Bus Request and Grant Cycle Timing
Table 29 and Table 30 on Page 43 and Figure 19 and Figure 20
on Page 43 describe external port bus request and grant cycle
operations for synchronous and for asynchronous BR.
Table 29. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tBS
BR Setup to Falling Edge of CLKOUT
4.0
ns
tBH
Falling Edge of CLKOUT to BR Deasserted Hold Time
0.0
ns
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
4.5
ns
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
4.5
ns
tDBG
CLKOUT High to BG High Setup
3.6
ns
tEBG
CLKOUT High to BG Deasserted Hold Time
3.6
ns
tDBH
CLKOUT High to BGH High Setup
3.6
ns
tEBH
CLKOUT High to BGH Deasserted Hold Time
3.6
ns
CLKOUT
tBH
tBS
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 19. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Rev. PrE |
Page 42 of 68 |
April 2007
tEBH
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 30. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tWBR
BR Pulsewidth
2 x tSCLK
ns
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
4.5
ns
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
4.5
ns
tDBG
CLKOUT High to BG High Setup
3.6
ns
tEBG
CLKOUT High to BG Deasserted Hold Time
3.6
ns
tDBH
CLKOUT High to BGH High Setup
3.6
ns
tEBH
CLKOUT High to BGH Deasserted Hold Time
3.6
ns
CLKOUT
tWBR
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 20. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Rev. PrE |
Page 43 of 68 |
April 2007
tEBH
ADSP-BF542/4/8/9
Preliminary Technical Data
Enhanced Parallel Peripheral Interface Timing
Table 31 and Figure 21 on Page 44 describes Enhanced Parallel
Peripheral Interface operations.
Table 31. Enhanced Parallel Peripheral Interface Timing
Parameter
Timing Requirements
tPCLKW
EPPI_CLK Width
tPCLK
EPPI_CLK Period
Timing Requirements - GP Input and Frame Capture Modes
tSFSPE
External Frame Sync Setup Before EPPI_CLK
External Frame Sync Hold After EPPI_CLK
tHFSPE
tSDRPE
Receive Data Setup Before EPPI_CLK
tHDRPE
Receive Data Hold After EPPI_CLK
Switching Characteristics - GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After EPPI_CLK
tHOFSPE
Internal Frame Sync Hold After EPPI_CLK
Transmit Data Delay After EPPI_CLK
tDDTPE
tHDTPE
Transmit Data Hold After EPPI_CLK
h
Perip
l
e
l
l
a
ar
ced P
n
a
h
En
Minimum
ns
ns
TBD
TBD
TBD
TBD
ns
ns
ns
ns
TBD
TBD
TBD
era
is
iming
T
e
rfac
l Inte
Page 44 of 68 |
April 2007
Unit
TBD
TBD
TBD
Figure 21. Enhanced Parallel Peripheral Interface Timing
Rev. PrE |
Maximum
TBD
ns
ns
ns
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
Serial Ports Timing
Table 32 through Table 35 on Page 46 and Figure 22 on Page 46
through Figure 24 on Page 48 describe Serial Port operations.
Table 32. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1
tHFSE
TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)
tSDRE
Receive Data Setup Before RSCLK1
1
1
3.0
ns
3.0
ns
3.0
ns
tHDRE
Receive Data Hold After RSCLK
3.0
ns
tSCLKEW
TSCLK/RSCLK Width
4.5
ns
tSCLKE
TSCLK/RSCLK Period
15.0
ns
Switching Characteristics
tDFSE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tHOFSE
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tDDTE
Transmit Data Delay After TSCLK
2
tHDTE
Transmit Data Hold After TSCLK2
1
2
10.0
0.0
ns
ns
10.0
0.0
ns
ns
Referenced to sample edge.
Referenced to drive edge.
Table 33. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1
8.0
ns
tHFSI
TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)1
–1.5
ns
tSDRI
Receive Data Setup Before RSCLK1
8.0
ns
tHDRI
Receive Data Hold After RSCLK1
–1.5
ns
tSCLKEW
TSCLK/RSCLK Width
4.5
ns
tSCLKE
TSCLK/RSCLK Period
15.0
ns
Switching Characteristics
tDFSI
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tHOFSI
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
tDDTI
Transmit Data Delay After TSCLK2
tHDTI
Transmit Data Hold After TSCLK
tSCLKIW
TSCLK/RSCLK Width
1
2
2
3.0
–1.0
ns
3.0
2
ns
ns
–2.0
ns
4.5
ns
Referenced to sample edge.
Referenced to drive edge.
Table 34. Serial Ports—Enable and Three-State
Parameter
Min
Max
Unit
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLK1
tDDTTE
Data Disable Delay from External TSCLK
tDTENI
Data Enable Delay from Internal TSCLK1
tDDTTI
Data Disable Delay from Internal TSCLK1
1
0
1
10.0
–2.0
Page 45 of 68 |
April 2007
ns
ns
3.0
Referenced to drive edge.
Rev. PrE |
ns
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 35. External Late Frame Sync
Parameter
Min
Max
Unit
10.0
ns
Switching Characteristics
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2
tDDTLFSE
Data Enable from late FS or MCE = 1, MFD = 0
tDTENLFS
1, 2
0
ns
1
MCE = 1, TFS enable and TFS valid follow tDTENLFS and tDDTLFSE.
2
If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
DATA RECEIVE- INTERNAL CLOCK
DATA RECEIVE- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLK
RSCLK
tDFSE
tDFSE
tHOFSE
tSFSI
tHFSI
tHOFSE
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT- INTERNAL CLOCK
DATA TRANSMIT- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
TSCLK
TSCLK
tDFSI
tHOFSI
tDFSE
tSFSI
tHFSI
tHOFSE
TFS
tSFSE
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TSCLK (EXT)
TFS ("LATE", EXT.)
TSCLK / RSCLK
tDDTTE
tDTENE
DT
DRIVE
EDGE
DRIVE
EDGE
TSCLK (INT)
TFS ("LATE", INT.)
TSCLK / RSCLK
tDTENI
tDDTTI
DT
Figure 22. Serial Ports
Rev. PrE |
Page 46 of 68 |
April 2007
tHFSE
ADSP-BF542/4/8/9
Preliminary Technical Data
EXTERNAL RFS WITHMCE =1, MFD= 0 (INTERNAL OREXTERNAL CLOCK)
DRIVE
SAMPLE
DRIVE
RSCLK
tHOFSE/I
tSFSE/I
RFS
tDDTE/I
tDTENLFS
tHDTE/I
1ST BIT
DT
2NDBIT
tDDTLFSE
LATEEXTERNAL TFS (INTERNAL OREXTERNAL CLOCK)
DRIVE
SAMPLE
DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I
TDTENLFS
DT
tHDTE/I
1ST BIT
2NDBIT
tDDTLFSE
Figure 23. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. PrE |
Page 47 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
tSFSE/I
tHOFSE/I
RFS
tDDTE/I
tHDTE/I
tDTENLSCK
DT
1ST BIT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I
tDTENLSCK
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLSCK
Figure 24. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. PrE |
Page 48 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Master Timing
Table 36 and Figure 25 describe SPI port master operations.
Table 36. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data input valid to SCK edge (data input setup)
tHSPIDM
SCK sampling edge to data input invalid
Switching Characteristics
tSDSCIM
SPISELx low to first SCK edge (x=0 or 1)
tSPICHM
Serial clock high period
tSPICLM
Serial clock low period
tSPICLK
Serial clock period
tHDSM
Last SCK edge to SPISELx high (x=0 or 1)
Sequential transfer delay
tSPITDM
tDDSPIDM
SCK edge to data out valid (data out delay)
tHDSPIDM
SCK edge to data out invalid (data out hold)
Minimum
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
MOSI
(OUTPUT)
tHDSPIDM
MSB
CPHA=1
tSSPIDM
MISO
(INPUT)
LSB
tHSPIDM
tSSPIDM
MSB VALID
LSB VALID
tDDSPIDM
MOSI
(OUTPUT)
CPHA=0
MISO
(INPUT)
tHSPIDM
tHDSPIDM
MSB
tSSPIDM
LSB
tHSPIDM
MSB VALID
LSB VALID
Figure 25. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrE |
Page 49 of 68 |
April 2007
Unit
7.5
–1.5
ns
ns
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
–1.0
ns
ns
ns
ns
ns
ns
ns
ns
SPISELx
(OUTPUT)
tSDSCIM
Maximum
tSPITDM
6
4.0
ADSP-BF542/4/8/9
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 37 and Figure 26 describe SPI port slave operations.
Table 37. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial clock high period
tSPICLS
Serial clock low period
Serial clock period
tSPICLK
tHDS
Last SCK edge to SPISS not asserted
tSPITDS
Sequential Transfer Delay
tSDSCI
SPISS assertion to first SCK edge
tSSPID
Data input valid to SCK edge (data input setup)
tHSPID
SCK sampling edge to data input invalid
Switching Characteristics
tDSOE
SPISS assertion to data out active
tDSDHI
SPISS deassertion to data high impedance
tDDSPID
SCK edge to data out valid (data out delay)
tHDSPID
SCK edge to data out invalid (data out hold)
Minimum
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
1.6
0
0
0
0
tSPICLS
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MISO
(OUTPUT)
tSSPID
MOSI
(INPUT)
LSB
tHSPID
tSSPID
tHSPID
MSB VALID
tDSOE
LSB VALID
tDDSPID
tDSDHI
MSB
LSB
tHSPID
CPHA=0
MOSI
(INPUT)
tDSDHI
MSB
CPHA=1
MISO
(OUTPUT)
tDDSPID
tSSPID
MSB VALID
LSB VALID
Figure 26. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrE |
Page 50 of 68 |
April 2007
Unit
ns
ns
ns
ns
ns
ns
ns
ns
8
8
10
10
SPISS
(INPUT)
tSPICHS
Maximum
ns
ns
ns
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
Figure 27 describes the UART ports receive and transmit operations. The maximum baud rate is SCLK/16. There is some
latency between the generation of internal UART interrupts
and the external data operations. These latencies are negligible
at the data transmission rates for the UART.
CLKOUT
(SAMPLE CLOCK)
UARTx Rx
DATA(5–8)
STOP
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
UARTx Tx
DATA(5–8)
STOP (1–2)
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 27. UART Ports—Receive and Transmit Timing
General-Purpose Port Timing
Table 38 and Figure 28 describe general-purpose
port operations.
Table 38. General-Purpose Port Timing
Parameter
Timing Requirement
General-Purpose Port Pin Input Pulse Width
tWFI
Switching Characteristic
tGPOD
General-Purpose Port Pin Output Delay from CLKOUT Low
Minimum
tSCLK + 1
0
CLKOUT
tGPOD
GPP OUTPUT
tWFI
GPP INPUT
Figure 28. General-Purpose Port Timing
Rev. PrE |
Page 51 of 68 |
Maximum
April 2007
Unit
ns
6
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
Timer Cycle Timing
Table 39 and Figure 29 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz.
Table 39. Timer Cycle Timing
Parameter
Timing Characteristics
tWL
Timer Pulse Width Input Low (Measured In SCLK Cycles)1
tWH
Timer Pulse Width Input High (Measured In SCLK Cycles)1
Timer Input Setup Time Before CLKOUT Low2
tTIS
tTIH
Timer Input Hold Time After CLKOUT Low2
Switching Characteristic
tHTO
Timer Pulse Width Output (Measured In SCLK Cycles)
tTOD
Timer Output Update Delay After CLKOUT High
1
2
Minimum
1tSCLK
1tSCLK
5
–2
1tSCLK
The minimum pulse widths apply for TMRx signals in width capture and external clock modes.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize timer flag inputs.
CLK OUT
t TOD
TIMER OUTPUT
t HTO
tTIS
t TIH
TIMER INPUT
tWH, tWL
Figure 29. Timer Cycle Timing
Rev. PrE |
Page 52 of 68 |
Maximum
April 2007
Unit
ns
ns
ns
ns
(232–1)tSCLK
6
ns
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
ATA/ATAPI Controller Timing
Table 40. ATA/ATAPI Controller Timing
Parameter
Timing Requirements
TBD
TBD
Switching Characteristic
TBD
TBD
Minimum
Maximum
TBD
ll
ontro
C
I
ATAP
A TA /
Unit
ns
TBD
ns
Maximum
Unit
D
is TB
g
n
i
m
er Ti
Figure 30. ATA/ATAPI Controller Timing
Up/Down Counter/Rotary Encoder Timing
Table 41. Up/Down Counter/Rotary Encoder Timing
Parameter
Timing Requirements
tWCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width
Switching Characteristic
tCIS
Counter Input Setup Time Before CLKOUT Low1
tCIH
Counter Input Hold Time After CLKOUT Low1
1
Minimum
tSCLK + 1
TBD
TBS
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
CLK OUT
tCIS
tCIH
CUD/CDG/CZM
tWCOUNT
Figure 31. Up/Down Counter/Rotary Encoder Timing
Rev. PrE |
Page 53 of 68 |
April 2007
ns
TBD
TBD
ns
ns
ADSP-BF542/4/8/9
Preliminary Technical Data
SD/SDIO Controller Timing
Table 42. SD/SDIO Controller Timing
Parameter
Timing Requirements
TBD
TBD
Switching Characteristic
TBD
TBD
Minimum
Maximum
TBD
ns
TBD
DI
SD/S
OC
is
iming
T
r
e
ll
ontro
Unit
ns
TBD
Figure 32. SD/SDIO Controller Timing
MXVR Timing
Table 43 and Table 44 describe the MXVR timing requirements.
Table 43. MXVR Timing—MXI Center Frequency Requirements
Parameter
fMXI_256
fMXI_384
fMXI_512
fMXI_1024
Fs = 38 KHz
9.728
14.592
19.456
38.912
MXI Center Frequency (256Fs)
MXI Center Frequency (384Fs)
MXI Center Frequency (512Fs)
MXI Center Frequency (1024Fs)
Fs = 44.1 KHz
11.2896
16.9344
22.5792
45.1584
Fs = 48 KHz
12.288
18.432
24.576
49.152
Unit
MHz
MHz
MHz
MHz
Table 44. MXVR Timing— MXI Clock Requirements
Parameter
Timing Requirements
FSMXI
MXI Clock Frequency Stability
FTMXI
MXI Frequency Tolerance Over Temperature
DCMXI
MXI Clock Duty Cycle
Rev. PrE |
Page 54 of 68 |
April 2007
Min
Max
Unit
–50
–300
40
+50
+300
60
ppm
ppm
%
ADSP-BF542/4/8/9
Preliminary Technical Data
HDMA A/C Timing- Host Read Cycle
Table 45 describe the HDMA A/C Host Read Cycle timing
requirements.
Table 45. Host Read Cycle Timing Requirements
Parameter
Description
Timing Requirements
tSADRDL
HADDR and HCE Setup before HRD assertion
tHADRDH
HADDR and HCE Hold after HRD assertion
tRDWL
HRD pulse width low
Value
1.5 * tsclk ns Min
2.5 ns Min
tDRDYRDL + tRDYPRD + tDRDHRDY ns Min (ACK mode)
1.5 * tsclk + 8.7 ns Min (INT mode)
2 * tsclk ns Min
TBD ns Min
HRD pulse width high
tRDWH
tDRDHRDY
HRD de-assertion delay after HRDY de-assertion
Switching Characteristics
tSDATRDY
Data valid after HRDY assertion
tDRDYRDL
HRDY assertion delay after hrd assertion
tRDYPRD
HRDY low pulse-width for Read access
tHDARWH
1 * tsclk ns Max
1.5 * tsclk + 8.7 ns
Data Delay (based on when the FIFO is empty - used
for cycle extension
1.0 ns
Data disable after HRD de-assertion
HOST_ADDR
HOST_CE
tHADRDH
tSADRDL
tRDWH
tRDWL
HOST_RD
tDRDYRDL
tRDYPRD
tDRDHRDY
ACK
tHDARWH
tSDATRDY
HOST_D15-0
Figure 33. HDMA A/C- Host Read Cycle
Rev. PrE |
Page 55 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
HDMA A/C Timing- Host Write Cycle
Table 46 describes the HDMA A/C Host Write Cycle timing
requirements.
Table 46. Host Write Cycle Timing Requirements
Parameter
Description
Timing Requirements
tSADWRH
HADDR/HCE Setup before HRD assertion
tHADWRH
HADDR/HCE Hold after HRD assertion
tWRWL
HWR pulse width low
Value
1.5 * tsclk + 10.8 ns Min
2.5 ns Min
tDRDYRDL + tRDYPRD + tDRDHRDY Min (ACK mode)
1.5 * tsclk + 8.7 ns Min (INT mode)
2 * tsclk ns
TBD ns Min
2.5 ns Min
2.5 ns Min
HWR pulse width high
tWRWH
tDWRHRDY
HWR de-assertion delay after HRDY de-assertion
tHDATWH
Data Hold after HWR de-assertion
tSDATWH
Data Setup valid after before HWR de-assertion
Switching Characteristics
tDRDYWRL
HRDY low delay after HWR/HCE assertion
HRDY low pulse-width for Write access
tRDYPWR
1.5 * tsclk + 8.7 ns Max
Data Delay (based on when the FIFO is empty - used
for cycle extension
HOST_ADDR
HOST_CE
tHADWRH
tSADWRH
tWRWH
tWRWL
HOST_RD
tDRDYWRL
tRDYPWR
tDRRHRDY
ACK
tHDATWH
tSDATWH
HOST_D15-0
Figure 34. HDMA A/C- Host Write Cycle
Rev. PrE |
Page 56 of 68 |
April 2007
wrh
ADSP-BF542/4/8/9
Preliminary Technical Data
JTAG Test And Emulation Port Timing
Table 47 and Figure 35 describe JTAG port operations.
Table 47. JTAG Port Timing
Parameter
Timing Parameters
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
tHTAP
tSSYS
System Inputs Setup Before TCK High1
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulsewidth2 (measured in TCK cycles)
Switching Characteristics
tDTDO
TDO Delay from TCK Low
System Outputs Delay After TCK Low3
tDSYS
Minimum
Maximum
20
4
4
4
5
4
0
1
Unit
ns
ns
ns
ns
ns
TCK
10
12
ns
ns
System Inputs=PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0, DQ15–0, DQS1–0, D15–0, ATAPI_PDIAG, CLKIN, RESET, NMI,
BMODE3–0, MFS, MLF_P, and MLF_M.
2
50 MHz Maximum
3
System Outputs=PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0, DQ15–0, DQS1–0, D15–0, DA12–0, DBA1–0, DQM1–0, DCLK2–1,
DCLK2–1, DCS1–0, DCKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, EMU, CLKOUT, CLKBUF, EXT_WAKE.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 35. JTAG Port Timing
Rev. PrE |
Page 57 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
POWER DISSIPATION
TEST CONDITIONS
Total power dissipation has two components: one due to internal circuitry (PINT) and one due to the switching of external
output drivers (PEXT). Table 48 through Table 50 show the
power dissipation for internal circuitry (VDDINT).
All timing parameters appearing in this data sheet were measured under the conditions described in this section.
See the ADSP-BF549 Blackfin Processor Hardware Reference for
definitions of the various operating modes and for instructions
on how to minimize system power.
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (Figure 36). The time
tENA_MEASURED is the interval from when the reference signal
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time tTRIP is the interval from when the
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time tENA is calculated as shown in the
equation:
Many operating conditions can affect power dissipation. System
designers should refer to EE-TBD: Estimating Power for ADSPBF542/BF544/BF548/BF549 Blackfin Processors on the Analog
Devices website (www.analog.com)—use site search on
“EE-TBD.” This document provides detailed information for
optimizing your design for lowest power.
Table 48. Internal Power Dissipation (Hibernate mode)
IDDHIBERNATE
IDDRTC
1
2
IDD (nominal)
Unit
TBD
μA
TBD
μA
Output Enable Time
t ENA = t ENA_MEASURED – t TRIP
If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
1
Measured at VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V).
2
Measured at VDDRTC = 3.3 V at 25°C.
Output Disable Time
Table 49. Internal Power Dissipation (Deep Sleep mode)
VDDINT
1
2
IDD (nominal )
Unit
0.8
TBD
mA
0.9
TBD
mA
1.0
TBD
mA
1.1
TBD
mA
1.26
TBD
mA
1
2
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the
equation:
t DECAY = ( C L ΔV ) ⁄ I L
The output disable time tDIS is the difference between
tDIS_MEASURED and tDECAY as shown in Figure 36. The time
tDIS_MEASURED is the interval from when the reference signal
Assumes VDDINT is regulated externally.
Nominal assumes an operating temperature of 25°C.
Table 50. Internal Power Dissipation (Full On1 mode)
VDDINT2 @ fCCLK
IDD (nominal3)
Unit
0.8 @ TBD MHz
TBD
mA
0.8 @ TBD MHz
TBD
mA
0.9 @ TBD MHz
TBD
mA
1.0 @ TBD MHz
TBD
mA
1.1 @ TBD MHz
TBD
mA
1.26 @ TBD MHz
TBD
mA
1
Processor executing 75% dual MAC, 25% ADD with moderate data bus activity.
Assumes VDDINT is regulated externally.
3
Nominal assumes an operating temperature of 25°C.
2
Rev. PrE |
Page 58 of 68 |
April 2007
ADSP-BF542/4/8/9
Preliminary Technical Data
switches to when the output voltage decays ΔV from the measured output high or output low voltage. The time tDECAY is
calculated with test loads CL and IL, and with ΔV equal to 0.5 V.
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
T J = T CASE + ( Ψ JT × P D )
REFERENCE
SIGNAL
tDIS_MEASURED
tDIS
where:
tENA-MEASURED
TJ = Junction temperature (ⴗC)
tENA
VOH
(MEASURED)
VOH (MEASURED) ⴚ ⌬V
VOH
2.0V (MEASURED)
TCASE = Case temperature (ⴗC) measured by customer at top
center of package.
VOL (MEASURED) + ⌬V
1.0V
ΨJT = From Table 51
VOL
(MEASURED)
tDECAY
VOL
(MEASURED)
PD = Power dissipation (see Power Dissipation on Page 58 for
the method to calculate PD)
tTRIP
OUTPUT STOPS DRIVING
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
T J = T A + ( θ JA × P D )
Figure 36. Output Enable/Disable
Example System Hold Time Calculation
where:
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the ADSP-BF542/4/8/9 processor’s
output voltage and the input threshold for the device requiring
the hold time. A typical ΔV will be 0.4 V. CL is the total bus
capacitance (per data line), and IL is the total leakage or threestate current (per data line). The hold time will be tDECAY plus
the minimum disable time (for example, tDDAT for an asynchronous memory write cycle).
50V
TO
OUTPUT
PIN
1.5V
Figure 37. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
1.5V
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heatsink is
required.
Values of θJB are provided for package comparison and printed
circuit board design considerations.
In Table 51, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Table 51. Thermal Characteristics
30pF
INPUT
OR
OUTPUT
TA = Ambient temperature (ⴗC)
1.5V
Figure 38. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Rev. PrE |
Parameter
θJA
θJA
θJA
θJB
θJC
ΨJT
ΨJT
ΨJT
Page 59 of 68 |
April 2007
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
18.4
15.8
15.0
9.75
6.37
0.27
0.60
0.66
Unit
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ADSP-BF542/4/8/9
Preliminary Technical Data
400-BALL BGA PINOUT
Table 52 lists the BGA pinout by signal for the ADSP-BF549.
Table 53 on Page 63 lists the BGA pinout by ball number.
Table 52. 400-Ball BGA Ball Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
AMS0
AMS1
AMS2
AMS3
AOE
ARE
ATAPI_PDIAG
AWE
BMODE0
BMODE1
BMODE2
BMODE3
CLKBUF
CLKIN
CLKOUT
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DA0
DA1
DA2
DA3
Ball No.
C17
C16
B2
A2
B3
A10
D9
B10
D10
C10
B12
P19
D12
W1
W2
W3
W4
D11
A11
L16
D13
C13
B13
B15
A15
B16
A16
B17
C14
C15
A17
D14
D15
E15
E14
D17
G19
G17
E20
G18
Signal
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DBA0
DBA1
DCAS
DCK1
DCK1
DCK2
DCK2
DCKE
DCS0
DCS1
DDR_VREF
DDR_VSSR
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM0
DQM1
DQS0
Ball No.
G16
F19
D20
C20
F18
E19
B20
F17
D19
H17
H16
F16
E16
D16
C18
D18
B18
C19
B19
M20
N20
L18
M19
L19
L20
L17
K16
K20
K17
K19
J20
K18
H20
J19
J18
J17
J16
G20
H19
F20
Rev. PrE |
Signal
DQS1
DRAS
DWE
EMU
EXT_WAKE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Page 60 of 68 |
April 2007
Ball No.
H18
E17
E18
R5
M18
A1
A13
A20
E3
J7
J8
J9
J10
J11
J12
N6
N7
N8
N9
N10
N11
N12
N13
N14
U8
B11
F3
F14
K7
K8
K9
K10
K11
K12
K13
P8
P9
P10
P11
P12
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDMC
GNDMP
GNDMX
MFS
MLF_M
Ball No.
P13
V6
G9
G10
G11
L7
L8
L9
L10
L11
L12
L13
L14
R9
R13
R14
R16
D1
H7
H8
H9
H10
H11
H12
M6
M7
M8
M9
M10
M11
M12
M13
M14
Y1
Y20
F6
E7
D4
E6
F4
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 52. 400-Ball BGA Ball Assignment (Alphabetically by Signal) (Continued)
Signal
MLF_P
MXI
MXO
NMI
PA_0
PA_1
PA_2
PA_3
PA_4
PA_5
PA_6
PA_7
PA_8
PA_9
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_0
PB_1
PB_2
PB_3
PB_4
PB_5
PB_6
PB_7
PB_8
PB_9
PB_10
PB_11
PB_12
PB_13
PB_14
PC_0
PC_1
PC_2
PC_3
PC_4
Ball No.
E4
C2
C1
C11
U12
V12
W12
Y12
W11
V11
Y11
U11
U10
Y10
Y9
V10
Y8
W10
Y7
W9
W5
Y2
T6
U6
Y4
Y3
W6
V7
W8
V8
U7
W7
Y6
V9
Y5
H2
J3
J2
H1
G2
Signal
PC_5
PC_6
PC_7
PC_8
PC_9
PC_10
PC_11
PC_12
PC_13
PD_0
PD_1
PD_2
PD_3
PD_4
PD_5
PD_6
PD_7
PD_8
PD_9
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
PE_0
PE_1
PE_2
PE_3
PE_4
PE_5
PE_6
PE_7
PE_8
PE_9
PE_10
PE_11
PE_12
PE_13
PE_14
Ball No.
G1
J5
H3
Y14
V13
U13
W14
Y15
W15
P3
P4
R1
R2
T1
R3
T2
R4
U1
U2
T3
V1
T4
V2
U4
U3
V19
T17
U18
V14
Y16
W20
W19
R17
V20
U19
T18
P2
M5
P5
U16
Signal
PE_15
PF_0
PF_1
PF_2
PF_3
PF_4
PF_5
PF_6
PF_7
PF_8
PF_9
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
PG_0
PG_1
PG_2
PG_3
PG_4
PG_5
PG_6
PG_7
PG_8
PG_9
PG_10
PG_11
PG_12
PG_13
PG_14
PG_15
PH_0
PH_1
PH_2
PH_3
PH_4
PH_5
PH_6
Rev. PrE |
Page 61 of 68 |
Ball No.
W17
K3
J1
K2
K1
L2
L1
L4
K4
L3
M1
M2
M3
M4
N4
N1
N2
J4
K5
L5
N3
P1
V15
Y17
W16
V16
Y19
Y18
U15
P16
R18
Y13
W13
W18
U14
V17
V18
U17
C3
D6
April 2007
Signal
PH_7
PH_8
PH_9
PH_10
PH_11
PH_12
PH_13
PI_0
PI_1
PI_2
PI_3
PI_4
PI_5
PI_6
PI_7
PI_8
PI_9
PI_10
PI_11
PI_12
PI_13
PI_14
PI_15
PJ_0
PJ_1
PJ_2
PJ_3
PJ_4
PJ_5
PJ_6
PJ_7
PJ_8
PJ_9
PJ_10
PJ_11
PJ_12
PJ_13
RESET
RTXI
RTXO
Ball No.
H4
D5
C4
C7
C5
D7
C6
A3
B4
A4
B5
A5
B6
A6
B7
A7
C8
B8
A8
A9
C9
D8
B9
R20
N18
M16
T20
N17
U20
P18
N16
R19
P17
T19
M17
P20
N19
C12
A14
B14
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 52. 400-Ball BGA Ball Assignment (Alphabetically by Signal) (Continued)
Signal
TCK
TDI
TDO
TMS
TRST
USB_DM
USB_DP
USB_ID
USB_RSET
USB_VBUS
USB_VREF
USB_XI
USB_XO
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
Ball No.
V3
V5
V4
U5
T5
E2
E1
G3
D3
D2
B1
F1
F2
J14
J15
F10
F11
F12
K14
K15
Signal
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
Ball No.
G15
H13
H14
H15
E9
E10
E11
E12
N5
N15
F8
F13
F15
K6
P15
G5
G6
G7
G14
R6
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
Rev. PrE |
Page 62 of 68 |
Ball No.
R7
R8
R15
H5
H6
M15
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
J6
J13
U9
F9
April 2007
Signal
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDMC
VDDMP
VDDMX
VDDRTC
VDDUSB
VDDUSB
VROUT0
VROUT1
XTAL
Ball No.
P6
P7
P14
G8
G12
G13
L6
L15
R10
R11
R12
F7
E8
E5
E13
F5
G4
A18
A19
A12
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 53 lists the BGA pinout by ball number for the ADSPBF549. Table 52 on Page 60 lists the BGA pinout by signal.
Table 53. 400-Ball BGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
Signal
GND
ADDR2
PI_0
PI_2
PI_4
PI_6
PI_8
PI_11
PI_12
AMS0
CLKIN
XTAL
GND
RTXI
D4
D6
D10
VROUT0
VROUT1
GND
USB_DP
USB_DM
GND
MLF_P
VDDMX
MFS
GNDMP
VDDMP
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDRTC
D14
D13
DCK1
DRAS
DWE
DA9
DA2
Ball No.
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
Signal
USB_VREF
ADDR1
ADDR3
PI_1
PI_3
PI_5
PI_7
PI_10
PI_15
AMS2
GND
ARE
D2
RTXO
D3
D5
D7
DCKE
DCS1
DA10
USB_XI
USB_XO
GND
MLF_M
VDDUSB
GNDMC
VDDMC
VDDEXT
VDDINT
VDDDDR
VDDDDR
VDDDDR
VDDEXT
GND
VDDEXT
DCAS
DA11
DA8
DA5
DQS0
Rev. PrE |
Ball No.
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
Page 63 of 68 |
Signal
MXO
MXI
PH_5
PH_9
PH_11
PH_13
PH_10
PI_9
PI_13
AOE
NMI
RESET
D1
D8
D9
ABE1
ABE0
DCK2
DCS0
DA7
PC_5
PC_4
USB_ID
VDDUSB
VDDEXT
VDDEXT
VDDEXT
VDDINT
GND
GND
GND
VDDINT
VDDINT
VDDEXT
VDDDDR
DA4
DA1
DA3
DA0
DQM0
April 2007
Ball No.
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
Signal
GND
USB_VBUS
USB_RSET
GNDMX
PH_8
PH_6
PH_12
PI_14
AMS1
AMS3
CLKBUF
AWE
D0
D11
D12
DCK1
D15
DCK2
DA12
DA6
PC_3
PC_0
PC_7
PH_7
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
GND
VDDDDR
VDDDDR
VDDDDR
DBA1
DBA0
DQS1
DQM1
DQ11
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 53. 400-Ball BGA Ball Assignment (Numerically by Ball Number) (Continued)
Ball No.
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
Signal
PF_1
PC_2
PC_1
PG_0
PC_6
VDDINT
GND
GND
GND
GND
GND
GND
VDDINT
VDDDDR
VDDDDR
DQ15
DQ14
DQ13
DQ12
DQ9
PF_14
PF_15
PG_3
PF_13
VDDEXT
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDEXT
PJ_7
PJ_4
PJ_1
PJ_13
DDR_VSSR
Ball No.
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
Signal
PF_3
PF_2
PF_0
PF_7
PG_1
VDDEXT
GND
GND
GND
GND
GND
GND
GND
VDDDDR
VDDDDR
DQ5
DQ7
DQ10
DQ8
DQ6
PG_4
PE_11
PD_0
PD_1
PE_13
VDDINT
VDDINT
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
PG_12
PJ_9
PJ_6
ATAPI_PDIAG
PJ_12
Rev. PrE |
Ball No.
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
Page 64 of 68 |
Signal
PF_5
PF_4
PF_8
PF_6
PG_2
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
CLKOUT
DQ4
DQ0
DQ2
DQ3
PD_2
PD_3
PD_5
PD_7
EMU
VDDEXT
VDDEXT
VDDEXT
GND
VDDINT
VDDINT
VDDINT
GND
GND
VDDEXT
GND
PE_7
PG_13
PJ_8
PJ_0
April 2007
Ball No.
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
Signal
PF_9
PF_10
PF_11
PF_12
PE_12
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDEXT
PJ_2
PJ_11
EXT_WAKE
DQ1
DDR_VREF
PD_4
PD_6
PD_10
PD_12
TRST
PB_2
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
PE_1
PE_10
PJ_10
PJ_3
ADSP-BF542/4/8/9
Preliminary Technical Data
Table 53. 400-Ball BGA Ball Assignment (Numerically by Ball Number) (Continued)
Ball No.
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
1
2
Signal
PD_8
PD_9
PD_15
PD_14
TMS
PB_3
PB_10
GND
VDDINT
PA_8
PA_7
PA_0
PC_10
PH_1
PG_11
PE_14
PH_4
PE_2
PE_9
PJ_5
3
4
5
6
7
Ball No.
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
8
9
Signal
PD_11
PD_13
TCK
TDO
TDI
GND
PB_7
PB_9
PB_13
PA_11
PA_5
PA_1
PC_9
PE_3
PG_5
PG_8
PH_2
PH_3
PE_0
PE_8
Ball No.
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Signal
BMODE0
BMODE1
BMODE2
BMODE3
PB_0
PB_6
PB_11
PB_8
PA_15
PA_13
PA_4
PA_2
PG_15
PC_11
PC_13
PG_7
PE_15
PH_0
PE_6
PE_5
10 11 12 13 14 15 16 17 18 19 20
R
A
R
B
R
C
D
G
S
S
G
G
S
S
E
S
S
S
F
S
S
G
S
S
H
S
S
J
S
S
K
S
S
L
R
M
G
N
P
R
T
U
V
W
Y
KEY:
VDDINT
S
VDDEXT
R
REFERENCES: VROUTO, VROUT1, DDR_VREF , USB_VREF
GND
G
GROUNDS: GNDMP, GNDMX, GNDMC, DDR_VSSR
NC
SUPPLIES: VDDDDR, VDDMP, VDDMX, VDDMC, VDDUSB, VDDRTC
I/O SIGNALS
Figure 39. 400-Ball Mini-BGA Ground Configuration (Top View)
Rev. PrE |
Page 65 of 68 |
April 2007
Ball No.
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Signal
GND
PB_1
PB_5
PB_4
PB_14
PB_12
PA_14
PA_12
PA_10
PA_9
PA_6
PA_3
PG_14
PC_8
PC_12
PE_4
PG_6
PG_10
PG_9
GND
ADSP-BF542/4/8/9
Preliminary Technical Data
OUTLINE DIMENSIONS
Dimensions in Figure 40 are shown in millimeters.
15.20 BSC SQ
17.00 BSC SQ
A1 BALL
0.80 BSC BALL PITCH
A1 BALL INDICATOR
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
TOP VIEW
0.28 MIN
0.12 MAX
COPLANARITY
1.70 MAX
SIDE VIEW
0.50
BALL DIAMETER 0.45
0.40
DETAIL A
SEATING PLANE
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM,
WITH THE EXCEPTION OF BALL DIAMETER.
3. CENTER DIMENSIONS ARE NOMINAL.
Figure 40. Chip Scale Package Ball Grid Array (Mini-BGA) BC-400
SURFACE MOUNT DESIGN
Table 54 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 54. BGA Data for Use with Surface Mount Design
Package
Chip Scale Package Ball Grid Array (Mini-BGA) BC-400
Rev. PrE |
Ball Attach Type
Solder Mask Defined
Page 66 of 68 |
April 2007
Solder Mask Opening
0.40 mm diameter
Ball Pad Size
0.50 mm diameter
ADSP-BF542/4/8/9
Preliminary Technical Data
ORDERING GUIDE
Part numbers that include “Z” are RoHS Compliant.
Part Number
ADSP-BF549BBCZ-ENG
1
Temperature Range (Ambient)
TBD1
Speed Grade (Max)
TBD1
For more information, see component engineering-grade agreement.
Rev. PrE |
Page 67 of 68 |
April 2007
Operating Voltage (Nominal)
TBD1
ADSP-BF542/4/8/9
Preliminary Technical Data
© 2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06512-0-4/07(PrE)
Rev. PrE |
Page 68 of 68 |
April 2007