a FEATURES Four Delay Lines with the Ability to Independently Adjust All Edges Pin Compatible and Functionally Equivalent with the BT624 Reduced Power Dissipation 44-Lead PLCC Package with Internal Heat Spreader APPLICATIONS Automatic Test Equipment Semiconductor Test Systems Board Test Systems Clocked ECL Circuits Four Channel ECL Delay Line AD53020 FUNCTIONAL BLOCK DIAGRAM GND S0 S1 AD53020 VWIDTH1 OUT1 IN1, IN1 OUT1 VDELAY1 VWIDTH2 OUT2 IN2, IN2 OUT2 DRVMODE VDELAY2 VWIDTH3 OUT3 IN3, IN3 OUT3 PRODUCT DESCRIPTION The AD53020 is a four-channel delay line designed for use in automatic test equipment and digital logic systems. High speed bipolar transistors and a 44-lead plastic PLCC package with internal heat spreader provide high frequency performance at a minimum of space, cost and power dissipation. Featuring full pin compatibility and functional equivalence to the BT624, the AD53020 offers independent analog control of positive and negative edges with five delay ranges. The AD53020 offers attractive performance with optimized power dissipation and linear delay vs. program voltage control. This device is also very stable over operating conditions and has very low jitter. Digital inputs are ECL compatible. They can either be provided independently for each channel (IN1, IN1 through IN4, IN4), or fanned out to all channels from Channel 2 (IN2, IN2). The choice of these two options is made by setting the DRVMODE input, with ECL Logic 0 providing four independent channels, and ECL Logic 1 enabling a logical OR function between each channel and the Channel Number 2. For maximum timing accuracy, differential signals are recommended for use with the digital inputs. However, single-ended operation is also supported and it is facilitated through the use of the VBB midpoint level generated on-chip. To make use of this feature, connect the VBB output to the inverting input of each channel. It is also advisable, when using the VBB output, to decouple this signal with a 0.1 µF ceramic capacitor to ground. The outputs of the AD53020 are ECL compatible and should be terminated by 50 Ω to –2.0 V at the inputs of the gates they drive. VDELAY3 VWIDTH4 OUT4 IN4, IN4 OUT4 VDELAY4 VEE VBB COMP1 COMP2 REXT1 REXT2 The delay is programmed through the VDELAY and VWIDTH pins for each channel. The acceptable range is –1.3 V to –0.1 V, representing the longest and the shortest delays provided by the device. An 0.01 µF ceramic capacitor to ground is recommended for each input. The bias current for each input is fixed by an internal current mirror. The value of the bias current is set by the external resistor at REXT1. A 1.3 kΩ resistor to ground at this pin establishes 1 mA bias in each input. The nominal voltage at the REXT1 pin is –1.3 V. The VDELAY affects both the positive and negative edges in all modes. The VWIDTH is an additional delay adjustment that is active in Modes 2, 3 and 5. VWIDTH has no effect in Modes 0 and 1. For Modes 2 and 3, the effect of the VWIDTH adjustment is to increase or decrease the delay of the negative edge relative to the positive edge. In Mode 5, the total delay for both positive and negative edges is set by the combination of VDELAY and VWIDTH. (continued on page 4) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD53020-Test Conditions (Unless otherwise noted): Recommended Operating AD53020–SPECIFICATIONS Conditions with all OUT and OUT outputs terminated through 50 ⍀ to –2.0 V, REXT1 = 1.3 k⍀, REXT2 = 2.94 k⍀. Typical values are based on nominal temperature, TA = +25ⴗC, and nominal supply voltage, VEE = –5.2 V. DC CHARACTERISTICS1 Parameter Symbol T(ⴗC) Min DIGITAL INPUT HIGH VOLTAGE IN, IN, DRVMODE, S0, S1 VIH 70 DIGITAL INPUT LOW VOLTAGE IN, IN, DRVMODE, S0 VIL DIGITAL INPUT LOW VOLTAGE, S1 VIL S1 THIRD STATE (EXTENDED DELAY) Typ Max Units –1.070 0.000 V 70 –1.950 –1.450 V 70 VEE –1.450 V Full VEE –3.2 V DIGITAL OUTPUT HIGH VOLTAGE VOH 70 –1.000 –0.735 V DIGITAL OUTPUT LOW VOLTAGE VOL 70 –1.950 –1.600 V DIGITAL INPUT BIAS CURRENT IN, IN, DRVMODE, S0, S1 IIN 2 –100 to +100 µA % Tpd/V POWER SUPPLY REJECTION RATIO PSRR Full 0.5 VEE SUPPLY CURRENT Mode 0 Modes 1, 2 Modes 3, 5 IEE IEE IEE Full Full Full 174 225 267 200 250 290 mA mA mA NOTES 1The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least two minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. 2This parameter is fully characterized, but not production tested. Specifications subject to change without notice. AC CHARACTERISTICS1 Parameter Symbol Min Typ Max Units MINIMUM PROPAGATION DELAYS2 Mode S1 S0 VDELAY 0 0 0 –0.1 V 1 0 1 –0.1 V 2 1 0 –0.1 V 3 1 1 –0.1 V 5 VEE 1 –0.1 V Tpd Min Tpd Min Tpd Min Tpd Min Tpd Min 3.6 4.9 3.9 5.2 6.8 4.5 6.3 5.3 7.1 8.8 5.4 7.3 6.8 8.8 10.3 ns ns ns ns ns DELAY ADJUSTMENT RANGES Mode S1 S0 0 0 0 1 0 1 2 1 0 3 1 1 5 VEE 1 Tpd Span Tpd Span Tpd Span Tpd Span Tpd Span 14.0 22.9 13.2 22.0 29.3 19.0 31.4 18.9 31.5 44.5 24.7 37.8 24.6 40.6 52.0 ns ns ns ns ns MINIMUM PULSEWIDTH3 1.9 ns RISING EDGE DELAY VS. VWIDTH DELAY Change (Modes 2 and 3)3 30 ps DELAY VS. DUTY CYCLE 50 ps VWIDTH RANGE OF ADJUSTMENT (VDELAY = –0.6 V, MODES 2 AND 3, DELAY RELATIVE TO VWIDTH = –0.7 V) VWIDTH = –0.1 V VWIDTH = –1.1 V VWIDTH = –1.3 V –5.5 +5.5 +6.5 3, 4 +4.0 –2– –4.0 ns ns ns REV. A AD53020 Parameter Symbol Min Typ Max Units RISING TO FALLING EDGE DELAY MATCHING (VDELAY = VFALL = –0.5 V)3 Modes 0, 1, 5 Modes 2, 3 0.1 1.0 ns ns PROPAGATION DELAY TEMPERATURE COEFFICIENT3, 5 0.05 % Tpd/°C OUTPUT RISE/FALL TIMES (20% to 80%)3 550 ps 3 DELAY LINEARITY MONOTONIC NOTES 1 The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least two minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. 2 All minimum propagation delay time measurements refer to both rising and falling edges for Modes 0, 1, 5; these measurements refer to rising edges for Modes 2 and 3 only. DRVMODE is logically low. 3 This parameter is fully characterized, but not production tested. 4 Delay on leading and trailing edges are measured by setting VDELAY = VWIDTH = –0.7 V. The variations for each delay are measured by changing the input duty cycle from 5% to 95% at a constant frequency of 10 MHz. 5 Propagation delay temperature coefficient measured at VDELAY = VWIDTH = –0.7 V. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 AD53020 Package Option 44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A 4 3 2 1 44 43 42 41 40 VEE1 5 IN2 6 GND2 +260 °C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Absolute maximum limits apply individually, not in combination. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2 To ensure lead solderability, handling with bare hands should be avoided and the device should be stored in environments at 24°C ± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%. VEE2 PIN CONFIGURATION IN2 50 +70 +150 +150 V V mA °C °C °C Package Description IN3 TSOL –55 –65 Model GND3 TA TS TJ 0 Units IN3 –6.0 VEE Max GND4 Min VEE3 VEE (Relative to GND) Voltage on Any Digital Pin Output Current Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature2 (Soldering, 5 sec) Symbol IN4 Parameter ORDERING GUIDE PIN 1 IDENTIFIER IN4 7 39 IN1 38 IN1 VEE4 8 37 GND1 VDELAY4 9 36 COMP1 VWIDTH4 10 VDELAY3 11 AD53020 35 REXT1 VWIDTH3 12 TOP VIEW (Not to Scale) 34 COMP2 VDELAY2 13 33 REXT2 32 DRVMODE VWIDTH2 14 VDELAY1 15 31 S0 VWIDTH1 16 30 S1 VBB 17 29 GND1 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD53020 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– OUT1 OUT1 GND2 OUT2 OUT2 GND3 OUT3 OUT3 GND4 OUT4 OUT4 18 19 20 21 22 23 24 25 26 27 28 WARNING! ESD SENSITIVE DEVICE AD53020 A second bias current reference is employed to set the bias current of the delay cells. This current is set by the external resistor at REXT2. A 2.94 kΩ resistor sets the nominal bias current of 500 µA. The nominal voltage at the REXT2 pin is –1.47 V. Table I. Truth Table for Mode Determination All decoupling capacitors should be located as close as possible to the AD53020 chip. S0 Mode 0 0 1 1 VEE VEE 0 1 0 1 0 1 0 1 2 3 Not Valid 5 19 ns 31 ns 19 ns 31 ns No No Yes Yes 45 ns No S0 and S1 accept logical ECL levels. In the case of S1 only, a third state is also accepted, at the negative supply, V EE. The mode is set by the inputs S0 and S1. These pins use standard ECL levels, with the addition of a third level for the S1 Pin, which can also be connected to VEE. Refer to Table I for the description of the modes and their respective settings. C3265a–0–2/99 The current references require compensation capacitors of 0.1 µF to VEE at each of the COMP1 and COMP2 pins. In addition, each VEE supply pin should also have its own decoupling capacitor of 0.1 µF to ground. Typical Independent Adjustment of Span Positive and Negative Edges? S1 Table II. Package Thermal Characteristics For Modes 2 and 3, it is important to note that an internal flipflop is used to provide the independent control of rising and falling edges. The state of this flip-flop is indeterminate upon power-up. The state becomes fixed once the first full pulse is provided to each channel, consisting of a positive edge followed by a negative edge. Air Flow, FM JA, ⴗC/W 0 400 30.2 20.9 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead PLCC (P-44A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 6 7 PIN 1 IDENTIFIER 0.025 (0.63) 0.015 (0.38) 40 39 0.050 (1.27) BSC 0.021 (0.53) 0.013 (0.33) TOP VIEW (PINS DOWN) 17 0.032 (0.81) 0.026 (0.66) 29 28 18 0.040 (1.01) 0.025 (0.64) 0.656 (16.66) SQ 0.650 (16.51) 0.110 (2.79) 0.085 (2.16) 0.695 (17.65) SQ 0.685 (17.40) PRINTED IN U.S.A. 0.020 (0.50) R 0.63 (16.00) 0.59 (14.99) –4– REV. A