REFIN REFOUT REFGND ADM1069 VREF SDA SCL A1 A0 SMBus INTERFACE 12-BIT SAR ADC EEPROM CLOSED-LOOP MARGINING SYSTEM CONFIGURABLE OUTPUT DRIVERS DUALFUNCTION INPUTS VX1 VX2 VX4 PDO2 PDO3 (HV CAPABLE OF DRIVING GATES OF N-CHANNEL FET) (LOGIC INPUTS OR SFDs) VX3 PDO1 PDO4 PDO5 PDO6 SEQUENCING ENGINE VP1 VP2 VP3 CONFIGURABLE OUTPUT DRIVERS PROGRAMMABLE RESET GENERATORS VH (LV CAPABLE OF DRIVING LOGIC SIGNALS) (SFDs) AGND PDO7 PDO8 PDOGND VOUT DAC VOUT DAC VOUT DAC VOUT DAC DAC1 DAC2 DAC3 DAC4 VDD ARBITRATOR GND VDDCAP 10 F REFIN REFOUT ADM1069 REFGND SDA SCL A1 A0 SMBus INTERFACE VREF OSC 12-BIT SAR ADC DEVICE CONTROLLER EEPROM GPI SIGNAL CONDITIONING VX1 CONFIGURABLE O/P DRIVER (HV) SFD PDO1 PDO2 PDO3 VX2 PDO4 PDO5 VX3 GPI SIGNAL CONDITIONING VX4 VP1 SEQUENCING ENGINE SFD SELECTABLE ATTENUATOR SFD SELECTABLE ATTENUATOR SFD VP2 CONFIGURABLE O/P DRIVER (HV) PDO6 CONFIGURABLE O/P DRIVER (LV) PDO7 CONFIGURABLE O/P DRIVER (LV) PDO8 VP3 VH AGND VDDCAP 10 F PDOGND VDD ARBITRATOR GND REG 5.25V CHARGE PUMP VOUT DAC VCCP DAC1 10 F VOUT DAC DAC2 DAC3 DAC4 25 32 VX1 VX2 VX3 VX4 VP1 VP2 VP3 VH 1 24 PIN 1 INDICATOR ADM1069 TOP VIEW (Not to Scale) 8 17 9 16 PDO1 PDO2 PDO3 PDO4 PDO5 PDO6 PDO7 PDO8 6 180 160 5 140 4 120 100 3 80 2 60 40 1 20 0 0 0 1 2 3 4 5 6 0 1 2 3 VVP1 (V) 4 5 6 VVP1 (V) 5.0 6 4.5 5 4.0 3.5 4 3.0 2.5 3 2.0 2 1.5 1.0 1 0.5 0 0 0 2 4 6 8 10 12 14 0 16 2 4 6 8 10 12 14 16 VVH (V) VVH (V) 350 5.0 4.5 300 4.0 250 3.5 3.0 200 2.5 150 2.0 1.5 100 1.0 50 0.5 0 0 0 1 2 3 VVP1 (V) 4 5 6 0 1 2 3 VVH (V) 4 5 6 14 1.0 0.8 12 0.6 10 0.4 0.2 8 0 6 –0.2 –0.4 4 –0.6 2 –0.8 0 0 2.5 5.0 7.5 10.0 12.5 15.0 –1.0 0 1000 ILOAD CURRENT ( A) 2000 3000 4000 CODE 5.0 1.0 4.5 0.8 4.0 0.6 3.5 0.4 3.0 0.2 VP1 = 5V 2.5 0 VP1 = 3V 2.0 –0.2 1.5 –0.4 1.0 –0.6 0.5 –0.8 0 0 1 2 3 4 5 6 –1.0 0 1000 ILOAD (mA) 2000 3000 4000 CODE 4.5 12000 4.0 9894 10000 3.5 VP1 = 5V 3.0 8000 2.5 6000 VP1 = 3V 2.0 1.5 4000 1.0 2000 0.5 25 0 81 0 0 10 20 30 ILOAD ( A) 40 50 60 2047 2048 CODE 2049 1.005 1.004 1.003 1.002 1.001 VP1 = 3.0V 1.000 VP1 = 4.75V DAC BUFFER OUTPUT 0.999 20k 47pF PROBE POINT 0.998 0.997 0.996 1 0.995 –40 CH1 200mV M1.00 s CH1 –20 0 20 40 60 80 100 80 100 TEMPERATURE ( C) 756mV 2.058 2.053 VP1 = 3.0V 2.048 DAC 100k BUFFER OUTPUT PROBE POINT VP1 = 4.75V 1V 2.043 1 2.038 –40 CH1 200mV M1.00 s CH1 944mV –20 0 20 40 TEMPERATURE ( C) 60 VDDCAP VP1 IN OUT 4.75V LDO EN VP2 IN OUT 4.75V LDO EN VP3 IN OUT 4.75V LDO EN VH IN EN SUPPLY COMPARATOR OUT 4.75V LDO INTERNAL DEVICE SUPPLY RANGE SELECT ULTRA LOW + VPn VREF – OV COMPARATOR GLITCH FILTER + LOW MID – UV FAULT TYPE COMPARATOR SELECT FAULT OUTPUT INPUT PULSE SHORTER THAN GLITCH FILTER TIMEOUT PROGRAMMED TIMEOUT INPUT PULSE LONGER THAN GLITCH FILTER TIMEOUT PROGRAMMED TIMEOUT INPUT INPUT T0 TGF T0 TGF OUTPUT OUTPUT T0 TGF T0 TGF VXn (DIGITAL INPUT) + DETECTOR – VREF = 1.4V GLITCH FILTER TO SEQUENCING ENGINE VFET (PDO1-6 ONLY) VDD VP4 CFG4 CFG5 CFG6 SEL VP1 SE DATA SMBus DATA CLK DATA PDO MONITOR FAULT STATE TIMEOUT SEQUENCE SEQUENCE STATES IDLE1 VX1 = 0 IDLE2 VP1 = 1 MONITOR FAULT STATES TIMEOUT STATES EN3V3 10ms VP1 = 0 VP2 = 1 EN2V5 DIS3V3 20ms (VP1 + VP2) = 0 VX1 = 1 VP3 = 1 PWRGD DIS2V5 VP2 = 0 (VP1 + VP2 + VP3) = 0 VX1 = 1 FSEL1 (VP1 + VP2) = 0 VP3 = 0 FSEL2 VP1 = 0 VP2 = 0 VX1 = 1 MONITORING FAULT DETECTOR 1-BIT FAULT DETECTOR VP1 FAULT SUPPLY FAULT DETECTION MASK SENSE 1-BIT FAULT DETECTOR VX4 VX4 SUPPLY FAULT DETECTION FAULT LOGIC INPUT CHANGE OR FAULT DETECTION MASK SENSE SEQUENCE DETECTOR 1-BIT FAULT DETECTOR LOGIC INPUT CHANGE OR FAULT DETECTION TIMER FAULT WARNINGS WARNINGS INVERT MASK FORCE FLOW (UNCONDITIONAL JUMP) SELECT 04735-032 VP1 DIGITIZED VOLTAGE READING NO ATTENUATION VXn 12-BIT ADC 2.048V VREF VPn/VH ATTENUATION NETWORK (DEPENDS ON RANGE SELECTED) DIGITIZED VOLTAGE READING 12-BIT ADC 2.048V VREF CONTROLLER VIN ADM1069 VH/VPn/VXn DC/DC CONVERTER OUTPUT FEEDBACK GND VIN CONTROLLER VOUT ADM1069 DEVICE CONTROLLER (SMBus) OUTPUT DC/DC CONVERTER FEEDBACK GND ATTENUATION RESISTOR DACOUTn PCB TRACE NOISE DECOUPLING CAPACITOR DAC MUX ATTENUATION RESISTOR DACOUTn PCB TRACE NOISE DECOUPLING CAPACITOR ADC DAC DEVICE CONTROLLER (SMBus) 12V IN 12V OUT 5V IN 5V OUT 3V IN 3V OUT IN DC-DC1 EN VH 5V OUT 3V OUT 3.3V OUT VP1 VP2 VP3 1.25V OUT 1.2V OUT 0.9V OUT VX1 VX2 VX3 IN DC-DC2 PDO3 PDO4 PDO5 PDO7 EN OUT 1.25V OUT POWER_GOOD SYSTEM RESET IN DC-DC3 EN VX4 OUT 1.2V OUT PDO8 DAC1 3.3V OUT REFIN VCCP VDDCAP GND IN OUT 10 F 3.3V OUT PDO1 PDO2 PDO6 POWER_ON OUT ADM1069 10 F 10 F EN TRIM DC-DC4 0.9V OUT SMBus POWER-UP (VCC > 2.5V) EEPROM E E P R O M L D DEVICE CONTROLLER D A T A LATCH A R A M L D U P D LATCH B FUNCTION (OV THRESHOLD ON VP1) 1 9 1 9 SCL 1 SDA 0 0 1 1 A1 A0 START BY MASTER R/W D7 D6 D5 D4 D3 D2 D1 ACK. BY SLAVE D0 ACK. BY SLAVE FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND CODE 1 9 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 FRAME 3 DATA BYTE D1 D0 ACK. BY SLAVE D7 D6 D5 D4 D3 D2 FRAME N DATA BYTE D1 D0 ACK. BY SLAVE STOP BY MASTER 1 9 1 9 SCL 1 SDA 0 0 1 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 ACK. BY SLAVE START BY MASTER 1 FRAME 1 SLAVE ADDRESS D0 ACK. BY MASTER 9 1 FRAME 2 DATA BYTE 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 FRAME 3 DATA BYTE D1 D0 D7 D6 D5 D4 ACK. BY MASTER D2 D1 D0 NO ACK. FRAME N DATA BYTE tF tR D3 STOP BY MASTER t HD ;STA t LO W SCL t HD; STA t HD ;DA T t HI G H t SU; S TA t SU ;ST O t SU; DAT SDA t BU F P S S P 1 2 S SLAVE ADDRESS W 3 4 5 6 A REGISTER ADDRESS (0x00 TO 0xDF) A P 1 2 3 SLAVE S ADDRESS W A 1 2 S SLAVE ADDRESS W 3 4 5 6 A COMMAND BYTE (0xFE) A P 1 2 3 SLAVE S ADDRESS W A 1 2 3 SLAVE W A S ADDRESS 4 5 6 7 8 RAM ADDRESS A DATA A P (0x00 TO 0xDF) 4 5 6 7 8 EEPROM EEPROM ADDRESS ADDRESS A A P LOW BYTE HIGH BYTE (0x00 TO 0xFF) (0xF8 TO 0xFB) 4 5 6 7 8 9 10 EEPROM EEPROM ADDRESS ADDRESS A LOW BYTE A DATA A P HIGH BYTE (0x00 TO 0xFF) (0xF8 TO 0xFB) 1 2 3 4 5 6 7 8 9 10 BYTE SLAVE COMMAND 0xFC DATA DATA DATA A S W A A A A A P COUNT ADDRESS (BLOCK WRITE) 1 2 N 1 2 S SLAVE ADDRESS R 3 4 5 6 A DATA A P 1 2 3 4 5 6 7 8 9 10 11 12 SLAVE COMMAND 0xFD SLAVE BYTE DATA S ADDRESS W A (BLOCK READ) A S ADDRESS R A COUNT A A 1 13 14 DATA A 32 P 1 2 3 4 5 6 7 8 9 10 11 12 SLAVE COMMAND 0xFD SLAVE BYTE DATA A S ADDRESS W A (BLOCK READ) A S ADDRESS R A COUNT A 1 13 14 15 DATA 32 A PEC A P 0.75 0.60 0.45 1.60 MAX 9.00 BSC SQ 32 25 1 24 PIN 1 7.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE VIEW A 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY 8 17 9 0.80 BSC LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBA 16 0.45 0.37 0.30