PM4344 TQUAD PMC-Sierra,Inc. Quad T1 Framer FEATURES • Monolithic single-chip device that integrates four full-featured T1 framers and transmitters for terminating duplex DS1 signals. • Supports SF, ESF, T1DM (DDS), and SLC®96 format DS1 signals. • Supports unframed mode. Supports B8ZS or AMI line codes. • Supports transfer of PCM and signalling data to/from 1.544 Mbit/s, 2.048 Mbit/s, 12.352 Mbit/s, or 16.384 Mbit/s backplane buses. • Supports n x DS0 backplane interface for fractional T1. • Provides robbed-bit signalling extraction/insertion, programmable idle and digital milliwatt code substitution, and two superframes of signalling debounce on a per-channel basis. • Provides trunk conditioning which forces programmable trouble code substitution and signalling conditioning on all/selected channels. • Provides ESF bit-oriented code detection/generation, and an HDLC interface for terminating/generating the ESF data link. • Software and functionally compatible with the PM4341A T1XC Single T1 Transceiver. Pin-compatible with the PM6344 EQUAD Quad E1 Framer. • Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring. • Low power 5 V CMOS technology. • Available in a rectangular 128-pin PQFP (14 by 20 mm) package. RECEIVE SECTION • Recovers clock and data using a digital PLL for high jitter tolerance. • Accepts/provides dual- or single-rail digital PCM inputs/outputs. Accepts gapped data streams to support higher rate demultiplexing. • Provides Loss Of Signal (LOS) detection, and red, yellow, and Alarm Indication Signal (AIS) alarm detection. • Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. • Provides programmable in-band loopback code detection. • Supports line and path performance monitoring according to AT&T and PMC-941030 (R7) ANSI specifications. Accumulators are provided for counting, ESF CRC-6 errors, Framing bit errors, Line Code Violations (LCVs), and Loss Of Frame (LOF) or change of frame alignment events. • Extracts the data link in ESF, T1DM (DDS), or SLC®96 modes. Extracts selected channels. • Provides a 2-frame elastic store buffer for jitter and wander attenuation. • Allows insertion of selected channels through a serial port. • Supports transmission of the AIS or the yellow alarm signal in all formats. • Provides a digital PLL for generation of a low jitter transmit clock. • Provides a FIFO buffer for jitter attenuation and transmit rate conversion. FIFO full or empty indication allows for bit-stuffing in higher rate multiplexing applications. TRANSMIT SECTION APPLICATIONS • Optionally accepts/provides dual-rail digital PCM inputs/outputs. • Provides per-channel minimum ones density through Bell (bit 7), GTE, DDS, or “jammed bit 8" (56 Kbit/s) zero code suppression. • Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. • Allows insertion of framed or unframed in-band loopback code sequences. • Allows insertion of a data link in ESF, T1DM (DDS) or SLC®96 modes. • T1/T3 Multiplexers and Digital Private Branch Exchanges (PBXs) • T1 Frame Relay Interfaces • T1 ATM Interfaces • Fractional T1 Interfaces • Digital Access and Cross-Connect Systems (DACS) and Electronic DSX Cross-Connect Systems (EDSXs) • Digital Loop Carriers (DLCs) • T1 Channel Service Units (CSUs) and Data Service Units (DSUs) • ISDN Primary Rate Interfaces (PRIs) • SONET Add/Drop Multiplexers (ADMs) BLOCK DIAGRAM TCLK1[1:4] Transmitter BTPCM/ BTDP[1:4]/MTD* BTSIG/BTDN[1:4] BTFP[1:4]/MTFP* BTCLK[1:4]/ MTCLK* BTIF Backplane Transmit Interface XPDE Pulse Density Enforcer XBAS Basic Transmitter: Frame Generation, Alarm Insertion, Trunk Conditioning, Line Coding TPSC Per-channel Controller: Signal, Idle, Zero Control XIBC In-band Loopback Code Generator XBOC Bit-oriented Code Generator XFDL HDLC Transmitter DTIF Digital Transmit Interface DJAT Digital Jitter Attenuator TCLKO[1:4] TDP/TDD[1:4] TDN/TFLG[1:4] TOPS Timing Options TDLCLK/TDLUDR[1:4] TDLSIG/TDLINT[1:4] BRCLK*/MRCLK* BRFPI*/MRFPI* Receiver MENB* PMON Performance Monitor Counters SIGX Signalling Extractor ELST Elastic Store XCLK/VCLK* RCLK[1:4] RDP/RDD[1:4] RDN/RLCV[1:4] DRIF DS-1 Receive Interface Internal Bus A[9:0]* CDRC Clock and Data Recovery FRMR Framer: Frame Alignment, Alarm Extraction IBCD In-band Loopback Code Detector ALMI Alarm Integrator CSB* ALE* MPIF Microprocessor Interface PDVD Pulse Density Violation Detector RBOC Bit-oriented Code Detector BRSIG/BRDN[1:4] BRFPO[1:4] MRD* RCLKO[1:4] RFP[1:4] FRAM Framer/Slip Buffer RAM RPSC Per-channel Controller: Trunk Conditioning RDB* WRB* BRPCM/BRDP[1:4] BRIF Backplane Receive Interface RFDL HDLC Receiver RDLSIG/ RDLINT[1:4] RDLCLK/ RDLEOM[1:4] INTB* RSTB* * These signals are shared between all four framers. D[7:0]* 1998 PMC-Sierra, Inc. October, 1998 PM4344 TQUAD Quad T1 Framer TYPICAL APPLICATIONS FULLY CHANNELIZED HDLC APPLICATION Processor 4 PM7366 FREEDM-8™ Frame Engine and Datalink Manager PM4344 TQUAD Quad T1 Framer PM4314 QDSX Quad T1/E1 LIU PM6344 EQUAD Quad E1 Framer Packet Memory PCI Bus STRUCTURED/UNSTRUCTURED T1 AAL1 OCTAL PORT CARD 4 PM4314 QDSX Quad T1/E1 LIU PM4344 TQUAD Quad T1 Framer PM73121 AAL1gator II™ AAL1 SAR Processor 4 PM4314 QDSX Quad T1/E1 LIU PM4344 TQUAD Quad T1 Framer UTOPIA Bus Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: [email protected] or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: [email protected] PMC-941030 (R7) 1998 PMC-Sierra, Inc. October, 1998 AAL1gator II and FREEDM-8 are trademarks of PMC-Sierra, Inc. SLC®96 is a registered trademark of AT&T.