A426316B Series Preliminary 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue November 15, 2000 Preliminary (November, 2000, Version 0.0) AMIC Technology, Inc. A426316B Series Preliminary 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Features n n n n Separate CAS ( UCAS , LCAS ) for byte selection Self refresh mode 256 refresh cycles, 4 ms refresh interval Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 400mil, 40-pin SOJ - 400mil, 40/44 TSOP type II package n Single 5V power supply/built-in VBB generator n Organization: 65,536 words X 16 bits n Part Identification: - A426316B - A426316B-L (with self-refresh mode) n High speed - 30/35/40 ns RAS access time - 16/18/20 ns column address access time - 10/11/12 ns CAS access time n Low power consumption - Operating: 75mA (-30 max) - Standby: 3 mA (TTL) Pin Configuration Pin Descriptions n SOJ n TSOP Symbol 16 17 18 19 20 PRELIMINARY 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O 15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS VCC I/O0 I/O 1 I/O 2 I/O 3 VCC I/O 4 I/O5 I/O 6 I/O 7 1 2 3 4 5 6 7 8 9 10 NC NC 13 14 15 16 17 18 19 20 21 22 WE RAS NC A0 A1 A2 A3 VCC A426316BV A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A426316BS VCC I/O0 I/O 1 I/O 2 I/O 3 VCC I/O 4 I/O 5 I/O 6 I/O 7 NC NC WE RAS NC A0 A1 A2 44 43 42 41 40 39 38 37 36 35 VSS I/O 15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 32 31 30 29 28 27 26 25 NC LCAS UCAS OE NC A7 A6 A5 24 23 A4 VSS (November, 2000, Version 0.0) 1 Description A0 – A7 Address Inputs I/O0 - I/O15 Data Input/Output RAS Row Address Strobe UCAS Column Address Strobe/Upper Byte Control LCAS Column Address Strobe/Lower Byte Control WE Write Enable OE Output Enable VCC +5V Power Supply VSS Ground NC No Connection AMIC Technology, Inc. A426316B Series Selection Guide Symbol Description -30 -35 -40 Unit tRAC Maximum RAS Access Time 30 35 40 ns tAA Maximum Column Address Access Time 16 18 20 ns tCAC Maximum CAS Access Time 10 11 12 ns tOEA Maximum Output Enable ( OE ) Access Time 10 11 12 ns tRC Minimum Read or Write Cycle Time 65 70 75 ns tPC Minimum EDO Page Mode Cycle Time 12 14 15 ns ICC1 Maximum Operating Current 95 85 75 mA ICC6 Maximum CMOS Standby Current 2 2 2 mA Functional Description The A426316B is a high performance CMOS Dynamic Random Access Memory organized as 65,536 words X 16 bits. The A426316B is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. address strobe ( UCAS and LCAS ) which acts as an output enable independent of RAS . Very EDO UCAS and LCAS to output access time eases system design. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 256 X 16 bits within a page, with cycle time as short as 12/14/15 ns. The A426316B features a high speed page mode operation in which high speed read, write and read-write are performed on any of the bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column PRELIMINARY (November, 2000, Version 0.0) The A426316B is best suited for graphics, digital signal processing and high performance peripherals. The A426316B is available in JEDEC standard 40-pin plastic SOJ package and 40/44 TSOP type II package. 2 AMIC Technology, Inc. A426316B Series REFRESH CONTROLLER Block Diagram VCC VSS Y0 - Y7 COLUMN DECODER UPPER BYTE DATA I/O BUFFER I/O15 I/O14 I/O13 I/O12 I/O 11 I/O 10 I/O9 I/O8 LOWER BYTE DATA I/O BUFFER I/O7 I/O6 I/O5 I/O4 I/O 3 I/O 2 I/O 1 I/O 0 SENSE AMP 256 X 16 A1 RAS CLOCK GENERATOR A2 A3 A4 A5 UCAS UCAS CLOCK GENERATOR LCAS LCAS CLOCK GENERATOR A6 A7 X0 - X7 ROW DECODER RAS ADDRESS BUFFERS A0 256 256 X 256 X 16 ARRAY WE CLOCK GENERATOR WE OE CLOCK GENERATOR OE SUBSTRATE BIAS GENERATOR Recommended Operating Conditions Symbol VCC (Ta = 0°C to +70°C) Description Supply Voltage VSS VIH Input Voltage VIL PRELIMINARY (November, 2000, Version 0.0) Min. Typ. Max. Unit 4.5 5.0 5.5 V 0.0 0.0 0.0 V 2.4 - VCC + 1 V -1.0 - 0.8 V 3 AMIC Technology, Inc. A426316B Series Truth Table Function RAS UCAS LCAS WE OE Address I/Os Standby H H H X X X High-Z Read: Word L L L H L Row/Col. Data Out Read: Lower Byte L H L H L Row/Col. I/O0-7 = Data Out I/O8-15 = High-Z Read: Upper Byte L L H H L Row/Col. I/O0-7 = High-Z I/O8-15 = Data Out Write: Word(Early) L L L L X Row/Col. Data In Write: Lower Byte(Early) L H L L X Row/Col. I/O0-7 = Data In I/O8-15 = X Write: Upper Byte(Early) L L H L X Row/Col. I/O0-7 = X I/O8-15 = Data In Read-Write L L L H→L L→H Row/Col. Data Out → Data In 1.2 EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles L L H→L H→L H→L H H H→L H→L H→L Row/Col. Col. Data Out Data Out 2 2 EDO-Page-Mode Write(Early) -First cycle -Subsequent Cycles L L H→L H→L H→L H→L L L X X Row/Col. Col. Data In Data In 1 1 EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles L L H→L H→L H→L L→H H→L H→L H→L L→H Row/Col. Col. Data In Data In 1, 2 1, 2 L→H→L L L H L Row/Col. Data Out 2 L→H→L L L L X Row/Col. Data In → High-Z 1 L H H X X Row High-Z CBR Refresh H→L L L X X X High-Z Self Refresh (L-ver only) H→L L L X X X High-Z Hidden Refresh Read Hidden Refresh Write RAS -Only Refresh Note: Notes 3 1. Byte Write may be executed with either UCAS or LCAS active. 2. Byte Read may be executed with either UCAS or LCAS active. 3. Only one CAS signal ( UCAS or LCAS ) must be active. PRELIMINARY (November, 2000, Version 0.0) 4 AMIC Technology, Inc. A426316B Series Absolute Maximum Ratings* *Comments Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . -1.0V to +7.0V Output Voltage (Vout) . . . . . . . . . . . . . . . . -1.0V to +7.0V Power Supply Voltage (VCC) . . . . . . . . . . -1.0V to +7.0V Operating Temperature (TOPR) . . . . . . . . . . 0°C to +70°C Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W Short Circuit Output Current (Iout) . . . . . . . . . . . . . 50mA Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C) Symbol Parameter -30 -35 -40 Unit Min. Max. Min. Max. Min. Max. Test Conditions IIL Input Leakage Current -10 +10 -10 +10 -10 +10 µA 0V ≤ Vin ≤ +5.5V Pins not under test = 0V IOL Output Leakage Current -10 +10 -10 +10 -10 +10 µA DOUT disabled, 0V ≤ Vout ≤ +5.5V ICC1 Operating Current - 95 - 85 - 75 mA RAS , UCAS , LCAS Notes 1, 2 Address cycling tRC = min. ICC2 TTL Standby Power Supply Current - 3 - 3 - 3 mA RAS = CAS ≥ VIH All other inputs ≥ VSS ICC3 Refresh Current - 95 - 85 - 75 mA RAS cycling, 1 UCAS = LCAS = VIH, ( RAS only Refresh) tRC = min. ICC4 EDO Page Mode Current - 95 - 85 - 75 mA RAS = VIL, 1, 2 UCAS , LCAS Address cycling tPC = min. ICC5 Refresh Current - 95 - 85 - 75 mA RAS , UCAS , LCAS cycling 1 tRC = min. ( CAS -before- RAS Refresh ) ICC6 CMOS Standby Power Supply Current - 2 - 2 - 2 mA ICC7 Self Refresh Mode Current - 3 - 3 - 3 mA RAS = CAS ≥ VCC - 0.2V All other inputs ≥ VSS RAS = CAS ≤ VSS + 0.2V All other inputs ≥ VSS VOH Output High Voltage 2.4 - 2.4 - 2.4 - V IOUT = -5.0mA VOL Output Low Voltage - 0.4 - 0.4 - 0.4 V IOUT = 4.2mA PRELIMINARY (November, 2000, Version 0.0) 5 AMIC Technology, Inc. A426316B Series AC Characteristics (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C) # Std Symbol -30 -35 -40 Parameter Unit Min. Max. Min. Max. Min. Max. Notes 1 tRC Random Read or Write Cycle Time 65 - 70 - 75 - ns 2 tRP RAS Precharge Time 25 - 25 - 25 - ns 3 tRAS RAS Pulse Width 30 75K 35 75K 40 75K ns 4 tCAS CAS Pulse Width 5 - 6 - 7 - ns 5 tRCD RAS to CAS Delay Time 15 20 16 24 17 28 ns 6 6 tRAD RAS to Column Address Delay Time 10 14 11 17 12 20 ns 7 7 tRSH CAS to RAS Hold Time 10 - 10 - 10 - ns 8 tCSH CAS Hold Time 30 - 35 - 40 - ns 9 tCRP CAS to RAS Precharge Time 5 - 5 - 5 - ns 10 tASR Row Address Setup Time 0 - 0 - 0 - ns 11 tRAH Row Address Hold Time 5 - 6 - 7 - ns Transition Time (Rise and Fall) 2 50 2 50 2 52 ns 4, 5 tREF Refresh Period - 4 - 4 - 4 ms 3 12 tCLZ CAS to Output in Low Z 0 - 0 - 0 - ns 8 13 tRAC Access Time from RAS - 30 - 35 - 40 ns 6,7 14 tCAC Access Time from CAS - 10 - 11 - 12 ns 6, 13 15 tAA Access Time from Column Address - 16 - 18 - 20 ns 7, 13 16 tAR Column Address Hold Time from RAS 26 - 28 - 30 - ns 17 tRCS Read Command Setup Time 0 - 0 - 0 - ns (November, 2000, Version 0.0) 6 tT PRELIMINARY AMIC Technology, Inc. A426316B Series AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C) # Std Symbol -30 -35 -40 Parameter Min. Max. Min. Max. Min. Max. Unit Notes 18 tRCH Read Command Hold Time 0 - 0 - 0 - ns 9 19 tRRH Read Command Hold Time Reference to RAS 0 - 0 - 0 - ns 9 20 tRAL Column Address to RAS Lead Time 16 - 18 - 20 - ns 21 tCOH Output Hold After CAS Low 5 - 5 - 5 - ns 22 tODS Output Disable Setup Time 0 - 0 - 0 - ns 23 tOFF Output Buffer Turn-Off Delay Time 0 6 0 6 0 6 ns 24 tASC Column Address Setup Time 0 - 0 - 0 - ns 25 tCAH Column Address Hold Time 5 - 5 - 5 - ns 26 tRPS RAS Precharge Setup Time 50 - 60 - 70 - ns 27 tWCS Write Command Setup Time 0 - 0 - 0 - ns 11 28 tWCH Write Command Hold Time 5 - 5 - 5 - ns 11 29 tWCR Write Command Hold Time to RAS 26 - 28 - 30 - ns 30 tWP Write Command Pulse Width 5 - 5 - 5 - ns 31 tRWL Write Command to RAS Lead Time 10 - 11 - 12 - ns 32 tCWL Write Command to CAS Lead Time 10 - 11 - 12 - ns 33 tDS Data-in setup Time 0 - 0 - 0 - ns 12 34 tDH Data-in Hold Time 5 - 5 - 5 - ns 12 35 tDHR Data-in Hold Time to RAS 26 - 28 - 30 - ns 36 tRMW Read-Modify-Write Cycle Time 100 - 105 - 100 - ns 37 tRWD RAS to WE Delay Time (Read-Modify-Write) 50 - 54 - 58 - ns PRELIMINARY (November, 2000, Version 0.0) 7 8, 10 11 AMIC Technology, Inc. A426316B Series AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C) # Std Symbol -30 -35 -40 Parameter Min. Max. Min. Max. Min. Max. Unit Notes 38 tCWD CAS to WE Delay Time (Read-Modify-Write) 26 - 28 - 30 - ns 11 39 tAWD Column Address to WE Delay Time (Read-Modify-Write) 32 - 35 - 35 - ns 11 40 tRASS RAS Pulse Width (Self Refresh Mode) 300 - 300 - 300 - µs 41 tCPN CAS Precharge Time ( CAS before RAS ) 10 100K 10 100K 10 100K ns 42 tPC Read or Write Cycle Time (EDO Page) 12 - 14 - 15 - ns 14 43 tCPA Access Time from CAS Precharge (EDO Page) - 19 - 21 - 23 ns 13 44 tCP CAS Precharge Time (EDO Page) 3 - 4 - 5 - ns 45 tPRM EDO Page Mode RMW Cycle Time 56 - 58 - 60 - ns 46 tCRW EDO Page Mode CAS Pulse Width (RMW) - 44 - 46 - 48 ns 47 tRASP RAS Pulse Width (EDO Page) 30 75K 35 75K 40 75K ns 48 tCSR CAS Setup Time ( CAS -before- RAS ) 0 - 0 - 0 - ns 3 49 tCHR CAS Hold Time ( CAS -before- RAS ) 7 - 8 - 8 - ns 3 50 tRPC RAS to CAS Precharge Time ( CAS -before- RAS ) 0 - 0 - 0 - ns 51 tROH RAS Hold Time Reference to OE 6 - 7 - 8 - ns 52 tOEA OE Access Time - 10 - 11 - 12 ns 53 tOED OE to Data Delay 5 - 5 - 5 - ns 54 tOEZ Output Buffer Turn-off Delay from OE 0 5 0 6 0 6 ns PRELIMINARY (November, 2000, Version 0.0) 8 8 AMIC Technology, Inc. A426316B Series AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C) # Std Symbol -30 -35 -40 Parameter Unit Min. Max. Min. Max. Min. Max. 55 tOEH OE Command Hold Time 10 - 10 - 10 - ns 56 tCPT CAS Precharge Time ( CAS -before- RAS Counter Test) 20 - 20 - 20 - ns Notes Notes: 1. 2. 3. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8ms). 4. AC Characteristics assume tT = 3ns. All AC parameters are measured with a load equivalent to one TTL loads and 50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC. 7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA. 8. Assumes three state test load (5pF and a 380Ω Thevenin equivalent). 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥ tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. These parameters are referenced to UCAS and LCAS leading edge in early write cycles and to WE leading edge in read-modify-write cycles. 13. Access time is determined by the longer of tAA or tCAC or tCPA. 14. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values. 15. These parameters are sampled and not 100% tested. PRELIMINARY (November, 2000, Version 0.0) 9 AMIC Technology, Inc. A426316B Series Word Read Cycle tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) UCAS tCRP(9) tCAS(4) LCAS tRAD(6) tASR(10) A0 ~ A7 tRAL(20) tRAH(11) tASC(24) Row Address tCAH(25) Column Address tAR(16) tRCH(18) tRCS(17) tRRH(19) WE tROH(51) tOEA(52) OE tCAC(14) tAA(15) tRAC(13) I/O0 ~ I/O15 tOFF(23) tOEZ(54) High-Z Valid Data-out tCLZ(12) : High or Low PRELIMINARY (November, 2000, Version 0.0) 10 AMIC Technology, Inc. A426316B Series Word Write Cycle (Early Write) tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) UCAS tCRP(9) tCAS(4) LCAS tAR(16) tRAD(6) tASR(10) tRAL(20) tRAH(11) tCAH(25) tASC(24) A0 ~ A7 Row Address Column Address tWCR(29) tCWL(32) tRWL(31) tWP(30) WE tWCS(27) tWCH(28) OE tDHR(35) tDS(33) I/O0 ~ I/O15 tDH(34) Valid Data-in : High or Low PRELIMINARY (November, 2000, Version 0.0) 11 AMIC Technology, Inc. A426316B Series Word Write Cycle (Late Write) tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) UCAS tCRP(9) tCAS(4) LCAS tAR(16) tRAD(6) tASR(10) tRAL(20) tRAH(11) tCAH(25) tASC(24) A0 ~ A7 Row Address Column Address tCWL(32) tRWL(31) tWCR(29) tWP(30) WE tOEH(55) tOED(54) OE tDHR(35) tDS(33) I/O0 ~ I/O15 tDH(34) High-Z Vaild Data-in : High or Low PRELIMINARY (November, 2000, Version 0.0) 12 AMIC Technology, Inc. A426316B Series Word Read-Modify-Write Cycle tRWC(36) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCRP(9) tCAS(4) UCAS LCAS tAR(16) tRAD(6) tASR(10) A0 ~ A7 tRAH(11) tASC(24) Row Address tCAH(25) Column Address tAWD(39) tCWL(32) tCWD38) tRCS(17) tRWD(37) t RWL(31) WE tWP(30) tOED(53) tOEA(52) tOEZ(54) OE tOEH(55) tCAC(14) tAA(15) tDS(33) tDH(34) tRAC(13) I/O0 ~ I/O15 High-Z Data-out Data-in tCLZ(12) : High or Low PRELIMINARY (November, 2000, Version 0.0) 13 AMIC Technology, Inc. A426316B Series EDO Page Mode Word Read Cycle tRASP(47) tRP(2) RAS tCSH(8) tCRP(9) tPC(42) tRSH(7) tCRP(9) tRCD(5) tCP(44) tCAS(4) tCAS(4) tCAS(4) UCAS LCAS tCSH(8) tAR(16) tRAL(20) tCAH(25) tRAD(6) tASR(10) A0 ~ A7 tCAH(25) tRAH(11) tASC(24) tASC(24) Row Column Column tCAH(25) Column tRCS(17) tRCS(17) tRCH(25) tRCH(25) tRCS(17) WE tAA(15) tAA(15) tRRH(19) tCPA(43) tOEA(52) tOEA(52) tOES(26) OE tCAC(14 tRAC(13) tOEP(41) ) tCAC(14) tCOH(21) tCLZ(12) I/O0 ~ I/O15 Data-out tOFF(23) tCAC(14) tOEZ(54) tOEZ(54) Data-out Data-out tCLZ(12) : High or Low PRELIMINARY (November, 2000, Version 0.0) 14 AMIC Technology, Inc. A426316B Series EDO Page Mode Early Word Write Cycle tRASP(47) tRP(2) RAS tCSH(8) tCRP(9) tPC(42) tRSH(7) tCRP(9) tRCD(5) tCAS(4) tCP(44) tCAS(4) tCP(44) tCAS(4) UCAS LCAS tRAL(20) tRAD(6) tASR(10) A0 ~ A7 tCAH(25) tRAH(11) tASC(24) Row tCAH(25) tASC(24) tCAH(25) tASC(24) Column Column tCWL(32) tCWL(32) Column tCWL(32) tRWL(31) tWCS(27) tWCS(27) tWCS(27) tWCH(28) tWCH(28) tWCH(28) WE tWP(30) tWP(30) tWP(30) OE tDH(34) tDS(33) I/O0 ~ I/O15 tDH(34) tDS(33) Data-in tDH(34) tDS(33) Data-in Data-in : High or Low PRELIMINARY (November, 2000, Version 0.0) 15 AMIC Technology, Inc. A426316B Series EDO Page Mode Word Read-Modify-Write Cycle tRP(2) tRASP(47) RAS tCSH(8) tCRP(9) tPCM(45) tRSH(7) tCRP(9) tRCD(5) tCAS(4) tCP(44) tCP(44) tCAS(4) tCAS(4) UCAS LCAS tRAL(20) tRAD(6) tASR(10) tCAH(25) tRAH(11) A0 ~ A7 Row tCAH(25) tCAH(25) tASC(24) t ASC(24) Column tASC(24) Column Column tCWL(32) tCWL(32) tCWL(32) tRWD(37) tRWL(31) tRCS(17) t CWD(38) tCWD(38) tCWD(38) WE tWP(30) tAWD(39) tWP(30) tAWD(39) tWP(30) tAWD(39) tROH(51) tOEA(52) tOEA(52) tOEA(52) OE tOEH(55) tOED(53) tCAC(14) tOED(53) tCPA(43) tAA(15) tCPA(43) tAA(15) tOEZ(54) tAA(15) tOEZ(54) tDH(34) tRAC(13) tOEZ(54) tDH(34) tDH(34) tDS(33) tDS(33) tDS(33) I/O0 ~ I/O15 t OED(53) High-Z tCLZ(12) tCLZ(12) tCLZ(12) Data-in Data-out Data-in Data-out Data-in Data-out : High or Low PRELIMINARY (November, 2000, Version 0.0) 16 AMIC Technology, Inc. A426316B Series RAS Only Refresh Cycle tRC(1) tRAS(3) tRP(2) RAS tRPC(50) tCRP(9) UCAS LCAS tASR(10) tRAH(11) Row A0 ~ A7 Note: WE, OE = Don't care. : High or Low CAS Before RAS Refresh Cycle tRC(1) tRP(2) tRAS(3) tRP(2) RAS tRPC(50) tCHR(49) tCSR(48) tCPN(41) UCAS LCAS tOFF(23) High-Z I/O0 ~ I/O15 Note: WE, OE, A0 ~ A7 = Don't care. PRELIMINARY (November, 2000, Version 0.0) : High or Low 17 AMIC Technology, Inc. A426316B Series Timing Waveform of CAS -before- RAS Refresh Counter Test Cycle tRAS (3) tRP (2) RAS tRSH (7) tCSR (48) tCHR (49) tCPT (56) tCAS (4) CAS tRAL (20) tCAH (25) Address Col Address tAA (15) tCAC (14) tCLZ (12) tOFF (23) I/O Data Out tRRH (19) Read Cycle tRCS (17) tRCH (18) WE tOEA (52) tROH (53) OE tRWL(31) tCWL(32) tWCS(27) tWP(30) tWCH(28) Write Cycle WE tDS (33) I/O tDH (34) Data In OE tWP (30) tAWD(39) tCWD(38) tRCS (17) tCWL(32) Read-Write Cycle WE tOEA(52) tOED (53) OE tAA (15) tCLZ (12) tOEZ (54) tCAC (14) I/O PRELIMINARY Data Out (November, 2000, Version 0.0) 18 tDS (33) tDH (34) Data In AMIC Technology, Inc. A426316B Series Hidden Refresh Cycle (Word Read) tRC(1) tRC(1) tRAS(3) tRP(2) tRAS(3) tRP(2) RAS tAR(16) tCRP(9) tRCD(5) tRSH(7) tCHR(49) tCRP(9) UCAS LCAS tRAD(6) tASR(10) tRAL(20) tCAH(25) tRAH(11) tASC(24) A0 ~ A7 Row Column tRCS(17) tRRH(19) WE tAA(15) OE tCAC(14) tOFF(23) tCLZ(12) tRAC(13) I/O0 ~ I/O15 High-Z Valid Data-out : High or Low PRELIMINARY (November, 2000, Version 0.0) 19 AMIC Technology, Inc. A426316B Series Hidden Refresh Cycle (Early Word Write) tRC(1) tRC(1) tRAS(3) tRP(2) tRAS(3) tRP(2) RAS tAR(16) tCRP(9) tRCD(5) tRSH(7) tCHR(49) tCRP(9) UCAS LCAS tRAD(6) tASR(10) tRAH(11) tRAL(20) tCAH(25) tASC(24) A0 ~ A7 Row Column tWCS(27) tWCH(28) tWP(30) WE OE tDS(33) I/O0 ~ I/O15 tDH(34) Valid Data-in : High or Low PRELIMINARY (November, 2000, Version 0.0) 20 AMIC Technology, Inc. A426316B Series Self Refresh Mode (A426316B-L Only) tPR(2) tRASS(40) tRPS(26) RAS tCHS(21) tCSR(48) tRPC(50) tCRP(9) UCAS LCAS tCPN(41) tASR(10) ROW A0 ~ A7 COL tOFF(23) High-Z I/O0 ~ I/O15 : High or Low Note: WE, OE = Don't care. n Self Refresh Mode. a. Entering the Self Refresh Mode: The A426316B-L Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal “low” longer than 300µs. b. Continuing the Self Refresh Mode: The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode. It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A426316B exits the Self Refresh Mode when the RAS signal is brought “high”. PRELIMINARY (November, 2000, Version 0.0) 21 AMIC Technology, Inc. A426316B Series Capacitance15 (f = 1MHz, Ta = Room Temperature, VCC = 5V ± 10%) Symbol Signals CIN1 A0 – A7 CIN2 RAS , UCAS , Parameter Max. Unit Test Conditions 5 pF Vin = 0V Input Capacitance 7 pF Vin = 0V I/O Capacitance 7 pF Vin = Vout = 0V LCAS , WE , OE CI/O I/O0 - I/O15 Ordering Codes Package\ RAS Access Time 30ns 35ns 40ns Self-Refresh 40L SOJ (400 mil) A426316BS-30 A426316BS-35 A426316BS-40 No 40/44L TSOP type II (400mil) A426316BV-30 A426316BV-35 A426316BV-40 No 40L SOJ (400mil) A426316BS-30L A426316BS-35L A426316BS-40L Yes 40/44L TSOP II (400mil) A426316BV-30L A426316BV-35L A426316BV-40L Yes PRELIMINARY (November, 2000, Version 0.0) 22 AMIC Technology, Inc. A426316B Series Package Information SOJ 40L Outline Dimensions 21 1 20 E 40 HE unit: inches/mm L A A2 C D b b1 A1 e D S Seating Plane Symbol e1 y θ Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A - - 0.144 - - 3.66 A1 0.025 - - 0.64 - - A2 0.105 0.110 0.115 2.67 2.79 2.92 b1 0.026 0.028 0.032 0.66 0.71 0.81 b 0.016 0.018 0.022 0.41 0.46 0.56 C 0.008 0.010 0.014 0.20 0.25 0.36 D 1.020 1.025 1.030 25.91 26.04 26.16 E 0.395 0.400 0.405 10.03 10.16 10.29 e 0.044 0.050 0.056 1.12 1.27 1.42 e1 0.355 0.366 0.376 9.114 9.383 9.652 HE 0.430 0.440 0.450 10.92 11.18 11.43 L 0.081 0.093 0.105 2.083 2.39 2.70 S - - 0.050 - - 1.27 y - - 0.004 - - 0.10 θ 0° - 10° 0° - 10° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. PRELIMINARY (November, 2000, Version 0.0) 23 AMIC Technology, Inc. A426316B Series Package Information TSOP 40/44L (Type II) Outline Dimensions unit: inches/mm HE E 44 θ L L1 1 B e D S A L A1 A2 c D y Dimensions in inches L1 Dimensions in mm Symbol Min Nom Max Min Nom Max A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 0.039 0.041 0.95 1.00 1.05 B 0.013 0.015 0.017 0.32 0.37 0.42 c 0.003 0.005 0.009 0.08 0.13 0.23 D 0.720 0.725 0.730 18.28 18.41 18.54 E 0.395 0.400 0.405 10.03 10.16 10.29 e 0.031 BSC 0.80 BSC HE 0.455 0.463 0.471 11.56 11.76 11.96 0.60 L 0.016 0.020 0.024 0.40 0.50 L1 - 0.031 - - 0.80 - S - - 0.035 - - 0.90 y - - 0.004 - - 0.10 θ 1° 3° 5° 1° 3° 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. PRELIMINARY (November, 2000, Version 0.0) 24 AMIC Technology, Inc.