AD AD9784

14-Bit, 200 MSPS/500 MSPS TxDAC+® with
2×/4×/8× Interpolation and Signal Processing
AD9784
Preliminary Technical Data
FEATURES
PRODUCT DESCRIPTION
14-bit resolution, 200 MSPS input data rate
Selectable 2×/4×/8× interpolation filters
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single or dual-channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface
SFDR: 90 dBc @10 MHz
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = ±0.75 LSB
INL = ±1.5 LSB
3.3 V compatible digital Interface
On-chip 1.2 V reference
80-lead thermally enhanced TQFP package
The AD9784 is a 14-bit, high speed, CMOS DAC with 2×/4×/8×
interpolation and signal processing features tuned for communications applications. It offers state of the art distortion and
noise performance. The AD9784 was developed to meet the
demanding performance requirements of multicarrier and third
generation base stations. The selectable interpolation filters
simplify interfacing to a variety of input data rates while also
taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.
The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single ended or
differential mode. Internal dividers generate the required data
rate interface clocks.
The AD9784 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9784 is
manufactured on an advanced low cost 0.25 µm CMOS process.
APPLICATIONS
Digital quadrature modulation architectures
Multicarrier WCDMA, GSM, TDMA, DCS,
PCS, CDMA Systems
FUNCTIONAL BLOCK DIAGRAM
2×
fDAC/2
fDAC/4
fDAC/8
0
90
CLK–
2×
×2
2×
×4
×8
CLOCK DISTRIBUTION AND CONTROL
LPF
CSB
SCLK
×2/×4/×8/×16
DATA PORT
SYNCHRONIZER
2×
IOUTA
IOUTB
SDO
×1
LATCH
16-BIT DAC
HILBERT
Q
CLOCK
MULTIPLIER
CLK+
ZERO
STUFF
REFIO
SDIO
0
90
DATACLK/
PLL_LOCK
∆t
FSADJ
RESET
03152-PrD-001
P2B[15:0]
90
SPI
P1B[15:0]
DATA ASSEMBLER
0
Re()/Im()
I
REFERENCE
CIRCUITS
2×
×1/×2/×4/×8/×16
2×
CALIBRATION
LATCH
Figure 1.
Rev. PrC
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infringements of patents or other rights of third parties that may result from its use.
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Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9784
Preliminary Technical Data
TABLE OF CONTENTS
Product Highlights ........................................................................... 3
Digital Filter Specifications ........................................................... 23
AD9784–Specifications.................................................................... 4
Digital Interpolation Filter Coefficients.................................. 23
DC Specifications ......................................................................... 4
AD9784 Clock/Data Timing..................................................... 24
Dynamic Specifications ............................................................... 5
Interpolation Modes .................................................................. 27
Digital Specifications ................................................................... 6
Real and Complex Signals......................................................... 28
Pin Configuration and Function Descriptions............................. 7
Modulation Modes..................................................................... 29
Clock .............................................................................................. 7
Power Dissipation ...................................................................... 34
Analog............................................................................................ 8
Dual Channel Complex Modulation with Hilbert ................ 35
Data ................................................................................................ 8
Hilbert Transform Implementation......................................... 36
Serial Interface .............................................................................. 9
Operating the AD9784 Rev E Evaluation Board........................ 40
Definitions of Specifications ......................................................... 10
Power Supplies............................................................................ 40
Typical Performance Charatceristics ........................................... 12
PECL Clock Driver .................................................................... 40
Serial Control Interface.................................................................. 17
Data Inputs.................................................................................. 41
General Operation of the Serial Interface ............................... 17
SPI Port ........................................................................................ 41
Instruction Byte .......................................................................... 17
Operating with PLL Disabled ................................................... 41
Serial Interface Port Pin Descriptions ..................................... 17
Operating with PLL Enabled .................................................... 42
MSB/LSB Transfers..................................................................... 18
Analog Output ............................................................................ 42
Notes on Serial Port Operation ................................................ 18
Outline Dimensions ....................................................................... 52
Mode Control (via SPI Port) ......................................................... 19
ESD Caution................................................................................ 52
REVISION HISTORY
Revision PrC: Preliminary Version
Rev. PrC | Page 2 of 52
Preliminary Technical Data
AD9784
PRODUCT HIGHLIGHTS
1.
The AD9784 is a member of a high speed interpolating
TxDAC+ family with 16-/14-/12-bit resolutions.
6.
Flexible clock with single-ended or differential input:
CMOS, 1 V p-p sine wave and LVPECL capability.
2.
2×/4×/8× user selectable interpolating filter eases data rate
and output signal reconstruction filter requirements.
7.
3.
200 MSPS input data rate.
4.
Ultrahigh speed 500 MSPS DAC conversion rate.
Complete CMOS DAC function operates from a 2.7 V to
3.6 V single analog (AVDD) supply and a 2.5 V (DVDD)
digital supply. The DAC full-scale current can be reduced
for lower power operation, and a sleep mode is provided
for low-power idle periods.
5.
Internal PLL/clock divider provides data rate clock for easy
interfacing.
8.
On-chip voltage reference: The AD9784 includes a 1.20 V
temperature-compensated band gap voltage reference.
Rev. PrC | Page 3 of 52
AD9784
Preliminary Technical Data
AD9784–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, unless
otherwise noted
Parameter
RESOLUTION
DC Accuracy1
Integral Nonlinearity
Differential Nonlinearity
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (Ext Reference Mode)
Small Signal Bandwith
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
AVDD1, AVDD2
Voltage Range
Analog Supply Current (IAVDD1)
Analog Supply Current (IAVDD2)
IAVDD1 in SLEEP Mode
ACVDD, ADVDD
Voltage Range
Analog Supply Current (IACVDD)
Analog Supply Current (IADVDD)
CLKVDD
Voltage Range
Clock Supply Current (ICLKVDD)
DVDD
Voltage Range
Digital Supply Current (IDVDD)
DRVDD
Voltage Range
Digital Supply Current (IDRVDD)
Nominal Power Dissipation4
OPERATING RANGE
Min
Typ
14
Unit
Bits
1.5
0.75
LSB
LSB
TBD
3
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
10
–1.0
1.14
Max
20
+1.0
1.20
1
0.1
1.26
V
µA
1.25
V
MΩ
MHz
10
0.5
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm /°C
3.1
3.3
3.5
V
mA
mA
mA
2.35
2.5
2.65
V
mA
mA
2.35
2.5
2.65
V
mA
2.35
2.5
2.65
V
mA
2.35
2.5/3.3
3.5
V
mA
W
°C
1.25
–40
1
Measured at IOUTA driving a virtual ground.
Nominal full-scale current, IOUTFS, is 32× the IREF current.
3
Use an external amplifier to drive any external load.
4
Measured under the following conditions: fDATA = 125 MSPS, fDAC = 500 MSPS, 4× Interpolation, fDAC/4 Modulation, Hilbert Off.
2
Rev. PrC | Page 4 of 52
+85
Preliminary Technical Data
AD9784
DYNAMIC SPECIFICATIONS
Table 2. TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA,
Differential Transformer Coupled Output, 50 Ω Doubly Terminated, unless otherwise noted
Parameter
DYNAMIC PERFORMANCE
Maximum DAC Output Update Rate (fDAC)
Output Settling Time (tST) (to 0.025%)
Output Propogation Delay5 (tPD)
Output Rise Time (10%–90%)6
Output Fall Time (90%–10%)6
Output Noise (IOUTFS = 20 mA)
AC LINEARITY—BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS)
fDATA = 160 MSPS; fOUT= 1 MHz
fDATA = MSPS; fOUT = MHz
fDATA = MSPS; fOUT = MHz
fDATA = MSPS; fOUT = MHz
fDATA = MSPS; fOUT = MHz
fDATA = MSPS; fOUT = MHz
Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = –6 dBFS)
fDATA = 160 MSPS; fOUT1 = 25 MHz; fOUT2 = 31 MHz
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
Total Harmonic Distortion (THD)
fDATA = MSPS; fOUT = MHz; 0 dBFS
fDATA = MSPS; fOUT = MHz; 0 dBFS
Signal-to-Noise Ratio (SNR)
fDATA = MSPS; fOUT = MHz; 0 dBFS
fDATA = MSPS; fOUT = MHz; 0 dBFS
Adjacent Channel Power Ratio (ACPR)
WCDMA with MHz BW, MHz Channel Spacing
IF = 16 MHz, fDATA = 65.536 MSPS
IF = 32 MHz, fDATA = 131.072 MSPS
Four-Tone Intermodulation
MHz, MHz, MHz and MHz at –12 dBFS (fDATA = MSPS, Missing Center)
AC LINEARITY—IF MODE
Four-Tone Intermodulation at IF = MHz
MHz, MHz, MHz and MHz at dBFS
fDATA = MSPS, fDAC = MHz
5
6
Propagation delay is delay from CLK input to DAC update.
Measured single-ended into 50 Ω load.
Rev. PrC | Page 5 of 52
Min
Typ
500
Max
Unit
MSPS
ns
ns
ns
ns
pA√Hz
95
dBc
dBc
dBc
dBc
dBc
80
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dBFS
dBFS
dBc
dBc
dBFS
dBFS
AD9784
Preliminary Technical Data
DIGITAL SPECIFICATIONS
Table 3. TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V, IOUTFS = 20 mA, unless otherwise
noted
Parameter
DIGITAL INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
LOCK INPUTS
Input Voltage Range
Common-Mode Voltage
Differential Voltage
PLL CLOCK ENABLED
Input Setup Time (ts)
Input Hold Time (tH)
Latch Pulse Width (tLPW)
PLL CLOCK DISABLED
Input Setup Time (ts)
Input Hold Time (tH)
Latch Pulse Width (tLPW)
CLK to PLLLOCK Delay (tOD)
Min
Typ
DRVDD – 0.9
DRVDD
0
–10
–10
Max
Unit
0.9
+10
+10
V
V
µA
µA
pF
5
0
0.75
0.5
1.5
1.5
2.65
2.25
V
V
V
ns
ns
ns
ns
ns
ns
ns
Rev. PrC | Page 6 of 52
Preliminary Technical Data
AD9784
DNC
ADVDD
ADGND
ACVDD
ACGND
AVDD2
AVDD1
AGND2
AGND1
IOUTA
IOUTB
AGND1
AVDD1
AGND2
AVDD2
ACGND
ADGND
ACVDD
ADVDD
NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
FSADJ
59
REFIO
CLKVDD 3
58
RESET
CLKGND 4
57
CSB
CLK+ 5
56
SCLK
CLK– 6
55
SDIO
CLKGND 7
54
SDO
DGND 8
53
DGND
DVDD 9
52
DVDD
51
P2B0
50
P2B1
P1B13 12
49
P2B2
P1B12 13
48
P2B3
P1B11 14
47
P2B4
P1B10 15
46
P2B5
DGND 16
45
DGND
DVDD 17
44
DVDD
P1B9 18
P1B8 19
43
P2B6
42
P2B7
P1B7 20
41
P2B8
CLKVDD 1
LPF 2
PIN 1
IDENTIFIER
AD9784
P1B15 10
TOP VIEW
(Not to Scale)
P1B14 11
03151-PrD-001
P2B10
P2B9
P2B11
P2B12
DGND
DVDD
IQSEL/P2B15
ONEPORTCLOCK/P2B14
P2B13
DRVDD
DATACLK/PLL_LOCK
P1B0
P1B2
P1B1
DVDD
DGND
P1B3
P1B4
P1B5
NC = NO CONNECT
P1B6
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 2. Pin Configuration
CLOCK
Table 4. Clock Pin Function Descriptions
Pin
No.
5, 6
2
31
Mnemonic
CLK+, CLK–
LPF
DATACLK/PLL_LOCK
Direction
I
I/O
I/O
Description
Differential Clock Input.
PLL Loop Filter.
PLOCKEXT DCLKEXT
04h[0]
02h[3]
0
0
0
1
1, 3
4, 7
CLKVDD
CLKGND
1
X
Mode
Pin configured for input of channel data rate or synchronizer clock.
Internal clock synchronizer may be turned on or off with DCLKCRC
(02h[2]).
Pin configured for output of channel data rate or synchronizer clock
Internal Clock PLL Status Output:
0: Internal clock PLL is not locked.
1: Internal clock PLL is locked.
Clock Domain 2.5 V.
Clock Domain 0 V.
Rev. PrC | Page 7 of 52
AD9784
Preliminary Technical Data
ANALOG
Table 5. Analog Pin Function Descriptions
Pin No.
59
60
70, 71
61
62, 79
63, 78
64, 77
65, 76
66, 75
67, 74
68, 73
69, 72
Mnemonic
REFIO
FSADJ
IOUTB, IOUTA
DNC
ADVDD
ADGND
ACVDD
ACGND
AVDD2
AGND2
AVDD1
AGND1
Direction
A
A
A
Description
Reference.
Full-Scale Adjust.
Differential DAC Output Currents.
Do not connect.
Analog Domain Digital Content 2.5 V.
Analog Domain Digital Content 0 V.
Analog Domain Clock Content 2.5 V.
Analog Domain Clock Content 0 V.
Analog Domain Clock Switching 3.3 V.
Analog Domain Switching 0 V.
Analog Domain Quiet 3.3 V.
Analog Domain Quiet 0 V.
DATA
Table 6. Data Pin Function Descriptions
Pin No.
10–15, 18–24,
27–29
Mnemonic
P1B15–P1B0
Direction
I
32
IQSEL/P2B15
I
33
ONEPORTCLK/P2B14
I/O
34, 37–43,
46–51
30
9, 17, 26,
36, 44, 52
8, 16, 25,
35, 45, 53
P2B13–P2B0
I
Description
Input Data Port One.
ONEPORT
02h[6]
Mode
0
Latched Data Routed for 1 Channel Processing.
1
Latched Data Demultiplexed by IQSEL and Routed for Interleaved
I/Q Processing.
ONEPORT
IQPOL IQSEL/
02h[6]
02h[1] P2B15 Mode (IQPOL == 0)
0
X
X
Latched data routed to Q channel bit 15(MSB)
processing.
1
0
0
Latched data on data port one routed to Q
channel processing.
1
0
1
Latched data on data port one routed to I
channel processing.
1
1
0
Latched data on data port one routed to I
channel processing.
1
1
1
Latched data on data port one routed to Q
channel processing.
ONEPORT
02h[6]
0
Latched data routed for Q channel Bit 14 processing.
1
Pin configured for output of clock at twice the channel data route.
Input Data Port Two Bits 13–0.
DRVDD
DVDD
Digital Output Pin Supply, 2.5 V or 3.3 V.
Digital Domain 2.5 V.
DGND
Digital Domain 0 V.
Rev. PrC | Page 8 of 52
Preliminary Technical Data
AD9784
SERIAL INTERFACE
Table 7. Serial Interface Pin Function Descriptions
Pin No.
54
Mnemonic
SDO
Direction
O
55
SDIO
I/O
56
57
58
SCLK
CSB
RESET
I
I
I
Description
SDIODIR
CSB 00h[7]
Mode
1
X
High Impedance.
0
0
Serial Data Output.
0
1
High Impedance.
SDIODIR
CSB 00h[7]
Mode
1
X
High Impedance.
0
0
Serial Data Output.
0
1
Serial Data Input/Output Depending on Bit 7 of the Serial Instruction Byte.
Serial interface clock.
Serial interface chip select.
Resets entire chip to default state.
Rev. PrC | Page 9 of 52
AD9784
Preliminary Technical Data
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Integral Nonlinearity or INL)
Glitch Impulse
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Differential Nonlinearity (or DNL)
Spurious-Free Dynamic Range
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.
Monotonicity
Total Harmonic Distortion
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Signal-to-Noise Ratio (SNR)
S/N is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc. The
value for SNR is expressed in decibels.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed
which has a sharp transition band near fDATA/2. Images which
would typically appear around fDAC (output data rate) can be
greatly suppressed.
Pass-Band
Frequency band in which any input applied therein passes
unattenuated to the DAC output.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Stop-Band Rejection
The amount of attenuation of a frequency outside the passband applied to the DAC, relative to a full-scale signal applied at
the DAC input within the pass-band.
Group Delay
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Number of input clocks between an impulse applied at the
device input and peak DAC output current. A half-band FIR
filter has constant group delay over its entire frequency range
Settling Time
Impulse Response
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Response of the device to an impulse applied to the input.
Rev. PrC | Page 10 of 52
Preliminary Technical Data
AD9784
Adjacent Channel Power Ratio (or ACPR)
Complex Image Rejection
A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
In a traditional two part upconversion, two images are created
around the second IF frequency. These images are redundant
and have the effect of wasting transmitter power and system
bandwidth. By placing the real part of a second complex
modulator in series with the first complex modulator, either the
upper or lower frequency image near the second IF can be
rejected.
Complex Modulation
The process of passing the real and imaginary components of a
signal through a complex modulator (transfer function = ejwt =
coswt + jsinwt) and realizing real and imaginary components
on the modulator output.
Rev. PrC | Page 11 of 52
AD9784
Preliminary Technical Data
TYPICAL PERFORMANCE CHARATCERISTICS
–000
–000
–000
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
(TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, Differential Transformer
Coupled Output, 50 Ω Doubly Terminated, unless otherwise noted)
TBD
–000
–000
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
–000
TBD
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 6. Single-Tone Spectrum @ FDATA = 78 MSPS with FOUT = FDATA/3
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
–000
–000
–000
Figure 3 Single-Tone [email protected] FDATA = 65 MSPS With FOUT = FDATA/3
–000
TBD
–000
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
Figure 4. In-Band SFDR vs. FOUT @ FDATA = 65 MSPS
–000
–000
–000
–000
TBD
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 7. In-Band SFDR Vs. FOUT @ FDATA = 78 MSPS
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
TBD
–000
–000
TBD
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 5. Out-of-Band SFDR vs. FOUT @ FDATA = 65 MSPS
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
Figure 8. Out-of-Band SFDR vs. FOUT @ FDATA = 78 MSPS
Rev. PrC | Page 12 of 52
–000
AD9784
–000
–000
–000
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
Preliminary Technical Data
TBD
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
Figure 9. Single-Tone Spectrum @ FDATA = 160 MSPS with FOUT = FDATA/3
–000
–000
–000
TBD
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 12. Third Order IMD Products vs. FOUT @ FDATA = 65 MSPS
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
TBD
–000
–000
–000
–000
–000
TBD
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
Figure 10. In-Band SFDR vs. FOUT @ FDATA = 160 MSPS
–000
–000
–000
–000
TBD
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 13. Third Order IMD Products vs. FOUT @ FDATA = 78 MSPS
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
–000
–000
TBD
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 11. Out-of-Band SFDR vs. FOUT @ FDATA = 160 MSPS
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 14. Third Order IMD Products vs. FOUT @ FDATA = 160 MSPS
Rev. PrC | Page 13 of 52
Preliminary Technical Data
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
AD9784
TBD
–000
–000
–000
–000
TBD
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
Figure 15. TPC 13. Third Order IMD Products vs. FOUT and Interpolation Rate
1× – FDATA = 160 MSPS
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 18. 3rd Order IMD Products vs. AVDD @ FOUT = 10 MHz,
FDAC = 320 MSPS, FDATA = 160 MSPS
2× – FDATA = 160 MSPS
4× – FDATA = 80 MSPS
8× – FDATA = 50 MSPS
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
–000
–000
–000
TBD
–000
TBD
–000
–000
–000
–000
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
Figure 19. SNR vs. Data Rate for fOUT = 5 MHz
Figure 16. Third Order IMD Products vs. AOUT and Interpolation Rate FDATA =
50 MSPS for All Cases
1× – FDAC = 50 MSPS
2× – FDAC = 100 MSPS
4× – FDAC = 200 MSPS
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
8× – FDAC = 400 MSPS
TBD
–000
–000
–000
–000
TBD
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
Figure 17. SFDR vs. AVDD @ FOUT = 10 MHz; FDAC = 320 MSPS FDATA = 160 MSPS
Rev. PrC | Page 14 of 52
–000
–000
–000
ALL CAPS (Initial caps)
Figure 20. SFDR vs. Temperature @ fOUT = fDATA/11
–000
AD9784
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
Preliminary Technical Data
TBD
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
TBD
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
TBD
TBD
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
TBD
–000
–000
–000
–000
–000
Figure 25. Single Tone Spurious Performance, FOUT = 10 MHz,
FDATA = 80 MSPS, Interpolation = 4×
Figure 22. Two Tone IMD Performance, FDATA = 150 MSPS, No Interpolation
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
–000
–000
Figure 24. Two Tone IMD Performance, FDATA = 90 MSPS, Interpolation = 4×
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
–000
–000
–000
–000
–000
TBD
–000
Figure 21. Single Tone Spurious Performance, fOUT = 10 MHz, fDATA = 150 MSPS,
No Interpolation
ALL CAPS (Initial caps)
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
Figure 23. Single Tone Spurious Performance, FOUT = 10 MHz, FDATA = 150
MSPS, Interpolation = 2×
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 26. Two Tone IMD Performance, FOUT = 10 MHz, FDATA = 50 MSPS,
Interpolation = 8×
Rev. PrC | Page 15 of 52
Preliminary Technical Data
–000
–000
–000
–000
–000
ALL CAPS (Initial caps)
ALL CAPS (Initial caps)
AD9784
TBD
–000
–000
–000
–000
TBD
–000
–000
–000
–000
ALL CAPS (Initial caps)
–000
–000
–000
Figure 27. Single Tone Spurious Performance, FOUT = 10 MHz, FDATA = 50 MSPS,
Interpolation = 8×
–000
–000
–000
ALL CAPS (Initial caps)
–000
Figure 28. Eight Tone IMD Performance, FDATA = 160 MSPS, Interpolation = 8×
Rev. PrC | Page 16 of 52
Preliminary Technical Data
AD9784
SERIAL CONTROL INTERFACE
INSTRUCTION BYTE
SDO (PIN 54)
SCLK (PIN 56)
AD9784 SPI
PORT INTERFACE
CSB (PIN 57)
The instruction byte contains the following information:
03151-PrD-002
SDIO (PIN 55)
Table 8.
Figure 29. AD9784 SPI Port Interface
The AD9784 serial port is a flexible, synchronous serial
communications port allowing easy interface to many industrystandard microcontrollers and microprocessors. The serial I/O
is compatible with most synchronous transfer formats,
including both the Motorola SPI® and Intel® SSR protocols. The
interface allows read/write access to all registers that configure
the AD9784. Single or multiple byte transfers are supported as
well as MSB first or LSB first transfer formats. The AD9784’s
serial interface port can be configured as a single pin I/O
(SDIO) or two unidirectional pins for in/out (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the
AD9784. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9784, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9784 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, the number of bytes in
the data transfer, and the starting register address for the first
byte of the data transfer. The first eight SCLK rising edges of
each communication cycle are used to write the instruction byte
into the AD9784.
A logic high on the CS pin, followed by a logic low, will reset the
SPI port timing to the initial state of the instruction cycle. This
is true regardless of the present state of the internal registers or
the other signal levels present at the inputs to the SPI port. If the
SPI port is in the midst of an instruction cycle or a data transfer
cycle, none of the present data will be written.
The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the AD9784 and the system controller. Phase 2 of the
communication cycle is a transfer of 1, 2, 3, or 4 data bytes as
determined by the instruction byte. Normally, using one
multibyte transfer is the preferred method. However, single byte
data transfers are useful to reduce CPU overhead when register
access requires one byte only. Registers change immediately
upon writing to the last bit of each transfer byte.
N1
0
0
1
1
N2
0
1
0
1
Description
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer will occur after the instruction byte write.
Logic high indicates read operation. Logic 0 indicates a write
operation. N1, N0, Bits 6 and 5 of the instruction byte,
determine the number of bytes to be transferred during the data
transfer cycle. The bit decodes are shown in the following table:
Table 9.
MSB
17
R/W
16
N1
15
N0
14
A4
13
A3
12
A2
11
A1
LSB
10
A0
A4, A3, A2, A1, A0, Bits 4, 3, 2, 1, 0 of the instruction byte,
determine which register is accessed during the data transfer
portion of the communications cycle. For multibyte transfers,
this address is the starting byte address. The remaining register
addresses are generated by the AD9784.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock. The serial clock pin is used to
synchronize data to and from the AD9784 and to run the
internal state machines. SCLK’s maximum frequency is 15 MHz.
All data input to the AD9784 is registered on the rising edge of
SCLK. All data is driven out of the AD9784 on the falling edge
of SCLK.
CSB—Chip Select. Active low input starts and gates a communication cycle. It allows more than one device to be used on
the same serial communications lines. The SDO and SDIO pins
will go to a high impedance state when this input is high. Chip
select should stay low during the entire communication cycle.
SDIO—Serial Data I/O. Data is always written into the
AD9784 on this pin. However, this pin can be used as a
bidirectional data line. The configuration of this pin is
controlled by Bit 7 of register address 00h. The default is
Logic 0, which configures the SDIO pin as unidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In the
case where the AD9784 operates in a single bidirectional I/O
mode, this pin does not output data and is set to a high
impedance state.
Rev. PrC | Page 17 of 52
AD9784
Preliminary Technical Data
MSB/LSB TRANSFERS
INSTRUCTION CYCLE
R/W N1 N0 A4A 3A
2A 1A
SDO
D30 D20 D10 D00
D7 D6N D5N
D30 D20 D10 D00
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SDIO
A0
A1 A2
A3 A4
N0 N1 R/W D00 D10 D20
D4N D5N D6N D7N
D00 D10 D20
D4N D5N D6N D7N
SDO
03152-PrD-005
SCLK
Figure 31. Serial Register Interface Timing LSB First
tDS
tSCLK
CSB
tPWH
The same considerations apply to setting the software reset,
SWRST (00h[5]) bit. All other registers are set to their default
values but the software reset doesn’t affect the bits in register
address 00h and 04h.
D7 D6N D5N
Figure 30. Serial Register Interface Timing MSB First
NOTES ON SERIAL PORT OPERATION
The AD9784 serial port configuration bits reside in Bits 6 and 7
of register address 00h. It is important to note that the
configuration changes immediately upon writing to the last bit
of the register. For multibyte transfers, writing to this register
may occur during the middle of communication cycle. Care
must be taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.
0
03152-PrD-004
SDIO
tPWL
SCLK
tDS
SDIO
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
03152-PrD-006
The AD9784 serial port controller address will increment from
1Fh to 00h for multibyte I/O operations if the MSB first mode is
active. The serial port controller address will decrement from
00h to 1Fh for multibyte I/O operations if the LSB first mode is
active.
SCLK
Figure 32. Timing Diagram for Register Write
CSB
SCLK
tDV
SDIO
SDO
It is recommended to use only single byte transfers when
changing serial port configurations or initiating a software
reset.
DATA BIT n
DATA BIT n–1
Figure 33. Timing Diagram for Register Read
Rev. PrC | Page 18 of 52
03152-PrD-007
The AD9784 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by register address DATADIR
(00h[6]). The default is MSB first. When this bit is set active
high, the AD9784 serial port is in LSB first format. That is, if the
AD9784 is in LSB first mode, the instruction byte must be
written from least significant bit to most significant bit.
Multibyte data transfers in MSB format can be completed by
writing an instruction byte that includes the register address of
the most significant byte. In MSB first mode, the serial port
internal byte address generator decrements for each byte
required of the multibyte communication cycle. Multibyte data
transfers in LSB first format can be completed by writing an
instruction byte that includes the register address of the least
significant byte. In LSB first mode, the serial port internal byte
address generator increments for each byte required of the
multibyte communication cycle.
DATA TRANSFER CYCLE
CSB
Preliminary Technical Data
AD9784
MODE CONTROL (VIA SPI PORT)
Table 10.
Address
COMMS
FILTER
DATA
MODULATE
PLL
DCLKCRC
VERSION
CALMEMCK
MEMRDWR
MEMADDR
MEMDATA
DCRSTAT
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
Bit 7
SDIODIR
INTERP[1]
DATAFMT
CHANNEL
PLLON
DATADJ[3]
Bit 6
DATADIR
INTERP[0]
ONEPORT
HILBERT
PLLMULT[1]
DATADJ[2]
RESERVED
CALSTAT
MEMADDR[7]
RESERVED
CALEN
MEMADDR[6]
Bit 5
SWRST
Bit 4
SLEEP
DCLKSTR
MODDUAL
PLLMULT[0]
DATADJ[1]
CALMEM[1]
XFERSTAT
MEMADDR[5]
MEMDATA[5]
Bit 3
PDN
ZSTUFF
DCLKPOL
DCLKEXT
SIDEBAND
MOD[1]
PLLDIV[1]
PLLDIV[0]
DATADJ[0]
MODSYNC
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VERSION[3]
CALMEN[0]
XFEREN
SMEMWR
MEMADDR[4]
MEMADDR[3]
MEMDATA[4]
MEMDATA[3]
Bit 2
HPFX8
DCLKCRC
MOD[0]
PLLAZ[1]
MODADJ[2]
VERSION[3]
CALCKDIV[2]
SMEMRD
MEMADDR[2]
MEMDATA[2]
DCRSTAT[2]
Bit 1
PLLLOCK
HPFX4
IQPOL
Bit 0
EXREF
HPFX2
CRAYDIN
PLLAZ[0]
MODADJ[1]
PLOCKEXT
MODADJ[0]
VERSION[3]
CALCKDIV[2]
FMEMRD
MEMADDR[1]
MEMDATA[1]
DCRSTAT[1]
VERSION[3]
CALCKDIV[2]
UNCAL
MEMADDR[0]
MEMDATA[0]
DCRSTAT[0]
Table 11.
COMMS(00)
SDIODIR
Bit
7
Direction
I
Default
0
DATADIR
6
I
0
SWRST
SLEEP
PDN
PLLOCK
5
4
3
1
I
I
I
O
0
0
0
0
EXREF
0
I
0
Description
0: SDIO pin configured for input only during data transfer
1: SDIO configured for input or output during data transfer
0: Serial data uses MSB first format
1: Serial data uses LSB first format
1: Default all serial register bits, except addresses 00h and 04h
1: DAC output current off
1: All analog and digital circuitry, except serial interface, off
0: With PLL on, indicates that PLL is not locked
1: With PLL on, indicates that PLL is locked
0: Internal band gap reference
1: External reference
Table 12.
FILTER(01)
INTERP[1:0]
Bit
[7:6]
Direction
I
Default
00
ZSTUFF
HPFX8
3
2
I
I
0
0
HPFX4
1
I
0
HPFX2
0
I
0
Description
00: No interpolation
01: Interpolation 2×
10: Interpolation 4×
11: Interpolation 8×
1: Zero Stuffing on
0: ×8 interpolation filter configured for low pass
1: ×8 interpolation filter configured for high pass
0: ×4 interpolation filter configured for low pass
1: ×4 interpolation filter configured for high pass
0: ×2 interpolation filter configured for low pass
1: ×2 interpolation filter configured for high pass
Rev. PrC | Page 19 of 52
AD9784
Preliminary Technical Data
Table 13.
DATA(02)
DATAFMT
Bit
7
Direction
I
Default
0
ONEPORT
6
I
0
DCLKSTR
5
I
0
DCLKPOL
4
I
0
DCLKEXT
3
I
0
DCLKCRC
2
I
0
IQPOL
1
I
0
GRAYDIN
0
I
0
Description
0: Twos complement data format
1: Unsigned binary input data format
0: I and Q input data onto ports one and two respectively
1: I and Q input data interleaved onto port one
0: DATACLK pin 12 mA drive strength
1: DATACLK pin 24 mA drive strength
0: Input data latched on DATACLK rising edge
1: Input data latched on DATACLK falling edge
0: With PLOCKEXT off, DATACLK pin inputs channel data rate or modulator synchronizer clock
1: With PLOCKEXT off, DATACLK pin outputs channel data rate or modulator synchronizer clock
0: With PLOCKEXT off, and DATACLK pin as input, DATACLK clock recovery off
1: With PLOCKEXT off, and DATACLK pin as input, DATACLK clock recovery on
0: In one port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data into Q channel
1: In one port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data into Q channel
0: Gray decoder off
1: Gray decoder on
Table 14.
MODULATE(03)
CHANNEL
Bit
7
Direction
I
Default
0
HILBERT
MODDUAL
6
5
I
I
0
0
SIDEBAND
4
I
0
MOD[1:0]
[3:2]
I
00
Description
MODDUAL
CHANNEL
03h [5]
03h[7]
0
0
I channel processing routed to DAC
0
1
Q channel processing routed to DAC
1
0
Modulator real output routed to DAC
1
1
Modulator imaginary output routed to DAC
1: With MODDUAL on, Hilbert transform on
0: Modulator uses a single channel
1: Modulator uses both I and Q channels
0: With MODDUAL on, lower sideband rejected
1: With MODDUAL on, upper sideband rejected
00: No modulation
01: fS/2 modulation
10: fS /4 modulation
11: fS /8 modulation
Rev. PrC | Page 20 of 52
Preliminary Technical Data
AD9784
Table 15.
PLL(04)
PLLON
Bit
7
Direction
I
Default
0
PLLMULTI[1:0]
[6:5]
I
00
PLLDIV[1:0]
[4:3]
I
00
PLLAZBW[1:0]
[2:1]
I
00
PLOCKEXT
0
I
0
Description
0: PLL off
1: PLL on
PLL MULTIPLY FACTOR
00: ×2
00: ×4
00: ×8
00: ×16
PLLMULT rate divide factor
00:/1
00:/2
00:/4
00:/8
PLL Autozero settling bandwidth as fraction of CLK ±rate
00: /8 (lowest)
01: /4
10: /2 (highest)
0: With PLL on, DATACLK/PLL_LOCK pin configured for DATACLK input/output
1: With PLL on, DATACLK/PLL_LOCK pin configured for output of PLLLOCK
Table 16.
DCLKCRC(05)
DATADJ[3:0]
Bit
[7:4]
Direction
I
Default
0000
MODSYNC
3
I
00
MODADJ[2:0]
[2:0]
I
000
Description
DATACLK offset. Twos complement respresentation
0111: +7
:
0000: 0
:
1000: -8
0: With PLOCKEXT off, channel data rate clock synchronizer mode
1: With PLOCKEXT off, state machine clock synchronizer mode
Modulator coefficient offset
fS/8
fS/4
fS/2
000
1
1
1
001
1/√2
0
–1
010
0
–1
1
011
–1/√2
0
–1
100
–1
1
1
101
–1/√2
0
–1
110
0
–1
1
111
1/√2
0
–1
Table 17.
VERSION(0D)
VERSION[3:0]
Bit
[3:0]
Direction
O
Default
–
Rev. PrC | Page 21 of 52
Description
Hardware version identifier
AD9784
Preliminary Technical Data
Table 18.
CALMEMCK(OE)
CALMEM
Bit
[5:4]
Direction
O
Default
00
CALCKDIV[2:0]
[2:0]
I
00
Description
Calibration memory
00: Uncalibrated
01: Self Calibration
10: Factory calibration
11: User input
Calibration clock divide ratio from channel data rate
000: /32
001: /64
:
110: /2048
111: /4096
Table 19.
MEMRDWR(OF)
CALSTAT
Bit
7
Direction
O
Default
0
CALEN
XFERSTAT
6
5
I
O
0
0
XFEREN
SMEMWR
SMEMRD
FMEMRD
UNCAL
4
3
2
1
0
I
I
I
I
I
0
0
0
0
0
Description
0: Self Calibration cycle not complete
1: Self Calibration cycle complete
1: Self Calibration in progress
0: Factory memory transfer not complete
1: Factory memory transfer complete
1: Factory memory transfer in progress
1: Write static memory data from external port
1: Read static memory to external port
1: Read factory memory data to external port
1: Use uncalibrated
Table 20.
MEMADDR(10)
MEMADDR [7:0]
Bit
[7:0]
Direction
I/O
Default
00000000
Description
Address of factory or static memory to be accessed
Table 21.
MEMDATA(11)
MEMDATA [5:0]
Bit
[5:0]
Direction
I/O
Default
000000
Description
Data or factory or static memory access
Table 22.
DCRCSTAT(12)
DCRCSTAT (2)
Bit
2
Direction
O
Default
0
DCRCSTAT(1)
1
O
0
DCRCSTAT(0)
0
O
0
Description
0: With DATACLK CRC on, lock has never been achieved
1: With DATACLK CRC on, lock has been achieved at least once
0: With DATACLK CRC on, system is currently not locked
1: With DATACLK CRC on, system is currently locked
0: With DATACLK CRC on, system is currently locked
1: With DATACLK CRC on, system lost lock due to jitter
Rev. PrC | Page 22 of 52
Preliminary Technical Data
AD9784
DIGITAL FILTER SPECIFICATIONS
DIGITAL INTERPOLATION FILTER COEFFICIENTS
–20
Upper Coefficient
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
H(28)
H(27)
H(26)
H(25)
H(24)
H(23)
Integer Value
9
0
–27
0
65
0
–131
0
239
0
–407
0
665
0
–1070
0
1764
0
–3273
0
10358
16384
–40
–60
–80
–100
–120
–140
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
Figure 34. ×2 Interpolation Filter Response
0
–20
–40
–60
–80
–100
0.5
03152-PrD-009
0.5
03152-PrD-010
–120
Table 24. Stage 2 Interpolation Filter Coefficients
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
Upper Coefficient
H(19)
H(18)
H(17)
H(16)
H(15)
H(14)
H(13)
H(12)
H(11)
Integer Value
19
0
–120
0
436
0
–1284
0
5045
8192
03152-PrD-008
Table 23. Stage 1 Interpolation Filter Coefficients
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
0
–140
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
Figure 35. ×4 Interpolation Filter Response
0
–20
–40
–60
–80
Table 25. Stage 3 Interpolation Filter Coefficients
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
Upper Coefficient
H(11)
H(10)
H(9)
H(8)
H(7)
Integer Value
7
0
–53
0
302
512
–100
–120
–140
–0.5
Rev. PrC | Page 23 of 52
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
Figure 36. ×8 Interpolation Filter Response
AD9784
Preliminary Technical Data
AD9784 CLOCK/DATA TIMING
DLL Disabled, Two-Port Data Mode, DATACLK as Output
With the interpolation set to 1×, the DATACLK output is a
delayed and inverted version of DACCLK at the same
frequency. Note that DACCLK refers to the differential clock
inputs applied at Pins 5 and 6. As Figure 37 shows, there is a
constant delay between the rising edge of DACCLK and the
falling edge of DATACLK.
The DCLKPOL bit (Reg 02 Bit 4) allows the data to be latched
into the AD9784 on either the rising or falling edge of
DACCLK. With DCLKPOL = 1, the data is latched in on the
rising edge of Diff Clk, as shown in Figure 37. With DCLKPOL
= 0, as shown in Figure 38, data is latched in on the falling edge
of DACCLK. The setup and hold times are always with respect
to the latched edge of DACCLK.
DACCLKIN
DATACLKOUT
tD = 5ns TYP
t12
tH = 2.9ns TYP
DATA
03152-PrD-066
tS = –0.5ns TYP
Figure 37. Data Timing, DLL Off, 1× Interpolation, DCLKPOL = 1
DACCLKIN
DATACLKOUT
tD = 6ns TYP
tH = 2.9ns TYP
DATA
Figure 38. Data Timing, DLL Off, 1× Interpolation, DCLKPOL = 0
Rev. PrC | Page 24 of 52
03152-PrD-067
tS = –0.5ns TYP
Preliminary Technical Data
AD9784
With the interpolation set to 2×, the DACCLK input runs at
twice the speed of the DATACLK. Data is latched into the
AD9784’s inputs on every other rising edge of DACCLK, as
shown in Figure 40 and Figure 41. With DCLKPOL = 1, as
shown in Figure 40, the latching edge of DACCLK is the rising
edge that occurs just before the falling edge of DATACLK. With
DCLKPOL = 0, as in Figure 41, the latching edge of DACCLK is
the rising edge of DACCLK that occurs just before the rising
edge of DATACLK. The setup and hold time values are identical
to those in Figure 37 and Figure 38.
interpolation mode. Again, similar to operation in the 2×
interpolation mode, with DCLKPOL = 1, the latching edge of
DACCLK is the rising edge that occurs just before the falling
edge of DATACLK. With DCLKPOL = 0, the latching edge of
DACCLK is the rising edge that occurs just before the rising
edge of DATACLK. The setup and hold time values are identical
to those in 1× and 2× interpolation
03152-PrD-068
Note that there is a slight difference in the delay from the rising
edge of DACCLK to the falling edge of DATACLK, and the
delay from the rising edge of DACCLK to the rising edge of
DATACLK. As Figure 39 shows, the DATACLK duty cycle is
slightly less than 50%. This is true in all modes.
With the interpolation set to 4× or 8×, the DACCLK input runs
at 4× or 8× the speed of the DATACLK output. The data is
latched in on a rising edge of DACCLK, similar to the 2×
interpolation mode. However, the latching edge is every fourth
edge in 4× interpolation mode and every eighth edge in the 8×
Figure 39
DACCLKIN
DATACLKOUT
tD = 5ns TYP
tH = 2.9ns TYP
DATA
03152-PrD-069
tS = –0.5ns TYP
Figure 40. Data Timing, DLL Off, 2× Interpolation, DCLKPOL = 1
DACCLKIN
DATACLKOUT
tD = 6ns TYP
tH = 2.9ns TYP
DATA
Figure 41. Data Timing, DLL Off, 2× Interpolation, DCLKPOL = 0
Rev. PrC | Page 25 of 52
03152-PrD-070
tS = –0.5ns TYP
AD9784
Preliminary Technical Data
DATAADJUST Synchronization
When designing the digital interface for high speed DACs, care
must be taken to ensure that the DAC input data meets setupand-hold requirements. Often, compensation must be used in
the clock delay path to the digital engine driving the DAC. The
AD9784 has the on chip capability to vary the DACCLK’s
latching edge. With the interpolation function enabled, this
allows the user the choice of multiple edges upon which to latch
the data. For instance, if the AD9784 is using 8× interpolation,
the user may latch from one of eight edges before the rising
edge of DATACLK, or seven edges after this rising edge. The
specific edge upon which data is latched is controlled by SPI
Register 05h, Bits 7:4. Table 26 shows the relationship of the
latching edge of DACCLK and DATACLK with the various
settings of the DATAADJ bits.
Figure 42, Figure 43, and Figure 44 show the alignment for the
latching edge of DACCLK with 4× interpolation and different
settings for DATAADJ. In Figure 42, DATAADJ is set to 0000,
with DCLKPOL set to 0 so that the latching edge of DACCLK is
immediately before the rising edge of DATACLK. The data
transitions shown in Figure 42 are synchronous with the
DACCLK, so that DACCLK and data are constant with respect
to each other. The only visible change when DATAADJ is
altered is that DATACLK moves, indicating the latching edge
has moved as well. Note that when DATAADJ is altered, the
latching edge with respect to DATACLK remains the same, but
the latching edge of DACCLK follows the edge of DATACLK.
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
Table 26.
Bit 4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Latching Edge wrt DATACLK
0
+1
+2
+3
+4
+5
+6
+7
–8
–7
–6
–5
–4
–3
–2
–1
03152-PrD-071
DACCLK
LATCHING EDGE
DATA TRANSITION
Figure 42. DATAADJ = 0000
Figure 43 shows the same conditions, but now DATAADJ is set
to 1111. This moves DATACLK to the left in the plot, indicating
that it occurs one DACCLK cycle before it did in Figure 42. As
explained previously, the latching edge of DACCLK also moves
one cycle back in time.
Note that the data in Figure 40 and Figure 41 was taken with the
DATAADJ default of 0000. With DCLKPOL = 0, the latching
edge of DACCLK is just previous to the rising edge of
DATACLK; with DCLKPOL = 1, the latching edge of DACCLK
is just previous to the falling edge of DATACLK.
With 8× interpolation, the user has the capability of using one
of 16 edges to latch the data. This is due to the fact that there are
eight DAC clock edges before and after the DATACLK until the
next DATACLK latching edge. With 4× interpolation, there are
only four latching edges of DACCLK available before and after
each DATACLK edge. Therefore, in 4× interpolation, only the
even numbered values for DATAADJ are available, and the
options are changed from +3 cycles to –4 cycles. With 2×
interpolation, there are only two edges available before and after
DATACLK, so the choices for DATAADJ are diminished to +1
cycle to –2 cycles.
Rev. PrC | Page 26 of 52
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DACCLK
LATCHING EDGE
DATA TRANSITION
Figure 43. DATAADJ = 1111
03152-PrD-072
Bit 7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SPI Reg 05h
Bit 6 Bit 5
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Preliminary Technical Data
AD9784
Figure 44 shows the same conditions, with DATAADJ now set
to 0001, thus moving DATACLK to the right in the plot. This
indicates that it occurs one DACCLK cycle after it did in
Figure 42. Now the latching edge of DACCLK moves forward in
time one cycle.
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
03152-PrD-073
DACCLK
LATCHING EDGE
DATA TRANSITION
Figure 44. DATAADJ = 0001
INTERPOLATION MODES
Table 27.
INTERP[1]
0
0
1
1
INTERP[0]
0
1
0
1
Mode
No Interpolation
×2 Interpolation
×4 Interpolation
×8 Interpolation
The digital filter’s frequency domain response exhibits
symmetry about half the output data rate and dc. It will cause
images of the input data to be shaped by the interpolation
filter’s frequency response. This has the advantage of causing
input data images, which fall in the stop band of the digital filter
to be rejected by the stop-band attenuation of the interpolation
filter; input data images falling in the interpolation filter’s passband will be passed. In band-limited applications, the images at
the output of the DAC must be limited by an analog reconstruction filter. The complexity of the analog reconstruction filter is
determined by the proximity of the closest image to the
required signal band. Higher interpolation rates yield larger
stop-band regions, suppressing more input images and resulting
in a much relaxed analog reconstruction filter.
A DAC shapes its output with a sinc function, having a null at
the sampling frequency of the DAC. The higher the DAC sampling rate compared to the input signal bandwidth, the less the
DAC sinc function will shape the output. Figure 45 shows the
interpolation filters of the AD9784 under different interpolation
rates, normalized to the input data rate, fSIN. The higher the
interpolation rate the more input data images fall in the
interpolation filter stop band and are rejected; the band-width
between passed images is larger with higher interpolation
factors. The sinc function shaping is also reduced with a higher
interpolation factor.
Table 28.
Interpolation is the process of increasing the number of points
in a time domain waveform by approximating points between
the input data points; on a uniform time grid, this produces a
higher output data rate. Applied to an interpolation DAC, a
digital interpolation filter is used to approximate the interpolated points, having an output data rate increased by the
interpolation factor. Interpolation filter responses are achieved
by cascading individual digital filter banks, whose filter
coefficients are given in Table 1; filter responses are shown in
Figure 34.
Mode
No Interpolation
×2 Interpolation
×4 Interpolation
×8 Interpolation
Rev. PrC | Page 27 of 52
Sinc Shaping
at 0.43fSIN (dB)
–2.8241
–0.6708
–0.1657
–0.0413
Bandwidth to First Image
fSIN
2fSIN
4fSIN
8fSIN
AD9784
Preliminary Technical Data
SINC RESPONSE
NO INTERPOLATION
0
–50
INTERP[1] = 0
INTERP[0] = 0
–100
–150
–8
–6
–4
–2
–0
2
4
6
8 fSIN
×2 INTERPOLATION
0
–50
INTERP[1] = 0
INTERP[0] = 1
–100
–150
–8
–6
–4
–2
0
2
4
6
8 fSIN
×4 INTERPOLATION
0
–50
INTERP[1] = 1
INTERP[0] = 0
–100
–150
–8
–6
–4
–2
0
2
4
6
8 fSIN
×8 INTERPOLATION
0
–50
–100
–150
–8
–6
–4
–2
0
2
4
6
8 fSIN
03152-PrD-011
INTERP[1] = 1
INTERP[0] = 1
Figure 45. Interpolation Modes
REAL AND COMPLEX SIGNALS
A complex signal contains both magnitude and phase
information. Given two signals at the same frequency, if a point
in time can be taken such that the signal leading in phase is
cosinusoidal and the lagging signal is sinusoidal, then
information pertaining to the magnitude and phase of a
combination of the two signals can be derived; the combination
of the two signals can be considered a complex signal. The
cosine and sine can be represented as a series of exponentials;
recalling that a multiplication by j is a counter clockwise
rotation about the Re/Im plane, the phasor representation of a
complex signal, with frequency f, can be shown Figure 46.
Im
Im
Re
C
A/2
A/2
2πft
Re
A/2
A
–f
0
+f
FREQUENCY
A/2
Acos(2πft) = A
Asin(2πft) = A
e+j2πft + e–j2πft
2
e+j2πft + e–j2πft
2j
=
=
A
2
A
2
[e+j2πft + e–j2πft]
[ je+j2πft + e–j2πft]
03152-PrD-012
C = Ae2πft = Acos(2πft) + jAsin(2πft)
The cosine term represents a signal on the real plane with
mirror symmetry about dc; this is referred to as the real, inphase or I component of a complex signal. The sine term
represents a signal on the imaginary plane with mirror
asymmetry about dc; this term is referred to as the imaginary,
quadrature or Q complex signal component.
The AD9784 has two channels of interpolation filters, allowing
both I and Q components to be shaped by the same filter
transfer function. The interpolation filters’ frequency response
is a real transfer function. Two DACs are required to represent a
complex signal. A single DAC can only synthesize a real signal.
When a DAC synthesizes a real signal, negative frequency
components fold onto the positive frequency axis. If the input to
the DAC is mirror symmetrical about dc, the folded negative
frequency components fold directly onto the positive frequency
components in phase producing constructive signal summation.
If the input to the DAC is not mirror symmetric about dc,
negative frequency components may not be in phase with
positive frequency components and will cause destructive signal
summation. Different applications may or may not benefit from
either type of signal summation.
Figure 46. Complex Phasor Representation
Rev. PrC | Page 28 of 52
Preliminary Technical Data
AD9784
MODULATION MODES
Table 29. Single Channel Modulation
MODDUAL
0
0
0
0
0
0
0
0
CHANNEL
0
0
0
0
1
1
1
1
MOD[1]
0
0
1
1
0
0
1
1
MOD[0]
0
1
0
1
0
1
0
1
Either channel of the AD9784’s interpolation filter channels can
be routed to the DAC and modulated. In single channel
operation the input data may be modulated by a real sinusoid;
the input data and the modulating sinusoid will contain both
positive and negative frequency components. A double
sideband output results when modulating two real signals. At
the DAC output the positive and negative frequency
components will add in phase resulting in constructive signal
summation.
As the modulating sinusoidal frequency becomes a larger
fraction of the DAC update rate, fDAC, the more the sinc function
of the DAC shapes the modulated signal bandwidth, and the
closer the first image moves. As the AD9784 interpolation
filter’s pass band represents a large portion of the input data’s
Nyquist band, under certain modulation and interpolation
modes it is possible for modulated signal bands to touch or
overlap images if sufficient interpolation is not used.
Figure 48 shows the effect of real modulation under all
interpolation modes. The sinc shaping at the corners of the
modulated signal band and the bandwidth to the first image for
those cases whose pass bands do not touch or overlap are
tabulated.
Mode
I Channel, no modulation
I Channel, modulation by fDAC/2
I Channel, modulation by fDAC/4
I Channel, modulation by fDAC/8
Q Channel, no modulation
Q Channel, modulation by fDAC/2
Q Channel, modulation by fDAC/4
Q Channel, modulation by fDAC/8
Table 30.
Modulation
none
fDAC/2
fDAC/4
fDAC/8
None
fSIN
fSIN
Overlap
Overlap
Interpolation
×2
×4
2 fSIN
4 fSIN
2 fSIN
4 fSIN
Touching
2 fSIN
Overlap
Touching
×8
8 fSIN
8 fSIN
4 fSIN
6 fSIN
Table 31.
Modulation
None
fDAC/4
None
0
–2.8241
–0.0701
–22.5378
Overlap
fDAC/8
Overlap
fDAC/2
Interpolation
×2
×4
0
0
–0.6708
–0.1657
–1.1932
–2.3248
–9.1824
–6.1190
Touching –0.2921
–1.9096
Overlap
Touching
Modulated pass band edges sinc shaping(lower/upper).
Rev. PrC | Page 29 of 52
×8
0
–0.0413
–3.0590
–4.9337
–0.5974
–1.3607
–0.0727
–0.4614
AD9784
Preliminary Technical Data
fDAC
7fDAC/8
3fDAC/4
fDAC/2
fDAC/2
3fDAC/4
3fDAC/8
3fDAC/8
5fDAC/8
fDAC/4
fDAC/4
5fDAC/8
fDAC/8
fDAC/8
0
–fDAC/8
–fDAC/4
–3fDAC/8
–fDAC/2
–5fDAC/8
–3fDAC/4
–7fDAC/8
–fDAC
FILTERED INTERPOLATION IMAGES
fDAC
03152-PrD-013
7fDAC/8
–fDAC/8
–fDAC/4
–3fDAC/8
–fDAC/2
–5fDAC/8
–3fDAC/4
–7fDAC/8
–fDAC
fS/8 MODULATION
Figure 47. Double Sideband Modulation
NO INTERPOLATION
0
INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1
–50
–100
–6
–4
–2
0
2
4
6
8 fSIN
×2 INTERPOLATION
0
INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1
–50
–100
–150
–8
–6
–4
–2
0
2
4
6
8 fSIN
×4 INTERPOLATION
0
INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1
–50
–100
–150
–8
–6
–4
–2
0
2
4
6
INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1
–50
–100
–150
–8
8 fSIN
×8 INTERPOLATION
0
–6
–4
–2
0
2
4
Figure 48. Real Modulation by fDAC/2 under all Interpolation Modes
Rev. PrC | Page 30 of 52
6
8 fSIN
03152-PrD-014
–150
–8
Preliminary Technical Data
AD9784
NO INTERPOLATION
0
INTERP[1] = 0
INTERP[0] = 0
–50
MOD[1] = 1
–100
–150
–8
MOD[0] = 0
–6
–4
–2
0
2
4
6
8 fSIN
×2 INTERPOLATION
0
INTERP[1] = 0
–50
INTERP[0] = 1
MOD[1] = 1
–100
–150
–8
MOD[0] = 0
–6
–4
–2
0
2
4
6
8 fSIN
×4 INTERPOLATION
0
INTERP[1] = 1
–50
INTERP[0] = 0
MOD[1] = 1
–100
–150
–8
MOD[0] = 0
–6
–4
–2
0
2
4
6
8 fSIN
×8 INTERPOLATION
0
INTERP[1] = 1
MOD[1] = 1
–100
–150
–8
MOD[0] = 0
–6
–4
–2
0
2
4
6
8 fSIN
03215-PrD-015
INTERP[0] = 1
–50
Figure 49. Real Modulation by fDAC/4 under all Interpolation Modes
NO INTERPOLATION
0
INTERP[1] = 0
INTERP[0] = 0
–50
MOD[1] = 1
–100
–150
–8
MOD[0] = 0
–6
–4
–2
0
2
4
6
8 fSIN
×2 INTERPOLATION
0
INTERP[1] = 0
INTERP[0] = 1
–50
MOD[1] = 1
–100
–150
–8
MOD[0] = 0
–6
–4
–2
0
2
4
0
8 fSIN
6
×4 INTERPOLATION
INTERP[1] = 1
INTERP[0] = 0
–50
MOD[1] = 1
–100
MOD[0] = 0
–6
–4
–2
0
2
4
0
8 fSIN
6
×8 INTERPOLATION
INTERP[1] = 1
INTERP[0] = 1
–50
MOD[1] = 1
–100
–150
8–
MOD[0] = 0
–6
–4
–2
0
2
4
Figure 50. Real Modulation by fDAC/8 under all Interpolation Modes
Rev. PrC | Page 31 of 52
6
8 fSIN
03152-PrD-017
–150
–8
AD9784
Preliminary Technical Data
Table 32. Dual Channel Complex Modulation
MODSING
0
0
0
0
0
0
0
0
REALIMAG
0
0
0
0
1
1
1
1
MOD[1]
0
0
1
1
0
0
1
1
MOD[0]
0
1
0
1
0
1
0
1
Mode
Real output, no modulation
Real output, modulation by fDAC/2
Real output, modulation fDAC/4
Real output, modulation fDAC/8
Image output, no modulation
Imag output, modulation by fDAC/2
Imag output, modulation by fDAC/4
Imag output, modulation by fDAC/8
Table 33.
In dual channel mode, the two channels may be modulated by a
complex signal, with either the real or imaginary modulation
result directed to the DAC. Assume initially that the complex
modulating signal is defined for a positive frequency only; this
causes the output spectrum to be translated in frequency by the
modulation factor only. No additional sidebands are created as a
result of the modulation process, and therefore the bandwidth
to the first image from the baseband bandwidth is the same as
the output of the interpolation filters. Furthermore, pass bands
will not overlap or touch. The sinc shaping at the corners of the
modulated signal band are tabulated. Figure 52 shows the
complex modulations.
Modulation
None
None
0
–2.8241
–0.0701
–22.5378
–0.4680
–6.0630
–1.3723
–4.9592
fDAC/2
fDAC/4
fDAC/8
Interpolation
×2
×4
0
0
–0.6708
–0.1657
–1.1932
–2.3248
–9.1824
–6.1190
–0.0175
–0.2921
–3.3447
–1.9096
–0.1160
–0.0044
–1.7195
–0.7866
×8
0
–0.0413
–3.0590
–4.9337
–0.5974
–1.3607
–0.0727
–0.4614
Modulated passband edges sinc shaping(lower/upper).
Figure 51. Complex Modulation
Rev. PrC | Page 32 of 52
5fDAC/8
3fDAC/4
7fDAC/8
5fDAC/8
3fDAC/4
7fDAC/8
fDAC
fDAC/2
fDAC/2
3fDAC/8
fDAC
03152-PrD-018
3fDAC/8
fDAC/4
NO NEGATIVE
SIDEBAND
fDAC/8
0
–fDAC/8
–fDAC/4
–3fDAC/8
–fDAC/2
–5fDAC/8
–3fDAC/4
–7fDAC/8
–fDAC
fS/8 MODULATION
fDAC/4
fDAC/8
0
–fDAC/8
–fDAC/4
–3fDAC/8
–fDAC/2
–5fDAC/8
–3fDAC/4
–7fDAC/8
–fDAC
FILTERED INTERPOLATION IMAGES
Preliminary Technical Data
AD9784
×2 INTERPOLATION
0
INTERP[1] = 0
INTERP[0] = 1
–50
MOD[1] = 0
–100
–150
–8
MOD[0] = 1
–6
–4
–2
0
2
4
0
6
8f
SIN
×4 INTERPOLATION
INTERP[1] = 1
INTERP[0] = 0
–50
MOD[1] = 0
–100
–150
–8
MOD[0] = 1
–6
–4
–2
0
2
4
0
6
8f
SIN
×8 INTERPOLATION
INTERP[1] = 1
INTERP[0] = 1
–50
–150
–8
MOD[0] = 1
–6
–4
–2
0
2
4
6
8f
SIN
03152-PrD-019
MOD[1] = 0
–100
Figure 52. Complex Modulation by fDAC/2 under all Interpolation Modes
×2 INTERPOLATION
0
INTERP[1] = 0
INTERP[0] = 1
–50
MOD[1] = 1
–100
–150
–8
MOD[0] = 0
–6
–4
–2
0
2
4
0
6
8 fSIN
×4 INTERPOLATION
INTERP[1] = 1
INTERP[0] = 0
–50
MOD[1] = 1
–100
–150
–8
MOD[0] = 0
–6
–4
–2
0
2
4
0
6
8 fSIN
×8 INTERPOLATION
INTERP[1] = 1
INTERP[0] = 1
–50
–150
–8
MOD[0] = 0
–6
–4
–2
0
2
4
6
8 fSIN
03152-PrD-020
MOD[1] = 1
–100
Figure 53. Complex Modulation by fDAC/4 under all Interpolation Modes
×2 INTERPOLATION
0
INTERP[1] = 0
INTERP[0] = 1
–50
MOD[1] = 1
–100
–150
–8
MOD[0] = 1
–6
–4
–2
0
2
4
0
6
8 fSIN
×4 INTERPOLATION
INTERP[1] = 1
INTERP[0] = 0
–50
MOD[1] = 1
–100
–150
–8
MOD[0] = 1
–6
–4
–2
0
2
4
0
6
8 fSIN
×8 INTERPOLATION
INTERP[1] = 1
INTERP[0] = 1
–50
–150
–8
MOD[0] = 1
–6
–4
–2
0
2
4
Figure 54. Complex Modulation by fDAC/8 under all Interpolation Modes
Rev. PrC | Page 33 of 52
6
8 fSIN
03152-PrD-021
MOD[1] = 1
–100
AD9784
Preliminary Technical Data
POWER DISSIPATION
60
The AD9784 has seven power supply domains: two 3.3 V analog
domains (AVDD1 and AVDD2), two 2.5 V analog domains
(ADVDD and ACVDD), one 2.5 V clock domain (CLKVDD),
and two digital domains (DVDD, which runs from 2.5 V, and
DRVDD, which can run from 2.5 V or 3.3 V).
4×
2×
40
IDVDD (mA)
The current needed for the 3.3 V analog supplies, AVDD1 and
AVDD2, is consistent across speed and varying modes of the
AD9784. Nominally, the current for AVDD1 is 29 mA across all
speeds and modes, while the current for AVDD2 is 20 mA.
8×
50
30
1×
20
0
25
50
75
100 125 150
FDATA (MSPS)
175
200
225
250
Figure 56. CLKVDD Supply Current vs. Clock Speed and Interpolation Rates
30
425
400
375
350
325
300
275
250
225
200
175
150
125
100
75
50
25
0
2× fs/8
4× fs/8
8× fs/8
4× fs/4
25
8× fs/4
2× fs/4
8×
2×
4×
20
4×
8×
IDVDD (mA)
2×
15
1×
10
1×
0
25
50
75
100 125 150
FDATA (MSPS)
175
200
225
250
Figure 55. DVDD Supply Current vs. Clock Speed, Interpolation, and
Modulation Rates
0
0
25
50
75
100 125 150
FDATA (MSPS)
175
200
225
250
Figure 57. ADVDD and ACVDD Supply Current vs. Clock Speed and
Interpolation Rates
Rev. PrC | Page 34 of 52
03152-PrD-079
5
03152-PrD-077
IDVDD (mA)
0
03152-PrD-078
10
The current for the 2.5 V analog supplies and the digital
supplies varies depending on speed and mode of operation.
Figure 55, Figure 56, and Figure 57 show this variation. Note
that CLKVDD, ADVDD, and ACVDD vary with clock speed
and interpolation rate, but not with modulation rate.
Preliminary Technical Data
AD9784
fDAC
7fDAC/8
3fDAC/4
5fDAC/8
fDAC/2
3fDAC/8
fDAC/4
fDAC/8
0
–fDAC/8
–fDAC/4
–3fDAC/8
–fDAC/2
–5fDAC/8
–3fDAC/4
–fDAC
–7fDAC/8
FILTERED INTERPOLATION IMAGES
fDAC
7fDAC/8
3fDAC/4
5fDAC/8
fDAC/2
3fDAC/8
fDAC/4
fDAC/8
0
–fDAC/8
–fDAC/4
–3fDAC/8
–fDAC/2
–5fDAC/8
–3fDAC/4
–fDAC
–7fDAC/8
fS/8 MODULATION
fDAC
03152-PrD-022
7fDAC/8
3fDAC/4
5fDAC/8
fDAC/2
3fDAC/8
fDAC/4
fDAC/8
0
–fDAC/8
–fDAC/4
–3fDAC/8
–fDAC/2
–5fDAC/8
–3fDAC/4
–fDAC
–7fDAC/8
fS/4 MODULATION
Figure 58. Complex Modulation with Negative Frequency Aliasing
DUAL CHANNEL COMPLEX MODULATION WITH
HILBERT
Table 34.
HILBERT
0
1
Mode
Hilbert transform off
Hilbert transform on
When complex modulation is performed, the entire spectrum is
translated by the modulation factor. If the resulting modulated
spectrum is not mirror symmetric about dc, when the DAC
synthesizes the modulated signal, negative frequency components will fall on the positive frequency axis and can cause
destructive summation of the signals. For some applications,
this can be seen as distorting the modulated output signal.
By performing a second complex modulation with a modulating signal having a fixed π/2 phase difference, Figure 59 (Y),
relative to the original complex modulation signal, Figure 59
(X), taking the Hilbert transform of the new resulting complex
modulation, and subtracting it from the original complex modulation output all negative frequency components can be folded
in phase to the positive frequency axis before being synthesized
by the DAC. When the DAC synthesizes the modulated output
there are no negative frequency components to fold onto the
positive frequency axis out of phase; consequently no distortion
is produced as a result of the modulation process.
0
ALIASED NEGATIVE FREQUENCY INTERPOLATION IMAGES
X = Ae j2π(f + fm)t
Y = Ae j2π(f + fm)t – π/2
Im
Im
C=X–Z
Re
Im
Re
–50
A/2
A/2
A/2
f
A/2
A/2
A
A/2
00
00
A/2
f
A/2
A/2
f
A/2
f
A
03152-PrD-023
A/2
dBFS
A/2
Re
Figure 59. Negative Frequency Image Rejection
–100
–150
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
Figure 60. Negative Frequency Aliasing Distortion
Rev. PrC | Page 35 of 52
0.5
03152-PrD-024
Re
Z = HILBERT(Y)
Im
AD9784
Preliminary Technical Data
Figure 60 shows this effect at the DAC output for a mirror
asymmetic signal about dc produced by complex modulation
without a Hilbert transform. The signal bandwidth was narrowed to show the aliased negative frequency interpolation
images.
The transfer function of an ideal Hilbert transform has a +90°
phase shift for negative frequencies, and a –90° phase shift for
positive frequencies. Because of the discontinuities that occur at
0 Hz and at 0.5 × Sample Rate, any real implementation of the
Hilbert Transform trades off bandwidth versus ripple.
In contrast, Figure 61 shows the same waveform with the
Hilbert transform applied. Clearly, the aliased interpolation
images are not present.
Figure 62 and Figure 63 show the gain of the Hilbert transform
versus frequency. Gain is essentially flat, with a pass-band ripple
of 0.1dB over the frequency range 0.07 × Sample Rate to
0.43 × Sample Rate.
0
dBFS
–50
–150
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
03152-PrD-025
–100
Figure 64 shows the phase response of the Hilbert transform
implemented in the AD9784. The phase response for positive
frequencies begins at –90° at 0 Hz, followed by a linear phase
response (pure time delay) equal to nine filter taps (nine clock
cycles). For negative frequencies, the phase response at 0 Hz is
+90°, again followed by a linear phase delay of nine filter taps.
To compensate for the unwanted 9-cycle delay, an equal delay of
nine taps is used in the AD9784 digital signal path opposite to
the Hilbert transform. This delay block is noted as t on the data
sheet.
Figure 61. Effects of Hilbert Transform
10
0
–10
–20
If the output of the AD9784 is to be used with a quadrature
modulator, negative frequency images are cancelled without the
need of a Hilbert transform.
–30
–40
–50
HILBERT TRANSFORM IMPLEMENTATION
–60
The Hilbert transform on the AD9784 is implemented as a 19coefficient FIR. The coefficients are given in Table 35
–70
900 1000
03152-PrD-074
900 1000
03152-PrD-075
–90
Table 35.
Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
–80
–100
Integer Value
–6
0
–17
0
–40
0
–91
0
–318
0
318
0
91
0
40
0
17
0
6
100
200
300
400
500
600
700
800
Figure 62. Hilbert Transform Gain
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
100
200
300
400
500
600
700
800
Figure 63. Hilbert Transform Ripple
Rev. PrC | Page 36 of 52
Preliminary Technical Data
AD9784
A baseband double sideband signal modulated to IF increases
IF filter complexity and reduces power efficiency. If the baseband signal is complex, a single sideband IF modulation can be
used, relaxing IF filter complexity and increasing power
efficiency.
4
3
2
1
The AD9784 has the ability to place the baseband single sideband complex signal either above the IF frequency or below it.
Figure 66 illustrates the baseband selection.
0
–1
–2
–4
100
200
400
600
800
1000
1200
0
03152-PrD-076
–3
–50
dBFS
Figure 64. Phase Response of Hilbert Transform
Table 36. Dual Channel Complex Modulation Sideband
Selection
–100
–150
–0.5
AD9784
LO
Q
AD9784
Im()
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.4
0.5
Figure 66. Upper IF Sideband Rejected
Re()
0
90
03151-PrD-003
I
–0.4
03152-PrD-027
Mode
Lower IF sideband rejected
Upper IF sideband rejected
03152-PrD-028
Sideband
0
1
0
Figure 65. AD9784 Driving Quadrature Modulator
The AD9784 can be configured to drive a quadrature modulator, representatively as in Figure 65. Where two AD9784s are
used with one AD9784 producing the real output, the second
AD9784 produces the imaginary output. By configuring the
AD9784 as a complex modulator coupled to a quadrature
modulator, IF image rejection is possible. The quadrature
modulator acts as the real part of a complex modulation producing a double sideband spectrum at the local oscillator (LO)
frequency, with mirror symmetry about dc.
dBFS
–50
Rev. PrC | Page 37 of 52
–100
–150
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
Figure 67. Lower IF Sideband Rejected
AD9784
Preliminary Technical Data
0
0
IF
fIF
–fIF
–fIF
BASEBAND
fIF
SIDEBAND = 0
03152-PrD-029
fIF
0
–fIF
SIDEBAND = 1
Figure 68. IF Quadrature Modulation of Real and Complex Baseband Signals
Table 37. Data Port Synchronization
PLOCKEXT
1
0
0
0
0
0
0
DCLKEXT
X
0
0
1
1
1
1
MODSYNC
X
0
1
0
0
1
1
DCLKCRC
X
X
X
0
1
0
1
Mode
PLL output
Dataclk Master
Modulator Master
Dataclk Slave
Dataclk Slave
Modulator Slave
Modulator Slave
In applications where two or more AD9784s are used to synthesize several digital data paths, it may be necessary to ensure that
the digital inputs to each device are latched synchronously. In
complex data processing applications, digital modulator phase
alignment may be required between two AD9784s. In order to
allow data synchronization and phase alignment, only one
AD9784 should be configured as a master device, providing a
reference clock for another slave-configured AD9784.
With synchronization enabled, a reference clock signal is
generated on the DATACLK/PLL_LOCK pin of the master. The
DATACLK/PLL_LOCK pins on the slave devices act as inputs
for the reference clock generated by the master. The DATACLK/
PLL_LOCK pin on the master and all slaves must be directly
connected. All master and slave devices must have the same
clock source connected to their respective CLK+/CLK– pins.
When configured as a master, the reference clock generated may
take one of two forms. In modulator master mode, the reference
clock will be a square wave with a period equal to 16 cycles of
the DAC update clock. Internal to the AD9784 is a 16-state
finite state machine, running at the DAC update rate. This state
machine generates all internal and external synchronization
clocks and modulator phasings. The rising edge of the master
reference clock is time aligned to the internal state machine’s
state zero. Slave devices use the master’s reference clock to
synchronize their data latching and align their modulator’s
phase by aligning their local state machine state zero to the
master.
Function
PLL locked flag output, synchronizer disabled
Channel data rate clock output
Modulator synchronization clock output
Input channel data rate clock, DLL off
Input channel data rate clock, DLL on
Input modulator synchronizer clock, DLL off
Input modulator synchronizer clock, DLL on
The second master mode, DATACLK master mode, generates a
reference clock that is at the channel data rate. In this mode, the
slave devices align their internal channel data rate clock to the
master. If modulator phase alignment is needed, a concurrent
serial write to all slave devices is necessary. To achieve this, the
CSB pin on all slaves must be connected together and a group
serial write to the MODADJ register bits must be performed;
the modulator coefficient alignment is updated on the next
rising edge of the internal state machine following a successful
serial write, Figure 69. Modulator master mode does not need a
concurrent serial write as slaves lock to the master phase
automatically.
In a slave device, the local channel data rate clock and the digital
modulator clock are created from the internal state machine.
The local channel data rate clock is used by the slave to latch
digital input data. At high data rates, the delay inherent in the
signal path from master to slave may cause the slave to lag the
master when acquiring synchronization. To account for this, an
integer number of the DAC update clock cycles may be
programmed into the slave device as an offset. The value in
DATADJ allows the local channel data rate clock in the slave
device to advance by up to eight cycles of the DAC clock or
delayed by up to seven cycles, Figure 70.
The digital modulator coefficients are updated at the DAC clock
rate and decoded in sequential order from the state machine
according to Figure 71. The MODADJ bits can be used to align
a different coefficient to the finite state machine’s zero state as
shown in Figure 72.
Rev. PrC | Page 38 of 52
Preliminary Technical Data
AD9784
DAC
CLOCK
STATE
MACHINE
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
MODULATOR
COEFFICIENT
1
0
–1
0
1
0
–1
0
1
0
–1
0
–1
0
1
0
–1
0
1
0
–1
0
1
0
MODADJ
1
0
–1
0
000
–1
0
1
0
000
03152-PrD-030
STATE MACHINE
CYCLE CLOCK
CHANNEL DATA
RATE CLOCK
Figure 69. Synchronous Serial Modulator Phase Alignment
DATADJ[3:0]
0000
1111
0001
DAC CLOCK
03152-PrD-031
RECEIVED CHANNEL
DATA RATE CLOCK
LOCAL CHANNEL
DATA RATE CLOCK
–1
+1
Figure 70. Local Channel Data Rate Clock Synchronized with Offset
STATE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DECODE
1
0
1/ 2
0
0
0
–1/ 2
0
–1
0
–1/ 2
0
0
0
–1/ 2
0
fs/8
0
0
0
2
3
4
1
5
6
2
7
03152-PrD-032
fs/4
fs/2
1
3
1
Figure 71. Digital Modulator State Machine Decode
MODADJ[2:0]
000
010
101
DAC CLOCK
14
15
0
1
2
3
15
0
1
15
0
1
2
MODULATOR
COEFFICIENT
–1
0
1
0
–1
0
0
–1
0
1
0
–1
0
03152-PrD-033
STATE
MACHINE
STATE MACHINE
CYCLE CLOCK
Figure 72. Local Modulator Coefficient Synchronized with Offset
Rev. PrC | Page 39 of 52
AD9784
Preliminary Technical Data
OPERATING THE AD9784 REV E EVALUATION BOARD
This section helps the user get started with the AD9784
evaluation board. Because it is intended to provide starter
information to power up the board and verify correct operation,
a description of some of the more advanced modes of operation
has been omitted. For a description of the various SPI registers
and the effect they have on the operating modes of the AD9784,
see the Mode Control (via SPI Port) section.
POWER SUPPLIES
The AD9784 Rev E Evaluation Board has five power supply
connectors, labeled VDDIN, CVDIN, VDD2IN, VDD3IN, and
AVDIN. The AD9784 itself actually has seven power supply
domains. To reconcile the power supply domains on the chip
with the power supply connectors on the evaluation board, use
Table 38.
Additionally, the DRVDD power supply on the AD9784 is used
to supply power for the digital input bus. DRVDD can be run
from 2.5 V or 3.3 V. On the evaluation board, DRVDD is jumper
selectable by JP1, just to the left of the chip on the evaluation
board. With the jumper set to the 3.3 V position, DRVDD chip
receives its power from VDD3IN. With the jumper set to the 2.5
V position, DRVDD receives its power from AVDIN.
CLKVDDS
PECL CLOCK DRIVER
The AD9784 system clock is driven from an external source via
connector S1. The AD9784 Evaluation Board includes an
OnSemiconductor MC100EPT22 PECL clock driver. In the
factory, the evaluation board is set to use this PECL driver as a
single-ended-to-differential clock receiver. The PECL driver can
be set to run from 2.5 V from the CVDIN power connector, or
3.3 V from the VDD3IN power connector. This setting is done
via jumper, JP2, situated next to the CVDIN power connector,
and by setting input bias resistors R23 and R4 on the evaluation
board. The factory default is for the PECL driver to be powered
from CVDIN at 2.5 V (R23 = 90.9 Ω, R4 = 115 Ω). To operate
the PECL driver with a 3.3 V supply, R23 must be replaced with
a 115 Ω resistor and R4 must be replaced with a 115 Ω resistor,
as well as changing the position of JP2. The schematic of the
PECL driver section of the evaluation board is shown below in
Figure 73. A low jitter sine wave can be used as the clock source.
Care must be taken to make sure the clock amplitude does not
exceed the power supply rails for the PECL driver.
CLKVDDS
CLK+
ACLKX
R23
115Ω
7
R5
50Ω
MC100EPT22
1
COND;5
U2
CLKVDDS;8
2
R4
90.9Ω
R6
50Ω
R7
50Ω
CLK–
03152-PrD-080
C32
0.1µF
Figure 73. PECL Driver on AD9784 Rev E Evaluation Board
Table 38.
Evaluation Board Label
VDDIN
CVDIN
VDD2IN
VDD3IN
AVDIN
PS Domain on Chip
DVDD
CLKVDD
ACVDD and ADVDD
AVDD2
AVDD1
Nominal Power
Supply Voltage (V)
2.5
2.5
2.5
3.3
3.3
Description
SPI port
Clock circuitry
Analog circuitry containing clock and digital interface circuitry
Switching analog circuitry
Analog output circuitry
Rev. PrC | Page 40 of 52
Preliminary Technical Data
AD9784
DATA INPUTS
SPI PORT
Digital data inputs to the AD9784 are accessed on the
evaluation board through connectors J1 and J2. These are 40 pin
right angle connectors that are intended to be used with
standard ribbon cable connectors. The input levels should be
either 3.3 V or 2.5 V CMOS, depending on the setting of the
DRVDD jumper JP1. The data format is selectable through
Register 02h, Bit 7 (DATAFMT). With this bit set to a default 0,
the AD9784 assumes that the input data is in twos complement
format. With this bit set to 1, data should be input in offset
binary format.
SW1 is a hard reset switch that sets the AD9784 to its default
state. It should be used every time the AD9784 power supply is
cycled or the clock is interrupted, or if new data is to be written
via the SPI port. For a description of the various SPI registers
and the effect they have on the operating modes of the AD9784,
see the Mode Control (via SPI Port) section. Set the SPI
software to read back data from the AD9784 and verify that
when the software is run, the expected values are read back.
When the evaluation board is first powered up and the clock
and data are running, it is recommended that the proper
operating current is verified. Depress reset switch SW1 to
ensure that the AD9784 is in the default mode. The default
mode for the AD9784 is for the internal PLL to be disabled, and
the interpolation set to 1×. The modulator is turned off in the
default mode. The nominal operating currents for the
evaluation board in the power-up default mode are shown in
Table 39.
Additionally, the DRVDD power supply on the AD9784 is used
to supply power for the digital input bus. DRVDD can be run
from 2.5 V or 3.3 V. On the evaluation board, DRVDD is jumper
selectable by JP1, just to the left of the chip on the evaluation
board. With the jumper set to the 3.3 V position, DRVDD chip
receives its power from VDD3IN. With the jumper set to the
2.5 V position, DRVDD receives its power from AVDIN.
OPERATING WITH PLL DISABLED
The SPI registers referenced in this section are shown in
Table 40.
With the PLL disabled, the evaluation board clock input must
be run at the intended DAC sample rate, up to the specified
limit of 500 MSPS. At the same time, the interpolation rate
should be set so the input data rate does not exceed the 200
MSPS limit. In the default mode with the PLL disabled, the
DATACLK signal from the AD9784 is available at connector S2.
The rate of this clock is the system clock applied at S1, divided
by the interpolation rate. DATACLK can be used to synchronize
the external data into the AD9784.
Table 39. Nominal Operating Currents in Power-Up Default Mode
Evaluation Board Power Supply
VDDIN
CVDIN
VDD2IN
VDD3IN
AVDIN
50 MSPS
24
79
1
30
27
Nominal Current @ Speed (mA)
100 MSPS
150 MSPS
49
74
83
87
4
6
30
30
27
27
200 MSPS
99
92
8
30
27
Table 40. SPI Registers
Register
01h
04h
Bit 7
0
0
1
1
Bit 7
INTERP[1]
PLLON
Bit 6
INTERP[0]
PLLMULT[1]
Interpolation Rate
Bit 6
Rate
0
1×
1
2×
0
4×
1
8×
Bit 6
0
0
1
1
Bit 5
Bit 4
Bit 3
Bit 0
PLLMULT[0]
PLLDIV[1]
PLLDIV[0]
PLOCKEXT
PLL Multiplier
Bit 5
0
1
0
1
Rev. PrC | Page 41 of 52
Mult
2×
4×
8×
16×
Bit 4
0
0
1
1
PLL Divider
Bit 3
0
1
0
1
Div
÷1
÷2
÷4
÷8
AD9784
Preliminary Technical Data
OPERATING WITH PLL ENABLED
ANALOG OUTPUT
Note that a specific revision of the AD9784 on the Rev E
Evaluation Board has a nonfunctioning PLL. This revision can
be identified by the xxx.
The analog output of the AD9784 is accessed via connector S3.
Once all settings are selected and current levels, PLL lock state,
and SPI port functionality are verified, the analog signal at S3
can be viewed. For most of the AD9784’s applications, a
spectrum analyzer is the instrument of choice to verify proper
performance. A typical spectral plot is shown in Figure 74, with
the AD9784 synthesizing a two-tone signal in the default mode
with a 200 MSPS sample rate. A single tone CW signal should
provide output power of approximately +0.5 dBm to the
spectrum analyzer.
With the AD9784 PLL enabled, the evaluation board clock input
must be run at the data input rate, up to the specified 200 MSPS
limit. The PLL controls the internal clock multiplication and
drives the interpolation filters and digital modulator. The
internal PLL has a VCO in the control loop that is designed to
operate optimally over the 200 MHz to 500 MHz range. The
VCO speed can be calculated as follows:
VCO Speed = Input Data Rate × PLLMULT[1,0]
The interpolation rate is set by Bits 6 and 7. With the PLL
enabled, the settings for the interpolation rate, the PLL
multiplier, and the PLL divide are interrelated. The interpolation
rate must meet the following criteria:
Interpolation Rate = [Settings of Bits 6, 7] = [PLLMULT ÷
PLLDIVIDER]
If the spectrum does not look correct at this point, the data
input may be violating setup and hold times with respect to the
input clock. To correct this, the user should vary the input data
timing. If this is not possible, SPI Register 02h, Bit 4 can be
inverted. This bit controls the clock edge upon which the data is
latched. If these methods do not correct the spectrum, it is
unlikely that the issue is timing related. This note should then
be reread to verify that all instructions have been followed.
Therefore, assuming the input data rate is constant and the
VCO is at optimal speed, if the interpolation rate is increased by
a factor of M, the PLLMULT setting must be decreased by the
same factor M.
10
0
–10
–20
–30
–40
–50
–60
–60
–70
–80
–90
–100
START 100 kHz
19.9 MHz/
STOP 200 MHz
Figure 74. Typical Spectral Plot
Rev. PrC | Page 42 of 52
03152-PrD-081
With the PLL enabled, DATACLK connector S2 indicates the
lock state of the PLL. A Logic 1 from S2 indicates lock; a Logic 0
indicates the PLL is not currently locked.
Rev. PrC | Page 43 of 52
Figure 75. Power Supply Distribution
2.5VQ
CGND;3,4,5
03152-PrD-082
S11
SMAEDGE
3.3VQ
AGND; 3,4,5
CLKVDD_IN
2
SMAEDGE
1
S10
3.3V
AGND2; 3,4,5
AVDD_IN
S9
SMAEDGE
2.5VN
DGND; 3,4,5
ADVDD3_IN
S5
SMAEDGE
2.5V
AGND2; 3,4,5
DVDD_IN
S7
SMAEDGE
ADVDD2_IN
TP6
RED
TP4
RED
TP2
RED
TP18
BLK
TP13
RED
TP1
RED
C69
0.1µF
C68
0.1µF
AVD1
C67
0.1µF
C48
0.1µF
C47
0.1µF
POWER INPUT FILTERS
FERRITE
C63
+
22µF
16V
L1
FERRITE
+ C64
22µF
16V
L2
FERRITE
C65
+
22µF
16V
L3
FERRITE
+ C46
22µF
16V
TP17
BLK
L9
FERRITE
+ C45
22µF
16V
L8
FERRITE
L12
L11
TP7
BLK
JP5
CVD
TP5
BLK
JP10
TP3
BLK
AVD2
JP9
TP16
BLK
VDD
JP34
1
3
A
B
JP33
JP30
C76
0.1µF
C34
0.1µF
JP6
JP8
JP7
CLKVDDS
DRVDD
AVDD2
ACVDD
ADVDD
BLK
BLK
BLK
BLK
ACLKX
BLK
TP30 TP31 TP32 TP33 TP34
FERRITE
L6
JP1
2
1
3
A B
C29
22µF
16V
JP36
C75
0.1µF
JP1 2
CLKVDD
AVDD
AVDD2
DVDDS
DVDD
DVDD
TP12 FERRITE
BLK
AVD3
C32
0.1µF
L7
VAL
L10
VAL
L13
VAL
L14
VAL
R4
90.9Ω
7
R23
115Ω
CLKVDDS
BLK
TP36
BLK
TP35
C35
0.1µF
CLKVDDS
MC100EPT22
1
CGND; 5
U2
CLKVDDS; 8
2
+ C28
4.7µF
6.3V
6
4
CLKVDDS; 8
CGND; 5
U2
MC100EPT22
3
CLK–
AUX CLOCK
50Ω
R6
50Ω
R5
50Ω
R7
CLK+
Preliminary Technical Data
AD9784
Figure 76. Local Circuitry
Rev. PrC | Page 44 of 52
TP14
WHT
IQ
B
A
S6
1
2
3
03152-PrD-083
DGND; 3,4,5
OPCLK_3
JP28
BD15
C33
0.1µF
OPCLK
JP27
BD14
+ C7
10µF
6.3V
DVDD
+ C8
10µF
6.3V
DVDD
+ C9
10µF
6.3V
DVDD
OPCLK
S4
DATACLK
S2
C54
0.001µF
DGND; 3,4,5
+ C31
10µF
6.3V
DRVDD
+ C10
10µF
6.3V
C26
0.001µF
C23
0.001µF
C24
0.001µF
C25
0.001µF
C36
0.1µF
C39
0.1µF
C41
0.1µF
C40
0.1µF
RESET 58
SPI_CSB 57
22 P1B5
23 P1B4
24 P1B3
AD05
AD04
AD03
DVDD6 52
29 P1B0LSB
AD00
P2B2 49
P2B3 48
32 P2B15MSB-IQSEL
33 P2B14-OPCLK
P2B7 42
39 P2B10
AD9786BTSP
P2B8 41
P2B6 43
38 P2B11
BD11
BD10
40 P2B9
DVDD5 44
37 P2B12
BD12
BD09
P2B5 46
DCOM5 45
36 DVDD4
BD08
BD07
BD06
BD05
BD03
BD04
P2B4 47
34 P2B13
U1
BD01
P2B1 50
31 DCLK-PLLL
BD02
BD00
SPSDO
SPSDI
SPCLK
SPCSB
RESET
TP11
WHT
C37
0.1µF
+ C30
10V
10µF
C17
0.1µF
C19
0.1µF
C15
0.1µF
C66
10µF
6.3V
C2
10µF
6.3V
+
C3
10µF
6.3V
4
C22
0.001µF
DVDD
+ C6
10µF
6.3V
C38
0.1µF
3
6
4
DVDD
R42
49.9Ω
2
1
DRVDD
AGND; 3,4,5
S3
TP29
BLK
SW1
FLOAT; 5
4
3
AVDD2
AGND; 3,4,5
S3
OUT1
C61
0.001µF
S
P
1
TTWB-1-B
T2B
NC = 5
S
P
TC1-1T
+ C5
10µF
6.3V
6
5
4
1
2
3
T2A
NC = 5
R9
49.9Ω
R10
49.9Ω
C18
0.001µF
RESET
C21
0.001µF
6
T3
S
1
C4
0.1µF
3
P
ADVDD
AVDD
C62
0.1µF
R8
C16
2.000kΩ
0.1µF 0.01%
TP8
WHT
TP10
WHT
+
+
C55
0.001µF
C14
0.1µF
C20
0.001µF
ACVDD
C49
0.1µF
P2B0LSB 51
35 DCOM4
BD13
DCOM6 53
28 P1B1
AD01
30 DRVDD1
SP-SDO 54
27 P1B2
AD02
SP-SDI 55
REFIO 59
21 P1B6
AD06
SP-CLK 56
DNC1 61
FSADJ 60
20 P1B7
AD07
26 DVDD3
ADVDDP2 62
19 P1B8
AD08
25 DCOM3
ADCOMP2 63
18 P1B9
AD10
AD09
AVDD2P2 66
15 P1B10
AD11
ACVDDP2 64
ACOM2P2 67
14 P1B11
AD12
17 DVDD2
AVDD1P1 68
13 P1B12
ACCOM2P2 65
ACOM1P21 69
12 P1B13
AD13
16 DCOM2
IOUTB 70
11 P1B14
IOUTA 71
ACOM1P11 72
AVDD1P2 73
ACOM2P12 74
AD14
10 P1B15MSB
9 DVDD1
8 DCOM1
7 CLKCOM2
S1
CGND; 3,4,5
JP23
AVDD2P1 75
ACCOMP1 78
3 CLKVDD2
DNC2 80
ADVDDP1 79
2 LPF
1 CLKVDD1
C49
1pF
6 CLK–
AD15
C42
0.1µF
ACLKX
CLK+
C11
0.1µF
ACVDDP1 77
CLK–
DVDD
C12
0.1µF
ACOM2P1 76
R1
50Ω
+C1
10µF
6.3V
CLKVDD
5 CLK+
3
4
JP22
CLKVDD
4 CLKCOM1
2
5
T1
T1-1T
1
T2A
6
TP15
WHT
C13
0.1µF
R3
10kΩ
ADTL1-12
R2
10kΩ
AD9784
Preliminary Technical Data
Preliminary Technical Data
R29
100Ω
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
3
4
5
6
7
8
9
10
2
AX13
3
AX12
4
AX11
5
AX10
6
AX09
7
AX08
8
AX07
1
AX06
2
AX05
3
AX04
4
AX03
5
AX02
6
AX01
7
AX00
8
1
2
3
4
5
6
7
8
9 10
RP1 22
RP1 22
RP1 22
RP1 22
RP1 22
RP1 22
RP1 22
RP1 22
RP2 22
RP2 22
RP2 22
RP2 22
RP2 22
RP2 22
RP2 22
RP2 22
RP6
DNP
R1 R2 R3 R4 R5 R6 R7 R8 R9
AX00
R38
100Ω
AX04
2
RP5
DNP
AX14
AX07
AX05
R1 R2 R3 R4 R5 R6 R7 R8 R9
1
RIBBON
J1
AX06
JP12
AX11
AX15
RCOM
2
JP3
AX10
R33
100Ω
1
DATA-A
AX09
R32
100Ω
RCOM
AX12
R28
100Ω
AX08
R31
100Ω
R39
100Ω
R40
100Ω
R34
100Ω
R41
100Ω
2
3
4
5
6
7
8
9
10
RP7
DNP
16
AD15
15
AD14
14
AD13
13
AD12
12
AD11
11
AD10
10
AD09
9
AD08
16
AD07
15
AD06
14
AD05
13
AD04
12
AD03
11
AD02
10
AD01
9
AD00
1
2
3
4
5
6
7
8
9 10
RP8
DNP
R1 R2 R3 R4 R5 R6 R7 R8 R9
JP21
R44
100Ω
R43
100Ω
1
R1 R2 R3 R4 R5 R6 R7 R8 R9
AX01
JP19
AX02
AX03
03152-PrD-084
AX13
R27
100Ω
R30
100Ω
RCOM
AX14
R26
100Ω
RCOM
AX15
AD9784
R46
100Ω
Figure 77. Digital Data Port A Input Terminations
Rev. PrC | Page 45 of 52
AD9784
Preliminary Technical Data
R60
100Ω
BX13
R64
100Ω
3
4
5
6
7
8
9
BX14
2
BX13
3
BX12
4
BX11
5
BX10
6
BX09
7
BX08
8
BX07
1
BX06
2
BX05
3
BX04
4
BX03
5
BX02
6
BX01
7
BX00
8
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
SDO
36
35
CLK
38
37
SDI
40
39
CSB
1
RIBBON
J2
2
3
4
5
6
7
8
9 10
RP3 22
RP3 22
RP3 22
RP3 22
RP3 22
RP3 22
RP3 22
RP3 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP11
DNP
R1 R2 R3 R4 R5 R6 R7 R8 R9
BX00
BX07
R55
100Ω
BX04
2
RP12
10 DNP
1
3
BX05
R1 R2 R3 R4 R5 R6 R7 R8 R9
BX15
4
BX06
JP31
BX11
R54
100Ω
R53
100Ω
R56
100Ω
R47
100Ω
2
3
4
5
6
7
8
9
10
RP9
DNP
16
BD15
15
BD14
14
BD13
13
BD12
12
BD11
11
BD10
10
BD09
9
BD08
16
BD07
15
BD06
14
BD05
13
BD04
12
BD03
11
BD02
10
BD01
9
BD00
1
2
3
4
5
6
7
8
9 10
RP10
DNP
R1 R2 R3 R4 R5 R6 R7 R8 R9
JP25
R51
100Ω
R49
100Ω
1
R1 R2 R3 R4 R5 R6 R7 R8 R9
BX01
JP24
BX02
BX03
03152-PrD-085
1
RCOM
2
JP26
BX10
R63
100Ω
1
DATA-B
BX09
R59
100Ω
RCOM
BX12
BX08
R58
100Ω
RCOM
R61
100Ω
BX14
R57
100Ω
RCOM
R62
100Ω
BX15
R52
100Ω
Figure 78. Digital Data Port B Input Terminations
Rev. PrC | Page 46 of 52
Preliminary Technical Data
AD9784
DVDDS
Q
5
OPCLK_3
+ C52
4.7µF
6.3V
C53
0.1µF
6
Q_
CLR
15
DGND;8
74LCX112
DVDDS;16
U7
SDO
SDI
CLK
10
PRE
11
9
J
Q
13
CLK
12
7
K
Q_
CLR
14
74LCX112
DGND;8
U7
DVDDS;16
CSB
SW2
SW3
SW4
A
A
A
3
2
2
B 1
2
SPCSB
U5
12
1
4
U5
10
3
SPSDI
U5
8
5
1
U6
2
13
74AC14
R21
10kΩ
R20
10kΩ
3
U5
U5
9
R45
9kΩ
U6
11
4
U6
6
B 1
B 1
SPI PORT
P1
1
2
3
4
5
6
12
U6
DVDDS
10
74AC14
9
74AC14
U6
74AC14
74AC14
5
R48
9kΩ
B 1
3
2
74AC14
74AC14
SPSDO
11
2
74AC14
74AC14
6
13
A
3
74AC14
74AC14
SPCLK
U5
R50
9kΩ
3
SW5
U6
8
+ C43
4.7µF
6.3V
74AC14
Figure 79. SPI and One-Port Clock Circuitry
Rev. PrC | Page 47 of 52
C50
0.1µF
+ C44
4.7µF
6.3V
C51
0.1µF
03152-PrD-086
OPCLK
3
J
1
CLK
2
K
4
PRE
Preliminary Technical Data
03152-PrD-087
AD9784
03152-PrD-088
Figure 80. PCB Assembly, Primary Side
Figure 81. PCB Assembly, Secondary Side
Rev. PrC | Page 48 of 52
AD9784
03152-PrD-089
Preliminary Technical Data
03152-PrD-090
Figure 82. PCB Assembly, Layer 1 Metal
Figure 83. PCB Assembly, Layer 6 Metal
Rev. PrC | Page 49 of 52
Preliminary Technical Data
03152-PrD-091
AD9784
03152-PrD-092
Figure 84. PCB Assembly, Layer 2 Metal (Ground Plane)
Figure 85. PCB Assembly, Layer 3 Metal (Power Plane)
Rev. PrC | Page 50 of 52
AD9784
03152-PrD-093
Preliminary Technical Data
03152-PrD-094
Figure 86. PCB Assembly, Layer 4 Metal (Power Plane)
Figure 87. PCB Assembly, Layer 5 Metal (Ground Plane)
Rev. PrC | Page 51 of 52
AD9784
Preliminary Technical Data
OUTLINE DIMENSIONS
14.00 SQ
1.20
MAX
0.75
0.60
0.45
12.00 SQ
80
60
60
SEATING
PLANE
80
61
61
1
1
PIN 1
TOP VIEW
(PINS DOWN)
BOTTOM
VIEW
20
41
21
6.00
SQ
20
41
40
40
21
0.15
0.05
1.05
1.00
0.95
7°
3.5°
0°
0.20
0.09
COPLANARITY
0.08
0.50 BSC
0.27
0.22
0.17
GAGE PLANE
0.25
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 88. 80-Lead Thermally Enhanced TQFP
(SV-80)
Dimensions shown in millimeters)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR03151–0–3/04(PrC)
Rev. PrC | Page 52 of 52