CMOS ±5 V/+5 V/+3 V Triple SPDT Switch ADG633 FEATURES ±2 V to ±6 V Dual Supply 2 V to 12 V Single Supply Automotive Temperature Range –40oC to +125oC <0.2 nA Leakage Currents 52 On Resistance over Full Signal Range Rail-to-Rail Switching Operation 16-Lead Chip Scale/TSSOP Packages Typical Power Consumption <0.1 W TTL/CMOS Compatible Inputs Package Upgrades to 74HC4053 and MAX4053/MAX4583 APPLICATIONS Automotive Applications Automatic Test Equipment Data Acquisition Systems Battery Powered Systems Communication Systems Audio and Video Signal Routing Relay Replacement Sample-and-Hold Systems Industrial Control Systems GENERAL DESCRIPTION The ADG633 is a low voltage CMOS device comprising three independently selectable SPDT (single pole double throw) switches. They are fully specified for ±5 V, +5 V, and +3 V supplies. The ADG633 switches are turned on with a logic low (or high) on the appropriate control input. Each switch conducts equally well in both directions when ON and has an input signal range that extends to the supplies. An EN input is used to enable or disable the device. When disabled, all channels are switched off. These parts are designed on an enhanced process that provides lower power dissipation yet gives high switching speeds. Low power consumption and an operating supply range of 2 V to 12 V make the ADG633 ideal for battery-powered portable instruments. All channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. All digital inputs have 0.8 V to 2.4 V logic thresholds, ensuring TTL/CMOS logic compatibility when using single +5 V or dual ±5 V supplies. FUNCTIONAL BLOCK DIAGRAM ADG633 S1B D1 S1A S3A D3 S3B S2A D2 S2B LOGIC A0 A1 A2 EN SWITCHES SHOWN FOR A LOGIC 1 INPUT PRODUCT HIGHLIGHTS 1. Single- and dual-supply operation. The ADG633 offers high performance and is fully specified and guaranteed with ±5 V, +5 V and +3 V supply rails. 2. Automotive temperature range –40oC to +125oC. 3. Guaranteed break-before-make switching action. 4. Low power consumption, typically <0.1 W. 5. Small 16-lead TSSOP and 16-lead 4 mm 4 mm chip scale packages. The ADG633 is available in small 16-lead TSSOP packages and 16-lead 4 mm 4 mm chip scale packages. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADG633–SPECIFICATIONS DUAL SUPPLY1 (V DD = +5 V ±10%, VSS = –5 V ±10%, GND = 0 V, unless otherwise noted.) Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS2 tTRANS tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection +25C 52 75 0.8 1.3 9 12 B Version Y Version –40C –40C to +85C to +125C VSS toVDD 90 100 1.8 2 13 14 ±0.005 ±0.2 ±0.005 ±0.2 ±0.005 ±0.2 ±5 ±5 ±5 2.4 0.8 0.005 ±1 2 60 90 70 95 25 40 40 110 130 120 135 45 50 10 Unit Test Conditions/Comments V typ max typ max typ max VDD = +4.5 V, VSS = –4.5 V VS = ±4.5 V, IS = 1 mA; Test Circuit 1 nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ pC max dB typ Off Isolation 2 4 –90 Total Harmonic Distortion, THD + N 0.025 % typ Channel-to-Channel Crosstalk –90 dB typ –3 dB Bandwidth 580 MHz typ CS (OFF) CD (OFF) CD, CS (ON) 4 7 12 pF typ pF typ pF typ 0.01 A typ A max A typ A max POWER REQUIREMENTS IDD ISS 0.01 1 1 VS = +3.5 V, IS = 1 mA VDD = +5 V, VSS = –5 V; VS = ±3 V, IS = 1 mA VDD = +5.5 V, VSS = –5.5 V VD = ±4.5 V, VS = 4.5 V; Test Circuit 2 VD = ±4.5 V, VS = 4.5 V; Test Circuit 3 VD = VS = ±4.5 V; Test Circuit 4 VIN = VINL or VINH RL = 300 , CL = 35 pF, VS = 3 V; Test Circuit 5 RL = 300 , CL = 35 pF, VS = 3 V; Test Circuit 7 RL = 300 , CL = 35 pF, VS = 3 V; Test Circuit 7 RL = 300 , CL = 35 pF, VS1 = VS2 = 3 V; Test Circuit 6 VS = 0 V, RS = 0 , CL = 1 nF; Test Circuit 8 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 9 RL = 600 , 2 V p-p, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 11 RL = 50 , CL = 5 pF; Test Circuit 10 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +5.5 V, VSS = –5.5 V Digital Inputs = 0 V or 5.5 V Digital Inputs = 0 V or 5.5 V NOTES 1Temperature range is as follows: B Version: –40°C to +85°C. Y Version: –40°C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. 0 ADG633 SINGLE SUPPLY1 (V DD = 5 V ±10%, VSS = 0 V, GND = 0 V, unless otherwise noted.) Parameter +25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0 toVDD 160 200 9 14 10 16 ±0.005 ±0.2 ±0.005 ±0.2 ±0.005 ±0.2 ±5 ±5 ±5 2.4 0.8 0.005 CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS tTRANS 85 150 4.5 8 13 B Version Y Version –40C –40C to +85C to +125C ±1 2 Unit Test Conditions/Comments V typ max typ max typ VDD = 4.5 V, VSS = 0 V VS = 0 V to 4.5 V, IS = 1 mA; Test Circuit 1 VS = +3.5 V, IS = 1 mA nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ VDD = 5.5 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; Test Circuit 2 VS = 1 V/4.5 V, VD = 4.5 V/1 V; Test Circuit 3 VS = VD = 1 V or 4.5 V; Test Circuit 4 VIN = VINL or VINH 2 tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection 100 150 100 150 25 35 90 190 220 190 220 45 50 10 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ pC max dB typ Off Isolation 0.5 1 –90 Channel-to-Channel Crosstalk –90 dB typ –3 dB Bandwidth 520 MHz typ CS (OFF) CD (OFF) CD, CS (ON) 5 8 12 pF typ pF typ pF typ 0.01 A typ A max POWER REQUIREMENTS IDD 1 NOTES 1Temperature range is as follows: B Version: –40°C to +85°C. Y Version: –40°C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. 0 VDD = 5 V, VSS = 0 V VS = 1.5 V to 4 V, IS = 1 mA –3– RL = 300 , CL = 35 pF, VS = 3 V; Test Circuit 5 RL = 300 , CL = 35 pF, VS = 3 V; Test Circuit 7 RL = 300 , CL = 35 pF, VS = 3 V; Test Circuit 7 RL = 300 , CL = 35 pF, VS1 = VS2 = 3 V; Test Circuit 6 VS = 2.5 V, RS = 0 , CL = 1 nF; Test Circuit 8 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 9 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 11 RL = 50 , CL = 5 pF; Test Circuit 10 f = 1 MHz f = 1 MHz f = 1 MHz VDD = 5.5 V Digital Inputs = 0 V or 5.5 V ADG633–SPECIFICATIONS SINGLE SUPPLY1 (V DD = 2.7 V to 3.6 V, VSS = 0 V, GND = 0 V, unless otherwise noted.) B Version Y Version Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS2 tTRANS tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection +25C 185 300 2 4.5 –40C to +85C 0 toVDD 350 400 6 7 ±0.005 ±0.2 ±0.005 ±0.2 ±0.005 ±0.2 ±5 ±5 ±5 2.0 0.5 0.005 ±1 2 170 300 200 310 30 40 180 –40C to +125C 370 400 380 420 55 75 10 Unit Test Conditions/Comments V typ max typ max VDD = 2.7 V, VSS = 0 V VS = 0 V to 2.7 V, IS = 0.1 mA; Test Circuit 1 VS = +1.5 V, IS = 0.1 mA nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ pC max dB typ Off Isolation 1 2 –90 Channel-to-Channel Crosstalk –90 dB typ –3 dB Bandwidth 500 MHz typ CS (OFF) CD (OFF) CD, CS (ON) 5 8 12 pF typ pF typ pF typ 0.01 A typ A max POWER REQUIREMENTS IDD 1 VDD = 3.3 V VS = 1 V/3 V, VD = 3 V/1 V; Test Circuit 2 VS = 1 V/3 V, VD = 3 V/1 V; Test Circuit 3 VS = VD = 1 V or 3 V; Test Circuit 4 VIN = VINL or VINH RL = 300 , CL = 35 pF, VS = 1.5 V; Test Circuit 5 RL = 300 , CL = 35 pF, VS = 1.5 V; Test Circuit 7 RL = 300 , CL = 35 pF, VS = 1.5 V; Test Circuit 7 RL = 300 , CL = 35 pF, VS1 = VS2 = 1.5 V; Test Circuit 6 VS = 1.5 V, RS = 0 , CL = 1 nF; Test Circuit 8 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 9 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 11 RL =50 , CL = 5 pF; Test Circuit 10 f = 1 MHz f = 1 MHz f = 1 MHz VDD = 3.3 V Digital Inputs = 0 V or 3.3 V NOTES 1Temperature range is as follows: B Version: –40°C to +85°C. Y Version: –40°C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. –4– REV. 0 ADG633 ABSOLUTE MAXIMUM RATINGS1 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C JA Thermal Impedance, 16-Lead TSSOP . . . . . . . . 150.4°C/W JA Thermal Impedance (4-Layer Board), 16-Lead LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV (TA = 25°C, unless otherwise noted.) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +13 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6.5 V Analog Inputs2 . . . . . . . . . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V Digital Inputs2 . . . . . . . . . . . . . . . . GND – 0.3 V to VDD + 0.3 V or 10 mA, whichever occurs first Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA (Pulsed at 1 ms, 10% duty cycle max) Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature Range Automotive (Y Version) . . . . . . . . . . . . . . . –40°C to +125°C Industrial (B Version) . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . –65°C to +150°C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2Overvoltages at A , EN, S, or D will be clamped by internal diodes. Current should X be limited to the maximum ratings given. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG633 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model Temperature Range Package Description Package Option ADG633YRU ADG633YCP –40°C to +125°C –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) Chip Scale Package (LFCSP) RU-16 CP-16 PIN CONFIGURATIONS TSSOP Table I. ADG633 Truth Table A2 A1 A0 EN Switch Condition X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 NONE D1–S1A, D2–S2A, D3–S3A D1–S1B, D2–S2A, D3–S3A D1–S1A, D2–S2B, D3–S3A D1–S1B, D2–S2B, D3–S3A D1–S1A, D2–S2A, D3–S3B D1–S1B, D2–S2A, D3–S3B D1–S1A, D2–S2B, D3–S3B D1–S1B, D2–S2B, D3–S3B S2B 1 16 VDD S2A 2 15 D2 S3B 3 14 D1 ADG633 D3 4 13 S1B TOP VIEW S3A 5 (Not to Scale) 12 S1A EN 6 11 A0 VSS 7 10 A1 GND 8 9 A2 X = Don’t Care S2B VDD D2 S2A LFCSP 16 15 14 13 S3B 1 D3 2 S3A 3 ADG633 TOP VIEW (Not to Scale) EN 4 9 A0 –5– A1 7 8 VSS GND A2 5 6 REV. 0 12 D1 11 S1B 10 S1A ADG633 TERMINOLOGY Parameter Definition VDD VSS IDD ISS GND S D AX EN Most Positive Power Supply Potential. Most Negative Power Supply Potential. Positive Supply Current. Negative Supply Current. Ground (0 V) Reference. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Active Low Digital Input. When high, device is disabled and all switches are OFF. When low, AX logic inputs determine ON switches. VD, VS Analog Voltage on Terminals D, S. RON Ohmic Resistance between D and S. RON On Resistance Match between Any Two Channels, i.e., RON max – RON min. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of On Resistance as measured over the specified analog signal range. IS (OFF) Source Leakage Current with the Switch OFF. ID (OFF) Drain Leakage Current with the Switch OFF. ID, IS (ON) Channel Leakage Current with the Switch ON. VINL Maximum Input Voltage for Logic 0. VINH Minimum Input Voltage for Logic 1. IINL, IINH Input Current of the Digital Input. CS (OFF) OFF Switch Source Capacitance. Measured with reference to ground. CD (OFF) OFF Switch Drain Capacitance. Measured with reference to ground. CD,CS (ON) ON Switch Capacitance. Measured with reference to ground. CIN Digital Input Capacitance. tON (EN) Delay between Applying the Digital Control Input and the Output Switching ON. See Test Circuit 7. tOFF (EN) Delay between Applying the Digital Control Input and the Output Switching OFF. t BBM ON Time, measured between 80% points of both switches when switching from one address state to another. Charge Injection A Measure of the Glitch Impulse Transferred from the Digital Input to the Analog Output during Switching. OFF Isolation A Measure of Unwanted Signal Coupling through an OFF Switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The Frequency at which the Output Is Attenuated by 3 dB. ON Response The Frequency Response of the ON Switch. Insertion Loss The Loss Due to the On Resistance of the Switch. –6– REV. 0 Typical Performance Characteristics–ADG633 40 VDD, VSS = 4.5V 20 10 0 –5.5 VDD = 3V 150 –1.5 0.5 VDD = 4.5V VDD = 5V VDD = 5.5V 100 2.5 0 4.5 0 2 4 6 8 VD, VS – V ON RESISTANCE – 80 +25C 60 –40C 40 1 1.5 2 2.5 3 3.5 4 4.5 +85C 150 +25C –40C 100 0 5 0 0.5 1 1.5 2 VD, VS – V 2.5 3 TPC 5. On Resistance vs. VD (VS) for Different Temperatures (Single Supply) 1.5 14 1.0 0.5 VDD = 3V VSS = 0V VD = 2.4V VS = 1V –0.5 IS, ID (ON) –1.0 0 20 40 60 80 100 TEMPERATURE – C 120 TPC 7. Leakage Currents vs. Temperature (Single Supply) REV. 0 0 1 2 3 4 5 VDD = +5V VSS = –5V VD = 4V VS = 4V ID(OFF) IS(OFF) 0 IS, ID(ON) –0.5 –1.5 0 20 40 60 80 100 TEMPERATURE – C 120 TPC 6. Leakage Currents vs. Temperature (Dual Supply) 90 VDD = +5V VSS = –5V 80 10 tON 70 6 4 VDD = 3V VSS = 0V 2 VDD = +5V VSS = –5V 0 –4 –5 –4 –3 60 50 40 30 tOFF 20 VDD = 5V VSS = 0V –2 –1.5 –1 0.5 100 12 QINJ – pC 0 –2 TPC 3. On Resistance vs. VD (VS) for Different Temperatures (Dual Supply) TA = 25C 8 IS, ID (OFF) –3 –1.0 TPC 4. On Resistance vs. VD (VS) for Different Temperatures (Single Supply) VDD = 5V VSS = 0V VD = 4V VS = 1V –4 VD, VS – V 50 0.5 0 –5 12 1.0 VD, VS – V CURRENT – nA 10 +125C 200 20 0 0 –40C 20 TIME – ns ON RESISTANCE – +85C +25C 30 VDD = 3V VSS = 0V 250 120 +85C 40 1.5 300 VDD = 5V VSS = 0V +125C 10 +125C 50 TPC 2. On Resistance vs. VD (VS) for Single Supply TPC 1. On Resistance vs. VD (VS) for Dual Supply 100 60 VDD = 10V VD, VS – V 140 70 VDD = 12V VDD, VSS = 5.5V –3.5 VDD = 3.3V 50 VDD, VSS = 5V ON RESISTANCE – ON RESISTANCE – 50 30 80 200 60 VDD = 5V VSS = 5V 90 VDD = 2.7V VDD, VSS = 3.3V 70 100 TA = 25C VDD, VSS = 3V 80 ON RESISTANCE – 250 VDD, VSS = 2.7V TA = 25C 90 CURRENT – nA 100 –2 –1 0 1 2 3 4 VS – V TPC 8. Charge Injection vs. Source Voltage –7– 10 5 0 –40 –20 0 20 40 60 80 TEMPERATURE – C 100 120 TPC 9. tON /tOFF Times vs. Temperature (Dual Supply) ADG633 ��� 0 0 �������� ��� –20 –2 �������� ��� VDD = +5V VSS = –5V TA = 25C –40 ��� dB ��� dB ���������� –4 �������� ��� –80 �� –8 �������� ���� �������� � ��� ��� � �� �� �� �� ���������������� 0 –10 –100 100k ��� –30 –120 1M 10M 100M FREQUENCY – Hz TPC 11. ON Response vs. Frequency VDD = –5V VSS = +5V TA = 25C –20 VDD = +5V VSS = –5V TA = 25C –10 ��� ��� TPC 10. tON /tOFF Times vs. Temperature (Single Supply) ���� ���������� ��������� ��������� ��������� 100k 1M 10M 100M FREQUENCY – Hz TPC 12. OFF Isolation vs. Frequency 10000 VSS = 0V 1000 VDD = 12V �� ������������ –50 –60 –70 –80 100 IDD – A –40 dB –60 –6 � VDD = 5V 10 1 –90 VDD = 3V ��� –100 0.1 –110 –120 –130 100k ���� �� 1M 10M 100M FREQUENCY – Hz �� ��� ��� ��� �� �� �� ��� ��� �������������� TPC 14. THD + Noise TPC 13. Crosstalk vs. Frequency 0.01 0 2 4 6 8 V(/EN) – V 10 12 TPC 15. VDD Current vs. Logic Level LOGIC THRESHOLD VOLTAGE – V 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 VDD – V 8 10 12 TPC 16. Logic Level Threshold vs. VDD –8– REV. 0 ADG633 Test Circuits IDS V1 S VS D IS (OFF) A S D IS (OFF) ��� ��� ��� � ��� Test Circuit 4. ID (ON) 3V ADDRESS DRIVE (VIN) VSS A1 S1A VS1A S1B VS1B 50% 50% 0V 90% VOUT ADG633 90% VOUT D EN RL 300 GND CL 35pF tTRANSITION tTRANSITION Test Circuit 5. Transition Time, tTRANSITION ��� ��� ����� ����� ��� �� ��� ��� �� ������� ����������� ��� �� ��� �� �� ��� �� ������ ���� �� EN ��� �� ���� �� ���� ��� ���� ��� ���� Test Circuit 6. Break-Before-Make Delay, tBBM REV. 0 � ��� VSS VDD A2 ������� EN �� 0.1F A0 ��� ��� A Test Circuit 2. IS (OFF) VDD A Test Circuit 3. ID (OFF) VD 0.1F ID (OFF) VD VS 50 D RON = V1/IDS Test Circuit 1. On Resistance VIN S NC –9– �� ADG633 ��� ��� ����� �� ����� ��� �� ������ ����������� ��� �� ��� �� �� ��� �� ������EN� ��� �� ������ �� EN ��� ��� �� ���� �� ���� ��� ��� ���� ����� ����� ������ �� ����� �EN� Test Circuit 7. Enable Delay, tON (EN ( ), tOFF (EN (EN) ��� ��� �� ��� �� �� �� �� ������ � � �� ����������� ����� EN ��� �� ���� �� ��� ���� ��� ����� ����������������� Test Circuit 8. Charge Injection VDD VDD A1 A0 NETWORK ANALYZER VSS 50 LOGIC 1 EN RL 50 GND D VOUT VS INSERTION LOSS = 20 LOG VOUT WITH SWITCH VOUT WITHOUT SWITCH Test Circuit 10. Bandwidth VDD A2 VSS 0.1F VDD VSS A1 VS VOUT RL 50 GND 0.1F 50 VS EN Test Circuit 9. OFF Isolation NETWORK ANALYZER 50 S A0 VOUT OFF ISOLATION = 20 LOG NETWORK ANALYZER VSS A1 VS D 0.1F VDD A2 50 S VSS 0.1F 0.1F 0.1F A2 VDD VSS 50 EN A0 ADG633 NETWORK ANALYZER DA SA RL 50 DB VOUT GND CROSSTALK = 20 LOG VOUT VS Test Circuit 11. Channel-to-Channel Crosstalk –10– REV. 0 ADG633 OUTLINE DIMENSIONS 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153AB 16-Lead Frame Chip Scale Package [LFCSP] 4 mm 4 mm Body (CP-16) Dimensions shown in millimeters 4.0 BSC SQ PIN 1 INDICATOR 0.65 BSC 3.75 BSC SQ TOP VIEW 12 MAX 1.00 0.90 0.80 0.60 MAX PIN 1 INDICATOR 0.60 MAX 0.75 0.55 0.35 13 12 16 1 BOTTOM VIEW 9 4 8 5 1.95 BSC 1.00 MAX 0.65 NOM 0.05 MAX 0.02 NOM SEATING PLANE 0.38 0.30 0.23 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC REV. 0 –11– 2.25 1.70 SQ 0.75 –12– PRINTED IN U.S.A. C03275–0–2/03(0)