19-2696; Rev 0; 1/03 KIT ATION EVALU E L B AVAILA 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR The switching frequency is adjustable from 600kHz to 1.5MHz with an external resistor. Alternatively, the controller can be synchronized to an external clock generated to another MAX8529 or a system clock. One MAX8529 can be set to generate an in-phase, or 90degree out-of-phase, clock signal for synchronization with additional controllers. This allows two controllers to operate either as an interleaved two- or four-phase system with each output shifted by 90 degrees. These devices also feature soft-start and soft-stop. The MAX8529 eliminates the need for current-sense resistors by utilizing the low-side MOSFET’s on-resistance as a current-sense element. This protects the DC-to-DC components from damage during output overload conditions or when output short circuit faults without requiring a current-sense resistor. Adjustable foldback current limit reduces power dissipation during short-circuit conditions. The MAX8529 includes a power-on reset output to signal the system when both outputs reach regulation. The MAX8529 is available in a 24-pin QSOP package. An evaluation kit is available to speed designs. Features ♦ Low Output Noise in DSL Band ♦ Ceramic Input/Output Capacitors ♦ Step-Down or Step-Up/Step-Down Operation ♦ Four Output, 90-Degree Out-of-Phase Operation (Using Two MAX8529s) ♦ Foldback Current Limit ♦ 4.75V to 23V Input Supply Range ♦ 0 to 18V Output Voltage Range (Up to 6A) ♦ >90% Efficiency ♦ Fixed-Frequency PWM Operation ♦ Adjustable 600kHz to 1.5MHz Switching Frequency ♦ External SYNC Input ♦ Clock Output for Master/Slave Synchronization ♦ Soft-Start and Soft-Stop ♦ RST Output with 140ms Minimum Delay ♦ Lossless Current Limit (No Sense Resistor) Ordering Information PART MAX8529EEG TEMP RANGE PIN-PACKAGE -40°C to +85°C 24 QSOP Pin Configuration Applications xDSL Modems and Routers DSP, ASIC, and FPGA Power Supplies Set-Top Boxes Broadband Routers TOP VIEW COMP2 1 24 EN FB2 2 23 DH2 ILIM2 3 22 LX2 OSC 4 21 BST2 V+ 5 REF 6 20 DL2 MAX8529 19 VL GND 7 18 PGND CKO 8 17 DL1 SYNC 9 16 BST1 ILIM1 10 15 LX1 FB1 11 14 DH1 COMP1 12 13 RST QSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8529 General Description The MAX8529 dual, synchronized, step-down controller generates two outputs from input supplies ranging from 4.75V to 23V. Each output is adjustable from sub-1V to 18V. Input voltage ripple and total RMS input ripple current are reduced by synchronized 180-degree out-ofphase operation. MAX8529 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR ABSOLUTE MAXIMUM RATINGS V+ to GND ..............................................................-0.3V to +25V PGND to GND .......................................................-0.3V to +0.3V VL to GND ..................-0.3V to the lower of +6V and (V+ + 0.3V) BST1, BST2 to GND ...............................................-0.3V to +30V LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) DL1, DL2 to PGND........................................-0.3V to (VL + 0.3V) CKO, REF, OSC, ILIM1, ILIM2, COMP1, COMP2 to GND ..........................-0.3V to (VL + 0.3V) FB1, FB2, RST, SYNC, EN to GND...........................-0.3V to +6V VL to GND Short Circuit..............................................Continuous REF to GND Short Circuit ...........................................Continuous Continuous Power Dissipation (TA = +70°C) 24-Pin QSOP (derate 9.4mW/°C above +70°C)...........762mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 10kΩ, compensation components for COMP_ are from Figure 1, TA = -40°C to +85°C (Note 1), unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS GENERAL V+ Operating Range (Note 2) 4.75 23.00 VL = V+ (Note 2) 4.75 5.50 V V+ Operating Supply Current VL unloaded, no MOSFETs connected 4.0 4.8 7.0 mA V+ Standby Supply Current EN = LX_ = FB_ = 0V 0.50 0.65 1.00 mA Thermal Shutdown Rising temperature, typical hysteresis = 10°C Current-Limit Threshold PGND - LX_ VL REGULATOR Output Voltage ROSC = 10kΩ °C 160 ILIM_ = VL 75 100 RILIM_ = 100kΩ 32 50 62 RILIM_ = 600kΩ 225 300 375 5.5V < V+ < 23V, 1mA < ILOAD < 50mA 4.75 5 5.25 V 4.4 4.55 4.7 V 1.98 2.00 2.02 V 0 4 10 mV VL Undervoltage Lockout Trip Level 125 mV REFERENCE Output Voltage IREF = 0µA Reference Load Regulation 0µA < IREF < 50µA SOFT-START Digital Ramp Period Internal 6-bit DAC for one converter to ramp from 0V to full scale (Note 3) Soft-Start Steps 1024 DC-toDC Clocks 64 Steps FREQUENCY 2 Low End of Range ROSC = 10kΩ 540 600 600 kHz High End of Range ROSC = 5kΩ 1020 1200 1380 kHz DH_ Minimum Off-Time ROSC = 5kΩ 110 160 ns _______________________________________________________________________________________ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR (V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 10kΩ, compensation components for COMP_ are from Figure 1, TA = -40°C to +85°C (Note 1), unless otherwise noted.) PARAMETER CONDITIONS MIN SYNC Range Internal oscillator nominal frequency must be set to half of the SYNC frequency 1000 SYNC Input Pulse Width (Note 3) SYNC Rise/Fall Time (Note 3) High 100 Low 100 TYP MAX UNITS 2800 kHz ns 100 ns ERROR AMPLIFIER FB_ Input Bias Current 250 nA 0.99 1.00 1.01 V 0°C to +85°C 1.25 1.8 2.70 -40°C to +85°C 1.2 1.8 2.9 FB_ Input Voltage Set Point FB_ to COMP_ Transconductance mS DRIVERS DL_, DH_ Break-Before-Make Time CLOAD = 5nF DH_ On-Resistance DL_ On-Resistance 30 ns Low 1.5 2.5 High 3 5 Low 0.6 1.5 High 3 5 Ω Ω LOGIC INPUTS (EN, SYNC) Input Low Level Typical 15% hysteresis, VL = 4.75V Input High Level VL = 5.5V 2.4 Input High/Low Bias Current VEN = 0 or 5.5V -1 0.8 V +1 µA 0.4 V V +0.1 LOGIC OUTPUTS (CKO) Output Low Level VL = 5V, sinking 5mA Output High Level VL = 5V, sourcing 5mA 4.0 V COMP_ Pulldown Resistance During Shutdown and Current Limit Ω 17 RST OUTPUT Output-Voltage Trip Level Output Low Level Both FBs must be over this to allow the reset timer to start; there is no hysteresis 0.87 0.9 0.93 VL = 5V, sinking 3.2mA 0.4 VL = 1V, sinking 0.4mA 0.3 Output Leakage V+ = VL = 5V, V RST = 5.5V, VFB = 1V Reset Timeout Period VFB_ = 1V FB_ to Reset Delay FB_ overdrive from 1V to 0.85V 140 315 4 V V 1 µA 560 ms µs Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: Operating supply range is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation. Note 3: Guaranteed by design and not production tested. _______________________________________________________________________________________ 3 MAX8529 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Circuit of Figure 1, VIN = 6V, TA = +25°C, unless otherwise noted.) OUTPUT VOLTAGE ACCURACY vs. LOAD EFFICIENCY vs. LOAD EFFICIENCY (%) 80 70 OUT2 60 OUT1 50 40 30 20 1.0 MAX8529 toc02 90 OUTPUT VOLTAGE ACCURACY (%) MAX8529 toc01 100 0.5 0 OUT1 OUT2 -0.5 10 0 0.1 1 -1.0 10 0 1 2 LOAD (A) 3 5 SWITCHING FREQUENCY vs. ROSC -0.5 -1.0 -1.5 MAX8529 toc04 0 1600 SWITCHING FREQUENCY (kHz) MAX8529 toc03 0.5 1400 1200 1000 800 600 -2.0 0 50 100 150 4 6 LOAD TRANSIENT RESPONSE (OUTPUT 1) LOAD TRANSIENT RESPONSE (OUTPUT 2) MAX8529 toc05 10µs/div 10 8 ROSC (kΩ) LOAD CURRENT (mA) 4 4 LOAD (A) VL VOLTAGE ACCURACY vs. LOAD CURRENT VL VOLTAGE ACCURACY MAX8529 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR MAX8529 toc06 VOUT2 50mV/div AC-COUPLED VOUT1 50mV/div AC-COUPLED VOUT1 50mV/div AC-COUPLED VOUT2 50mV/div AC-COUPLED IOUT1 1A/div IOUT2 1A/div 0A 0A 10µs/div _______________________________________________________________________________________ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR SOFT-START AND SOFT-STOP WAVEFORM OUT-OF-PHASE WAVEFORM RESET TIMEOUT MAX8529 toc07 MAX8529 toc09 MAX8529 toc08 5V/div 5V EN 0V VOUT2 10mV/div AC-COUPLED 5V EN 0V VLX2 5V/div VOUT2 2V/div 0V VOUT1 2V/div 0V VOUT2 1V/div 0V VOUT1 1V/div 0V VLX1 5V/div 0V VRST 0V 0V 400µs/div VOUT1 10mV/div AC-COUPLED 200ns/div 100ms/div EXTERNALLY SYNCHRONIZED SWITCHING WAVEFORM MAX8529 toc10 CKO OUTPUT WAVEFORM CKO OUTPUT WAVEFORM MAX8529 toc11 5V VSYNC 0V MAX8529 toc12 SYNC = GND SYNC = VL 5V VCKO 0V 5V VCK0 0V 5V VCK0 0V VLX1 5V/div 0V VLX1 5V/div 0V VLX1 5V/div 0V VOUT1 10mV/div AC-COUPLED VOUT1 10mV/div AC-COUPLED VOUT1 10mV/div AC-COUPLED 200ns/div 200ns/div 200ns/div SHORT-CIRCUIT CURRENT FOLDBACK AND RECOVERY OUTPUT2 NOISE SPECTRUM MAX8529 toc14 MAX8529 toc13 VOUT1 50mV/div AC-COUPLED SHORT VOUT2 VOUT2 1V/div 400nV/√Hz 0V 4nV/√Hz 40nV/√Hz IOUT2 2A/div 0A 200µs/div 0 250 750 500 FREQUENCY (kHz) 1000 1250 _______________________________________________________________________________________ 5 MAX8529 Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 6V, TA = +25°C, unless otherwise noted.) 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR MAX8529 Pin Description PIN NAME 1 COMP2 Compensation Pin for Regulator 2 (REG2). Compensate REG2’s control loop as shown in Figure 1. FB2 Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive-divider between REG2’s output and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB2 to a resistive voltage-divider from REF to REG2’s output (see the Setting the Output Voltage section). ILIM2 Current-Limit Adjustment for Regulator 2 (REG2). The PGND–LX2 current-limit threshold defaults to 100mV if ILIM2 is connected to VL. Connect a resistor (RILIM2) from ILIM2 to GND to adjust the REG2’s current-limit threshold (VITH2) from 50mV (RILIM2 = 100kΩ) to 300mV (RILIM2 = 600kΩ) (see the Setting the Valley Current Limit section). OSC Oscillator Frequency Set Input. The controller generates the clock signal by dividing down the oscillator, so the switching frequency equals half the synchronization frequency (fSW = fOSC / 2). Connect a resistor from OSC to GND (ROSC) to set the switching frequency from 600kHz (ROSC = 10kΩ) to 1500kHz (ROSC = 4kΩ). The controller still requires ROSC when an external clock is connected to SYNC. When using SYNC, set ROSC for one half of the SYNC input. 2 3 4 5 V+ Input Supply Voltage (4.75V to 23V) 6 REF 2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor. 7 GND Analog Ground CKO Clock Output. Clock Output for external 2- or 4-phase synchronization (see the Clock Synchronization (SYNC, CKO) section). SYNC Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect SYNC to a 1200kHz to 2800kHz clock for external synchronization. Connect SYNC to GND for 2phase operation as a master controller. Connect SYNC to VL for 4-phase operation as a master controller (see the Clock Synchronization (SYNC, CKO) section). ILIM1 Current-Limit Adjustment for Regulator 1 (REG1). The PGND–LX1 current-limit threshold defaults to 100mV if ILIM1 is connected to VL. Connect a resistor (RILIM1) from ILIM1 to GND to adjust REG1’s current-limit threshold (VITH1) from 50mV (RILIM1 = 100kΩ) to 300mV (RILIM1 = 600kΩ) (see the Setting the Valley Current Limit section). 11 FB1 Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive-divider between REG1’s output and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB1 to a resistive voltage-divider from REF and REG1’s output (see the Setting the Output Voltage section). 12 COMP1 Compensation Pin for Regulator 1 (REG1). Compensate REG1’s control loop as shown in Figure 1. RST Open-Drain Reset Output. RST is low when either output voltage is more than 10% below its regulation point. After soft-start is completed and both outputs exceed 90% of their nominal output voltage (VFB_ > 0.9V), RST becomes high impedance after a 140ms delay and remains high impedance as long as both outputs maintain regulation. Connect a resistor between RST and the logic supply for logic-level voltages. 8 9 10 13 6 FUNCTION _______________________________________________________________________________________ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR PIN NAME FUNCTION 14 DH1 High-Side Gate Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1. 15 LX1 External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver. 16 BST1 Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic capacitor and diode according to Figure 1. 17 DL1 Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to VL. 18 PGND Power Ground Internal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers and external boost circuitry for the high-side gate drivers. 19 VL 20 DL2 Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to VL. 21 BST2 Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic capacitor and diode according to Figure 1. 22 LX2 External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver. 23 DH2 High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2. 24 EN Active-High Enable Input. A logic low shuts down both controllers. Connect to VL for always-on operation. Detailed Description DC-to-DC PWM Controller The MAX8529 step-down converter uses a PWM voltage-mode control scheme (Figure 2) for each out-ofphase controller. The controller generates the clock signal by dividing down the internal oscillator or SYNC input when driven by an external clock, so each controller’s switching frequency equals half the oscillator frequency (fSW = fOSC / 2). An internal transconductance error amplifier produces an integrated error voltage at the COMP pin, providing high DC accuracy. The voltage at COMP sets the duty cycle using a PWM comparator and a ramp generator. At each rising edge of the clock, REG1’s high-side N-channel MOSFET turns on and remains on until either the appropriate duty cycle or until the maximum duty cycle is reached. REG2 operates outof-phase, so the second high-side MOSFET turns on at each falling edge of the clock. During each high-side MOSFET’s on-time, the associated inductor current ramps up. During the second-half of the switching cycle, the highside MOSFET turns off and the low-side N-channel MOSFET turns on. Now the inductor releases the stored energy as its current ramps down, providing current to the output. Under overload conditions, when the inductor current exceeds the selected valley current limit (see the Current-Limit Circuit (ILIM_) section), the highside MOSFET does not turn on at the appropriate clock edge and the low-side MOSFET remains on to let the inductor current ramp down. Synchronized Out-of-Phase Operation The two independent regulators in the MAX8529 operate 180 degrees out-of-phase to reduce input filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component cost and saves board space, making the MAX8529 ideal for cost-sensitive applications. Dual-switching regulators typically operate both controllers in-phase, and turn on both high-side MOSFETs at the same time. The input capacitor must then support the instantaneous current requirements of both controllers simultaneously, resulting in increased ripple voltage and current when compared to a single switching regulator. The higher RMS ripple current lowers efficiency due to power loss associated with the input capacitor’s effective series resistance (ESR). This typically requires more lowESR input capacitors in parallel to minimize input voltage ripple and ESR-related losses, or to meet the necessary ripple-current rating. _______________________________________________________________________________________ 7 MAX8529 Pin Description (continued) MAX8529 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR 5.4V TO 6.6V VIN D1A, B CMPSH-3A C2 10µF 10V X5R (2x) C8 0.22µF 10V 5 19 IN 16 L1 1.0µH DO3316P -102HC 1.8V AT 3A VOUT1 C3 0.1µF 14 R1 3.3Ω 15 R2 3.3Ω N1A, B C1 FDS 22µF 6912A 6V X5R (2x) R3 16.5kΩ R5 560Ω 17 18 C4 390pF VL BST1 BST2 DH1 DH2 LX1 LX2 DL1 DL2 C5 1nF 21 23 20 U1 FB2 COMP1 COMP2 1 10 VL 24 13 6 R9 100kΩ C7 0.22µF ILIM1 ILIM2 EN SYNC RST CKO REF OSC GND 7 3 9 L2 1.5µH DO3316P -152HC 2.5V AT 3A VOUT2 N2A, B FDS 6912A C12 22µF 6V X5R R12 (2x) 16.5kΩ R13 11.0kΩ R15 10kΩ C14 10pF R7 22kΩ RESET R11 3.3Ω 2 C6 27pF R8 68kΩ R10 3.3Ω 22 MAX8529 12 C10 0.1µF PGND 11 FB1 R4 20.5kΩ R6 10kΩ C11 10µF 10V X5R (2x) C9 4.7µF 10V X5R R14 560Ω C13 390pF C5 1nF R16 68kΩ R17 68kΩ 8 4 R18 4.99kΩ VL Figure 1. Standard Application Circuit With dual synchronized out-of-phase operation, the MAX8529’s high-side MOSFETs turn on 180 degrees outof-phase. The instantaneous input current peaks of both regulators no longer overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the required input capacitor ripple-current rating, allowing fewer or less expensive capacitors, and reduces shielding requirements for EMI. The out-of-phase waveforms in the Typical Operating Characteristics demonstrate synchronized 180-degree out-of-phase operation. 8 Internal 5V Linear Regulator (VL) All MAX8529 functions are internally powered from an on-chip, low-dropout 5V regulator. The maximum regulator input voltage (V+) is 23V. Bypass the regulator’s output (VL) with a 4.7µF ceramic capacitor to PGND. The VL dropout voltage is typically 500mV, so when V+ is greater than 5.5V, VL is typically 5V. The MAX8529 also employs an undervoltage lockout circuit that disables both regulators when VL falls below 4.5V. _______________________________________________________________________________________ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR MAX8529 REF VREF 2.0V V+ 5V LINEAR REGULATOR MAX8529 GND VL COMP1 BST1 FB1 CONVERTER 1 DH1 gm LX1 SOFT-START DAC R Q S Q DL1 PGND OSC SYNC OSCILLATOR CK0 5µA RST ILIM1 RESET EN VREF UVLO AND SHUTDOWN VL - 0.5V VL BST2 DH2 LX2 CONVERTER 2 COMP2 FB2 DL2 ILIM2 Figure 2. Functional Diagram The internal VL linear regulator can source over 50mA to supply the IC, power the low-side gate driver, charge the external boost capacitor, and supply small external loads. When driving large FETs, little or no regulator current may be available for external loads. For example, when switched at 600kHz, a single large FET with 18nC total gate charge requires 18nC ✕ 600kHz = 11mA. To drive larger MOSFETs, or deliver larger loads, connect VL to an external power supply from 4.75V to 5.5V. _______________________________________________________________________________________ 9 High-Side Gate-Drive Supply (BST_) Gate-drive voltages for the high-side N-channel switches are generated by the flying-capacitor boost circuits (Figure 3). A boost capacitor (connected from BST_ to LX_) provides power to the high-side MOSFET driver. On startup, the synchronous rectifier (low-side MOSFET) forces LX_ to ground and charges the boost capacitor to 5V. On the second half-cycle, after the low-side MOSFET turns off, the high-side MOSFET is turned on by closing an internal switch between BST_ and DH_. This provides the necessary gate-to-source voltage to turn on the highside switch, an action that boosts the 5V gate-drive signal above VIN. The current required to drive the highside MOSFET gates (fSWITCH ✕ QG) is ultimately drawn from VL. MOSFET Gate Drivers (DH_, DL_) The DH and DL drivers are optimized for driving moderate-size N-channel high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen with a large VIN - VOUT differential. The DL_ low-side drive waveform is always the complement of the DH_ high-side drive waveform (with controlled dead time to prevent cross-conduction or “shoot-through”). An adaptive dead-time circuit monitors the DL_ output and prevents the high-side FET from turning on until DL_ is fully off. There must be a low-resistance, lowinductance path from the DL_ driver to the MOSFET gate in order for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX8529 interprets the MOSFET gate as “off” while there is actually charge still left on the gate. Use very short, wide traces (50mils to 100mils wide if the MOSFET is 1in from the device). The dead time at the DH off edge is determined by a fixed 30ns internal delay. Synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side Schottky catch diode with a low-resistance MOSFET switch. Additionally, the MAX8529 uses the synchronous rectifier to ensure proper startup of the boost gate-driver circuit and to provide the current-limit signal. The internal pulldown transistor that drives DL_ low is robust, with a 0.5Ω (typ) on-resistance. This low onresistance helps prevent DL_ from being pulled up during the fast rise-time of the LX_ node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier MOSFET. However, for high-current applications, some combinations of high- and low-side FETs can cause excessive gate-drain coupling, leading to poor efficiency, EMI, and shoot-through currents. This can be remedied by adding a resistor (typically less than 5Ω) in series with BST_, which increases the turn-on time of the high-side FET without degrading the turn-off time (Figure 3). 10 Current-Limit Circuit (ILIM_) The current-limit circuit employs a “valley” current-sensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element. If the currentsense signal is above the current-limit threshold, the MAX8529 does not initiate a new cycle (Figure 4). Since valley current sensing is employed, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the low-side MOSFET’s onresistance, current-limit threshold, inductor value, and input voltage. The reward for this uncertainty is robust, lossless overcurrent sensing that does not require costly sense resistors. The adjustable current limit accommodates MOSFETs with a wide range of on-resistance characteristics (see the Design Procedure section). The current-limit threshold is adjusted with an external resistor at ILIM_ (Figure 1). The adjustment range is from 50mV to 300mV, corresponding to resistor values of 100kΩ to INPUT (VIN) VL BST_ 5Ω DH_ LX_ MAX8529 Figure 3. Reducing the Switching-Node Rise Time IPEAK ILOAD INDUCTOR CURRENT MAX8529 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR ILIMIT 0 TIME Figure 4. “Valley” Current-Limit Threshold Point ______________________________________________________________________________________ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR Undervoltage Lockout and Startup If VL drops below 4.5V, the MAX8529 assumes that the supply and reference voltages are too low to make valid decisions and activates the undervoltage lockout (UVLO) circuitry, which forces DH low and DL high to inhibit switching. RST is also forced low during UVLO. After VL rises above 4.5V, the controller powers up the outputs. Enable (EN), Soft-Start, and Soft-Stop Pull EN high to enable or low to shut down both regulators. During shutdown the supply current drops to 1mA (max), LX enters a high-impedance state (DH_ connected to LX_, and DL_ connected to PGND), and COMP_ is discharged to GND through a 17Ω resistor. VL and REF remain active in shutdown. For “always-on” operation, connect EN to VL. On the rising edge of EN both controllers enter softstart. Soft-start gradually ramps up to the reference voltage seen by the error amplifier in order to control the outputs’ rate of rise and reduce input surge currents during startup. The soft-start period is 1024 clock cycles (1024/f SW ), and the internal soft-start DAC ramps up the voltage in 64 steps. The output reaches regulation when soft-start is completed. On the falling edge of EN both controllers simultaneously enter softstop, which reverses the soft-start ramp. The part enters shutdown after soft-stop is complete. Reset Output RST is an open-drain output. RST pulls low when either output falls below 90% of its nominal regulation voltage. Once both outputs exceed 90% of their nominal regulation voltages and both soft-start cycles are completed, RST goes high impedance. To obtain a logic-voltage output, connect a pullup resistor from RST to the logic supply voltage. A 100kΩ resistor works well for most applications. If unused, leave RST grounded or unconnected. Clock Synchronization (SYNC, CKO) SYNC serves two functions: SYNC selects the clock output (CKO) type used to synchronize slave controllers, or it serves as a clock input so the MAX8529 can be synchronized with an external clock signal. This allows the MAX8529 to function as either a master or slave. CKO provides a clock signal synchronized to the MAX8529’s switching frequency, allowing either inphase (SYNC = GND) or 90-degrees out-of-phase (SYNC = VL) synchronization of additional DC-to-DC controllers (Figure 5). The MAX8529 supports the following three operating modes: • SYNC = GND: The CKO output frequency equals REG1’s switching frequency (fCKO = fDH1) and the CKO signal is in phase with REG1’s switching frequency. This provides 2-phase operation when synchronized with a second slave controller. • SYNC = VL: The CKO output frequency equals two times REG1’s switching frequency (fCKO = 2fDH1) and the CKO signal is phase shifted by 90 degrees with respect to REG1’s switching frequency. This provides 4-phase operation when synchronized with a second MAX8529 (slave controller). • SYNC Driven by External Oscillator: The controller generates the clock signal by dividing down the SYNC input signal, so that the switching frequency equals half the synchronization frequency (fSW = fSYNC / 2). REG1’s conversion cycles initiate on the rising edge of the internal clock signal. The CKO output frequency and phase match REG1’s switching frequency (fCKO = fDH1) and the CKO signal is in phase. Note that the MAX8529 still requires ROSC when SYNC is externally clocked and the internal oscillator frequency should be set to 50% of the synchronization frequency (fOSC = 0.5 fSYNC). Thermal-Overload Protection Thermal-overload protection limits total power dissipation in the MAX8529. When the device’s die junction temperature exceeds TJ = +160°C, an on-chip thermal sensor shuts down the device, forcing DL_ and DH_ low, allowing the IC to cool. The thermal sensor turns the part on again after the junction temperature cools by 10°C. During thermal shutdown, the regulators shut down, RST goes low, and soft-start is reset. If the VL linear-regulator output is short-circuited, thermal-overload protection is triggered. ______________________________________________________________________________________ 11 MAX8529 600kΩ. In adjustable mode, the current-limit threshold across the low-side MOSFET is precisely 1/10th the voltage seen at ILIM_. However, the current-limit threshold defaults to 100mV when ILIM is connected to VL. The logic threshold for switchover to this 100mV default value is approximately VL - 0.5V. Adjustable foldback current limit reduces power dissipation during short-circuit conditions (see the Design Procedure section). Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by LX_ and PGND. The IC must be mounted close to the low-side MOSFET with short direct traces making a Kelvin sense connection so that trace resistance does not add to the intended sense resistance of the low-side MOSFET. MAX8529 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR MAX8529 MAX8529 MAX8529 MAX8529 CK0 CK0 OSC SYNC OSC OSC SYNC VL SYNC SYNC VL SLAVE MASTER SLAVE MASTER 2-PHASE SYSTEM 180° PHASE SHIFT 4-PHASE SYSTEM 90° PHASE SHIFT DH1 DH1 MASTER MASTER DH2 DH2 DH1 DH1 SLAVE SLAVE DH2 DH2 Figure 5. Synchronized Controllers Design Procedure Effective Input Voltage Range Although the MAX8529 controllers can operate from input supplies ranging from 4.75V to 23V, the input voltage range can be effectively limited by the MAX8529’s duty-cycle limitations. The maximum input voltage is limited by the minimum on-time (tON(MIN)): VIN(MAX) ≤ VOUT t ON(MIN)fSW where tON(MIN) is 100ns. The minimum input voltage is limited by the maximum duty cycle (DMAX = 0.875): + VDROP1 V VIN(MIN) = OUT + VDROP2 - VDROP 0 .875 where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances. VDROP2 is the sum of the resistances in the charging path, including high-side switch, inductor, and PC board resistances. 12 Setting the Output Voltage For 1V or greater output voltages, set the MAX8529 output voltage by connecting a voltage-divider from the output to FB_ to GND (Figure 6). Select R_B (FB_ to GND resistor) to between 1kΩ and 10kΩ. Calculate R_A (OUT_ to FB_ resistor) with the following equation: V R _ A = R _ B OUT - 1 VSET where VSET = 1V (see the Electrical Characteristics) and VOUT can range from VSET to 18V. For output voltages below 1V, set the MAX8529 output voltage by connecting a voltage-divider from the output to FB_ to REF (Figure 6). Select R_C (FB to REF resistor) in the 1kΩ to 10kΩ range. Calculate R_A with the following equation: V - VOUT R _ A = R _ C SET VREF - VSET where V SET = 1V, V REF = 2V (see the Electrical Characteristics), and VOUT can range from 0 to VSET. ______________________________________________________________________________________ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR REF R_A R_C FB_ FB_ R_B R_A OUT_ MAX8529 L = MAX8529 VOUT_ > 1V VOUT_ < 1V Figure 6. Adjustable Output Voltage Setting the Switching Frequency The controller generates the clock signal by dividing down the internal oscillator or SYNC input signal when driven by an external oscillator, so the switching frequency equals half the oscillator frequency (fSW = fOSC/2). The internal oscillator frequency is set by a resistor (ROSC) connected from OSC to GND. The relationship between fSW and ROSC is: ROSC = VOUT (VIN - VOUT ) VINfSWIOUTLIR 6 × 109 Ω - Hz S fSW where fSW is in Hz, fOSC is in Hz, and ROSC is in Ω. For example, a 600kHz switching frequency is set with ROSC = 10kΩ. Higher frequencies allow designs with lower inductor values and less output capacitance. Consequently, peak currents and I2R losses are lower at higher switching frequencies, but core losses, gatecharge currents, and switching losses increase. A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by ROSC. This maintains output regulation even with intermittent SYNC signals. When an external synchronization signal is used, ROSC should set the switching frequency to one half SYNC rate (fSYNC). Inductor Selection Three key inductor parameters must be specified for operation with the MAX8529: inductance value (L), peak-inductor current (IPEAK), and DC resistance (RDC). The following equation assumes a constant ratio of inductor peak-to-peak AC current to DC average current (LIR). For LIR values too high, the RMS currents are where VIN, VOUT, and IOUT are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by ROSC (see the Setting the Switching Frequency section). The exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but also improve transient response and reduce efficiency due to higher peak currents. On the other hand, higher inductance increases efficiency by reducing the RMS current. However, resistive losses due to extra wire turns can exceed the benefit gained from lower AC current levels, especially when the inductance is increased without also allowing larger inductor dimensions. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The inductor’s saturation rating must exceed the peakinductor current at the maximum defined load current (ILOAD(MAX)): LIR IPEAK = ILOAD(MAX ) + I 2 LOAD(MAX ) Setting the Valley Current Limit The minimum current-limit threshold must be high enough to support the maximum expected load current with the worst-case low-side MOSFET on-resistance value since the low-side MOSFET’s on-resistance is used as the current-sense element. The inductor’s valley current occurs at ILOAD(MAX) minus half of the ripple current. The current-sense threshold voltage (V ITH) should be greater than the voltage on the low-side MOSFET during the ripple-current valley: LIR VITH > RDS(ON,MAX ) × ILOAD(MAX ) × 1 2 where R DS(ON) is the on-resistance of the low-side MOSFET (N L). Use the maximum value for R DS(ON) ______________________________________________________________________________________ 13 MAX8529 OUT_ high, and therefore I2R losses are high. Large inductances must be used to achieve very low LIR values. Typically inductance is proportional to resistance (for a given package type), which again makes I2R losses high for very low LIR values. A good compromise between size and loss is a 30% peak-to-peak ripple current to average-current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, and selected LIR determine the inductor value as follows: MAX8529 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR from the low-side MOSFET’s data sheet, an additional margin to account for RDS(ON) rise with temperature is also recommended. A good general rule is to allow 0.5% additional resistance for each °C of the MOSFET junction temperature rise. Connect ILIM_ to VL for the default 100mV (typ) currentlimit threshold. For an adjustable threshold, connect a resistor (RILIM_) from ILIM_ to GND. The relationship between the current-limit threshold (VITH_) and RILIM_ is: RILIM _ = VITH _ 0.5µA where RILIM_ is in Ω and VITH_ is in V. An RILIM resistance range of 100kΩ to 600kΩ corresponds to a current-limit threshold of 50mV to 300mV. When adjusting the current limit, 1% tolerance resistors minimize error in the current-limit threshold. For foldback current limit, a resistor (RFBI) is added from ILIM pin to output. The value of RILIM and RFBI can then be calculated as follows: First select the percentage of foldback, PFB, from 15% to 30%, then: RFBI = PFB × VOUT and 10 × VITH(1 - PFB ) × RFBI - 10 × VITH(1 - PFB )] [VOUT Input Capacitor The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit’s switching. The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents as defined by the following equation: IRMS = ILOAD VOUT (VIN - VOUT ) VIN IRMS has a maximum value when the input voltage equals twice the output voltage (VIN = 2VOUT), so IRMS(MAX) = ILOAD / 2. For most applications, nontantalum capacitors (ceramic, aluminum, polymer, or OS-CON) are preferred at the input due to their robustness with high inrush currents typical of systems that can be powered from very low impedance sources. Additionally, two (or more) smaller-value low-ESR capacitors can be connected in parallel for lower cost. Choose an input capacitor that 14 Output Capacitor The key selection parameters for the output capacitor are capacitance value, ESR, and voltage rating. These parameters affect the overall stability, output ripple voltage, and transient response. The output ripple has two components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitor’s ESR caused by the current flowing into and out of the capacitor: VRIPPLE ≅ VRIPPLE(ESR) + VRIPPLE(C) The output voltage ripple as a consequence of the ESR and output capacitance is: VRIPPLE(ESR) = IP-PRESR IP-P VRIPPLE(C) = 8COUT fSW V - VOUT VOUT IP-P = IN V fSWL IN where IP-P is the peak-to-peak inductor current (see the Inductor Selection section). These equations are suitable for initial capacitor selection, but final values should be verified by testing in a prototype or evaluation circuit. 5 × 10-6 (1 - PFB ) RILIM = exhibits less than 10°C temperature rise at the RMS input current for optimal long-term reliability. As a general rule, a smaller inductor ripple current results in less output ripple voltage. Since inductor ripple current depends on the inductor value and input voltage, the output ripple voltage decreases with larger inductance and increases with higher input voltages. However, the inductor ripple current also impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output-voltage sag is also a function of the maximum duty factor, which can be calculated from the minimum off-time and switching frequency: V L(ILOAD1 - ILOAD2 )2 OUT + t OFF(MIN) VINfSW VSAG = VIN - VOUT 2COUT VOUT - t OFF(MIN) VINfSW where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics), and fSW is set by ROSC (see the Setting the Switching Frequency section). ______________________________________________________________________________________ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR fP1 = 0 fP2 = 1 2π × R2 × C3 1 fP3 = 2π × R1 × fLC = (C1 × (C1 + Unity-gain crossover frequency: f0 = R1 × C3 × VVIN,MAX VOSC 1 2π × L O × C O where: VIN,MAX = Maximum input voltage VOSC = Oscillator ramp voltage = 1V LO = Output inductance CO = Output capacitance The goal is to place the two zeros below crossover and the two poles above crossover so that crossover occurs with a single-pole slope. The compensation procedure is as follows: 1) Select the crossover frequency such that: f0 < fZESR and f0 < C2) 1 × fS 5 fS = switching frequency C2) 2) Select R1 such that: 1 2π LO × CO R1 > 1 2π × R1 × C1 1 fZ2 = 2π × (R2 + R3) × C3 fZ1 = fZESR = × 2 gm 3) Place the first zero before the double pole: C1 ≥ 1 2π × RESR × CO 1 2π × (0.75) × fLC × R1 VIN DH GAIN (dB) LO VOUT LX DL CO R3 MAX8529 FB R2 C3 R4 R1 COMP C2 C1 fp1 fz1 fz2 fp2 fp3 FREQUENCY Figure 7. Compensation Network and Asymptotic Transfer Function ______________________________________________________________________________________ 15 MAX8529 Compensation The high switching frequency range of the MAX8529 allows the use of ceramic output capacitors. Since the ESR of ceramic capacitors is typically very low, the frequency of the associated transfer function zero is higher than the unity-gain crossover frequency and the zero cannot be used to compensate for the double pole created by the output inductor and capacitor. The solution is Type 3 compensation which takes advantage of local feedback to create two zeros and three poles (Figure 7). The frequency of the poles and zeros are described below: 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR MAX8529 4) Place the third pole at 1/2 the switching frequency. C2 ≤ 1 2π × (0.5) × fS × R1 C2 < 10pF can be omitted. 5) C3 ≤ 2π × f0 × L O × CO V × OSC R1 VIN 6) Place the second pole afer the ESR zero: 1 R2 ≤ 2π × fZESR × C3 If R2 < 1 gm (= 550Ω), increase R1 and go back to step 2. 7) Place the second zero at the double pole frequency: R3 ≥ 1 2π × fLC × C3 - R2 8) Set the output voltage: R4 = VFB × R3, VFB = 1V VOUT - VFB MOSFET Selection The MAX8529’s step-down controller drives two external logic-level N-channel MOSFETs as the circuit switch elements. The key selection parameters are: • On-resistance (RDS(ON)) • Maximum drain-to-source voltage (VDS(MAX)) • Minimum threshold voltage (VTH(MIN)) • Total gate charge (Qg) • Reverse transfer capacitance (CRSS) • Power dissipation All four N-channel MOSFETs must be a logic-level type with guaranteed on-resistance specifications at VGS ≥ 4.5V. For maximum efficiency, choose a high-side MOSFET (NH_) that has conduction losses equal to the switching losses at the optimum input voltage. Check to ensure that the conduction losses at minimum input voltage do not exceed MOSFET package thermal limits, or violate the overall thermal budget. Also, check to ensure that the conduction losses plus switching losses at the maximum input voltage do not exceed package ratings or violate the overall thermal budget. 16 Ensure that the MAX8529 DL _ gate drivers can drive NL _. In particular, check that the dv/dt caused by NH _ turning on does not pull up the NL _ gate through NL _’s drain-to-gate capacitance. This is the most frequent cause of cross-conduction problems. Gate-charge losses are dissipated by the driver and do not heat the MOSFET. All MOSFETs must be selected so that their total gate charge is low enough that VL can power all four drivers without overheating the IC: PVL = VIN × QG _ TOTAL × fSW MOSFET package power dissipation often becomes a dominant design factor. I2R power losses are the greatest heat contributor for both high-side and low-side MOSFETs. I2R losses are distributed between NH_ and NL _ according to duty factor as shown in the equations below. Switching losses affect only the high-side MOSFET, since the low-side MOSFET is a zero-voltage switched device when used in the buck topology. Calculate MOSFET temperature rise according to package thermal-resistance specifications to ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature. The worst-case dissipation for the high-side MOSFET (PNH) occurs at both extremes of input voltage, and the worst-case dissipation for the low-side MOSFET (PNL) occurs at maximum input voltage. Q + QGD V I f PNH(SWITCHING) = IN LOAD OSC GS I 2 GATE IGATE is the average DH driver output current capability determined by: IGATE = ( VL 2 RDS(ON)DH + RGATE ) where RDS(ON)DH is the high-side MOSFET driver’s onresistance (5Ω max), and RGATE is any series resistance between DH and BST (Figure 3). V PNH(CONDUCTION) = ILOAD2RDS(ON)NH OUT VIN PNH(TOTAL) = PNH(SWITCHING) + PNH(CONDUCTION) V PNL = ILOAD2RDS(ON)NL 1 - OUT VIN where PNH(CONDUCTION) is the conduction power loss in the high-side MOSFET, and PNL is the total low-side power loss. ______________________________________________________________________________________ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR Applications Information Independent Shutdown The two controllers in the MAX8529 can be shut down independently by pulling COMP to ground. DH is forced low and DL is forced high to inhibit switching. Digital soft-stop is not active when using this method for shutdown and the output voltage can go negative. Use a Schottky clamp diode to limit the negative swing of the output voltage. When COMP is released, DH and DL resume switching. In this mode, digital soft-start is not active and the inrush current is limited by the foldback current limit. Dropout Performance When working with low input voltages, the output voltage adjustable range for continuous-conduction operation is restricted by the minimum off-time (tOFF(MIN)). For best dropout performance, use the lowest (600kHz) switchingfrequency setting. Manufacturing tolerances and internal propagation delays introduce an error to the switching frequency and minimum off-time specifications. This error is more significant at higher frequencies. Also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN) as much as it ramps up during the maximum on-time (∆IUP). The ratio h = ∆IUP / ∆IDOWN is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and VSAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows tradeoffs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: V + VDROP1 VIN(MIN) = OUT + VDROP2 - VDROP1 1 - hfSW t OFF(MIN) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path, including high-side switch, inductor, and PC board resistances; and tOFF(MIN) is from the Electrical Characteristics. The absolute minimum input voltage is calculated with h = 1. If the calculated V+(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. Dropout Design Example: VOUT = 5V fSW = 600kHz tOFF(MIN) = 250ns VDROP1 = VDROP2 = 100mV h = 1.5 5V + 100mV VIN(MIN) = 1 - 1.5(600kHz)(250ns) +100mV − 100mV = 6.58V Calculating again with h = 1 gives the absolute limit of dropout: 5V + 100mV VIN(MIN) = ( )( ) 1 600 250 kHz ns +100mV − 100mV = 6V Therefore, VIN must be greater than 6V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 6.58V. Improving Noise Immunity Applications where the MAX8529 must operate in noisy environments can typically adjust their controller’s compensation to improve the system’s noise immunity. In particular, high-frequency noise coupled into the feedback loop causes jittery duty cycles. One solution is to lower the crossover frequency (see the Compensation section). PC Board Layout Guidelines Careful PC board layout is critical to achieve low switching losses and clean, stable operation. This is ______________________________________________________________________________________ 17 MAX8529 To reduce EMI caused by switching noise, add a 0.1µF ceramic capacitor from the high-side switch drain to the low-side switch source or add resistors in series with DL_ and DH_ to increase the MOSFETs’ turn-on and turn-off times. MAX8529 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR especially true for dual converters where one channel can affect the other. Refer to the MAX8529 EV kit data sheet for a specific layout example. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: 1) Isolate the power components on the top side from the analog components on the bottom side with a ground shield. Use a separate PGND plane under the OUT1 and OUT2 sides (referred to as PGND1 and PGND2). Avoid the introduction of AC currents into the PGND1 and PGND2 ground planes. Run the power-plane ground currents on the top side only. 2) Use a star ground connection on the power plane to minimize the crosstalk between OUT1 and OUT2. 3) Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. 4) Connect GND and PGND together close to the IC. Do not connect them together anywhere else. Carefully follow the grounding instructions under step 4 of the Layout Procedure section. 5) Keep the power traces and load connections short. This practice is essential for high efficiency. Use thick copper PC boards (2oz vs. 1oz) to enhance full-load efficiency by 1% or more. 6) LX_ and PGND connections to the synchronous rectifiers for current limiting must be made using Kelvin sense connections to guarantee the currentlimit accuracy. With 8-pin SO MOSFETs, this is best done by routing power to the MOSFETs from outside using the top copper layer, while connecting PGND and LX_ underneath the 8-pin SO package. 7) When trade-offs in trace lengths must be made, allow the inductor-charging path to be made longer than the discharge path. Since the average input current is lower than the average output current in step-down converters, this minimizes the power dissipation and voltage drops caused by board resistance. For example, allow some extra distance between the input capacitors and the high-side MOSFET rather than to allow distance between the inductor and the low-side MOSFET or between the inductor and the output filter capacitor. 18 8) 9) Ensure that the feedback connection to COUT_ is short and direct. Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from the sensitive analog areas (REF, COMP_, ILIM_, and FB_). Use PGND1 and PGND2 as EMI shields to keep radiated noise away from the IC, feedback dividers, and analog bypass capacitors. 10) Make all pin-strap control input connections (ILIM_, SYNC, and EN) to analog ground (GND) rather than power ground (PGND). Layout Procedure 1) Place the power components first, with ground terminals adjacent (NL _ source, CIN_, and COUT_). Make all these connections on the top layer with wide, copper-filled areas (2oz copper recommended). 2) Mount the controller IC adjacent to the synchronous rectifier MOSFETs (NL _), preferably on the back side in order to keep LX_, PGND_, and DL_ traces short and wide. The DL_ gate trace must be short and wide, measuring 50mils to 100mils wide if the low-side MOSFET is 1in from the controller IC. 3) Group the gate-drive components (BST_ diodes and capacitors, and VL bypass capacitor) together near the controller IC. 4) Make the DC-to-DC controller ground connections as follows: a) Create a small analog ground plane near the IC. b) Connect this plane to GND and use this plane for the ground connection for the reference (REF) V+ bypass capacitor, compensation components, feedback dividers, OSC resistor, and ILIM_ resistors (if any). c) Connect GND and PGND together under the IC (this is the only connection between GND and PGND). 5) On the board’s top side (power planes), make a star ground to minimize crosstalk between the two sides. Buck-Boost The MAX8529 step-down regulator can be configured as a buck-boost (step-up) regulator with the addition of a MOSFET switch and an output diode (Figure 8). When LX is high, the inductor current increases with a slope of VIN ______________________________________________________________________________________ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR 1 IOUT = (1 - D) × IL,DC + IL,RIPPLE 2 The output voltage is a function of the input voltage and the duty cycle: IPK = IL,DC + IL,RIPPLE VOUT = D × VIN 1- D Notice that the output voltage is increased by a factor of 1 / (1 - D) compared with a normal step-down regulator. The additional loop gain must be considered when designing the compensation circuit. Solving for D: DMAX = VOUT VIN,MIN + VOUT and the maximum additional gain is: G = 1 1 - DMAX The open-loop gain must be reduced by a factor of G for stability at a given bandwidth compared with a normal step-down regulator. Alternatively, the unity-gain crossover frequency can be reduced by a factor of G when applying the compensation equations. The output current is a fraction of the peak switch current and depends on the DC current in the inductor: MAX8529 / L. When LX is low, the inductor current decreases with a slope of (VOUT + VD) / L. The input and output currents are discontinuous, which allows the output voltage to be greater or less than the input voltage. and Choose L ≈ VIN × (1 - DMAX ) × DMAX 0.4 × IOUT × fSW where fSW is the switching frequency. Choose COUT > IOUT × DMAX VRIPPLE × fSW where VRIPPLE is the maximum output ripple voltage and COUT is a ceramic capacitor. Choose the output Schottky diode to be rated for IPK and VOUT. Similarly, choose the extra MOSFET to be rated for IPK, VGS,BR > VIN, and fast switching (< 50ns). The buck-boost portion of the circuit shown in Figure 8 delivers 24V at 50mA with 70% efficiency. A pre+load resistor is used to ensure constant frequency operation over the entire load range. Chip Information TRANSISTOR COUNT: 6688 PROCESS: BiCMOS ______________________________________________________________________________________ 19 MAX8529 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR 5.4V TO 6.6V VIN D1A, B CMPSH-3A C2 10µF 10V X5R C8 0.22µF 10V 5 19 IN 16 L2 2.5µH CDRH 5D28 3.3V AT 2A VOUT1 C3 0.1µF 14 R1 10Ω N1A, B FDS 6930A 15 R2 10Ω C1 10µF 6V X5R 17 18 R3 34kΩ BST1 BST2 DH1 DH2 LX1 LX2 DL1 DL2 C5 270pF 23 C10 0.1µF R10 10Ω 22 20 12 U1 FB2 R12 324kΩ 2 R13 14kΩ COMP1 COMP2 10 VL 24 13 6 R9 100kΩ VL C7 0.22µF R14 1kΩ R15 100kΩ 1 C13 39pF C14 180pF R7 150kΩ RESET D2 EC10 QS03L N3 FDN 359AN C6 10pF R8 68kΩ L3 33µH CDRH 5D28 R11 10Ω MAX8529 R6 27kΩ N2A, B NDS 9956A 21 PGND R4 14.7kΩ C4 150pF C11 4.7µF 10V X5R VL 11 FB1 R5 620Ω C9 4.7µF 10V X5R ILIM1 ILIM2 EN SYNC RST CKO REF OSC GND 7 R16 750kΩ 3 9 R17 22kΩ 8 4 R18 4.99kΩ Figure 8. Buck-Boost Application 20 ______________________________________________________________________________________ 24V AT 50mA VOUT2 C12 4.7µF 25V X5R R19 5.6kΩ 1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR QSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX8529 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)