MAXIM MAX1813EEI

19-2010; Rev 0; 4/01
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Applications
Notebook Computers
(Intel IMVP–II™/Coppermine™)
Docking Stations
CPU Core Supply
Single-Stage (BATT to VCORE) Converters
Two-Stage (+5V to VCORE) Converters
Typical Operating Circuit appears at end of data sheet.
Features
♦ High-Efficiency Voltage Positioning
♦ Quick-PWM Architecture
♦ ±1% VOUT Accuracy Over Line
♦ Adjustable Output Slew Rate
♦ 0.600V to 2V Adjustable Output Range (5-Bit DAC)
♦ 2V to 28V Battery Input Range
♦ 200/300/600/1000kHz Switching Frequency
♦ Output Undervoltage and Overvoltage Protection
♦ Drives Large Synchronous-Rectifier MOSFETs
♦ ±20% Accurate Current-Limit
♦ 10µA Shutdown Supply Current
♦ 2V ±1% Reference Output
♦ Power-Good (PGOOD) Indicator
♦ Small 28-Pin QSOP Package
Ordering Information
PART
MAX1813EEI
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
28 QSOP
Pin Configuration
TOP VIEW
V+ 1
28 DH
VPCS 2
27 LX
SKP/SDN 3
26 BST
TIME 4
25 D0
FB 5
CC 6
24 D1
MAX1813
23 D2
S0 7
22 D3
S1 8
21 D4
VCC 9
20 CODE
TON 10
19 ZMODE
REF 11
18 SUS
ILIM 12
17 VDD
PGOOD 13
16 DL
GND 14
15 PGND
QSOP
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
Coppermine and IMVP-ΙΙ are trademarks of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1813
General Description
The MAX1813 step-down controller is intended for core
CPU DC-DC converters in notebook computers. The
controller features a dynamically adjustable output (5bit DAC), ultra-fast transient response, high DC accuracy, and high efficiency necessary for leading-edge
CPU core power supplies. Maxim’s proprietary QuickPWM™ quick-response, constant-on-time PWM control
scheme handles wide input/output voltage ratios with
ease and provides 100ns “instant-on” response to load
transients while maintaining a relatively constant switching frequency.
The MAX1813 is designed specifically for CPU core
applications requiring a voltage-positioned supply. The
voltage-positioning input (VPCS), combined with a
high-DC-accuracy control loop, is used to implement a
power supply that modifies its output set point in
response to the load current. This arrangement
decreases full-load power dissipation and reduces the
required number of output capacitors.
The output voltage can be dynamically adjusted
through the 5-bit digital-to-analog converter (DAC)
inputs over a 0.600V to 2V range. The MAX1813
includes an internal multiplexer that selects between
three different DAC code settings. The first two inputs
are controlled by five digital input pins (D0–D4). The
third input is used for the suspend mode and controlled
by two 4-level input pins (S0, S1). Output voltage transitions are accomplished with a proprietary precision
slew-rate control that minimizes surge currents to and
from the battery while guaranteeing “just-in-time” arrival
at the new DAC setting.
The MAX1813’s 28V input range enables single-stage
buck conversion from high-voltage batteries for the
maximum possible efficiency. Alternatively, the controller’s high-frequency capability combined with twostage conversion (stepping down the +5V system
supply instead of the battery) allows the smallest possible physical size.
The MAX1813 is available in a 28-pin QSOP package.
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +30V
VCC, VDD to GND .....................................................-0.3V to +6V
PGND to GND.....................................................................±0.3V
D0–D4, CODE, ZMODE, SUS, PGOOD to GND ......-0.3V to +6V
SKP/SDN to GND (Note 1) .....................................-0.3V to +16V
ILIM, FB, CC, REF,
TON, TIME, S0, S1 to GND......................-0.3V to (VCC + 0.3V)
VPCS to GND ............................................................-2V to +30V
DL to PGND................................................-0.3V to (VDD + 0.3V)
BST to PGND..........................................................-0.3V to +36V
DH to LX ....................................................-0.3V to (VBST + 0.3V)
LX to BST..................................................................-6V to +0.3V
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin QSOP (derate 10.8mW/°C above +70°C)..........860mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: SKP/SDN may be forced to 12V, temporarily exceeding the absolute maximum rating, for the purpose of debugging prototype breadboards, using the no-fault test mode.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VPCS = ZMODE = GND = PGND, SKP/SDN = CODE = VCC, VOUT set to 1.5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Battery voltage, V+
Input Voltage Range
DC Output Voltage Accuracy
(Notes 2, 3)
2
28
VCC, VDD
4.5
5.5
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.925V to 2.0V
-1
+1
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.700V to 0.900V
-1.5
+1.5
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.600V to 0.675V
-1.83
+1.83
VPCS Input Bias Current
IVPS
VVPCS = 0 or 28V
-1
VPCS Transconductance
Gm
VVPCS = 0 to -100mV
18
VPCS Linear Input Range
FB Input Resistance
115
TIME Frequency Accuracy
IILIM
Minimum Off-Time (Note 4)
µA
22
µS
tON
tOFF(MIN)
-12
mV
265
-8
+8
380kHz nominal, RTIME = 47kΩ
-12
+12
VILIM = 0 or 5.0V
V+ = 12V, VFB = 1.2V
kΩ
+12
150kHz nominal, RTIME = 120kΩ
V+ = 5.0V, VFB = 1.2V
On-Time (Note 4)
180
%
+1
±100
RFB
38kHz nominal, RTIME = 470kΩ
ILIM Input Leakage Current
20
V
0.01
100
TON = GND
250
270
290
TON = REF
165
190
215
TON = open
320
355
390
TON = VCC
465
515
563
TON = REF, open, or VCC
400
500
TON = GND
300
375
Measured at VCC, FB forced above the
regulation point
1.4
2.5
%
nA
ns
ns
BIAS AND REFERENCE
Quiescent Supply Current (VCC)
2
ICC
_______________________________________________________________________________________
mA
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VPCS = ZMODE = GND = PGND, SKP/SDN = CODE = VCC, VOUT set to 1.5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Quiescent Supply Current (VDD)
IDD
Quiescent Supply Current (V+)
I+
CONDITIONS
MIN
TYP
MAX
UNITS
Measured at VDD, FB forced above the
regulation point
<1
5
µA
Measured at V+
25
40
µA
Shutdown Supply Current (VCC)
SKP/SDN = GND
2
5
µA
Shutdown Supply Current (VDD)
SKP/ SDN = GND
<1
5
µA
Shutdown Supply Current (V+)
SKP/SDN = GND, VCC = VDD = 0 or 5V
<1
5
µA
Reference Voltage
VREF
REF Fault Lockout Voltage
VCC = 4.5V to 5.5V, -40µA ≤ IREF ≤ +40µA
1.98
2
2.02
V
Falling edge, 1% hysteresis
1.5
1.6
1.7
V
FAULT PROTECTION
CODE = GND
2.20
2.25
2.30
CODE = VCC
1.95
2.00
2.05
Output Overvoltage Fault Preset
Threshold
VOVP
Measured at FB
Output Overvoltage Fault
Propagation Delay
tOVP
FB forced to 2% above trip threshold
V
µs
1.5
Output Undervoltage Fault
Threshold
With respect to unloaded output voltage
Output Undervoltage Fault
Propagation Delay
FB forced to 2% below trip threshold
10
µs
Output Undervoltage FaultBlanking Time
From SKP/SDN signal going high, clock
speed set by RTIME
256
clks
Current-Limit Threshold (Positive,
Default)
VITH
VGND - VVPCS, ILIM = VCC
Current-Limit Threshold
(Positive, Adjustable)
VITH
VGND - VVPCS
60
40
70
50
80
60
VILIM = 0.5V
40
50
60
VILIM = 2V (REF)
143
200
265
-72
-56
-40
Negative Current-Limit Threshold
VGND - VVPCS, with respect to VITH, ILIM =
VCC
Zero-Crossing Current-Limit
Threshold
VGND - VVPCS
Thermal Shutdown Threshold
Rising temperature, hysteresis = 15°C
VCC Undervoltage Lockout
Threshold
Rising edge, hysteresis = 20mV, switching
disabled below this level
4.05
PGOOD Lower Trip Threshold
Measured at FB with respect to unloaded
output voltage, falling edge
-15
PGOOD Upper Trip Threshold
Measured at FB with respect to unloaded
output voltage, rising edge
8
PGOOD Propagation Delay
Falling edge, FB forced 2% below or
above PGOOD trip threshold
PGOOD Output Low Voltage
ISINK = 1mA
PGOOD Leakage Current
High state, forced to 5.5V
%
mV
mV
mV
5
mV
160
°C
4.45
V
-12.5
-10.5
%
10
12
%
µs
1.5
0.4
V
1
µA
_______________________________________________________________________________________
3
MAX1813
ELECTRICAL CHARACTERISTICS (continued)
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VPCS = ZMODE = GND = PGND, SKP/SDN = CODE = VCC, VOUT set to 1.5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VBST - VLX forced to 5V
1.2
3.5
Ω
High state (pull up)
1.3
3.5
Low state (pull down)
0.4
1.0
IDH
DH forced to 2.5V, VBST - VLX forced to 5V
2.0
DL Gate Driver Sink Current
IDL
DL forced to 5V
4.0
A
DL Gate Driver Source Current
IDL
DL forced to 2.5V
1.3
A
DL rising
35
DH rising
26
GATE DRIVERS
DH Gate Driver On-Resistance
RON(DH)
DL Gate Driver On-Resistance
RON(DL)
DH Gate Driver Source/Sink
Current
Dead Time
Ω
A
ns
LOGIC AND I/O
Logic Input High Voltage
VIH
D0−D4, CODE, SUS, ZMODE; VCC = 4.5V
to 5.5V
Logic Input Low Voltage
VIL
D0−D4, CODE, SUS, ZMODE; VCC = 4.5V
to 5.5V
0.8
V
DAC Z-Mode Programming
Resistor, Low
D0−D4, 0 to 0.4V or 2.6V to 5.5V applied to
the resistor, ZMODE = CODE = GND or
ZMODE = CODE = VCC
1.05
kΩ
DAC Z-Mode Programming
Resistor, High
D0−D4, 0 to 0.4V or 2.6V to 5.5V applied to
the resistor, ZMODE = CODE = GND or
ZMODE = CODE = VCC
D0−D4, CODE Pull Up/Down
Entering impedance
mode
Logic Input Current
2.4
V
95
kΩ
Pull up
40
Pull down
8
D0−D4, CODE = VCC
-1
+1
SUS, ZMODE = GND or VCC
-1
+1
µA
4-Level Logic Input High (VCC)
TON (200kHz operation), S0, S1
VCC 0.4
4-Level Logic Input UpperMiddle (Float)
TON (300kHz operation), S0, S1
2.8
3.85
V
4-Level Logic Input LowerMiddle (REF)
TON (600kHz operation), S0, S1
1.65
2.35
V
4-Level Logic Low (GND)
TON (1000kHz operation), S0, S1
0.5
V
V
SKP/SDN High Input Level
(Skip Mode)
2.8
6.0
V
SKP/SDN Float Input Level
(Forced-PWM Mode)
1.4
2.2
V
0.5
V
SKP/SDN Low Input Level
(Shutdown Mode)
4
kΩ
_______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VPCS = ZMODE = GND = PGND, SKP/SDN = CODE = VCC, VOUT set to 1.5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
SKP/SDN NO FAULT Input Level
SKP/SDN, 4-Level Logic Input
Current
SKP/SDN, TON, S0, S1 = GND or VCC
MIN
TYP
MAX
UNITS
12
15
V
-3
3
µA
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VPCS = ZMODE = GND = PGND, SKP/SDN = CODE = VCC, VOUT set to 1.5V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
2
28
VCC, VDD
4.5
5.5
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.925V to 2.0V
-1
+1
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.700V to 0.900V
-1.5
+1.5
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.600V to 0.675V
-1.83
+1.83
VVPCS = 0 or 28V
-1
+1
VVPS = 0 to -40mV
18
22
VVPS = 0 to -100mV
16.5
22
UNITS
PWM CONTROLLER
Battery voltage, V+
Input Voltage Range
DC Output Voltage Accuracy
(Notes 2, 3)
VPCS Input Bias Current
IVPS
VPCS Transconductance
Gm
FB Input Resistance
RFB
380kHz nominal, RTIME = 47kΩ
TIME Frequency Accuracy
ILIM Input Leakage Current
IILIM
tON
Minimum Off-Time (Note 4)
tOFF(MIN)
265
-12
+12
150kHz nominal, RTIME = 120kΩ
-8
+8
38kHz nominal, RTIME = 470kΩ
-12
+12
VILIM = 0 or 5.0V
V+ = 5.0V, VFB = 1.2V
On-Time (Note 4)
115
V+ = 12V, VFB = 1.2V
100
TON = GND
250
290
TON = REF
165
215
TON = open
320
390
TON = VCC
465
563
TON = REF, open, or VCC
500
TON = GND
375
V
%
µA
µS
kΩ
%
nA
ns
ns
BIAS AND REFERENCE
Quiescent Supply Current (VCC)
ICC
Measured at VCC, FB forced above the
regulation point
2.5
mA
Quiescent Supply Current (VDD)
IDD
Measured at VDD, FB forced above the
regulation point
5
µA
Quiescent Supply Current (V+)
I+
Measured at V+
40
µA
Shutdown Supply Current (VCC)
SKP/SDN = GND
5
µA
Shutdown Supply Current (VDD)
SKP/SDN = GND
5
µA
_______________________________________________________________________________________
5
MAX1813
ELECTRICAL CHARACTERISTICS (continued)
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VPCS = ZMODE = GND = PGND, SKP/SDN = CODE = VCC, VOUT set to 1.5V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
Shutdown Supply Current (V+)
Reference Voltage
CONDITIONS
MIN
SKP/SDN = GND, VCC = VDD = 0 or 5V
VREF
REF Fault Lockout Voltage
MAX
UNITS
5
µA
VCC = 4.5V to 5.5V, -40µA ≤ IREF ≤ +40µA
1.98
2.02
V
Falling edge, 1% hysteresis
1.5
1.7
V
CODE = GND
2.20
2.30
CODE = VCC
1.95
2.05
FAULT PROTECTION
Output Overvoltage Fault Preset
Threshold
VOVP
Output Undervoltage Fault
Threshhold
Measured at FB
V
With respect to unloaded output voltage
60
80
%
40
60
mV
VILIM = 0.5V
40
60
VILIM = 2V (REF)
143
265
Current-Limit Threshold
(Positive, Default)
VITH
VGND - VVPCS, ILIM = VCC
Current-Limit Threshold
(Positive, Adjustable)
VITH
VGND - VVPCS
mV
Negative Current-Limit Threshold
VGND - VVPCS, with respect to VITH,
ILIM = VCC
-75
-35
mV
VCC Undervoltage Lockout
Threshold
Rising edge, hysteresis = 20mV, switching
disabled below this level
4.05
4.45
V
PGOOD Lower Trip Threshold
Measured at FB with respect to unloaded
output voltage, falling edge
-15
-10.5
%
PGOOD Upper Trip Threshold
Measured at FB with respect to unloaded
output voltage, rising edge
8
12
%
PGOOD Output Low Voltage
ISINK = 1mA
0.4
V
PGOOD Leakage Current
High state, forced to 5.5V
1
µA
VBST - VLX forced to 5V
3.5
Ω
High state (pull up)
3.5
Low state (pull down)
1.0
GATE DRIVERS
DH Gate Driver On-Resistance
RON(DH)
DL Gate Driver On-Resistance
RON(DL)
Ω
LOGIC AND I/O
Logic Input High Voltage
VIH
D0−D4, CODE, SUS, ZMODE; VCC = 4.5V
to 5.5V
Logic Input Low Voltage
VIL
D0−D4, CODE, SUS, ZMODE; VCC = 4.5V
to 5.5V
0.8
V
DAC Z-Mode Programming
Resistor, Low
D0−D4, 0 to 0.4V or 2.6V to 5.5V applied to
the resistor, ZMODE = CODE = GND or
ZMODE = CODE = VCC
1.05
kΩ
DAC Z-Mode Programming
Resistor, High
D0−D4, 0 to 0.4V or 2.6V to 5.5V applied to
the resistor, ZMODE = CODE = GND or
ZMODE = CODE = VCC
95
D0−D4, CODE = VCC
-1
+1
SUS, ZMODE = GND or VCC
-1
+1
Logic Input Current
6
2.4
_______________________________________________________________________________________
V
kΩ
µA
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VPCS = ZMODE = GND = PGND, SKP/SDN = CODE = VCC, VOUT set to 1.5V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
4-Level Logic Input High (VCC)
TON (200kHz operation), S0, S1
VCC 0.4
4-Level Logic Input UpperMiddle (Float)
TON (300kHz operation), S0, S1
2.8
3.85
V
4-Level Logic Input LowerMiddle (REF)
TON (600kHz operation), S0, S1
1.65
2.35
V
4-Level Logic Low (GND)
TON (1000kHz operation), S0, S1
0.5
V
V
SKP/SDN High Input Level
(Skip Mode)
2.8
6.0
V
SKP/SDN Float Input Level
(Forced-PWM Mode)
1.4
2.2
V
0.5
V
12
15
V
-3
+3
µA
SKP/SDN Low Input Level
(Shutdown Mode)
SKP/SDN NO FAULT Input Level
SKP/SDN, 4-Level Logic Input
Current
SKP/SDN, TON, S0, S1 = GND or VCC
Note 2: Output voltage accuracy specifications apply to DAC voltages from 0.6V to 2.0V.
Note 3: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple. In discontinuous conduction (SKP/SDN = VCC, light load), the output voltage will
have a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation.
Note 4: On-time and off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V,
and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to MOSFET switching speeds.
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
_______________________________________________________________________________________
7
MAX1813
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(Circuit from Figure 1, components from Table 2, TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.4V)
V+ = 4.5V
B1:
V+ = 7V
100
B1
A1
90
100
MAX1813 toc01
A1:
C1
90
B1
A1
D1: V+ = 24V
PWM MODE (SKIP = VCC)
V+ = 4.5V
B2:
V+ = 7V
C2:
V+ = 15V
D2:
V+ = 24V
D1
80
C2
70
D2
60
C2
D2
70
60
0.1
1
10
100
0.1
1
10
90
A1
B1
C1
80
C2
D1
D2
70
1.44
100
PWM MODE
SKIP MODE
1.42
1.40
1.38
VBATT = 7V
1.36
1.34
VBATT = 24V
1.32
B2
100
1.30
1.28
0.01
0.1
1
10
0
100
5
10
15
20
25
LOAD CURRENT (A)
LOAD CURRENT (A)
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.1V)
SWITCHING FREQUENCY
vs. LOAD CURRENT
SWITCHING FREQUENCY
vs. BATTERY INPUT VOLTAGE
1.08
VBATT = 7V
1.06
VBATT = 24V
1.04
1.02
300
250
200
SKIP MODE
150
100
0
5
10
15
20
LOAD CURRENT (A)
25
30
IOUT = 10A
315
VOUT = 1.4V
305
295
VOUT = 1.1V
285
VOUT = 1.4V
VBATT = 7V
50
1.00
30
MAX1813 toc08
PWM MODE
350
325
SWITCHING FREQUENCY (kHz)
1.10
MAX1813 toc07
1.12
400
SWITCHING FREQUENCY (kHz)
PWM MODE
SKIP MODE
MAX1813 toc06
LOAD CURRENT (A)
1.14
0
10
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.4V)
50
0.01
1
EFFECTIVE EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.1V)
A2
50
0.1
LOAD CURRENT (A)
60
B2
0.01
LOAD CURRENT (A)
A2
8
A2
MAX1813 toc04
MAX1813 toc03
C1
D1
80
B2
50
100
EFFECTIVE EFFICIENCY (%)
EFFECTIVE EFFICIENCY (%)
100
A1 B1
C2
70
A2
50
0.01
90
D1
80
60
B2
EFFECTIVE EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.4V)
C1
D2
OUTPUT VOLTAGE (V)
A2:
EFFICIENCY (%)
EFFICIENCY (%)
C1: V+ = 15V
MAX1813 toc05
SKIP MODE (SKIP = GND)
EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.1V)
MAX1813 toc02
EFFICIENCY CURVE LEGEND
OUTPUT VOLTAGE (V)
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
275
0
5
10
15
20
LOAD CURRENT (A)
25
30
0
4
8
12
16
BATTERY INPUT VOLTAGE (V)
_______________________________________________________________________________________
20
24
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
SWITCHING FREQUENCY
vs. TEMPERATURE
380
ON TIME (ns)
IOUT = 5A
280
260
360
IOUT = 5A
340
320
IOUT = 1A
IOUT = 10A
300
240
IOUT = 20A
280
260
220
-15
10
35
60
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
CURRENT-LIMIT DEVIATION
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT
vs. BATTERY INPUT VOLTAGE (SKIP MODE)
1.5
ICC + IDD
1.0
SUPPLY CURRENT (mA)
VILIM = 2V
1.0
1.2
MAX1813 toc11
2.0
0.5
-40
85
VILIM = 0.5V
0
-0.5
MAX1813 toc12
-40
VVPCS DEVIATION (mV)
IOUT = 1A
400
IOUT = 10A
300
MAX1813 toc10
IOUT = 20A
320
420
MAX1813 toc09
SWITCHING FREQUENCY (kHz)
340
ON TIME
vs. TEMPERATURE
0.8
VOUT = 1.4V
SKP/SDN = VCC
CODE = ZMODE = GND
0.6
0.4
-1.0
0.2
-1.5
IBATT
0
-2.0
-40
-15
10
35
60
0
85
NO-LOAD SUPPLY CURRENT
vs. BATTERY INPUT VOLTAGE (PWM MODE)
8
12
16
20
24
MAX1813 toc14
ICC + IDD
TRANSITION FREQUENCY vs. RTIME
1000
30
25
fSLEW (kHz)
SUPPLY CURRENT (mA)
MAX1813 toc13
40
35
4
BATTERY INPUT VOLTAGE (V)
TEMPERATURE (°C)
20
IBATT
15
100
10
VOUT = 1.4V
SKP/SDN = FLOAT
CODE = ZMODE = GND
5
0
TA = -40°C, 25°C, 85°C
10
0
4
8
12
16
BATTERY INPUT VOLTAGE (V)
20
24
10
100
1000
RTIME (kΩ)
_______________________________________________________________________________________
9
MAX1813
Typical Operating Characteristics (continued)
(Circuit from Figure 1, components from Table 2, TA = +25°C, unless otherwise noted.)
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Typical Operating Characteristics (continued)
(Circuit from Figure 1, components from Table 2, TA = +25°C, unless otherwise noted.)
LOAD TRANSIENT
(PWM MODE)
LOAD TRANSIENT
(VOLTAGE POSITIONING DISABLED)
LOAD TRANSIENT
(SKIP MODE)
MAX1813 toc15
MAX1813 toc17
MAX1813 toc16
20A
20A
20A
10A
A
0
1.41V
B
10A
A
0
0
1.41V
1.46V
1.36V
1.36V
1.31V
1.31V
20µs/div
A. IOUT = 0.3A TO 22A, 10A/div
B. VOUT = 1.4V, 50mV/div
SKP/SDN = FLOAT
B
1.36V
20µs/div
A. IOUT = 0.3A to 22A, 10A/div
B. VOUT = 1.4V, 50mV/div
SKP/SDN = FLOAT
DYNAMIC TRANSITION
(ZMODE TRANSITION)
MAX1813 toc18
B
1.41V
20µs/div
A. IOUT = 0.3A TO 22A, 10A/div
B. VOUT = 1.4V, 50mV/div
SKP/SDN = VCC
OUTPUT OVERLOAD WAVEFORM
A
10A
DYNAMIC TRANSITION
(SUS TRANSITION)
MAX1813 toc19
MAX1813 toc20
5V
5V
A
40A
A
20A
0
5V
A
0
5V
B
10A
0
1.4V
B
15A
C
0
C
5A
B
0
-10A
100mV
-5A
1.3V
-15A
D
C
1.2V
-100mV
1.1V
40µs/div
A. IOUT = 0 TO 40A, (0 to 35mΩ), 20A/div
B. VOUT = 1.4V, 1V/div
C. VPCS, 200mV/div
ILIM = VCC
10
D
1.3V
0.85V
40µs/div
A. VZMODE = 0 TO 5V, 5V/div
B. PGOOD, 5V/div
C. INDUCTOR CURRENT, 10A/div
D. VOUT = 1.3V TO 1.15V, IOUT = 1A, 100mV/div
CODE = VCC
40µs/div
A. VSUS = 0 TO 5V, 5V/div
B. PGOOD, 5V/div
C. INDUCTOR CURRENT, 10A/div
D. VOUT = 1.3V TO 0.85V, IOUT = 1A, 500mV/div
CODE = VCC
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
STARTUP WAVEFORM
(HEAVY LOAD)
STARTUP WAVEFORM
(NO LOAD, PWM MODE)
MAX1813 toc21
MAX1813 toc22
1.6V
1.6V
A
0
5V
A
0
5V
B
0
1.4V
C
B
0
1.4V
C
0
0
20A
10A
D
0
D
0
200µs/div
A. VSKP/SDN = 0 TO 1.6V, 2V/div
B. PGOOD, 5V/div
C. VOUT = 1.4V, ROUT = 63mΩ, 1V/div
D. INDUCTOR CURRENT, 20A/div
200µs/div
A. VSKP/SDN = 0 TO 1.6V, 2V/div
B. PGOOD, 5V/div
C. VOUT = 1.4V, NO LOAD, 1V/div
D. INDUCTOR CURRENT, 10A/div
STARTUP WAVEFORM
(NO LOAD, SKIP MODE)
SHUTDOWN WAVEFORM
MAX1813 toc24
MAX1813 toc23
1.6V
5V
A
A
0
0
5V
B
0
1.4V
5V
B
0
C
1.4V
0
C
20A
10A
D
D
0
0
200µs/div
A. VSKP/SDN = 0 TO 5V
B. PGOOD, 5V/div
C. VOUT = 1.4V, NO LOAD, 1V/div
D. INDUCTOR CURRENT, 10A/div
40µs/div
A. VSKP/SDN = 0 TO 1.6V, 2V/div
B. PGOOD, 5V/div
C. VOUT = 1.4V, ROUT = 63mΩ, 1V/div
D. INDUCTOR CURRENT, 20A/div
______________________________________________________________________________________
11
MAX1813
Typical Operating Characteristics (continued)
(Circuit from Figure 1, components from Table 2, TA = +25°C, unless otherwise noted.)
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
MAX1813
Pin Description
PIN
NAME
1
V+
2
VPCS
FUNCTION
Battery Voltage Sense Connection. Connect V+ to the input power source. V+ is used only for PWM
one-shot timing. DH on-time is inversely proportional to the input voltage over a 2V to 28V range.
Current-Sense Input. Connect a current-sense resistor (RSENSE) between VPCS and PGND. The
voltage on VPCS controls both the voltage-positioning and current-limit circuits. The slope of the
voltage-positioned output is controlled with the current-sense resistor and the gain resistor connected
between CC and REF. See Setting Voltage Positioning. The current-limit threshold is set by ILIM. If the
current-sense signal (inductor current × RSENSE) exceeds the current-limit threshold, the MAX1813
will not initiate a new cycle. VPCS can also be connected to LX to reduce component count, but CC
must be connected to REF to disable the voltage positioning.
3
SKP/SDN
Combined Shutdown and Skip-Mode Control. Drive SKP/SDN to GND for shutdown, leave SKP/SDN
open for low-noise forced-PWM mode, or drive to VCC for normal pulse-skipping operation:
Shutdown mode: SKP/SDN = GND
Low-noise forced-PWM mode: SKP/SDN = open
Normal pulse-skipping operation: SKP/SDN = VCC
Low-noise forced PWM mode causes inductor current recirculation at light loads and suppresses
pulse-skipping operation. Forcing SKP/SDN with 12V to 15V clears the fault latch and disables
undervoltage protection, overvoltage protection, and thermal shutdown with otherwise normal pulseskipping operation. Exiting shutdown clears the fault latch.
Do not connect SKP/SDN to voltages over 15V.
4
TIME
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
470kΩ to 47kΩ resistor sets the clock from 38kHz to 380kHz, respectively:
fSLEW = 150kHz x 120kΩ / RTIME.
5
FB
Feedback Input. Connect FB to the junction of the external inductor and output capacitor (Figure 1).
Compensation Capacitor and Voltage-Positioning Gain Adjustment. Connect a 47pF to 1000pF (47pF
typ) capacitor from CC to GND to adjust the loop’s response time. Connect a resistor (RAVPS) from
CC to REF to set the gain of the voltage positioning amplifier.
6
CC
 G R

V
VOUT = VOUT(PROG) 1 +  m AVPS VPCS  
 
VREF
 

where the voltage-positioning amplifer’s transconductance (Gm) is typically 20µS.
12
Suspend-Mode Voltage Select Inputs. S0 and S1 are 4-level logic inputs that select the suspendmode VID code for for the suspend-mode multiplexer inputs. If SUS is high, the suspend-mode VID
code is delivered to the DAC. See Suspend-Mode Internal Mux.
7, 8
S0, S1
9
VCC
Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V)
through a series 20Ω resistor. Bypass to GND with a 0.22µF or greater capacitor as close to the
MAX1813 as possible.
10
TON
On-Time Selection-Control Input. This is a 4-level input used to determine DH on-time. Connect to
GND, REF, or VCC, or leave TON unconnected to set the following switching frequencies: GND =
1000kHz, REF = 600kHz, floating = 300kHz, and VCC = 200kHz.
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
PIN
NAME
11
REF
+2.0V Reference Voltage Output. Bypass to GND with a 0.22µF or greater capacitor. The reference
can sink and source ±40µA (min) for external loads. Loading REF degrades FB accuracy according to
the REF load regulation error.
ILIM
Current-Limit Adjustment. The PGND - VPCS current-limit threshold defaults to 50mV if ILIM is tied to
VCC. In adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ILIM over a
500mV to 2.0V range. The logic threshold for switchover to the 50mV default value is approximately
VCC - 1V. Connect ILIM to REF for a fixed 200mV threshold.
12
FUNCTION
Open-Drain Power-Good Output. PGOOD is normally high when the output is in regulation. If VFB is not
within a +10%/-12.5% window of the DAC setting, PGOOD is asserted low. During DAC code
transitions, PGOOD is forced high until 1 clock period after the slew-rate controller finishes the
transition. PGOOD is low in shutdown, undervoltage lockout, and during soft-start. Any fault condition
forces PGOOD low, and it remains low until the fault is cleared.
13
PGOOD
14
GND
15
PGND
16
DL
Low-Side Gate-Driver Output. DL swings from GND to VDD. DL is forced high when a fault occurs, and
at the end of the shutdown sequence.
17
VDD
Supply Input for the DL Gate Drive. Connect to the system supply voltage (4.5V to 5.5V). Bypass to
PGND with a 1µF or greater capacitor.
18
SUS
Suspend-Mode Control Input. When SUS is high, the suspend-mode VID code, as programmed by S0
and S1, is delivered to the DAC. SUS overrides ZMODE. Connect SUS to GND if the suspend-mode
multiplexer is not used. See Table 6.
19
ZMODE
Performance-Mode Mux Contol Input. If SUS is low, ZMODE selects between two different VID codes.
If ZMODE = GND with CODE = VCC, or ZMODE = VCC with CODE = GND, the VID code is set by the
logic-level voltages on D0−D4. When initially entering impedance mode, the VID code is determined
by the impedance at D0−D4. See Tables 5 and 7.
20
CODE
Code Select Input. CODE acts like another VID code input to select between the Intel Mobile Voltage
Position II (IMVP-II™) or Coppermine™ VID codes. CODE also determines the polarity of the ZMODE
input. See Tables 5 and 7.
21−25
D4−D0
VID Code Inputs. D0 is the LSB and D4 is the MSB of the internal 5-bit DAC (see Tables 5 and 7). If
ZMODE = GND with CODE = VCC, or ZMODE = VCC with CODE = GND, D0−D4 are high-impedance
digital inputs, and the VID code is set by the logic-level voltages on D0−D4. When initially entering
impedance mode, the VID code is determined by the impedance at D0−D4 as follows:
Logic Low = source impedance is ≤1kΩ ±5%
Logic High = source impedance is ≥100kΩ ±5%.
26
BST
27
LX
External Inductor Connection. Connect LX to the switched side of the inductor. LX serves as the lower
supply rail for the DH high-side gate driver. LX does not connect to the current-limit comparator.
28
DH
High-Side Gate Driver Output. DH swings from LX to BST.
Analog Ground
Power Ground. PGND is one of the inputs to the current-limit comparator.
Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to the
standard high-power application circuit (Figure 1). An optional resistor in series with BST allows DH
pullup current to be adjusted.
______________________________________________________________________________________
13
MAX1813
Pin Description (continued)
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
+5V INPUT
BIAS SUPPLY
C1
1µF
BATTERY (VBATT)
7V TO 24V
C2
1µF
R1
20Ω
CIN
VDD
VCC
RGATE
100kΩ
ILIM
POWER-GOOD
INDICATOR
V+
BST
PGOOD
TIME
DH
CCOMP RTIME
47pF 120kΩ
CC
MAX1813
CREF
0.22µF
L1
0.68µH
1.4V OUTPUT
UP TO 22A
COUT
LX
DL
REF
QL
RVPCS
100Ω
D2
VPCS
CVPCS
1nF
RSENSE
SUS
OPEN
S0
OPEN
S1
CODE
D0
PGND
GND
ZMODE
FB
D1
TO VCC
QH
CBST
0.1µF
RAVPS
150kΩ
SUSPEND
MODE
D1
CFB
1nF
D2
D3
TON
D4
SKP/SDN
RFB
100Ω
OPEN (300kHz)
NOTE: SEE TABLE 1 FOR COMPLETE
LIST OF COMPONENT VALUES
OPEN (FORCED-PWM)
Figure 1. Standard High-Power Application Circuit
Detailed Description
The MAX1813 buck controller is targeted for low-voltage, high-current CPU core power supplies for notebook computers, which typically exhibit 0 to 22A (or
greater) load steps. The proprietary Quick-PWM pulsewidth modulator in the converter is specifically
designed for handling fast load steps while maintaining
a relatively constant operating frequency and inductor
operating point over a wide range of input voltages.
The Quick-PWM architecture circumvents the poor
load-transient timing problems of fixed-frequency current-mode PWMs while also avoiding the problems
caused by widely varying switching frequencies in conventional constant on-time and constant off-time PFM
schemes.
+5V Bias Supply (VCC and VDD)
The MAX1813 requires an external +5V bias supply in
addition to the battery. Typically, this +5V bias supply
is the notebook’s 95% efficient +5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
14
+5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the +5V supply can be generated
with an external linear regulator.
The +5V bias supply powers VCC (PWM controller) and
VDD (gate-drive power). The maximum current is:
IBIAS = ICC + ƒSW(QG1 + QG2) = 15mA to 45mA (typ)
where ICC is 1.4mA (typ), ƒSW is the switching frequency, and Q G1 and Q G2 are the MOSFET total gatecharge specification limits at VGS = 5V.
The battery input (V+) and +5V bias inputs (VCC and
VDD) can be connected together if the input source is a
fixed 4.5V to 5.5V supply. If the +5V bias supply is
powered up prior to the battery supply, the enable signal (SKP/SDN) must be delayed until the battery voltage is present in order to ensure startup.
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a constant-ontime, current-mode type with voltage feed-forward
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
CIRCUIT 1
(FIGURE 1)
COMPONENT
Table 2. Component Suppliers
MANUFACTURER
PHONE
[COUNTRY
CODE]
WEBSITE
Output Voltage
0.6V to 1.75V
MOSFETs
Input Voltage Range
7V to 24V
Maximum Load Current
22A
Fairchild
Semiconductor
[1] 888522-5372
www.fairchildsemi.com
Inductor
0.68µH
Sumida CDEP134H-0R6 or
Panasonic ETQP6F0R6BFA
International
Rectifier
[1] 310322-3331
www.irf.com
Frequency
300kHz (TON = float)
Siliconix
[1] 203268-6261
www.vishay.com
High-Side MOSFET
International Rectifier
(2) IRF7811A
Kemet
[1] 408986-0424
www.kemet.com
Panasonic
[1] 847468-5624
www.panasonic.com
Low-Side MOSFET
Fairchild (3) FDS7764A or
International Rectifier
(3) IRF7822A
Input Capacitor
(6) 10µF, 25V
Taiyo Yuden TMK432BJ106 or
TDK C4532X5R1E106M
Output Capacitor
(6) 220µF
Panasonic
EEFUE0E221R
Current-Sense Resistor
1.5mΩ Dale WSL 2512, plus
0.5mΩ copper PC board trace
ILIM Level
VCC (Default)
Voltage-Positioning Gain
Resistor
150kΩ
(Figure 2). This architecture relies on the output ripple
voltage to provide the PWM ramp signal. Thus, the output filter capacitor’s equivalent series resistance (ESR)
acts as a feedback resistor. The control algorithm is
simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional
to input voltage and directly proportional to output voltage (see On-Time One-Shot). Another one-shot sets a
minimum off-time (400ns typ). The on-time one-shot is
triggered if the error comparator is low, the low-side
switch current is below the current-limit threshold, and
the minimum off-time one-shot has timed out.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to the input and output voltages. The high-
Capacitors
Sanyo
[65] 2813226
(Singapore)
[1] 408749-9714
www.secc.co.jp
Taiyo Yuden
[03] 36673408
(Japan)
[1] 408573-4150
www.t-yuden.com
Coilcraft
[1] 800322-2645
www.coilcraft.com
Coiltronics
[1] 561752-5000
www.coiltronics.com
Sumida
[1] 408982-9660
www.sumida.com
Inductors
side switch on-time is inversely proportional to V+ and
directly proportional to the output voltage as set by the
DAC code. This algorithm results in a nearly constant
switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be
selected to avoid noise-sensitive regions such as the
455kHz IF band; second, the inductor ripple-current
operating point remains relatively constant, resulting in
______________________________________________________________________________________
15
MAX1813
Table 1. Component Selection for
Standard Applications
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
VBATT
5V TO 24V
REF
ILIM
V+
TON
5V
BIAS
VCC
5V BIAS
SUPPLY
FROM
DAC
TON
COMPUTE
BST
MAX1813
DH
CHIP
SUPPLY
Q
TOFF
ONE-SHOT
9R
TRIG
R
LX
GND
REF
S
2V
REF
TON
TRIG ONE-SHOT
SET
SOFT-START
Q
R CLR Q
Q
VPCS
ZERO
CROSSING
VDD
CC
DL
VPCS
S
Gm
2V
REF
SKP/SDN
REF
-12%
REF
+10%
SET
Q
PGND
R CLR Q
OVP/UVP
DETECT
FB
SUS
PGOOD
5-BIT
R-2R
DAC
S0
DECODER
(SEE FIGURE 6)
AND
SLEW-RATE CONTROLLER
S1
OSC
ZMODE CODE D0
D1
D2
D3
TIME
D4
Figure 2. Functional Diagram
16
______________________________________________________________________________________
VOUT
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
K(VOUT + 75mV)
VIN
where K is set by the TON pin-strap connection, and
75mV is an approximation to accommodate for the
expected drop across the low-side MOSFET switch and
current-sense resistor (Table 3).
The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics
table. On-times at operating points far removed from
the conditions specified can vary over a wide range.
For example, the 1000kHz setting will typically run
about 10% slower with inputs much greater than +5V,
due to the very short on-times required.
Although the on-time is set by TON, the input voltage,
and the output voltage, other factors also contribute to
the overall switching frequency. The on-time guaranteed in the Electrical Characteristics table is influenced
by switching delays in the external high-side MOSFET.
Resistive losses—including the inductor, both
MOSFETs, output capacitor ESR, and PC board copper
losses in the output and ground—tend to raise the
switching frequency at higher output currents. Switch
dead-time can increase the effective on-time, reducing
the switching frequency. This effect occurs only in
PWM mode (SKP/SDN = float) when the inductor current reverses at light or negative load currents. With
reversed inductor current, the inductor’s EMF causes
LX to go high earlier than normal, extending the on-time
by a period equal to the DH-rising dead-time (26ns
typ).
When the controller operates in continuous
mode, the dead-time is no longer a factor, and the
actual switching frequency is:
(VOUT + VDROP1)
t ON (VIN + VDROP1 − VDROP2 )
where VDROP1 is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2 is
the sum of the resistances in the charging path, including high-side switch, inductor, and PC board resistances; and t ON is the on-time calculated by the
MAX1813.
Automatic Pulse-Skipping Switchover
In skip mode (SKP/SDN = high, Table 4), an inherent
automatic switchover to PFM takes place at light
loads (Figure 3). This switchover is controlled by a
comparator that truncates the low-side switch on-time
at the inductor current’s zero crossing. This mechanism
causes the threshold between pulse-skipping PFM and
nonskipping PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation. For a 7V to 24V input voltage range, this threshold is relatively constant, with
∆i
VBATT - VOUT
=
L
∆t
IPEAK
INDUCTOR CURRENT
t ON =
ƒ SW =
ILOAD = IPEAK/2
0
ON-TIME
TIME
Figure 3. Pulse-Skipping/Discontinuous Crossover Point
Table 3. Approximate K-Factor Errors
TON SETTING
(kHz)
K-FACTOR
(µs)
APPROXIMATE
K-FACTOR ERROR
(%)
MINIMUM RECOMMENDED VBATT
AT VOUT = 1.4V (V)
200
4.9
±9
1.8
300
3.3
±10
2.0
600
1.8
±13
2.9
1000
1.05
±13
3.5
______________________________________________________________________________________
17
MAX1813
easy design methodology and predictable output voltage ripple.
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Table 4. Operating Mode Truth Table
SKP/SDN
DL
MODE
COMMENTS
GND
High
Shutdown
Micropower shutdown state (ICC = 2µA typ).
VCC
Switching
Normal
Operation
Automatic switchover from PWM mode to pulse-skipping PFM mode at
light loads. Prevents inductor current from recirculating into the input.
Float
Switching
Forced PWM
Low-noise forced-PWM mode causes inductor current to reverse at
light loads and suppresses pulse-skipping operation.
12V
Switching
NO-FAULT Test
Mode
Test mode with overvoltage, undervoltage, and thermal shutdown
faults disabled. Otherwise, the converter operates as if SKP/SDN =
VCC.
VCC or Float
High
FAULT
The fault latch set by the overvoltage protection, output undervoltage
protection, or thermal shutdown. The MAX1813 will remain in FAULT
mode until VCC power is cycled or SKP/SDN is forced low.
only a minor dependence on the input voltage:
V
  V − VOUT 
ILOAD(SKIP) ≈ K  OUT   IN

 2L  
VIN

where K is the on-time scale factor (Table 3). The loadcurrent level at which PFM/PWM crossover occurs
(ILOAD(SKIP)) is equal to 1/2 the peak-to-peak ripple
current, which is a function of the inductor value (Figure
3). For example, in the standard application circuit with
K = 3.3µs (300kHz), VIN = 12V, VOUT = 1.4V, and L =
0.68µH, switchover to pulse-skipping operation occurs
at ILOAD = 3.0A or about 1/4 full load. The crossover
point occurs at an even lower value if a swinging (softsaturation) inductor is used.
The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping
operation; this is a normal operating condition that
improves light-load efficiency. Trade-offs in PFM noise
vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-transient response (especially at low input voltage levels).
Forced-PWM Mode
The low-noise, forced-PWM mode (SKP/SDN left floating, Table 4) disables the zero-crossing comparator
that controls the low-side switch on-time. The resulting
low-side gate-drive waveform is forced to be the complement of the high-side gate-drive waveform. This, in
turn, causes the inductor current to reverse at light
18
loads because the PWM loop strives to maintain a duty
ratio of VOUT/VIN. The benefit of forced-PWM mode is
to keep the switching frequency nearly constant, but it
results in higher no-load supply current that can be
15mA to 45mA, depending on the external MOSFETs
and switching frequency.
The MAX1813 uses forced-PWM mode during all transitions, while the slew-rate controller is active. During
downward output voltage transitions, forced-PWM
allows the MAX1813 to sink current, thereby rapidly
pulling down the output voltage. When a transition uses
high negative inductor current, due to voltage positioning, the output voltage may not settle to its intended
final value until after the slew-rate controller terminates.
For this reason, most applications should use PWM
mode exclusively, although skip mode is beneficial in
the low-power suspend state (see Shutdown and Mode
Control).
Shutdown and Mode Control (SKP/SDN)
When SKP/SDN is driven low, the MAX1813 enters the
low-current shutdown mode (Table 4). Shutdown forces
PGOOD low immediately and ramps down the output
voltage in 25mV increments at the clock rate set by
R TIME . Once the output voltage ramps down, the
MAX1813 pulls DH low, forces DL high, and shuts
down the reference, so the total supply current (ICC +
IDD + I+) drops to 4µA (typ).
When SKP/SDN is left floating or driven high, the
MAX1813 begins the startup sequence. First, the reference powers up. After the reference exceeds its 1.6V
undervoltage lockout threshold, the DAC determines
the target output voltage and starts ramping up the output voltage. The slew-rate controller increases the out-
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Current-Limit Circuit (ILIM)
The current-limit circuit employs a unique “valley” current-sensing algorithm. If the current-sense signal is
above the current-limit threshold, the MAX1813 will not
initiate a new cycle (Figure 4). The actual peak current
is greater than the current-limit threshold by an amount
equal to the inductor ripple current. Therefore the exact
current-limit characteristic and maximum load capability are a function of the current-limit threshold, inductor
value, and input voltage. The reward for this uncertainty
is robust, loss-less over-current sensing. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every
circumstance.
There is also a negative current limit that prevents
excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to
approximately 120% of the positive current limit and
therefore tracks the positive current limit when ILIM is
adjusted.
The MAX1813 measures the current by sensing the
voltage between VPCS and PGND. Connect an external
sense resistor between the source of the low-side Nchannel MOSFET and PGND. The signal provided by
this current-sense resistor is also used for voltage positioning (see Setting Voltage Positioning). Reducing the
sense voltage increases the relative measurement
error. However, the configuration eliminates the uncertainty of using the low-side MOSFET on-resistance to
measure the current, so the resulting current-limit tolerance is tighter when sensing with a 1% sense resistor.
The voltage at ILIM sets the current-limit threshold. For
voltages from 500mV to 2V, the current-limit threshold
voltage is precisely 0.1 x VILIM. Set this voltage with a
resistive divider between REF and GND. The currentlimit threshold defaults to 50mV when ILIM is tied to
VCC. The logic threshold for switchover to this 50mV
default value is approximately VCC - 1V.
MAX1813
IPEAK
ILOAD
INDUCTOR CURRENT
put voltage in 25mV increments at the clock rate set by
RTIME until the MAX1813 reaches the selected output
voltage. The MAX1813 does not feature traditional variable current-limit soft-start, so full output current is
immediately available. Once the slew-rate controller terminates, output undervoltage fault blanking period
ends, and the output voltage is in regulation, PGOOD
goes high.
Leave SKP/SDN floating for forced-PWM operation, or
connect SKP/SDN to VCC for normal operation. During
all transitions, the MAX1813 uses PWM mode while the
slew-rate controller is active. Exiting shutdown clears
the fault latch.
ILIMIT
0
TIME
Figure 4. “Valley” Current-Limit Threshold Point
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the current-sense signals seen by VPCS and GND. The IC
must be mounted close to the current-sense resistor
with short, direct traces making a Kelvin sense connection (see PC Board Layout Guidelines).
MOSFET Gate Drivers (DH and DL)
The DH and DL drivers are optimized for driving moderate-sized, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VIN - VOUT differential exists. An adaptive dead-time
circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate for the adaptive dead-time
circuit to work properly. Otherwise, the sense circuitry
in the MAX1813 will interpret the MOSFET gate as “off”
while there is actually charge still left on the gate. Use
very short, wide traces (50 to 100 mils wide if the MOSFET is 1 inch from the device). The dead time at the
other edge (DH turning off) is determined by a fixed
35ns internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.4Ω (typ) on-resistance. This helps prevent DL from being pulled up during the fast rise-time
of the LX node, due to capacitive coupling from the
drain to the gate of the low-side synchronous-rectifier
MOSFET. However, for high-current applications, some
combinations of high- and low-side FETs may cause
excessive gate-drain coupling, leading to poor
______________________________________________________________________________________
19
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
to select the new 0.600V to 1.750V DAC codes, which
are compatible with the IMVP-II specifications. CODE
also determines the polarity of ZMODE (Table 7).
+5V
VBATT
BST
5Ω TYP
DH
LX
MAX1813
Figure 5. Reducing the Switching-Node Rise Time
Suspend-Mode Operation (S0, S1)
When the CPU clock stops, the processor enters suspend mode and requires a lower supply voltage to minimize power consumption. The MAX1813 includes
suspend-mode output voltages that are selected using
two 4-level input pins (S0 and S1, Table 6). When the
CPU clock stops, drive SUS high to transition to the
suspend-mode output voltage. During the transition,
the MAX1813 asserts forced-PWM mode to sink current
and pull down the output voltage until PGOOD goes
high.
When SUS is driven high, suspend mode overrides the
5-bit DAC setting. When SUS is low, the MAX1813
determines the output voltage from the 5-bit DAC
(D0–D4), CODE, and ZMODE settings.
Internal Multiplexers (ZMODE, SUS)
efficiency, EMI, and shoot-through currents. This is
often remedied by adding a resistor less than 5Ω in
series with BST, which increases the turn-on time of the
high-side FET without degrading the turn-off time
(Figure 5).
DAC Converter (D0-D4)
The digital-to-analog converter (DAC) programs the
output voltage. It receives a preset digital code from
the CPU pins, digital logic, general-purpose I/O, or an
external multiplexer. Do not leave D0–D4 floating; use
1MΩ or less pullups if the inputs may float.
The state of DO–D4 can be changed while the switchmode power supply is active, initiating a transition to a
new output voltage level. During this interval, the slewrate controller is active, so the MAX1813 uses forcedPWM mode. If this mode of DAC control is used,
connect ZMODE low. Change D0–D4 together, avoiding greater than 1µs skew between bits. Otherwise,
incorrect DAC readings may cause a partial transition
to the wrong voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages (Table 5) are compatible with the
Coppermine™ and Intel’s Mobile Voltage Positioning II
(IMVP-II™) specifications.
VID Code Options (CODE)
The MAX1813 contains two separate sets of VID codes.
The CODE pin selects between the two output voltage
tables (Table 5). Drive CODE low to select the older
0.925V to 2.000V DAC codes, which are compatible
with the Coppermine specifications. Drive CODE high
20
The MAX1813 has a unique internal multiplexer that
can select one of three different VID code settings for
different processor states. Depending on the logic level
at SUS, the suspend (SUS) mode multiplexer selects
the VID code settings from either the D0-D4 input
decoder or the S0/S1 input decoder. The ZMODE multiplexer selects one of the two D0-D4 input modes, setting the VID code based on either the voltage on D0-D4
(logic mode) or the impedance decoder output (impedance mode) (Figure 6).
When SUS is high, the suspend-mode multiplexer
selects the VID code from the S0/S1 input decoder. The
decoder outputs are determined by inputs S0 and S1
(Table 6). When SUS is low, the suspend-mode multiplexer selects the D0-D4 input decoder output.
In logic mode (Table 7), the logic-level voltages on D0D4 set the DAC settings. In this mode, the inputs are
continuously active and can be dynamically changed
by external logic. The logic-mode VID code setting is
typically used for the battery-mode state, and the
source of this code is sometimes the VID pins of the
CPU with suitable pullup resistors.
Impedance mode (Table 7) is programmed by external
resistors in series with D0–D4, using a unique scheme
that allows two sets of data bits using only one set of
pins. When the MAX1813 initially enters impedance
mode, the resistances at D0–D4 are sampled by the
impedance decoder to see if there is a large resistance
in series with the pin. If the voltage level on a DAC input
pin is a logic low, an internal switch connects that pin to
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
MAX1813
Table 5. Output Voltage vs. DAC Codes
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUTPUT VOLTAGE (V)
CODE = 0
CODE = 1
0
2.000
1.750
0
1
1.950
1.700
1
0
1.900
1.650
0
1
1
1.850
1.600
0
1
0
0
1.800
1.550
0
1
0
1
1.750
1.500
0
0
1
1
0
1.700
1.450
0
0
1
1
1
1.650
1.400
0
1
0
0
0
1.600
1.350
0
1
0
0
1
1.550
1.300
0
1
0
1
0
1.500
1.250
0
1
0
1
1
1.450
1.200
0
1
1
0
0
1.400
1.150
0
1
1
0
1
1.350
1.100
0
1
1
1
0
1.300
1.050
0
1
1
1
1
NO CPU*
1.000
1
0
0
0
0
1.275
0.975
1
0
0
0
1
1.250
0.950
1
0
0
1
0
1.225
0.925
1
0
0
1
1
1.200
0.900
1
0
1
0
0
1.175
0.875
1
0
1
0
1
1.150
0.850
1
0
1
1
0
1.125
0.825
1
0
1
1
1
1.100
0.800
1
1
0
0
0
1.075
0.775
1
1
0
0
1
1.050
0.750
1
1
0
1
0
1.025
0.725
1
1
0
1
1
1.000
0.700
1
1
1
0
0
0.975
0.675
1
1
1
0
1
0.950
0.650
1
1
1
1
0
0.925
0.625
1
1
1
1
1
NO CPU*
0.600
*In the NO CPU State, DH and DL are held low and the slew-rate controller is set for 0.425V.
______________________________________________________________________________________
21
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ZMODE
MUX
D0
D1
D2
D3
D4
D0-D4
DECODER
01 OR 10
OUT
IMPEDANCE
DECODER
IN
SUS MUX
0
OUT
00 OR 11
CODE
OUT
OUT
SEL0 SEL1
(FIGURE 7)
ZMODE
CODE
DAC
S0/S1
DECODER
S0
S1
IN
1
OUT
SUS
MAX1813
SUS
Figure 6. Internal Multiplexers Block Diagram
an internal 40kΩ pullup for about 4µs to see if the pin
voltage can be forced high (Figure 7). If the pin voltage
cannot be pulled to a logic high, the pin is considered
low impedance, and its impedance-mode logic state is
low. If the pin can be pulled to a logic high, the impedance is considered high and so is the impedancemode logic state. Similarly, if the voltage level on the
pin is a logic high, an internal switch connects the pin
to an internal 8kΩ pulldown to see if the pin voltage can
be forced low. If so, the pin is high impedance, and its
impedance-mode logic state is high. In either sampling
condition, if the pin’s logic level does not change, the
pin is determined to be low impedance, and the impedance-mode logic state is low.
Table 6. Suspend-Mode Output Voltages
S1
S0
OUTPUT VOLTAGE (V)
GND
GND
0.975
GND
REF
0.950
GND
Float*
0.925
GND
VCC
0.900
REF
GND
0.875
REF
REF
0.850
REF
Float*
0.825
REF
VCC
0.800
Float*
GND
0.775
Float*
REF
0.750
Float*
Float*
0.725
Float*
VCC
0.700
VCC
GND
0.675
VCC
REF
0.650
Output Voltage Transition Timing (TIME)
VCC
Float*
0.625
The MAX1813 is designed to perform output voltage
transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a
given output capacitance. This makes the IC very suitable for IMVP-II CPUs and other CPUs that operate in
two or more modes with different core voltage levels.
The IMVP-II CPUs operate at multiple clock frequencies
and require multiple core voltages. When transitioning
VCC
VCC
0.600
A high pin impedance (logic high) is 100kΩ or greater,
and a low impedance (logic low) is 1kΩ or less. The
guaranteed levels for these impedances are 95kΩ and
1.05kΩ to allow the use of standard 100kΩ and 1kΩ resistors with 5% tolerance.
22
*Float = no connection
Table 7. ZMODE Polarity Table
CODE
ZMODE
0
0
Impedance Mode
0
1
Logic Mode
1
0
Logic Mode
1
1
Impedance Mode
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
VCC
MAX1813
3.0V TO 5.5V
26kΩ
26kΩ
26kΩ
26kΩ
26kΩ
D4
100kΩ
100kΩ
D3
B-DATA
LATCH
D2
where ƒSLEW = 150kHz x 120kΩ/RTIME, VOLD is the
original output voltage, and VNEW is the new output
voltage. See TIME Frequency Accuracy in Electrical
Characteristics for ƒSLEW accuracy.
The practical range of RTIME is 47kΩ to 470kΩ, corresponding to 2.6µs to 26µs per 25mV step. Although the
DAC takes discrete 25mV steps, the output filter makes
the transitions relatively smooth. The average inductor
current required to make an output voltage transition is:
IL ≅ COUT × 25mV × ƒ SLEW
D1
Power-On Reset and Undervoltage
Lockout
D0
8kΩ
8kΩ
8kΩ
8kΩ
8kΩ
GND
Figure 7. Internal Mux Impedance-Mode Data Test and Latch
from one clock frequency to another, the CPU first goes
into a low-power state, then the output voltage and
clock frequency are changed. The change must be
accomplished in 100µs or the system may halt.
At the beginning of an output voltage transition, the
MAX1813 forces the PGOOD output high. PGOOD
remains masked high until the slew-rate controller has
set the internal DAC to the final value and one additional slew-rate clock period has passed.
The output voltage transition is performed in 25mV
increments, preceded by a 4µs delay and followed by
one additional clock period after which PGOOD will
remain high if the output voltage is in regulation. The
total time for a transition depends on RTIME, the voltage
difference, and the accuracy of the MAX1813’s slewrate clock. The greater the output capacitance, the
higher the surge current required for the transition. The
MAX1813 will automatically control the current to the
minimum level required to complete the transition in the
calculated time, as long as the surge current is less
than the current limit set by ILIM. The transition time is
given by:
 1
VOLD - VNEW  

t TRAN ≤ 4µs + 
1+


25mV
 ƒ SLEW 
V CC undervoltage lockout (UVLO) circuitry inhibits
switching, forces PGOOD low, and forces the DL gate
driver high. If the VCC voltage drops below 4.2V, it is
assumed that there is not enough supply voltage to
make valid decisions. To protect the output from overvoltage faults, DL is forced high in this mode; this will
force the output to ground. This results in large negative inductor current and possibly small negative output
voltages. If VCC is likely to drop in this fashion, the output can be clamped with a Schottky diode to PGND to
reduce the negative excursion.
Power-on reset (POR) occurs when VCC rises above
approximately 2V. This resets the fault latch and prepares the PWM for operation. When VCC rises above
4.2V, the DAC inputs are sampled, and the output voltage begins to slew to the DAC setting. To ensure correct startup, V+ should be present before VCC. If the
converter attempts to bring the output into regulation
without V+ present, the fault latch will trip. For automatic startup, the battery voltage (V+) should be present
before VCC. The SKP/SDN pin can be forced low or
VCC power cycled to reset the fault latch.
Power-Good Output (PGOOD)
PGOOD is the open-drain output of a window comparator. This power-good output remains high impedance
as long as the output voltage is within +10%/-12.5% of
the regulation voltage. When the output voltage is
greater than 10% or less than the -12.5% window limits,
the internal MOSFET is activated and pulls the output
low. While the slew-rate controller is active (except during startup and shutdown), the MAX1813 forces
PGOOD high. PGOOD is low in shutdown, input undervoltage lockout, and during startup. Any fault condition
forces PGOOD low until the fault is cleared. For logiclevel output voltages, connect an external pullup resistor between PGOOD and V CC (or V DD ). A 100kΩ
resistor works well in most applications.
______________________________________________________________________________________
23
MAX1813
+5V
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Output Overvoltage Protection
The overvoltage protection circuit is designed to protect the CPU against a shorted high-side MOSFET by
drawing high current and activating the battery’s protection circuit. The output voltage is continuously monitored for overvoltage. If the output exceeds the
overvoltage threshold, the fault protection is triggered
and the circuit shuts down. The DL low-side gate-driver
output latches high, which turns on the synchronousrectifier MOSFET with 100% duty and, in turn, rapidly
discharges the output filter capacitor, forcing the output
to ground. If the condition that caused the overvoltage
(such as a shorted high-side MOSFET) persists, the
battery’s protection circuit will engage. The MAX1813 is
latched off and won’t restart until SKP/SDN is toggled
or VCC power is cycled.
Overvoltage protection can be defeated using the nofault test mode (see No-Fault Test Mode).
Output Undervoltage Protection
The output undervoltage protection (UVP) function is
similar to foldback current limiting but employs a timer
rather than a variable current limit. If the MAX1813 output voltage is under 70% of the nominal value, the
PWM is latched off and won’t restart until SKP/SDN is
toggled or VCC power is cycled. To allow startup, UVP
is ignored during the undervoltage fault-blanking time
(the first 256 cycles of the slew rate after startup).
UVP can be defeated using the no-fault test mode (see
No-Fault Test Mode).
Thermal Fault Protection
The MAX1813 features a thermal fault protection circuit.
When the temperature rises above +160°C, the DL lowside gate-driver output latches high until SKP/SDN is
toggled or VCC power is cycled. The threshold has
+15°C of thermal hysteresis, which prevents the regulator from restarting until the die cools off.
Thermal shutdown can be defeated using the no-fault
test mode (see No-Fault Test Mode).
No-Fault Test Mode
The over/undervoltage protection features can complicate the process of debugging prototype breadboards
since there are at most a few milliseconds in which to
determine what went wrong. Therefore, a test mode is
provided to disable the overvoltage protection, undervoltage protection, and thermal shutdown features, and
clear the fault latch if it has been set. In “no-fault” test
mode, the regulator operates as if SKP/SDN were high
(SKIP mode). Forcing 12V to 15V on SKP/SDN activates
no-fault test mode.
24
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:
Input voltage range: The maximum value (VIN(MAX))
must accommodate the worst-case high AC-adapter
voltage. The minimum value (VIN(MIN)) must account for
the lowest input voltage after drops due to connectors,
fuses, and battery selector switches. If there is a choice
at all, lower input voltages result in better efficiency.
Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines
the instantaneous component stresses and filtering
requirements, and thus drives output capacitor selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load current
(I LOAD ) determines the thermal stresses and thus
drives the selection of input capacitors, MOSFETs, and
other critical heat-contributing components. Modern
notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x
80%.
Switching frequency: This choice determines the
basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements
in MOSFET technology that are making higher frequencies more practical.
Inductor operating point: This choice provides tradeoffs between size vs. efficiency. Low inductor values
cause large ripple currents, resulting in the smallest
size but poor efficiency and high output noise. The minimum practical inductor value is one that causes the
circuit to operate at the edge of critical conduction
(where the inductor current just touches zero with every
cycle at maximum load). Inductor values lower than this
grant no further size-reduction benefit.
The MAX1813’s pulse-skipping algorithm initiates skip
mode at the critical-conduction point. Thus, the inductor operating point also determines the load-current
value at which PFM/PWM switchover occurs. The optimum operating point is usually found between 20% and
50% ripple current.
The inductor ripple current impacts transient-response
performance, especially at low VIN - VOUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output fil-
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
VSAG =
 V

K
L(ILOAD1 -ILOAD2 )2  OUT  + t OFF(MIN) 
 VIN 

 (V - V

)K 
2COUT VOUT  IN OUT  - t OFF(MIN) 
V



IN


where tOFF(MIN) is the minimum off-time (see Electrical
Characteristics), and K is from Table 3.
Inductor Selection
The switching frequency and operating point (% ripple
or LIR) determine the inductor value as follows:
L=
VOUT × (VIN − VOUT )
VIN × ƒ SW × ILOAD(MAX) × LIR
Example: ILOAD(MAX) = 22A, VIN = 12V, VOUT = 1.4V,
fSW = 300kHz, 30% ripple current, or LIR = 0.3.
1.4V × (12V -1.4V)
L=
= 0.62µH
12V × 300kHz × 22A × 0.3
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (IPEAK).
IPEAK = ILOAD(MAX) + (ILOAD(MAX) x LIR / 2)
Setting the Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus
half of the ripple current; therefore:
 ILOAD(MAX)LIR 
ILIMIT(LOW) >ILOAD(MAX) - 

2


where I LIMIT(LOW) equals the minimum current-limit
threshold voltage divided by RSENSE. For the 50mV
default setting, the minimum current-limit threshold is
40mV.
threshold is precisely 1/10th the voltage seen at ILIM.
For an adjustable threshold, connect a resistive divider
from REF to GND, with ILIM connected to the center
tap. The external 0.5V to 2.0V adjustment range corresponds to a 50mV to 200mV current-limit threshold.
When adjusting the current limit, use 1% tolerance
resistors and a 10µA divider current to prevent a significant increase of errors in the current-limit tolerance.
Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements. Also, the capacitance
value must be high enough to absorb the inductor
energy going from a full-load to no-load condition without tripping the overvoltage protection circuit.
In CPU VCORE converters and other applications where
the output is subject to large load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
RESR = VSTEP(MAX) / ILOAD(MAX)
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalums, OS-CONs, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent VSAG
and VSOAR from causing problems during load transients. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the
rising load edge is no longer a problem (see the VSAG
equation in the Design Procedure). The amount of overshoot due to stored inductor energy can be calculated
as:
VSOAR ≈
IPEAK 2 L
2COUT VOUT
where IPEAK is the peak inductor current.
Output Capacitor Stability Considerations
Stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:
Connect ILIM to VCC for a default 50mV current-limit
threshold. In the adjustable mode, the current-limit
______________________________________________________________________________________
25
MAX1813
ter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time:
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ƒ
ƒ ESR = SW
π
where:
ƒ ESR =
1
2πRESR COUT
For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below
50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP
capacitors in wide-spread use at the time of publication
have typical ESR zero frequencies below 30kHz. In the
standard application used for inductor selection, the
ESR needed to support a 30mVp-p ripple is 30mV/(22A
x 0.3) = 4.5mΩ. Six 220µF/2.5V Panasonic SP capacitors in parallel provide 2.5mΩ (max) ESR. The capacitors’ typical ESR results in a zero at 48kHz.
Don’t put high-value ceramic capacitors directly across
the output without taking precautions to ensure stability.
Ceramic capacitors have a high ESR zero frequency
and may cause erratic, unstable operation. However,
it’s easy to add enough series resistance by placing
the capacitors a couple of inches downstream from the
junction of the inductor and the FB pin.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feed-back
loop instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there isn’t enough voltage ramp in the output voltage signal. This “fools” the
error comparator into triggering a new cycle immediately after the minimum off-time period has expired.
Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability, which is caused by insufficient ESR.
Loop instability can result in oscillations at the output
after line or load perturbations that can cause the output voltage to rise above or fall below the tolerance
limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for overshoot and ringing. It can help to monitor simultaneously
the inductor current with an AC current probe. Don’t
allow more than one cycle of ringing after the initial
step-response under/overshoot.
26
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents
defined by the following equation:
IRMS =ILOAD
VOUT (VIN - VOUT )
VIN
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their
resistance to inrush surge currents typical of systems
with a mechanical switch or connector in series with the
input. If the MAX1813 is operated as the second stage
of a two-stage power-conversion system, tantalum
input capacitors are acceptable. In either configuration,
choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
circuit longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>20A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
The high-side MOSFET (QH) must be able to dissipate
the resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Calculate both of these sums.
Ideally, the losses at VIN(MIN) should be roughly equal
to losses at VIN(MAX), with lower losses in between. If
the losses at VIN(MIN) are significantly higher than the
losses at VIN(MAX), consider increasing the size of QH.
Conversely, if the losses at VIN(MAX) are significantly
higher than the losses at VIN(MIN), consider reducing
the size of QH. If VIN does not vary over a wide range,
the minimum power dissipation occurs where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible on-resistance (R DS(ON)), comes in a moderatesized package (i.e., one or two SO-8s, DPAK or
D2PAK), and is reasonably priced. Make sure that the
DL gate driver can supply sufficient current to support
the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction problems may occur.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (QH), the worstcase power dissipation due to resistance occurs at the
minimum input voltage:
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
PD (QH Re sistive) =
VIN
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power-dissipation specifications often limits how small
the MOSFET can be. Again, the optimum occurs when
the switching losses equal the conduction (RDS(ON))
losses. High-side switching losses don’t usually
become an issue until the input is greater than approximately 15V.
Calculating the power dissipation in the high-side MOSFET (QH) due to switching losses is difficult since it
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including
verification using a thermocouple mounted on Q1:
2
PD (QH Switching) =
VIN(MAX) CRSS ƒ SW ILOAD
IGATE
where CRSS is the reverse transfer capacitance of QH,
and IGATE is the peak gate-drive source/sink current
(1A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC-adapter
voltages are applied, due to the squared term in the C
x VIN2 x ƒSW switching-loss equation. If the high-side
MOSFET chosen for adequate RDS(ON) at low battery
voltages becomes extraordinarily hot when biased from
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (QL), the worst-case power
dissipation always occurs at the maximum input
voltage:
 

2
V
PD (QL Re sistive) = 1-  OUT   ILOAD RDS(ON)


  VIN(MAX)  


The worst case MOSFET power dissipation occurs
under heavy overloads that are greater than
ILOAD(MAX) but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To protect against this possibility, you can “overdesign” the
circuit to tolerate:
I

LOAD(MAX)LIR
ILOAD = ILIMIT(HIGH) + 


2


where I LIMIT(HIGH) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (D1) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal
to 1/3 of the load current. This diode is optional and
can be removed if efficiency isn’t critical.
Setting Voltage Positioning
Voltage positioning dynamically changes the output
voltage set point in response to the load current. When
the output is loaded, the signal fed back from the VPCS
input adjusts the output voltage set point, thereby
decreasing power dissipation. The load-transient
response of this control loop is extremely fast yet well
controlled, so the amount of voltage change can be
accurately confined within the limits stipulated in the
microprocessor power-supply guidelines. To understand the benefits of dynamically adjusting the output
voltage, see Voltage Positioning and Effective
Efficiency.
The amount of output voltage change is adjusted by an
external gain resistor (RAVPS). Place RAVPS between
REF and CC (Figure 8). The voltage developed across
the current-sense resistor (VVPCS) relates to the output
voltage as follows:
 G R

V
VOUT = VOUT(PROG) 1+  m AVPS VPCS  
VREF
 
 
where VOUT(PROG) is the programmed output voltage
set by the DAC code (Table 5), and the VPCS transconductance (G m ) is typically 20µS (see Electrical
Characteristics). The MAX1813 contains internal
clamps to limit the voltage positioning between 10%
below and 2% above the programmed output voltage.
The MAX1813 determines the load current from the
voltage across the current-sense resistor (R SENSE )
between the source of the low-side MOSFET and
PGND. Therefore, the current-sense voltage present at
VPCS is determined by:
VVPCS = -ILOADRSENSE (1-D)
______________________________________________________________________________________
27
MAX1813
2
VOUTILOAD RDS(ON)
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
simple low-pass RC filter with a 100ns time constant
(100Ω x 1000pF) sufficiently reduces the noise on the
current-sense signal (Figure 8).
REF
CREF
Voltage-Positioning Compensation (CC)
Q2
DL
RAVPS
VPCS
CC
RVPCS
Applications Information
CVPCS
CCOMP
RSENSE
MAX1813
PGND
GND
Figure 8. Voltage-Positioning Block Diagram
where D = V OUT /V IN is the regulator’s duty cycle.
However, since the ratio of the output-to-input voltage
is usually relatively large, the effect of the duty cycle on
the circuit’s performance is not significant. Therefore,
the complete expression for the voltage-positioned output depends upon the load current, the value of the
voltage-positioning gain resistor, and the value of the
current-sense resistor:
 G R

R
I
VOUT ≈ VOUT(PROG) 1-  m AVPS SENSE LOAD  
V
 
 
REF
The MAX1813 voltage-positioning circuit has several
advantages over older circuits, which added a fixed
voltage offset on the sense point and used a low-value
resistor in series with the output. The new circuit uses
the same current-sense resistor for both voltage positioning and current-limit detection. This simultaneously
provides accurate current limiting and voltage positioning. Since the new circuit adjusts the output voltage
within the control loop, the voltage-positioning signal
may be internally amplified. The additional gain allows
the use of low-value current-sense resistors, so the
power dissipated in this sense resistor is significantly
lower than a single resistor connected directly in series
with the output.
The current-sense signal from the sense resistor to the
VPCS pin should be filtered to eliminate the effect of
switching noise on the voltage-positioned output. A
28
The voltage-positioning compensation capacitor filters
the amplified VPCS signal, allowing the user to adjust
the dynamics of the voltage-positioning loop. Since the
output impedance of the transconductance amplifier is
much greater than RAVPS, the pole provided by this
node can be approximated by 1/(2πRAVPSCCOMP). The
response time is set with a 47pF to 1000pF capacitor
from CC to GND.
Voltage Positioning and Effective
Efficiency
Powering new mobile processors requires careful
attention to detail to reduce cost, size, and power dissipation. As CPUs became more power hungry, it was
recognized that even the fastest DC-DC converters
were inadequate to handle the transient power requirements. After a load transient, the output instantly
changes by ESRCOUT x ∆ILOAD. Conventional DC-DC
converters respond by regulating the output voltage
back to its nominal state after the load transient occurs
(Figure 9). However, the CPU only requires that the output voltage remains above a specified minimum value.
Dynamically positioning the output voltage to this lower
limit allows the use of fewer output capacitors and
reduces power consumption under load.
For a conventional (nonvoltage-positioned) circuit, the
total voltage change is:
VOLTAGE POSITIONING THE OUTPUT
1.4V
A
1.4V
B
A. CONVENTIONAL CONVERTER (50mV/div)
B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
Figure 9. Voltage Positioning the Output
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ESR STEP-DOWN
AND STEP-UP
(ISTEP x ESR)
VOUT
CAPACITIVE SAG
(dV/dt = IOUT/COUT)
RECOVERY
from the hot CPU are beneficial. Effective efficiency is
defined as the efficiency required of a non-voltagepositioned circuit to equal the total dissipation of a voltage-positioned circuit for a given CPU operating
condition.
Calculate effective efficiency:
1) Start with the efficiency data for the positioned circuit
VIN, IIN, VOUT, IOUT).
2) Model the load resistance for each data point:
RLOAD = VOUT / IOUT
3) Calculate the output current that would exist for each
RLOAD data point in a nonpositioned application:
INP = VNP / RLOAD
ILOAD
where VNP = 1.4V (in this example).
Figure 10. Transient-Response Regions
VP-P1 = 2 x (ESRCOUT x ∆ILOAD) + VSAG + VSOAR
where V SAG and V SOAR are defined in Figure 10.
Setting the converter to regulate at a lower voltage
when under load allows a larger voltage step when the
output current suddenly decreases (Figure 9). So the
total voltage change for a voltage-positioned circuit is:
VP-P2 = (ESRCOUT x ∆LOAD) + VSAG + VSOAR
where V SAG and V SOAR are defined in the Design
Procedure. Since the amplitudes are the same for both
circuits (VP-P1 = VP-P2), the voltage-positioned circuit
requires only twice the ESR. Since the ESR specification is achieved by paralleling several capacitors, fewer
units are needed for the voltage-positioned circuit.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Because the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in
RSENSE. However, the gain of the voltage positioning
block reduces the power dissipation in RSENSE. For a
nominal 1.4V, 22A output (RLOAD = 63.6mΩ), reducing
the output voltage 6% gives a 1.32V output voltage and
a 20.7A output current. Given these values, CPU power
consumption is reduced from 30.8W to 27.3W. The
additional power consumption of RSENSE is:
2.0mΩ x (20.7A)2 = 0.86W
and the overall power savings is:
30.8W - (27.3W + 0.86W) = 2.62W
In effect, 2.62W of CPU dissipation is saved and the
power supply dissipates much of the savings, but both
the net savings and the transfer of dissipation away
4) Calculate effective efficiency as:
Effective efficiency = (VNP x INP) / (VIN x IIN) = calculated nonpositioned power output divided by the
measured voltage-positioned power input.
5) Plot the efficiency data point at the nonpositioned
current, INP.
The effective efficiency of voltage-positioned circuits is
shown in the Typical Operating Characteristics.
Dropout Performance
The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable
500ns (max) minimum off-time one-shot. For best
dropout performance, use the slower (200kHz) on-time
settings. When working with low input voltages, the
duty-factor limit must be calculated using worst-case
values for on- and off-times. Manufacturing tolerances
and internal propagation delays introduce an error to
the TON K-factor. This error is greater at higher frequencies (Table 3). Also, keep in mind that transientresponse performance of buck regulators operated
close to dropout is poor, and bulk output capacitance
must often be added (see the VSAG equation in the
Design Procedure).
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN)
as much as it ramps up during the on-time (∆IUP). The
ratio h = ∆IUP/∆IDOWN is an indicator of ability to slew
the inductor current higher in response to increased
load and must always be greater than 1. As h
approaches 1, the absolute minimum dropout point, the
inductor current cannot increase as much during each
switching cycle, and VSAG greatly increases unless
additional output capacitance is used.
______________________________________________________________________________________
29
MAX1813
CAPACITOR SOAR
(ENERGY IN L
TRANSFERRED TO COUT)
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between VSAG, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:




 VOUT + VDROP1 
VIN(MIN) = 
+ VDROP2 − VDROP1
 h × t OFF(MIN)  
 1

 
K

where VDROP1 and VDROP2 are the parasitic voltage
drops in the discharge and charge paths (see On-Time
One-Shot), t OFF(MIN) is from the Electrical Characteristics table, and K is taken from Table 3. The absolute
minimum input voltage is calculated with h = 1.
If the calculated V+(MIN) is greater than the required
minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated,
calculate V SAG to be sure of adequate transient
response.
Dropout Design Example:
VOUT = 1.4V
ƒSW = 600kHz
K = 1.8µs; worst-case K = 1.58µs
tOFF(MIN) = 500ns
VDROP1 = VDROP2 = 100mV


1.4V+100mV
VIN(MIN) = 

1(0.5
µ
s
×
1.5/1.58
µ
s)


+ 100mV − 100mV = 2.9V
Calculating again with h = 1 gives the absolute limit of
dropout:


1.4V+100mV
VIN(MIN) = 

 1- (0.5µs × 1.0/1.58µs) 
+ 100mV − 100mV = 2.2V
Therefore, VIN must be greater than 2.2V, even with
very large output capacitance, and a practical input
voltage with reasonable output capacitance would be
2.9V.
30
Using Skip Mode During Suspend
For most active CPU modes, the minimum load currents are too high to benefit from pulse-skipping operation, so PWM mode should be used exclusively. Skip
mode can, in fact, be a hindrance to properly executing
output voltage transitions (see Forced PWM Mode).
However, processor suspend currents can be low
enough to benefit from low-power pulse skipping.
For processors with three-state outputs, SKP/SDN and
SUS may be directly controlled. If only digital logic is
available, SKP/SDN and SUS may be controlled with
two digital outputs with the circuit shown in Figure 11.
In normal operation, SKP/SDN remains biased at 2V by
the resistive voltage-divider and the MAX1813’s internal
circuitry. When the circuit goes into suspend mode
(SUS high), the pin remains biased at 2V for approximately 200µs before it goes high. This delay causes the
MAX1813 to remain in PWM mode long enough to
correctly complete the negative output voltage transition to the suspend-state voltage. Thereafter, the
MAX1813 will operate with low-quiescent-current SKIP
mode. When the circuit returns to normal operation
(SUS low), the delay on the SKP/SDN does not affect
the transition dynamics because the MAX1813 automatically returns to PWM mode and continues to supply
current until the output is in regulation. The ON/OFF
signal overrides both normal forced-PWM operation
and suspend mode.
Using the ZMODE Multiplexer
There are many ways to use the versatile ZMODE multiplexer. The preferred method will depend on when and
how the VID DAC codes for the various states are
determined. If the output voltage codes are fixed at PC
board design time, program both codes with a simple
combination of pin-strap connections and series resistors (Figure 12). If the output voltage codes are chosen
during PC board assembly, both codes can be independently programmed with resistors (Figure 13). This
matrix of 10 resistor-footprints can be programmed to
all possible logic-mode and impedance-mode code
combinations with only 5 resistors.
Often, the CPU pins provide one set of codes that are
typically used with pullup resistors to provide the logic
mode VID code, and resistors in series with D0–D4 set
the impedance-mode code. Since some of the CPU’s
VID pins may float, the open-circuit pins can present a
problem for the ZMODE multiplexer’s impedance
mode. For impedance mode to work, any pins intended
to be low during this mode must appear to be low
impedance at least for the 4µs sampling interval.
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
MAX1813
SUS
VCC
INV1
R3
30kΩ
SUSPEND
INV2
C1
10nF
R2
80kΩ
R1
120kΩ
MAX1813
SKP/SDN
INV3
ON/OFF
tDELAY
tDELAY
SUSPEND
ON/OFF
SKIP
(2.8V TO 6V)
FORCED-PWM
(1.4V TO 2.2V)
SHUTDOWN
(0 TO 0.5V)
MAX1813
OPERATING
MODE
Figure 11. Three-State Operating Mode Control
2.7V TO 5.5V
1kΩ
3.0V TO 5.5V
100kΩ
MAX1813
D4
D4
MAX1813
100kΩ
D3
D3
ZMODE LOW
VID = 01100
1.15V
D2
D1
D2
100kΩ
D1
D0
ZMODE
1kΩ
100kΩ
1kΩ
D0
ZMODE
ZMODE = HIGH = 1.25V
ZMODE = LOW = 1.15V
NOTE: USE PULLUP FOR LOGIC MODE 1, PULLDOWN FOR LOGIC MODE 0.
USE ≥100kΩ FOR IMPEDANCE MODE 1, ≤1kΩ FOR IMPEDANCE MODE 0.
Figure 12. Using the Internal Mux with Hard-Wired Logic-Mode
and Impedance-Mode DAC Codes
ZMODE HIGH
VID = 01010
1.25V
ZMODE = HIGH = 1.25V
ZMODE = LOW = 1.15V
Figure 13. Using the Internal Mux with Both VID Codes
Resistor-Programmed
______________________________________________________________________________________
31
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
If the CPU’s VID pins float, the open-circuit pins can
present a problem for the MAX1813’s internal mux. The
processor’s VID pins can be used for the voltage-mode
setting, together with suitable pullup resistors.
However, the impedance mode VID code is set with
resistors in series with D0–D4, and for the impedance
mode to work, any pins intended to be impedance
mode logic low must appear to be low impedance, at
least for the 4µs sampling interval.
Use one of the two following methods to make the D0D4 inputs appear low impedance (Figure 14). By using
low-impedance pullup resistors with the CPU’s VID
pins, each pin provides the low impedance needed for
the mux to correctly interpret the impedance-mode setting. Unfortunately, the low resistances cause several
mA of additional quiescent current for each of the
CPU’s grounded VID pins. Since D0–D4 need to briefly
appear low impedance for sampling, the additional quiescent current may be avoided by using high-impedance pullups that are bypassed with a large enough
capacitance to make them appear low impedance for
the 4µs sampling interval. As noted in Figure 14, 4.7nF
capacitors allow the inputs to appear low impedance
even though they are pulled up with 1MΩ resistors.
In some cases, it is desirable to determine the impedance-mode code during system boot so that several
processor types can be used without hardware modifications. Figure 15 shows one way to implement this
configuration. The desired code is determined by the
system BIOS and programmed into one register of the
MAX1609 using the SMBus™ serial interface. The
MAX1609’s other register is left in its power-up state (all
outputs high impedance). When SMBSUS is low, the
outputs are high impedance and do not affect the
logic-mode VID code setting. When SMBSUS is high,
the programmed register is selected, and the MAX1609
forces a low impedance on the appropriate VID input
pins. The ZMODE signal is delayed relative to the SMBSUS pin because the VID pins that are pulled low
by the MAX1609 take significant time to rise
when they are released. One additional benefit of
using the MAX1609 for this application is that the
application uses only five of the MAX1609’s high-voltage, open-drain outputs. The other three outputs can
be used for other purposes.
Adjusting VOUT with a Resistive-Divider
The output voltage can be adjusted with a resistivedivider rather than the DAC if desired (Figure 16). The
drawback is that the on-time doesn’t automatically
receive correct compensation for changing output volt-
age levels. This can result in variable switching frequency as the resistor ratio is changed, and/or excessive switching frequency. The equation for adjusting
the output voltage is:

R4 
VOUT = VFB 1+

 R5 RINT 
where VFB is the currently selected DAC value, and
RINT is the FB input resistance. In resistor-adjusted circuits, the DAC code should be set as close as possible
to the actual output voltage to minimize the shift in
switching frequency.
Offsetting the Output Voltage
When required, accurate positive and negative output
voltage adjustments may be made using external resistors to offset the feedback voltage. Place an offset
resistor between the output and FB. The offset voltage
may then be controlled by adjusting the current across
this offset resistor. For a positive voltage offset, connect
a resistor between FB and GND to sink current as
shown in Figure 17.
VOS(POS) =
 RFB  V
 R_  OUT(PROG)
For a negative offset voltage, place a resistor between
REF and FB to source current as shown in Figure 18.
VOS(NEG) =
 RFB  (V
 R_  OUT(PROG) − VREF )
The reference can only support ±40µA of current, so a
unity-gain buffer must be used to generate the negative
offset reference voltage. Select RFB to be between 50Ω
and 500Ω to avoid output voltage regulation error from
the FB pin’s input current.
Adjusting VOUT Above 2V
The feed-forward circuit that makes the on-time dependent on the input voltage maintains a nearly constant
switching frequency as the input voltage (ILOAD) and
the DAC code are changed. This works extremely well
as long as FB is connected directly to the output. When
the output is adjusted with a resistive-divider, the
switching frequency is increased by the inverse of the
divider ratio.
This change in frequency can be compensated with the
addition of a resistive-divider to the battery-sense input
(V+). Attach a resistor-divider from the battery voltage
SMBus is a trademark of Intel Corp.
32
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
MAX1813
3.15V TO 5.5V
*OPTIONAL
4.7nF
1MΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
MAX1813
D4
100kΩ
D3
CPU
D2
100kΩ
D1
D0
ZMODE
CPU VID =
01100 → 1.15V
(ZMODE LOW)
ZMODE = HIGH = 1.25V
ZMODE = LOW = 1.15V
ZMODE HIGH
VID = 01010 → 1.25V
*TO REDUCE QUIESCENT CURRENT, 1kΩ PULLUP RESISTORS CAN BE REPLACED BY 1MΩ RESISTORS WITH 4.7nF CAPACATORS IN PARALLEL.
Figure 14. Using the Internal Mux with CPU Driving the Logic-Mode CID Code
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
3.3V
100kΩ
VID4
100kΩ
VID3
100kΩ
CPU
VID2
MAX1813
100kΩ
VID1
100kΩ
VID0
ZMODE
3.3V
3.3kΩ
MAX1609
1nF
ADD0
ADDRESS
ADD1
0
1
1
0
1
1
1
DATA
SMBUS
CLOCK
0
1
1
SMBUS
GMUXSEL
Figure 15. Using the ZMODE Multiplexer
______________________________________________________________________________________
33
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
QH
DH
L1
VOUT
LX
COUT
R4
QL
DL
MAX1813
RVPCS
R5
VPCS
CVPCS
RSENSE
PGND
GND
FB
CFB
VOUT = VFB (1 + R4/R5)
Figure 16. Adjusting VOUT with a Resistive-Divider
Q1
DH
L1
VOUT
LX
MAX1813
COUT
Q2
DL
RVPCS
RFB
MAX4634
VPCS
R1
CVPCS
RSENSE
R2
PGND
GND
R3
R4
REF
CREF
LOGIC
FB
CFB
ADD0
ADD1
INH
CONTROL
LOGIC
Figure 17. Adding a Positive Offset Voltage
34
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
MAX1813
Q1
DH
L1
VOUT
LX
MAX1813
COUT
Q2
DL
RVPCS
RFB
VPCS
MAX4634
CVPCS
RSENSE
R5
PGND
R6
GND
VCC
MAX4322
R7
REF
R8
CREF
LOGIC
FB
CFB
ADD0
ADD1
INH
CONTROL
LOGIC
Figure 18. Adding a Negative Offset Voltage
to V+ on the MAX1813, with the same attenuation factor
as the output divider. The V+ input has a nominal
600kΩ input impedance, which should be considered
when selecting resistor values.
One-Stage (Battery Input) vs. Two-Stage
(5V Input) Applications
The MAX1813 can be used with a direct battery connection (one stage) or can obtain power from a regulated 5V supply (two stage). Each approach has
advantages, and careful consideration should go into
the selection of the final design.
The one-stage approach offers smaller total inductor
size and fewer capacitors overall due to the reduced
demands on the 5V supply. The transient response of
the single stage is better due to the ability to ramp the
inductor current faster. The total efficiency of a single
stage is better than the two-stage approach.
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipation. The power supply can be placed closer to the
CPU for better regulation and lower I2R losses from PC
board traces. Although the two-stage design has slower transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvantages. They have ultra-low ESR and are noncombustible, relatively small, and nonpolarized. However,
they are also expensive and brittle, and their ultra-low
ESR characteristic can result in excessively high ESR
zero frequencies. In addition, their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load conditions, unless a small
inductor value is used (high switching frequency) or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored inductor energy. In
some cases, there may be no room for electrolytics,
creating a need for a DC-DC design that uses nothing
but ceramics.
The MAX1813 can take advantage of the small size and
low ESR of ceramic output capacitors. To ensure stable
operation, there must be sufficient resistance in series
with the inductor and output capacitor (see “Output
Capacitor Stablility Considerations”).
Output overshoot (V SOAR) determines the minimum
output capacitance requirement (see Output Capacitor
Selection). Often the switching frequency is increased
to 1000kHz or 600kHz, and the inductor value is
reduced to minimize the energy transferred from inductor to capacitor during load-step recovery. The efficiency penalty for operating at 1000kHz is about 5% and
______________________________________________________________________________________
35
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
about 2-3% at 600kHz when compared to the 300kHz
voltage-positioned circuit, primarily due to the high-side
MOSFET switching losses.
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance causes a measurable efficiency penalty.
PC Board Layout Guidelines
4) VPCS and GND connections for current limiting and
voltage positioning must be made using Kelvin
sensed connections to guarantee the current-sense
accuracy.
5) When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 19). If possible, mount all of the power components on the top side of the board, with their ground
terminals flush against one another. Follow these guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitterfree operation.
2) Connect all analog grounds to a separate solid copper plane, which connects to the MAX1813’s GND
pin. This includes the VCC, REF, and CC capacitors,
as well as the resistive-dividers connected to FB
and ILIM.
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
ALL ANALOG GROUNDS
CONNECT TO LOCAL PLANE ONLY
VIA TO VPCS
6) Ensure the FB connection to the output is short and
direct.
7) Route high-speed switching nodes away from sensitive analog areas (CC, REF, ILIM). Make all pin-strap
control input connections (SKP/SDN, ILIM, CODE,
SUS, ZMODE, etc.) to analog ground or VCC rather
than power ground (PGND) or VDD.
VIA TO V+
VIA TO GND
NEAR RSENSE
BATTERY
INPUT
GND
INPUT
CIN
MAX1813
VCC
REF
GND
GND
OUTPUT
RSENSE
CC
;
;
Q1
VDD
Q2
PGND
D1
D1
COUT
VOUT
VIA TO
SOURCE
OF Q2
L1
CONNECT LOCAL ANALOG GROUND PLANE DIRECTLY TO GND FROM
THE SIDE OPPOSITE THE VDD CAPACITOR GND TO AVOID VDD GROUND
CURRENTS FROM FLOWING IN THE ANALOG GROUND PLANE.
VIA TO FB
VIA TO LX
NOTES: “STAR” GROUND IS USED.
D1 IS DIRECTLY ACROSS Q2.
INDUCTOR DISCHARGE PATH HAS LOW DC RESISTANCE.
Figure 19. Power-Stage PC Board Layout Example
36
______________________________________________________________________________________
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
plane where sensitive analog components, the GND
pin, and VCC bypass capacitor go. The GND plane
and PGND plane must meet only at a single point
directly beneath the IC. These two planes are then
connected to the high-power output ground with a
short connection from PGND to the source of the
low-side MOSFET (the middle of the star ground).
This point must also be very close to the output
capacitor ground terminal.
5) Connect the output power planes (VCORE and system ground planes) directly to the output filter
capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as
close to the CPU as is practical.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate trace must be short and wide
(50mils to 100mils wide if the MOSFET is 1 inch from
the controller IC).
3) Group the gate-drive components (BST diode and
capacitor, VDD bypass capacitor) together near the
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figure 19. This diagram can be viewed as
having three separate ground planes: output
ground, where all the high-power components go;
the power ground plane, where the PGND pin and
VDD bypass capacitor go; and an analog ground
Chip Information
TRANSISTOR COUNT: 8757
Typical Operating Circuit
BATTERY
2V TO 28V
+5V INPUT
VCC
VDD
SKIP
V+
ILIM
BST
REF
MAX1813
DH
CC
LX
TIME
DL
TON
VPCS
OUTPUT
0.925V TO 1.6V
D0
D1
DAC
INPUTS
D3
FB
D4
PGOOD
SUS
SUSPEND
MODE
PGND
D2
S0
S1
GND
CODE
ZMODE
______________________________________________________________________________________
37
MAX1813
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN ,
COUT, and D1 anode). If possible, make all these
connections on the top layer with wide, copper-filled
areas.
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
QSOP.EPS
MAX1813
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.