MOSEL V43728S04VCTG-75

PRELIMINARY
V43728S04V(C)TG-75
3.3 VOLT 8M x 72 HIGH PERFORMANCE
PC133 UNBUFFERED ECC SDRAM
MODULE
MOSEL VITELIC
Features
Description
■ 168 Pin Unbuffered 8,388,608 x 72 bit
Oganization SDRAM ECC DIMMs
■ Utilizes High Performance 8M x 8 SDRAM in
TSOPII-54 Packages
■ Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
■ Single +3.3V (± 0.3V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are LVTTL Compatible
■ 4096 Refresh Cycles every 64 ms
■ Serial Present Detect (SPD)
■ SDRAM Performance
The V43728S04V(C)TG-75 memory module is
organized 8,388,608 x 72 bits in a 168 pin memory
module. The 8M x 72 memory module uses 9
Mosel-Vitelic 8M x 8 SDRAM. The x72 modules are
ideal for use in high performance computer systems
where increased memory density and fast access
times are required.
Key Component Timing Parameters
-7
Units
tCK
Clock Frequency (max.)
143
MHz
tAC
Clock Access Time CAS
Latency = 3
5.4
ns
V43728S04V(C)TG-75-01
■ Supported Latencies at 133 MHz Operation
CL
tRCD
tRP
tRC
3
3
3
8
V43728S04V(C)TG-75 Rev. 1.2 September 2000
CLK
1
V43728S04V(C)TG-75
MOSEL VITELIC
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO
CB1
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2
CB3
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4
CB5
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
NC
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6
CB7
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Pin Names
A0–A11
Address Inputs
I/O1–I/O64
Data Inputs/Outputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Read/Write Input
BA0, BA1
Bank Selects
CKE0, CKE1
Clock Enable
CS0–CS3
Chip Select
CLK0–CLK3
Clock Input
DQM0–DQM7
Data Mask
VCC
Power (+3.3 Volts)
VSS
Ground
SCL
Clock for Presence Detect
SDA
Serial Data OUT for Presence
Detect
SA0–A2
Serial Data IN for Presence
Detect
CB0–CB7
Check Bits (x72 Organization)
NC
No Connection
DU
Don’t Use
V43728S04V(C)TG-75 Rev. 1.2 September 2000
2
V43728S04V(C)TG-75
MOSEL VITELIC
Part Number Information
V
4
3
72
8
S
0
4
V
C
G
T
-
75
MOSEL-VITELIC
MANUFACTURED
-75
133 MHz
(PC133 3-3-3)
GOLD
SDRAM
TSOP
3.3V
WIDTH
LVTTL
DEPTH
4 BANKS
168 PIN UNBUFFERED
DIMM X 8 COMPONENT
COMPONENT
REVISION
LEVEL
BLANK = B REV
C = C REV
REFRESH
RATE 4K
V43728S04V(C)TG-75-02
Block Diagram
WE
CS0
CS
DQM WE
I/O1–I/O8
DQM0
I/O1–I/O8
D0
DQM4
I/O40–I/O33
10
CS
D1
DQM5
I/O48–I/O41
10
BC0–7
CS
DQM WE
I/O1–I/O8
CS
WE
DQM
I/O1–I/O8
CS
WE
DQM
I/O1–I/O8
CS
D4
10
DQM WE
I/O1–I/O8
DQM1
I/O9–I/O16
DQM WE
I/O1–I/O8
D5
10
DQM WE
I/O1–I/O8
CS
WE
DQM
I/O1–I/O8
CS
10
CS2
DQM2
I/O17–I/O24
D2
DQM6
I/O49–I/O56
10
CS
WE
DQM
I/O1–I/O8
DQM3
I/O25–I/O32
D6
10
D3
DQM7
I/O57–I/O64
10
D7
10
E2PROM SPD (256 WORD X 8 BITS)
SCL0
SA2
SA1
SA0
SDA
WP
47K
CKE0
CKE: SDRAM D0-D7
RAS
RAS: SDRAM D0-D7
CAS
CAS: SDRAM D0-D7
WE
WE: SDRAM D0-D7
A(11:0)
BA0, BA1
CLOCK WIRING
CLOCK INPUT
LOAD
CLK0
CLK1
CLK2
CLK3
5 SDRAM
Termination
4 SDRAMS +3.3pF Cap
Termination
V43728S04V(C)TG-75 Rev. 1.2 September 2000
VCC
VSS
A(11:0): SDRAM D0-D7
BA0, BA1: SDRAM D0-D7
D0-D7
C0-C17
D0-D7
V43728S04V(C)TG-75-03
3
V43728S04V(C)TG-75
MOSEL VITELIC
Serial Presence Detect Information
etc. is written into the E2PROM device during
module production using a serial presence detect
protocol (I2C synchronous 2-wire bus)
A serial presence detect storage device E PROM - is assembled onto the module.
Information about the module configuration, speed,
2
SPD-Table for PC133 modules:
Hex Value
Byte Number
Function Described
SPD Entry Value
8Mx72
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
12
0C
4
Number of Column Addresses (for x8 SDRAM)
9
09
5
Number of DIMM Banks
1
01
6
Module Data Width
72
48
7
Module Data Width (continued)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAM Cycle Time at CL=3
7.5 ns
75
10
SDRAM Access Time from Clock at CL=3
5.4 ns
54
11
Dimm Config (Error Det/Corr.)
ECC
02
12
Refresh Rate/Type
Self-Refresh, 15.6µs
80
13
SDRAM width, Primary
x8
08
14
Error Checking SDRAM Data Width
n/a / x8
08
15
Minimum Clock Delay from Back to Back Random
Column Address
tccd = 1 CLK
01
16
Burst Length Supported
1, 2, 4, 8 & full Page
8F
17
Number of SDRAM Banks
4
04
18
Supported CAS Latencies
CL = 3
04
19
CS Latencies
CS Latency = 0
01
20
WE Latencies
WL = 0
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
22
SDRAM Device Attributes: General
Vcc tol ± 10%
0E
23
Minimum Clock Cycle Time at CAS Latency = 2
Not Supported
00
24
Maximum Data Access Time from Clock for CL = 2
Not Supported
00
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
26
Maximum Data Access Time from Clock at CL = 1
Not Supported
00
27
Minimum Row Precharge Time
20 ns
14
28
Minimum Row Active to Row Active Delay tRRD
15 ns
0F
29
Minimum RAS to CAS Delay tRCD
20 ns
14
30
Minimum RAS Pulse Width tRAS
45 ns
2D
V43728S04V(C)TG-75 Rev. 1.2 September 2000
4
V43728S04V(C)TG-75
MOSEL VITELIC
SPD-Table for PC133 modules: (Continued)
Hex Value
Byte Number
Function Described
SPD Entry Value
8Mx72
64 MByte
10
31
Module Bank Density (Per Bank)
32
SDRAM Input Setup Time
1.5 ns
15
33
SDRAM Input Hold Time
0.8 ns
08
34
SDRAM Data Input Setup Time
1.5 ns
15
35
SDRAM Data Input Hold Time
0.8 ns
08
62-61
Superset Information (May be used in Future)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65-71
72
00
Revision 2
02
9E
Mosel Vitelic
40
Manufacturer’s JEDEC ID Code (cont.)
00
Manufacturing Location
73-90
Module Part Number (ASCII)
91-92
PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
V43728S04V(C)TG-75
95-98
Assembly Serial Number
99-125
Reserved
00
126
Intel Specification for Frequency
64
127
Reserved
00
128+
Unused Storage Location
00
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Limit Values
Symbol
Parameter
Min.
Max.
Unit
VIH
Input High Voltage
2.0
VCC+0.3
V
VIL
Input Low Voltage
–0.5
0.8
V
VOH
Output High Voltage (IOUT = –2.0 mA)
2.4
—
V
VOL
Output Low Voltage (IOUT = 2.0 mA)
—
0.4
V
II(L)
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V)
–40
40
µA
IO(L)
Output leakage current
(DQ is disabled, 0V < VOUT < VCC)
–40
40
µA
V43728S04V(C)TG-75 Rev. 1.2 September 2000
5
V43728S04V(C)TG-75
MOSEL VITELIC
Capacitance
TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz
Limit Values
Symbol
Parameter
Max. 8M x 72
Unit
CI1
Input Capacitance (A0 to A11, RAS, CAS, WE)
65
pF
CI2
Input Capacitance (CS0-CS3)
40
pF
CICL
Input Capacitance (CLK0-CLK3)
40
pF
CI3
Input Capacitance (CKE0, CKE1)
60
pF
CI4
Input Capacitance (DQM0-DQM7)
15
pF
CIO
Input/Output Capacitance (I/O1-I/064)
15
pF
CSC
Input Capacitance (SCL, SA0-2)
8
pF
CSD
Input/Output Capacitance (SA0-SA2)
10
pF
Standby and Refresh Currents1
TA = 0°C to 70°C, VCC = 3.3V ± 0.3V
Symbol Parameter
Test Conditions
ICC1
Operating Current
ICC2P
ICC2PS
ICC2N
Max. x72
Unit
Note
Burst length = 4, CL = 3
tRC> = tRC(min),
tCK> = tCK(min), IO = 0 mA
900
mA
1,2
Precharged Standby Current in Power
Down Mode
CKE< = VIL(max), tCK> = tCK(min)
27
mA
CKE< = VIL(max), tCK = Infinite
18
mA
Precharged Standby Current in
Non-Power Down Mode
CKE> = VIH(min), tCK> = tCK(min),
Input changed once in 3 cycles
180
mA
CKE> = VIH(min), tCK = Infinite,
No Input change
90
mA
Active Standby Current in Power
Down Mode
CKE< = VIL(max), tCK> = tCK(min)
27
mA
CKE< = VIL(max), tCK = Infinite
18
mA
Active Standby Current in Non-Power
Down Mode
CKE> = VIH(min), tCK> = tCK(min),
Input changed one time
225
mA
CKE> = VIH(min), tCK = Infinite,
No Input change
135
mA
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
CS =
High
CS =
High
ICC4
Burst Operating Current
Burst length = Full Page,
tRC = Infinite, CL = 3,
tCK> = tCK(min), IO = 0 mA
900
mA
1, 2
ICC5
Auto Refresh Current
tRC>= tRC(min)
1100
mA
1,2
ICC6
Self Refresh Current
CKE = <0,2 V
9
mA
1,2
V43728S04V(C)TG-75 Rev. 1.2 September 2000
6
V43728S04V(C)TG-75
MOSEL VITELIC
AC Characteristics
TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns
Limit Values
-75
#
Symbol
Parameter
Min.
Max.
Unit
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
10
–
–
s
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
100
MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
–
_
5.4
6
ns
ns
Note
Clock and Clock Enable
1
2
3
tCK
tCK
tAC
2, 4
4
tCH
Clock High Pulse Width
2.5
–
ns
5
tCL
Clock Low Pulse Width
2.5
–
ns
6
tT
Transition Tim
0.3
1.2
ns
Setup and Hold Times
7
tIS
Input Setup Time
1.5
–
ns
5
8
tIH
Input Hold Time
0.8
–
ns
5
9
tCKS
Input Setup Time
1.5
–
ns
5
10
tCKH
CKE Hold Time
0.8
–
ns
5
11
tRSC
Mode Register Set-up Time
15
–
ns
12
tSB
Power Down Mode Entry Time
0
7.5
ns
Row to Column Delay Time
20
–
ns
6
Common Parameters
13
tRCD
14
tRP
Row Precharge Time
20
–
ns
6
15
tRAS
Row Active Time
45
100K
ns
6
16
tRC
Row Cycle Time
60
–
ns
6
17
tRRD
Activate(a) to Activate(b) Command Period
15
–
ns
6
18
tCCD
CAS(a) to CAS(b) Command Period
1
–
CLK
64
ms
Refresh Cycle
19
tREF
Refresh Period (4096 cycles)
—
20
tSREX
Self Refresh Exit Time
10
V43728S04V(C)TG-75 Rev. 1.2 September 2000
7
ns
V43728S04V(C)TG-75
MOSEL VITELIC
AC Characteristics
TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns (Continued)
Limit Values
-75
#
Symbol
Parameter
Min.
Max.
Unit
Note
2.7
–
ns
2
Read Cycle
21
tOH
Data Out Hold Time
22
tLZ
Data Out to Low Impedance Time
1
–
ns
23
tHZ
Data Out to High Impedance Time
–
5.4
ns
24
tDQZ
DQM Data Out Disable Latency
–
2
CLK
25
tWR
Write Recovery Time
1
–
CLK
26
tDQW
DQM Write Mask Latency
0
–
CLK
Write Cycle
V43728S04V(C)TG-75 Rev. 1.2 September 2000
8
7
V43728S04V(C)TG-75
MOSEL VITELIC
Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No
Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have VIL = 0.4V and VIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
CLOCK
50 Ohm
0.4V
tCL
tSETUP
Z=50 Ohm
tT
I/O
tHOLD
50 pF
1.4V
INPUT
tAC
tAC
tLZ
I/O
tOH
50 pF
1.4V
OUTPUT
Measurement conditions for
tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11. tDAL is equivalent to tDPL + tRP.
V43728S04V(C)TG-75 Rev. 1.2 September 2000
9
V43728S04V(C)TG-75
MOSEL VITELIC
Package Diagram
SDRAM DIMM Module Package
All measurements in mm.
133.35
127.35
10
11
40
41
84
3.0
1
17.78
34.925
(2.54 max)
42.18
1.27 ± 0.100
66.68
A
94
95
124
C
125
168
4.0 ± 0.100
85
B
6.35
3.125
3.125
6.35
2.0
8.25
4.45
Detail A
1.27
1.0 ± 0.05
2.4 min.
D
0.2 ± 0.15
2.0
Detail B
2.26
Detail C
V43728S04V(C)TG-75-04
RADIUS
1.27 + 0.10
Tolerances: ± (0.13) unless otherwise specified.
V43728S04V(C)TG-75 Rev. 1.2 September 2000
10
V43728S04V(C)TG-75
MOSEL VITELIC
Label Information
MOSEL VITELIC
Part Number
Criteria of PC100 or PC133
(refer to MVI datasheet)
V43728S04VCTG-75
PC133U-333-542-A
Taiwan XXXX-XXXXXXX
DIMM manufacture date code
Trace Code
PC133 U - 333 - 54 2 - A
UNBUFFERED DIMM
Gerber file Intel® PC100 x 8 Based
CL = 3 (CLK)
tRCD = 3 (CLK)
tRP = 3 (CLK)
V43728S04V(C)TG-75 Rev. 1.2 September 2000
JEDEC SPD Revision 2.0
tAC = 5.4 ns
11
V43728S04V(C)TG-75-05
MOSEL VITELIC
WORLDWIDE OFFICES
V43728S04V(C)TG-75
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
NO 19 LI HSIN ROAD
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
JAPAN
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 01698-748515
FAX: 01698-748516
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2666-3307
FAX: 852-2770-8011
WBG MARIVE WEST 25F
6, NAKASE 2-CHOME
MIHAMA-KU, CHIBA-SHI
CHIBA 261-7125
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FAX: 81-43-299-6555
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
71083 HERRENBERG
BENZSTR. 32
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
SOUTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
302 N. EL CAMINO REAL #200
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PHONE: 949-361-7873
FAX: 949-361-7807
© Copyright 2000, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
9/00
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461