CXD1178Q 8-bit 40MSPS RGB 3-channel D/A Converter Description The CXD1178Q is an 8-bit high-speed D/A converter for video band use. It has an input/output equivalent to 3 channels of R, G and B. It is suitable for use of digital TV, graphic display, and others. Features • Resolution 8-bit • Maximum conversion speed 40MSPS • RGB 3-channel input/output • Differential linearity error ±0.3LSB • Low power consumption 240 mW (200 Ω load at 2 Vp-p output) • Single 5 V power supply • Low glitch noise • Stand-by function Structure Silicon gate CMOS IC 48 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage AVDD, DVDD 7 V • Input voltage (All pins) VIN VDD+0.5 to VSS–0.5 V • Output current (Every each channel) IOUT 0 to 15 mA • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS 4.75 to 5.25 V • Reference input voltage VREF 2.0 V • Clock pulse width TPW1, TPW0 11.2 ns (min.) to 1.1 µs (max.) • Operating temperature Topr –40 to +85 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E90603F01 CXD1178Q Block Diagram (LSB) R0 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 (MSB) R7 8 (LSB) G0 9 2LSB’S CURRENT CELLS DECODER 47 DVDD 48 DVDD 36 RO 6MSB’S CURRENT CELLS LATCHES 37 RO 27 RCK DECODER CLOCK GENERATOR 43 AVDD 44 AVDD 2LSB’S CURRENT CELLS G1 10 45 AVDD 46 AVDD G2 11 38 GO G3 12 DECODER 6MSB’S CURRENT CELLS LATCHES G4 13 G5 14 G6 15 39 GO 28 GCK DECODER CLOCK GENERATOR (MSB) G7 16 2LSB’S CURRENT CELLS (LSB) B0 17 B1 18 33 AVSS 30 DVSS 31 DVSS B2 19 40 BO B3 20 DECODER 6MSB’S CURRENT CELLS LATCHES B4 21 B5 22 B6 23 41 BO 29 BCK DECODER CLOCK GENERATOR (MSB) B7 24 42 VG 34 VREF BLK 25 CE 26 CURRENT CELLS (FOR FULL SCALE) BIAS VOLTAGE GENERATOR —2— 35 IREF 32 VB CXD1178Q RO IREF VREF AVSS VB DVSS DVSS BCK GCK RCK CE BLK Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 19 B2 AVDD 43 18 B1 AVDD 44 17 B0 AVDD 45 16 G7 AVDD 46 15 G6 DVDD 47 14 G5 DVDD 48 13 G4 1 2 3 4 5 6 7 8 9 10 11 12 G3 VG G2 20 B3 42 G1 41 G0 BO R7 21 B4 R6 40 R5 BO R4 22 B5 R3 23 B6 GO 39 R2 GO 38 R1 24 B7 R0 RO 37 Pin Description and I/O Pins Equivalent Circuit Pin No. Symbol 1 to 8 R0 to R7 I/O Equivalent circuit DVDD Digital input R0 (LSB) to R7 (MSB) G0 (LSB) to G7 (MSB) B0 (LSB) to B7 (MSB) 1 9 to 16 G0 to G7 I to 24 17 to 24 DVSS B0 to B7 DVDD 25 BLK Description I Blanking input. This is synchronized with the clock input signal for each channel. No signal at “H” (Output 0 V). Output condition at “L”. 25 DVSS DVDD DVDD 32 VB O Connect a capacitor of about 0.1 µF. 32 DVSS —3— CXD1178Q Pin No. Symbol 27 RCK I/O Equivalent circuit Description DVDD 27 28 GCK I Clock input. 28 29 29 BCK 30, 31 33 DVSS AVSS DVSS — — Digital GND Analog GND DVDD 26 CE I Chip enable input. This is not synchronized with the clock input signal. No signal (Output 0 V) at “H” and minimizes power consumption. 26 DVSS 35 IREF Reference current output. Connect a resistance 16 times “16ROUT” that of output resistance value “ROUT”. O AVDD AVDD 35 AVDD AVSS 34 VREF I 34 AVDD AVSS Reference voltage input. Set full scale output value. 42 AVSS 42 VG O Connect a capacitor of about 0.1 µF. 43 to 46 AVDD — Analog VDD —4— CXD1178Q Pin No. Symbol 37 RO I/O Equivalent circuit Current output pins. Voltage output can be obtained by connecting a resistance. AVDD 39 Description GO 37 39 41 41 BO AVSS AVDD O 36 RO 36 38 40 38 Inverted current output. Normally dropped to analog GND. GO AVSS 40 BO 47, 48 DVDD — Digital VDD —5— CXD1178Q (fCLK=40 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, VREF=2.0 V, Ta=25 °C) Resolution Item Symbol n Conversion speed fCLK Integral non-linearity error Differential non-linearity error Output full-scale voltage Output full-scale ratio ∗1 Output full-scale current Output offset voltage Glitch energy Crosstalk EL ED VFS FSR IFS VOS GE CT IDD ISTB RIN CI VIH VIL IIH IIL ts th tPD tE tD Supply current Analog input resistance Input capacitance Digital input voltage Digital input current Setup time Hold time Propagation delay time CE enable time ∗2 CE disable time ∗2 ∗1 ∗2 Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=–40 to 85 °C Endpoint When “00000000” data input ROUT=75 Ω When 1 MHz sine wave input 14.3MHz color bar CE= “L” data input CE= “H” VREF Min. Typ. 8 Max. Unit bit 0.5 40 MSPS –2.5 –0.3 1.8 0 2.5 0.3 2.2 3.0 15 1 LSB LSB V % mA mV pV•s dB 2.0 1.5 10 30 57 42 1 48 2 1 9 AVDD=DVDD=4.75 to 5.25 V Ta=–20 to 75 °C AVDD=DVDD=4.75 to 5.25 V Ta=–20 to 75 °C ROUT=75 Ω ROUT=75 Ω 2.4 0.8 –5 CE= H→L CE= L→H Full-scale voltage of channel –1 Average of the full-scale voltage of the channels When the external capacitor for the VG pin is 0.1 µF. Full-scale output ratio = —6— MΩ pF V 5 µA 4 4 ns ns ns ms ms 5 10 10 1.8 1.8 mA × 100 (%) CXD1178Q Electrical Characteristics Measurement Circuit Analog Input Resistance Measurement Circuit Digital Input Current } +5.25V AVDD, DVDD A CXD1178Q V AVSS, DVSS Maximum Conversion Velocity Measurement Circuit R0 to R7 1 to 8 8bit COUNTER with LATCH G0 to G7 9 to 16 B0 to B7 17 to 24 RO 37 200 200 AVSS BO 41 200 25 BLK 0.1µ AVSS GO 39 AVSS 26 CE 32 VB AVDD VG 42 DVSS CLK 40MHz SQUARE WAVE 27 RCK VREF 34 28 GCK IREF 35 29 BCK 0.1µ 1k 3.3k AVSS —7— OSCILLOSCOPE CXD1178Q Setup Time Hold Time Glitch Energy } Measurement Circuit R0 to R7 1 to 8 8bit COUNTER with LATCH RO 37 G0 to G7 9 to 16 B0 to B7 17 to 24 75 AVSS GO 39 BO 41 75 AVSS 25 BLK 0.1µ DELAY CONTROLLER 26 CE 32 VB AVDD VG 42 DVSS CLK 1MHz SQUARE WAVE OSCILLOSCOPE 75 AVSS DELAY CONTROLLER 27 RCK VREF 34 28 GCK IREF 35 0.1µ 1k 1.2k 29 BCK AVSS Crosstalk Measurement Circuit R0 to R7 1 to 8 DIGITAL WAVEFORM GENERATOR RO 37 ALL “1” 200 G0 to G7 9 to 16 200 B0 to B7 17 to 24 AVSS BO 41 200 25 BLK 0.1µ AVSS GO 39 AVSS 26 CE 32 VB AVDD VG 42 DVSS CLK 40MHz SQUARE WAVE 27 RCK VREF 34 28 GCK IREF 35 0.1µ 1k 3.3k 29 BCK AVSS —8— SPECTRUM ANALIZER CXD1178Q DC Characteristics Measurement Circuit R0 to R7 1 to 8 RO 37 200 G0 to G7 9 to 16 CONTROLLER AVSS GO 39 B0 to B7 17 to 24 AVSS BO 41 200 25 BLK 0.1µ DVM 200 AVSS 26 CE 32 VB AVDD VG 42 DVSS CLK 40MHz SQUARE WAVE 27 RCK VREF 34 28 GCK IREF 35 0.1µ 1k 3.3k 29 BCK AVSS Propagation Delay Time Measurement Circuit R0 to R7 1 to 8 FREQUENCY DEMULTIPLIER G0 to G7 9 to 16 B0 to B7 17 to 24 RO 37 200 200 AVSS BO 41 200 25 BLK 0.1µ AVSS GO 39 AVSS 26 CE 32 VB AVDD VG 42 DVSS CLK 10MHz SQUARE WAVE 27 RCK VREF 34 28 GCK IREF 35 29 BCK 0.1µ 1k 3.3k AVSS —9— OSCILLOSCOPE CXD1178Q Description of Operation Timing Chart tPW1 tPW0 2V CLK AA AA AA AAA AA AA AA AAA AA AAAAAAA ts th ts th ts th DATA tPD D/A OUT 100% 50% tPD tPD 0% I/O Chart (when full scale output voltage at 2.00 V) Input code MSB LSB 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 Output voltage 2.0 V 1.0 V 0V B (Blue) OUT Application Circuit 200 AVSS G (Green) OUT 200 AVDD DVDD AVSS R (Red) OUT 0.1µ 200 48 47 46 45 44 43 42 41 40 39 38 37 AVSS (LSB) • • • R (Red) IN • • (MSB) (LSB) • • 1 36 2 35 3 34 4 5 33 6 31 7 30 8 29 9 28 10 27 11 26 12 25 • • • • • • 3.3k AVSS AVSS 0.1µF DVSS CLOCK IN DVSS (MSB) (LSB) • (MSB) • AVDD 1k 32 13 14 15 16 17 18 19 20 21 22 23 24 G (Green) IN 2V B (Blue) IN Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —10— CXD1178Q Notes on Operation • How to select the output resistance The CXD1178Q is a D/A converter of the current output type. To obtain the output voltage connect the resistance to current output pins (RO, GO and BO). For specifications we have; Output full scale voltage VFS=1.8 to 2.2 [V] Output full scale current IFS=less than 15 [mA] Calculate the output resistance value from the relation of VFS=IFS × ROUT. Also, 16 times resistance of the output resistance is connected to reference current pin IREF. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS=VREF × 16ROUT/RIR. VREF is the voltage set at the VREF pin and ROUT is the resistance connected to current output pins (RO, GO and BO) while RIR is connected to IREF. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. • Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. • Power supply and ground To reduce noise effects separate analog and digital systems in the device periphery. For power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 µF, as close as possible to the pin. • Latch up Analog and digital power supply have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. • On inverted current output pins The RO, GO and BO are the inverted current output terminal as described in the Pin Description. The sums shown below become the constant value for any input data. a) The sum of the currents output from the RO and RO pins. b) The sum of the currents output from the GO and GO pins. c) The sum of the currents output from the BO and BO pins. However, the output current from the RO, GO and BO pins is not guaranteed of its performances such as linearity errors, etc. • On output full-scale voltage When the output full-scale voltage is used without adjustment in the application that uses the RGB signal, the color balance may be broke. —11— CXD1178Q Latch Up Prevention The CXD1178Q is a CMOS IC which required latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 43 to 46) and DVDD (Pins 47 and 48), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD 43 44 45 46 47 AVDD +5V 48 DVDD +5V CXD1178Q C C AVSS DIGITAL IC DVSS 33 30 31 AVSS DVSS b. When analog and digital supplies are from a common source (i) DVDD 43 44 45 46 47 AVDD 48 DVDD +5V CXD1178Q C AVSS C DIGITAL IC C DIGITAL IC DVSS 33 30 31 47 48 AVSS DVSS (ii) DVDD 43 44 45 46 AVDD DVDD +5V C CXD1178Q AVSS DVSS 33 30 31 AVSS DVSS —12— CXD1178Q 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD 43 44 45 46 47 AVDD +5V 48 DVDD +5V CXD1178Q C C AVSS DIGITAL IC DVSS 33 30 31 AVSS DVSS b. When analog and digital supplies are from common source (i) DVDD AVDD 43 44 45 46 47 AVDD 48 DVDD +5V CXD1178Q C AVSS C DIGITAL IC C DIGITAL IC DVSS 33 30 31 47 48 AVSS DVSS (ii) DVDD AVDD 43 44 45 46 AVDD DVDD +5V CXD1178Q AVSS DVSS 33 30 31 AVSS DVSS —13— CXD1178Q Example of Representative Characteristics AVDD=DVDD=5V VREF=2.0V RIR≈16ROUT Ta=25°C Glitch energy GE [pV•s] 2.0 1.0 AVDD=DVDD=5V ROUT=200Ω RIR=3.3kΩ Ta=25°C 100 0 100 200 Output resistance ROUT [Ω] Glitch energy vs. Output resistance 1.0 2.0 Reference voltage VREF [V] Output full scale voltage vs. Reference voltage 60 2.0 Crosstalk CT [dB] Output full scale VFS [V] Output full scale voltage VFS [V] 200 1.9 AVDD=DVDD=5V VREF=2.0V ROUT=200 Ω RIR=3.3k Ω 50 AVDD=DVDD=5V VREF=2.0V ROUT=200Ω RIR=3.3kΩ Ta=25°C 40 0 –40 –25 100k 0 25 50 75 85 Ambient temperature Ta [°C] Output full scale voltage vs. Ambient temperature 1M Output frequency FOUT [Hz] Crosstalk vs. Output frequency —14— 10M CXD1178Q Package Outline Unit : mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 0.15 36 25 24 13.5 37 48 + 0.2 0.1 – 0.1 13 12 0.8 + 0.15 0.3 – 0.1 0.24 M 0.9 ± 0.2 1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE SONY CODE QFP-48P-L04 EIAJ CODE QFP048-P-1212 JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER / PALLADIUM PLATING LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.7g —15—