19-1432; Rev 0; 3/99 Single-Supply, Low-Power, Serial 8-Bit ADCs The MAX1106/MAX1107 low-power, 8-bit, single-channel, analog-to-digital converters (ADCs) feature an internal track/hold (T/H), voltage reference, clock, and serial interface. The MAX1106 is specified from +2.7V to +3.6V and consumes only 96µA. The MAX1107 is specified from +4.5V to +5.5V and consumes only 107µA. The analog inputs are pin-configurable, allowing unipolar and singleended or differential operation. The full-scale analog input range is determined by the internal reference of +2.048V (MAX1106) or +4.096V (MAX1107), or by an externally applied reference ranging from 1V to VDD. The MAX1106/MAX1107 also feature a pin-selectable power-down mode that reduces power consumption to 0.5µA when the device is not in use. The 3-wire serial interface directly connects to SPI™, QSPI™, and MICROWIRE™ devices without external logic. Conversions up to 25ksps are performed using the internal clock. The MAX1106/MAX1107 are available in a 10-pin µMAX package with a footprint that is just 20% of an 8-pin plastic DIP. Applications Portable Data Logging Hand-Held Measurement Devices Features ♦ Single Supply: +2.7V to +3.6V (MAX1106) +4.5V to +5.5V (MAX1107) ♦ Low Power: 96µA at +3V and 25ksps 0.5µA in Power-Down Mode ♦ Pin-Programmable Configuration ♦ 0 to VDD Input Voltage Range ♦ Internal Track/Hold ♦ Internal Reference: +2.048V (MAX1106) +4.096V (MAX1107) ♦ 1V to VDD Reference Input Range ♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface ♦ Small 10-Pin µMAX Package Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX1106CUB 0°C to +70°C 10 µMAX MAX1106EUB -40°C to +85°C 10 µMAX MAX1107CUB 0°C to +70°C 10 µMAX MAX1107EUB -40°C to +85°C 10 µMAX Medical Instruments System Diagnostics Functional Diagram Solar-Powered Remote Systems 4–20mA-Powered Remote Systems VDD CONVST SCLK Receive-Signal-Strength Indicators Pin Configuration SHDN MAX1106 MAX1107 OUTPUT SHIFT REGISTER DOUT TOP VIEW VDD 1 10 SCLK IN+ 2 9 DOUT IN- 3 8 SHDN GND 4 7 CONVST REFOUT 5 6 REFIN MAX1106 MAX1107 INTERNAL OSCILLATOR CONTROL LOGIC IN+ INREFOUT µMAX SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ANALOG INPUT MUX INTERNAL REFERENCE T/H SAR CHARGE REDISTRIBUTION DAC REFIN GND ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX1106/MAX1107 General Description MAX1106/MAX1107 Single-Supply, Low-Power, Serial 8-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V IN+, IN-, REFIN, REFOUT, DOUT to GND..........................................-0.3V to (VDD + 0.3V) SHDN, SCLK, CONVST to GND ...............................-0.3V to +6V Continuous Power Dissipation (TA = +70°C) 10-pin µMAX (derate 5.6mW/°C above +70°C) ............444mW Operating Temperature Ranges MAX110_CUB ......................................................0°C to +70°C MAX110_EUB ...................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX1106 (VDD = +2.7V to +3.6V; IN- to GND; fSCLK = 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +2.048V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Relative Accuracy (Note 1) INL Differential Nonlinearity DNL Offset Error Bits VDD = 2.7V to 3.6V ±0.15 VDD = 5.5V (Note 2) ±0.2 No missing codes over temperature ±1 VDD = 2.7V to 3.6V ±0.2 VDD = 5.5V (Note 2) ±0.5 Gain Error (Note 3) ±1 ±1 Gain Temperature Coefficient Total Unadjusted Error ±0.5 ±0.8 TUE TA = +25°C LSB LSB LSB ppm/°C ±1 TA = TMIN to TMAX LSB ±0.5 LSB DYNAMIC PERFORMANCE (10kHz sine-wave input, 2.048Vp-p, 25ksps conversion rate) Signal-to-Noise Plus Distortion Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Small-Signal Bandwidth SINAD 49 dB THD -70 dB SFDR BW-3dB -3dB rolloff Full-Power Bandwidth 68 dB 1.5 MHz 0.8 MHz ANALOG INPUTS Input Voltage Range (Note 4) VIN_ On/off-leakage current, VIN+ or VIN- = 0 or VDD Input Leakage Current Input Capacitance 2 VIN+ to VIN- CIN 0 ±0.01 18 _______________________________________________________________________________________ VREFIN V ±1 µA pF Single-Supply, Low-Power, Serial 8-Bit ADCs (VDD = +2.7V to +3.6V; IN- to GND; fSCLK = 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +2.048V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 35 µs TRACK/HOLD Conversion Time tCONV Track/Hold Acquisition Time tACQ Figure 7 1 µs Aperture Delay 10 Aperture Jitter <50 ps Internal Clock Frequency 400 kHz External Clock Frequency Range ns For data transfer only 2 MHz INTERNAL REFERENCE Output Voltage VREFOUT REF Short-Circuit Current IREFSC 1.968 (Note 5) REF Tempco Load Regulation 0 to 0.5mA (Note 6) Capacitive Bypass at REFOUT 2.048 2.128 V 150 µA ±50 ppm/°C 4 mV 1 µF EXTERNAL REFERENCE Input Voltage Range VREFIN Input Current 1.0 +2.048V at REFIN, full scale VDD + 0.05 V 1 20 µA 3 5.5 V VDD = 3.6V, CL = 10pF 96 250 VDD = 5.5V, CL = 10pF 115 POWER REQUIREMENTS Supply Voltage VDD Supply Current (Notes 2, 7) IDD Power-Supply Rejection (Note 8) PSR 2.7 Power down, VDD = 3.6V µA 0.5 2.5 ±0.4 ±4 mV VDD ≤ 3.6V 2 VDD > 3.6V 3 V V Full-scale input, VDD = 2.7V to 3.6V DIGITAL INPUTS (SHDN, SCLK, and CONVST) Threshold Voltage High Threshold Voltage Low Input Hysteresis Input Current High VIH VIL VHYST 0.8 V 0.2 IIH Input Current Low IIL Input Capacitance CIN 15 V ±1 µA ±1 µA pF _______________________________________________________________________________________ 3 MAX1106/MAX1107 ELECTRICAL CHARACTERISTICS—MAX1106 (continued) MAX1106/MAX1107 Single-Supply, Low-Power, Serial 8-Bit ADCs ELECTRICAL CHARACTERISTICS—MAX1106 (continued) (VDD = +2.7V to +3.6V; IN- to GND; fSCLK = 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +2.048V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUT (DOUT) Output High Voltage VOH Output Low Voltage VOL Three-State Leakage Current Three-State Output Capacitance ISOURCE = 0.5mA VDD - 0.5 V ISINK = 5mA ISINK = 16mA 0.4 V V ±10 µA 0.8 IL Figure 6, DOUT High-Z ±0.01 COUT Figure 6, DOUT High-Z 15 pF TIMING CHARACTERISTICS (Figures 6 and 7) Acquisition Time tACQ 1 µs CONVST Pulse Width High tCSPW 1 µs CONVST Fall to Output Data Valid tCONV CONVST Rise to Output Enable SCLK Fall to Output Data Valid SCLK Pulse Width High SCLK Pulse Width Low SCLK Low to Output Disable SCLK Low to CONVST Rise SHDN Fall to Output Disable Wake-Up Time 4 tDV tDO tCH tCL tTR tSCC Figure 1, CLOAD = 100pF Figure 1, CLOAD = 100pF tSHDN Figure 2, CLOAD = 100pF External reference Internal reference (Note 9) tWAKE 20 200 200 Figure 2, CLOAD = 100pF 35 µs 240 200 ns ns ns ns ns ns ns µs ms 240 100 240 20 12 _______________________________________________________________________________________ Single-Supply, Low-Power, Serial 8-Bit ADCs (VDD = +4.5V to +5.5V; IN- = GND; fSCLK = 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +4.096V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Relative Accuracy (Note 1) INL Differential Nonlinearity DNL Bits ±0.15 No missing codes over temperature Offset Error ±0.2 Gain Error (Note 3) ±0.5 LSB ±1 LSB ±1 LSB ±1 Gain Temperature Coefficient Total Unadjusted Error ±0.8 TUE TA = +25°C ±1 TA = TMIN to TMAX LSB ppm/°C ±0.5 LSB DYNAMIC PERFORMANCE (10kHz sine-wave input, 4.096Vp-p, 25ksps conversion rate) Signal-to-Noise Plus Distortion SINAD 49 dB Total Harmonic Distortion (up to the 5th harmonic) THD -70 dB Spurious-Free Dynamic Range SFDR 68 dB 1.5 MHz 0.8 MHz Small-Signal Bandwidth BW-3dB -3dB rolloff Full-Power Bandwidth ANALOG INPUTS Input Voltage Range (Note 4) VIN_ 0 On/off-leakage current, VIN+ or VIN- = 0 or VDD Input Leakage Current Input Capacitance VIN+ to VIN- ±0.01 CIN VREFIN V ±1 µA 18 pF TRACK/HOLD Conversion Time tCONV Track/Hold Acquisition Time tACQ Figure 7 35 1 µs µs Aperture Delay 10 ns Aperture Jitter <50 ps Internal Clock Frequency 400 kHz External Clock Frequency Range For data transfer only 2 MHz 4.256 V INTERNAL REFERENCE Output Voltage VREFOUT REF Short-Circuit Current 3.936 IREFSC REF Tempco Load Regulation 0 to 0.5mA (Note 6) Capacitive Bypass at REFOUT 1 4.096 5 mA ±50 ppm/°C 4 mV µF _______________________________________________________________________________________ 5 MAX1106/MAX1107 ELECTRICAL CHARACTERISTICS—MAX1107 MAX1106/MAX1107 Single-Supply, Low-Power, Serial 8-Bit ADCs ELECTRICAL CHARACTERISTICS—MAX1107 (continued) (VDD = +4.5V to +5.5V; IN- = GND; fSCLK = 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +4.096V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EXTERNAL REFERENCE Input Voltage Range VREFIN Input Current 1.0 4.096V at REFIN, full scale VDD + 0.05 V 1 20 µA V POWER REQUIREMENTS Supply Voltage Supply Current (Notes 2, 7) Power-Supply Rejection (Note 8) VDD IDD PSR 5 5.5 VDD = 5.5V, CL = 10pF, full-scale input 4.5 115 250 Power down, VDD = 4.5V to 5.5V 0.5 2.5 ±0.4 ±4 mV 3 V External reference = 4.096V, full-scale input, VDD = 4.5V to 5.5V µA DIGITAL INPUTS (SHDN, SCLK, and CONVST) Threshold Voltage High VIH Threshold Voltage Low VIL Input Hysteresis Input Current High 0.8 VHYST V 0.2 IIH Input Current Low IIL Input Capacitance CIN V ±1 µA ±1 µA 15 pF DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance VOH VOL ISOURCE = 0.5mA VDD - 0.5 V ISINK = 5mA 0.4 ISINK = 16mA 0.8 IL Figure 6, DOUT High-Z ±0.01 COUT Figure 6, DOUT High-Z 15 ±10 V µA pF TIMING CHARACTERISTICS (Figures 6 and 7) Acquisition Time tACQ 1 µs CONVST Pulse Width High tCSPW 1 µs CONVST Fall to Output Data Valid tCONV CONVST Rise to Output Enable tDV Figure 1, CLOAD = 100pF SCLK Fall to Output Data Valid tDO Figure 1, CLOAD = 100pF SCLK Pulse Width High tCH 6 20 200 _______________________________________________________________________________________ 35 µs 240 ns 200 ns ns Single-Supply, Low-Power, Serial 8-Bit ADCs (VDD = +4.5V to +5.5V; IN- = GND; fSCLK = 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +4.096V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL SCLK Pulse Width Low CONDITIONS MIN tCL SCLK Low to Output Disable tTR SCLK Low to CONVST Rise tSCC SHDN Fall to Output Disable tSHDN Wake-Up Time TYP MAX 200 ns Figure 2, CLOAD = 100pF tWAKE UNITS 240 100 ns ns Figure 2, CLOAD = 100pF 240 ns External reference 20 µs Internal reference (Note 9) 12 ms Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 2: See Typical Operating Characteristics. Note 3: VREFOUT = +2.048V (MAX1106), VREFOUT = +4.096V (MAX1107), offset nulled. Note 4: Common-mode range (IN+, IN-) GND to VDD. Note 5: REFOUT supplies typically 2.5mA under normal operating conditions. Note 6: External load should not change during the conversion for specified accuracy. Note 7: Power consumption with CMOS levels. Note 8: Measured as VFS(2.7V) - VFS(3.6V) for MAX1106, and measured as VFS(4.5V) - VFS(5.5V) for MAX1107. Note 9: 1µF at REFOUT, internal reference settling to 0.5LSB. Typical Operating Characteristics (VDD = +3.0V (MAX1106), VDD = +5.0V (MAX1107); fSCLK = 2MHz; 25ksps conversion rate; external reference; 1µF at REFOUT; TA = +25°C; unless otherwise noted.) SUPPLY CURRENT (µA) 150 CLOAD = 10pF DOUT = 10101010 125 100 CLOAD = 47pF DOUT = 10101010 75 150 MAX1107, VDD = 5.0V 125 100 MAX1106, VDD = 3.0V 75 CLOAD = 10pF DOUT = 11111111 3.5 4.0 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0 50 3.0 0.45 0.05 50 2.5 0.50 MAX1106/07-03 MAX1106/07-02 DOUT = 10101010 CLOAD = 10pF INTERNAL REFERENCE 175 SUPPLY CURRENT (µA) MAX1106 (VDD = 2.7V TO 5.5V) MAX1107 (VDD = 4.5V TO 5.5V) INTERNAL REFERENCE 175 200 MAX1106/07-01 200 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN SUPPLY CURRENT (µA) SUPPLY CURRENT vs. SUPPLY VOLTAGE 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 MAX1106/MAX1107 ELECTRICAL CHARACTERISTICS—MAX1107 (continued) Typical Operating Characteristics (continued) (VDD = +3.0V (MAX1106), VDD = +5.0V (MAX1107); fSCLK = 2MHz; 25ksps conversion rate; external reference; 1µF at REFOUT; TA = +25°C; unless otherwise noted.) OFFSET ERROR vs. TEMPERATURE 0.4 0.2 0.1 0 -0.1 -0.2 0.2 0.1 0 -0.1 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 4.0 4.5 5.0 5.5 -0.15 -0.20 -40 -20 0 SUPPLY VOLTAGE (V) 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (°C) 0.6 GAIN ERROR (LSB) 0.2 0.8 0.1 0 -0.1 0.4 0.8 0.6 GAIN ERROR (LSB) 0.3 GAIN ERROR vs. REFERENCE VOLTAGE 1.0 MAX1106/07-08 1.0 MAX1106/07-07 0.4 REFERENCE VOLTAGE (V) GAIN ERROR vs. TEMPERATURE GAIN ERROR vs. SUPPLY VOLTAGE 0.5 0.2 0 -0.2 0.4 0.2 0 -0.2 -0.2 -0.4 -0.4 -0.3 -0.6 -0.6 -0.4 -0.8 -0.8 -0.5 -1.0 3.0 3.5 4.0 4.5 5.0 -1.0 -40 5.5 -20 0 20 40 60 80 SUPPLY VOLTAGE (V) TEMPERATURE (°C) INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE 0.2 0.4 0.3 DNL (LSB) 0.1 0 -0.1 -0.2 DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.3 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 0.5 MAX1106/07-10 0.3 100 MAX1106/07-11 2.5 DNL (LSB) GAIN ERROR (LSB) -0.05 MAX1106/07-09 3.5 0 MAX1106/07-12 3.0 0.10 0.05 -0.10 -0.5 2.5 8 0.15 OFFSET ERROR (LSB) 0.3 OFFSET ERROR (LSB) 0.3 OFFSET ERROR vs. REFERENCE VOLTAGE 0.20 MAX1106/07-05 MAX1106/07-04 0.4 OFFSET ERROR (LSB) 0.5 MAX1106/07-06 OFFSET ERROR vs. SUPPLY VOLTAGE 0.5 INL (LSB) MAX1106/MAX1107 Single-Supply, Low-Power, Serial 8-Bit ADCs -0.5 0 50 100 150 200 DIGITAL CODE 250 300 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5.0 5.5 Single-Supply, Low-Power, Serial 8-Bit ADCs FFT PLOT AMPLITUDE (dB) 0.1 0 -0.1 -0.2 -0.3 -20 -40 -60 -80 20.5 20.0 19.5 19.0 -0.4 -0.5 -100 0 50 100 150 200 250 300 18.5 0 2 DIGITAL CODE 4 6 8 10 14 12 2 22 VDD = 3V 21 20 VDD = 5V 19 18 17 15 20 40 60 80 4 5 6 MAX1106/07-17 1.0010 16 0 3 SUPPLY VOLTAGE (V) NORMALIZED REFERENCE VOLTAGE 23 -20 1 NORMALIZED REFERENCE VOLTAGE vs. TEMPERATURE MAX1106/07-16 25 24 -40 0 FREQUENCY (kHz) CONVERSION TIME vs. TEMPERATURE CONVERSION TIME (µs) INL (LSB) 0.2 21.0 CONVERSION TIME (µs) 0.3 fIN+ = 10.34kHz, 2Vp-p fSAMPLE = 25088Hz 0 21.5 MAX1106/07-14 0.4 CONVERSION TIME vs. SUPPLY VOLTAGE 20 MAX1106/07-13 0.5 MAX1106/07-15 INTEGRAL NONLINEARITY vs. DIGITAL CODE 1.0005 1.0000 0.9995 0.9990 0.9985 0.9980 100 -40 TEMPERATURE (°C) -20 0 20 40 60 80 100 TEMPERATURE (°C) Pin Description PIN NAME 1 VDD Positive Supply Voltage FUNCTION 2 IN+ Positive Analog Input. Sampled. Input range from GND to VDD. 3 IN- Negative Analog Input. Input range from GND to VDD. 4 GND 5 REFOUT Ground. 6 REFIN Reference Voltage Input. Reference voltage for analog-to-digital conversion. Connect REFOUT to REFIN for internal reference. Input range from 1V to VDD. 7 CONVST Conversion Start Input. Toggle CONVST high for 1µs minimum and then low to start internal conversion. Data is not clocked out unless CONVST is low. 8 SHDN Active-Low Shutdown. Connect to VDD for normal operation. 9 DOUT Serial Data Output. Data is clocked out on the falling edge of SCLK. DOUT is high impedance in shutdown or after all data is clocked out. 10 SCLK Serial Clock Input. Clocks data out of serial interface. Internal Reference Output. Bypass with 1µF to ground. 2.048V for MAX1106, 4.096V for MAX1107. _______________________________________________________________________________________ 9 MAX1106/MAX1107 Typical Operating Characteristics (continued) (VDD = +3.0V (MAX1106), VDD = +5.0V (MAX1107); fSCLK = 2MHz; 25ksps conversion rate; external reference; 1µF at REFOUT; TA = +25°C; unless otherwise noted.) MAX1106/MAX1107 Single-Supply, Low-Power, Serial 8-Bit ADCs VDD VDD DOUT DOUT 3k CLOAD 3k DOUT CLOAD CLOAD GND GND b) High-Z to VOL and VOH to VOL Figure 1. Load Circuits for Enable Time DOUT 3k CLOAD GND a) VOL to VOH 3k GND a) VOH to High-Z b) VOL to High-Z Figure 2. Load Circuits for Disable Time _______________Detailed Description The MAX1106/MAX1107 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to an 8-bit digital output. A simple serial interface provides easy interface to microprocessors (µPs). No external hold capacitors are required. All of the MAX1106/MAX1107 operating modes are pin configurable: internal or external reference, single-ended or pseudo-differential unipolar conversion, and power down. Figure 3 shows the typical operating circuit. VDD MAX1106 MAX1107 Track/Hold The input architecture of the ADCs is illustrated in Figure 4’s equivalent-input circuit of and is composed of the T/H, the input multiplexer, the input comparator, the switched capacitor DAC, and the auto-zero rail. The device is in acquisition mode most of the time. During the acquisition interval, the positive input (IN+) is tracked and is connected to the holding capacitor (CHOLD). The acquisition interval ends with the falling edge of CONVST. At this point the T/H switch opens and CHOLD is connected to the negative input (IN-), retaining charge on CHOLD as a sample of the signal at IN+. Once conversion is complete the T/H returns immediately to its tracking mode. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the minimum time needed for the signal to be acquired. It is calculated by: tACQ = 6(RS + RIN)18pF 1µF 0.1µF GND IN- CPU ON OFF SHDN REFOUT REFIN Analog Inputs VDD VDD IN+ ANALOG INPUTS 1µF I/O CONVST SCLK SCK (SK) DOUT MISO (SI) GND Figure 3. Typical Operating Circuit GND CAPACITIVE DAC REFIN IN+ CHOLD COMPARATOR IN- 18pF RIN 6.5k HOLD TRACK AUTOZERO RAIL Figure 4. Equivalent Input Circuit 10 ______________________________________________________________________________________ Single-Supply, Low-Power, Serial 8-Bit ADCs Pseudo-Differential Input The MAX1106/MAX1107 input configuration is pseudodifferential to the extent that only the signal at the sampled input (IN+) is stored in the holding capacitor (C HOLD ). IN- must remain stable within ±0.5LSB (±0.1LSB for best results) in relation to GND during a conversion. If a varying signal is applied at the IN- input, its amplitude and frequency need to be limited. The following equations determine the relationship between the maximum signal amplitude and its frequency to maintain ±0.5LSB accuracy: Assuming a sinusoidal signal at the IN- input, ( ) υIN- = VIN- sin(2πft) under the maximum voltage variation is determined by max ∆υIN∆t ( )≤ = 2πf VIN- 1 LSB t CONV = VREFIN 28 t CONV a 60Hz signal at IN- with an amplitude of 1.2V will generate ±0.5LSB of error. This is with a 35µs conversion time (maximum tCONV) and a reference voltage of 4.096V. When a DC reference voltage is used at IN-, connect a 0.1µF capacitor from IN_ to GND to minimize noise at the input. The common-mode input range of IN+ and IN- is GND to +VDD. Full-scale is achieved when (VIN- - VIN+) = VREFIN. VIN+ must be higher than VIN-. Conversion Process The comparator negative input is connected to the autozero rail. Since the device requires only a single supply, the ZERO node at the input of the comparator equals VDD/2. The capacitive DAC restores node ZERO to have 0V difference at the comparator inputs within the limits of 8-bit resolution. This action is equivalent to transferring a charge of 18pF(VIN+ - VIN-) from CHOLD to the binary-weighted capacitive DAC which, in turn, forms a digital representation of the analog-input signal. Input Voltage Range Internal protection diodes that clamp the analog input to VDD and GND allow the input pins (IN+ and IN-) to swing from (GND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions, the inputs must not exceed (VDD + 50mV) or be less than (GND - 50mV). The MAX1106/MAX1107 input range is from GND to VDD. The output code is invalid (code zero) when a negative input voltage (or a negative differential input voltage) is applied. The reference input-voltage range at REFIN is from 1V to (VDD + 50mV). Input Bandwidth The ADC’s input tracking circuitry has a 1.5MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Serial Interface The MAX1106/MAX1107 have a 3-wire serial interface. The CONVST and SCLK inputs are used to control the device, while the three-state DOUT pin is used to access the result of conversion. The serial interface provides easy connection to microcontrollers with SPI, QSPI, and MICROWIRE serial interfaces at clock rates up to 2MHz. For SPI and QSPI, set CPOL = CPHA = 0 in the SPI control registers of the microcontroller. Figure 5 shows the MAX1106/MAX1107 common serial-interface connections. Digital Inputs and Outputs The logic levels of the MAX1106/MAX1107 digital inputs are set to accept voltage levels from both 3V and 5V systems regardless of the supply voltages. A conversion is started by toggling CONVST. CONVST idles low and needs to be set high for at least 1µs to perform the autozero adjustment. CONVST must remain low during conversion and until the result of conversion has been clocked out. After CONVST is set low, allow 35µs for the conversion to be completed. While the internal conversion is in progress DOUT is low. Conversion is controlled by an internal 400kHz oscillator. The MSB is present at the DOUT pin immediately after conversion is completed. The conversion result is clocked out at the DOUT pin and is coded in straight binary (Figure 9). Data is clocked out at SCLK’s falling edge in MSB-first format at rates up to 2MHz. Once all data bits are clocked out, DOUT goes high impedance at the falling edge of the eighth SCLK pulse. ______________________________________________________________________________________ 11 MAX1106/MAX1107 where RIN = 6.5kΩ, RS = the source impedance of the input signal, and tACQ must never be less than 1µs. This is easily achieved by respecting the minimum CONVST high interval required and the time required to clock the data out. MAX1106/MAX1107 Single-Supply, Low-Power, Serial 8-Bit ADCs I/O Starting SCLK before conversion is complete corrupts the conversion in progress, and the data clocked out at DOUT does not represent the input signal. Bringing CONVST high at anytime during a conversion or while the data is clocked out will result in an incorrect conversion. A new conversion can be restarted only if all eight data bits of conversion have been clocked out. Toggle CONVST after all data is clocked out to restart a new conversion. CONVST SCK SCLK MISO DOUT +3V MAX1106 MAX1107 SS SHDN is used to place the MAX1106/MAX1107 in lowpower mode (see Power-Down section). In this mode DOUT is high impedance and any conversion in progress is stopped immediately. If a conversion is stopped by SHDN going low, the device must be reset by waiting 35µs and clearing the output register with eight SCLKs before the next conversion. a) SPI CS CONVST SCK SCLK MISO DOUT +3V How to Perform a Conversion MAX1106 MAX1107 SS The MAX1106/MAX1107 converts an input signal using the internal clock. This frees the µP from the burden of running the SAR conversion clock, and allows the conversion results to be read back at the µP’s convenience at any clock rate up to 2MHz. b) QSPI I/O CONVST SK SCLK SI DOUT Figures 6 and 7 show the serial interface timing characteristics. CONVST idles low. Toggle CONVST high for at least 1µs to perform the autozero adjustment. After CONVST goes low, conversion starts immediately. Allow 35µs for the internal conversion to complete and issue the MSB of the conversion at DOUT. CONVST needs to be held low once a conversion is started, while SCLK should remain low during conversion for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the MAX1106 MAX1107 c) MICROWIRE Figure 5. Common Serial-Interface Connections tCSPW 1µs (MIN) CONVST 100µs (MAX) 1 8 SCLK MSB HIGH-Z D7 DOUT ACQ CONVERSION D6 D5 D4 D3 D2 D1 LSB D0 HIGH-Z ACQUISITION A/D STATE tCONV = 35µs (MAX) Figure 6. Conversion Timing Diagram 12 ______________________________________________________________________________________ Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107 tCSPW CONVST tCH SCLK tSCC tCL #8 #1 tCONV tDV tDV tTR tDO DOUT Figure 7. Detailed Serial Interface Timing data out of this register at any time after the conversion is complete. After the eighth data-bit has clocked out, DOUT goes high impedance and remains so with additional SCLKs. Normally leave CONVST low until a new conversion needs to be started. CONVST should be high for a maximum of 100µs to maintain the 8-bit accuracy of the Autozero Circuit. The acquisition time, tACQ, starts immediately after the end of conversion and a new conversion can be started immediately after all data has been clocked out by toggling CONVST high. Figure 8 shows a timing diagram for a conversion at the data rate of 40ksps. Typically 20µs are necessary for the conversion to complete, 4µs for reading the eight bits of data with a serial clock of 2MHz, and 1µs to complete the zero rail adjustment and acquisition. The conversion time is guaranteed to be less than 35µs, therefore the data rate should be limited to 25ksps unless the conversion time for the specific condition is known. Conversion time can be determined by measuring the time between CONVST falling edge and DOUT rising edge with a full-scale input voltage. __________Applications Information Power-On Reset When power is first applied with SHDN high or connected to VDD, the MAX1106/MAX1107 is in track mode. Conversion can be started by toggling CONVST high to low as soon as the reference is settled when using the internal reference, or after 20µs when an external reference is used. Powering up the MAX1106/MAX1107 with CONVST 5V/div SCLK 5V/div tCONV DOUT 5V/div 5µs/div Figure 8. 40ksps Timing Diagram CONVST low will not start a conversion. No conversions should be performed until the reference voltage (internal or external) has stabilized. Shutdown Operation Pulling SHDN low places the converter in low-current power-down mode. In this state the converter draws typically 0.5µA. In shutdown the analog biasing circuit and the internal bandgap reference are powered down, and DOUT goes high impedance. The conversion stops coincidentally with SHDN going low. If shutdown occurs during a conversion, power up, wait 35µs, and clock SCLK eight times. ______________________________________________________________________________________ 13 MAX1106/MAX1107 Single-Supply, Low-Power, Serial 8-Bit ADCs When operating at speeds below the maximum sampling rate, the MAX1106/MAX1107’s power-down mode can save considerable power by placing the converter in a low-current shutdown state between conversions. Pull SHDN low after the conversion byte has been read to shut down the device completely. CONVST should remain low most of the time and toggled high for 1µs (100µs max) for the autozero adjustment. An external reference is recommended for best accuracy when using the shutdown feature. This requires only 20µs for the internal biasing circuit to stabilize before starting a new conversion. Alternatively, the internal reference can be used, but additional time is required for the reference to stabilize (when bypassed by a 1µF capacitor; at data rates above 1ksps, the reference stabilizes within 1LSB in 200µs). If the reference is completely discharged it requires 12ms to settle. No conversions should be performed until the reference voltage has stabilized. Internal or External Voltage Reference An external reference between 1V and VDD should be connected directly at the REFIN pin. To use the internal reference, connect REFOUT directly to REFIN and bypass REFOUT with a 1µF capacitor. The DC input impedance at REFIN is extremely high, consisting of leakage current only (typically 10nA). During a conversion, the reference must be able to deliver up to 20µA average load current and have an output impedance of 1kΩ or less at the conversion clock frequency. If the reference has higher output impedance or is noisy, bypass it close to the REFIN pin with a 0.1µF capacitor. The internal reference is active as long as SHDN is high and powers down when SHDN is low. 14 OUTPUT CODE FULL-SCALE TRANSITION 11111111 11111110 11111101 FS = VREFIN + VIN1LSB = VREFIN 256 00000011 00000010 00000001 00000000 0 (IN-) 1 2 3 FS INPUT VOLTAGE (LSB) FS - 1LSB Figure 9. Input/Output Transfer Function Transfer Function Figure 9 depicts the input/output transfer function. Code transitions occur at integer LSB values. Output coding is binary; with a 2.048V reference 1LSB = 8mV (VREFIN / 256). For single-ended operation connect INto GND. Full-scale is achieved at VIN+ = VREFIN - 1LSB. For pseudo-differential operation the VIN- voltage range is from GND to VDD, where full-scale is achieved at VIN+ = VREFIN + VIN- - 1LSB. VIN+ should not be higher than VDD + 50mV. Negative input voltages are invalid and give a zero output code. Voltages greater than fullscale give an all ones output code. ______________________________________________________________________________________ Single-Supply, Low-Power, Serial 8-Bit ADCs Figure 10 shows the recommended system-ground connections. A single-point analog ground (star-ground point) should be established at the A/D ground. Connect all analog grounds to the star ground. No digital-system ground should be connected to this point. The ground return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the comparator in the ADC. Bypass the supply to the star ground with 0.1µF and 1µF capacitors close to the V DD pin of the MAX1106/MAX1107. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10Ω resistor can be connected to form a lowpass filter. MAX1106/MAX1107 Layout, Grounding, and Bypassing For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or run digital lines underneath the ADC package. SYSTEM POWER SUPPLIES GND +3V/+5V 1µF 10Ω 0.1µF GND IN- VDD DGND VDD DIGITAL CIRCUITRY MAX1106 MAX1107 Figure 10. Power-Supply Connections Chip Information TRANSISTOR COUNT: 2373 ______________________________________________________________________________________ 15 Single-Supply, Low-Power, Serial 8-Bit ADCs 10LUMAX.EPS MAX1106/MAX1107 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.