19-1081; Rev 1; 8/96 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down ____________________________Features The MAX113/MAX117 are microprocessor-compatible, 8-bit, 4-channel and 8-channel analog-to-digital converters (ADCs). They operate from a single +3V supply and use a half-flash technique to achieve a 1.8µs conversion time (400ksps). A power-down pin (PWRDN) reduces current consumption to 1µA typical. The devices return from power-down mode to normal operating mode in less than 900ns, allowing large supplycurrent reductions in burst-mode applications. (In burst mode, the ADC wakes up from a low-power state at specified intervals to sample the analog input signals.) Both converters include a track/hold, enabling the ADC to digitize fast analog signals. Microprocessor (µP) interfaces are simplified because the ADC can appear as a memory location or I/O port without external interface logic. The data outputs use latched, three-state buffer circuitry for direct connection to an 8-bit parallel µP data bus or system input port. The MAX113/MAX117 input/reference configuration enables ratiometric operation. ♦ +3.0V to +3.6V Single-Supply Operation ♦ 4 (MAX113) or 8 (MAX117) Analog Input Channels ♦ Low Power: 1.5mA (operating mode) 1µA (power-down mode) ♦ Total Unadjusted Error ≤ 1LSB ♦ Fast Conversion Time: 1.8µs per Channel ♦ No External Clock Required ♦ Internal Track/Hold ♦ Ratiometric Reference Inputs ♦ Internally Connected 8th Channel Monitors Reference Voltage (MAX117) ______________Ordering Information The 4-channel MAX113 is available in a 24-pin DIP or SSOP. The 8-channel MAX117 is available in a 28-pin DIP or SSOP. For +5V applications, refer to the MAX114/MAX118 data sheet. TEMP. RANGE 0°C to +70°C 24 Narrow Plastic DIP MAX113CAG MAX113C/D MAX113ENG 0°C to +70°C 0°C to +70°C -40°C to +85°C 24 SSOP Dice* 24 Narrow Plastic DIP PIN-PACKAGE MAX113EAG -40°C to +85°C 24 SSOP MAX113MRG -55°C to +125°C 24 Narrow CERDIP** Ordering Information continued at end of data sheet. *Dice are specified at TA = +25°C, DC parameters only. **Contact factory for availability. ________________________Applications Battery-Powered Systems System-Health Monitoring Communications Systems PART MAX113CNG Portable Equipment Remote Data Acquisition Pin Configuration appears at end of data sheet. _________________________________________________________Functional Diagram REF+ D7 D6 D5 D4 4-BIT FLASH ADC (4MSBs) *IN8 *IN7 *IN6 *IN5 IN4 IN3 IN2 MUX 4-BIT DAC Σ IN1 REF+ 16 ADDRESS LATCH DECODE THREESTATE OUTPUT DRIVERS D3 D2 D1 D0 4-BIT FLASH ADC (4LSBs) TIMING AND CONTROL MAX113/MAX117 A0 *MAX117 ONLY A1 A2 REF- RD CS PWRDN MODE WR/RDY INT ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX113/MAX117 _______________General Description MAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +7V Digital Input Voltage to GND ......................-0.3V to (VDD + 0.3V) Digital Output Voltage to GND ...................-0.3V to (VDD + 0.3V) REF+ to GND..............................................-0.3V to (VDD + 0.3V) REF- to GND...............................................-0.3V to (VDD + 0.3V) IN_ to GND .................................................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 24 Narrow Plastic DIP (derate 13.33mW/°C above +70°C) ................................1.08W 24 SSOP (derate 8.00mW/°C above +70°C).................640mW 24 Narrow CERDIP (derate 12.50mW/°C above +70°C) .....1W 28 Wide Plastic DIP (derate 14.29mW/°C above +70°C) ................................1.14W 28 SSOP (derate 9.52mW/°C above +70°C).................762mW 28 Wide CERDIP (derate 16.67mW/°C above +70°C)....1.33W Operating Temperature Ranges MAX113C_G/MAX117C_I ....................................0°C to +70°C MAX113E_G/MAX117E_I ..................................-40°C to +85°C MAX113MRG/MAX117MJI..............................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3V to +3.6V, REF+ = 3V, REF- = GND, Read Mode (MODE = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1 LSB ACCURACY (Note 1) Resolution N Total Unadjusted Error TUE Differential Nonlinearity DNL 8 Bits ±1 LSB Zero-Code Error No-missing-codes guaranteed ±1 LSB Full-Scale Error ±1 LSB ±1/4 LSB Channel-to-Channel Mismatch DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Input Full-Power Bandwidth MAX11_C/E, fSAMPLE = 400kHz, fIN = 30.273kHz 45 MAX11_M, fSAMPLE = 340kHz, fIN = 30.725kHz 45 dB MAX11_C/E, fSAMPLE = 400kHz, fIN = 30.273kHz -50 MAX11_M, fSAMPLE = 340kHz, fIN = 30.725kHz -50 MAX11_C/E, fSAMPLE = 400kHz, fIN = 30.273kHz 50 MAX11_M, fSAMPLE = 340kHz, fIN = 30.725kHz 50 VIN_ = 3Vp-p Input Slew Rate, Tracking 0.28 dB dB 0.3 MHz 0.5 V/µs ANALOG INPUT Input Voltage Range VIN_ Input Leakage Current IIN_ Input Capacitance CIN_ VREFGND < VIN_ < VDD VREF+ V ±3 µA 32 pF REFERENCE INPUT Reference Resistance 4 kΩ REF+ Input Voltage Range VREF- VDD V REF- Input Voltage Range GND VREF+ V 2 RREF 1 2 _______________________________________________________________________________________ +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down MAX113/MAX117 ELECTRICAL CHARACTERISTICS (continued) (VDD = +3V to +3.6V, REF+ = 3V, REF- = GND, Read Mode (MODE = GND), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS Input High Voltage VINH Input Low Voltage VINL Input High Current IINH CS, WR, RD, PWRDN, A0, A1, A2 MODE 2 V 2.4 CS, WR, RD, PWRDN, A0, A1, A2 0.66 MODE 0.8 CS, RD, PWRDN, A0, A1, A2 ±1 WR ±3 MODE 15 Input Low Current IINL CS, WR, RD, PWRDN, MODE, A0, A1, A2 Input Capacitance (Note 2) CIN CS, WR, RD, PWRDN, MODE, A0, A1, A2 5 V µA 100 ±1 µA 8 pF LOGIC OUTPUTS Output Low Voltage VOL ISINK = 20µA, INT, D0–D7 0.1 ISINK = 400µA, INT, D0–D7 0.4 RDY, ISINK = 1mA 0.4 ISOURCE = 20µA, INT, D0–D7 VDD - 0.1 ISOURCE = 400µA, INT, D0–D7 VDD - 0.4 Output High Voltage VOH Three-State Current ILKG D0–D7, RDY, digital outputs = 0V to VDD Three-State Capacitance (Note 2) COUT D0–D7, RDY V V 5 ±3 µA 8 pF 3.6 V POWER REQUIREMENTS Supply Voltage VDD VDD Supply Current IDD MAX11_C 2.5 5 MAX11_E/M 2.5 6 VDD = 3.0V, CS = RD = 0V, PWRDN = VDD MAX11_C 1.5 3 MAX11_E/M 1.5 3.5 1 10 µA ±1/16 ±1/4 LSB CS = RD = VDD, PWRDN = 0V (Note 3) Power-Down VDD Current Power-Supply Rejection 3.0 VDD = 3.6V, CS = RD = 0V, PWRDN = VDD PSR VDD = 3.0V to 3.6V, VREF = 3.0V mA Note 1: Accuracy measurements performed at VDD = +3.0V. Operation over supply range is guaranteed by power-supply rejection test. Note 2: Guaranteed by design. Note 3: Power-down current increases if logic inputs are not driven to GND or VDD. _______________________________________________________________________________________ 3 MAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down TIMING CHARACTERISTICS (VDD = +3V, TA = +25°C, unless otherwise noted.) (Note 4) PARAMETER SYMBOL CONDITIONS TA = +25°C ALL GRADES MIN Conversion Time (WR-RD Mode) tCWR Conversion Time (RD Mode) TYP tRD < tINTL, CL = 100pF (Note 5) MAX TA = TMIN to TMAX MAX117C/E MIN MAX MAX117M MIN UNITS MAX 1.8 2.06 2.4 µs tCRD 2.0 2.4 2.6 µs Power-Up Time tUP 0.9 1.2 1.4 µs CS to RD, WR Setup Time tCSS 0 0 0 ns CS to RD, WR Hold Time tCSH 0 0 0 ns CS to RDY Delay tRDY CL = 50pF, RL = 5.1kΩ to VDD Data Access Time (RD Mode) tACC0 CL = 100pF (Note 5) RD to INT Delay (RD Mode) tINTH CL = 50pF Data Hold Time tDH (Note 6) Minimum Acquisition Time tACQ (Note 7) WR Pulse Width tWR 0.6 Delay Between WR and RD Pulses tRD 0.8 0.9 1.0 µs 400 500 600 ns RD Pulse Width (WR-RD Mode) tREAD1 tRD < tINTL, determined by tACC1 Data Access Time (WR-RD Mode) tACC1 tRD < tINTL, CL = 100pF (Note 5) 100 100 120 140 ns tCRD + 100 tCRD + 130 tCRD + 150 ns 160 170 180 ns 100 130 150 ns 450 600 10 0.66 700 10 0.8 ns 10 µs 400 500 600 ns 300 340 400 ns 1.45 1.6 1.8 µs RD to INT Delay tRI WR to INT Delay tINTL RD Pulse Width (WR-RD Mode) tREAD2 tRD > tINTL, determined by tACC2 Data Access Time (WR-RD Mode) tACC2 tRD > tINTL, CL = 100pF (Note 5) 180 220 250 ns WR to INT Delay tIHWR Pipelined mode, CL = 50pF 180 200 240 ns Data Access Time After INT tID Pipelined mode, CL = 100pF 100 130 150 ns Multiplexer Address Hold Time tAH CL = 50pF 0.7 180 50 220 60 250 70 ns ns Note 4: Input control signals are specified with tr = tf = 5ns, 10% to 90% of 3V, and timed from a voltage level of 1.3V. Timing delays get shorter at higher supply voltages. See the Conversion Time vs. Supply Voltage graph in the Typical Operating Characteristics to extrapolate timing delays at other power-supply voltages. Note 5: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V. Note 6: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V. Note 7: Also defined as the Minimum Address-Valid to Convert-Start Time. 4 _______________________________________________________________________________________ +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down EFFECTIVE BITS vs. INPUT FREQUENCY (WR-RD MODE) SIGNAL-TO-NOISE RATIO 0 MAX113/117-02 8.0 MAX113/117-01 1.4 7.5 fIN = 30.27kHz VIN = 2.88Vp-p fSAMPLE = 400ksps SNR = 48.8dB -20 VDD = 3.6V 1.0 VDD = 3.3V 0.8 6.5 6.0 5.0 0.4 -100 4.0 -20 20 140 100 60 -60 -80 fSAMPLE = 400kHz VIN = 2.98Vp-p 4.5 1k 10k TEMPERATURE (°C) 100k 40 0 1M 80 120 160 200 FREQUENCY (kHz) INPUT FREQUENCY (Hz) AVERAGE POWER CONSUMPTION vs. SAMPLING RATE USING PWRDN CONVERSION TIME vs. SUPPLY VOLTAGE 1200 1100 1000 900 MAX113/117-06 1300 5 POWER DISSIPATION (mW) MAX113/117-04 1400 tCRD (ns) 4 3 2 1 0 800 3.0 3.4 3.2 3.6 3.8 100 1000 SAMPLING RATE (ksps) TOTAL UNADJUSTED ERROR vs. POWER-UP TIME SUPPLY CURRENT vs. TEMPERATURE (EXCLUDING REFERENCE CURRENT) VDD = 3.0V 4 SUPPLY CURRENT (mA) 3 2 1 10 SUPPLY VOLTAGE (V) 5 4 1 4.0 MAX113/117-10 2.8 MAX113/117-08 -60 -40 5.5 VDD = 3.0V 0.6 SNR (dB) EFFECTIVE BITS 7.0 1.2 TUE (LSB) tCRD (NORMALIZED TO VALUE AT VDD = +3.3V, +25°C) 1.6 MAX113/117-03 CONVERSION TIME vs. AMBIENT TEMPERATURE VDD = 5.25V 3 VDD = 3.3V 2 VDD = 3.0V 1 VDD = 3.6V 0 0 120 160 200 240 tUP (ns) 280 320 -60 -20 20 60 100 140 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX113/MAX117 __________________________________________Typical Operating Characteristics (VDD = +3V, TA = +25°C, unless otherwise noted.) MAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down ______________________________________________________________Pin Description PIN 6 NAME FUNCTION MAX113 MAX117 — 1 IN6 Analog Input Channel 6 — 2 IN5 Analog Input Channel 5 1 3 IN4 Analog Input Channel 4 2 4 IN3 Analog Input Channel 3 3 5 IN2 Analog Input Channel 2 4 6 IN1 Analog Input Channel 1 5 7 MODE Mode Selection Input. Internally pulled low with a 15µA current source. MODE = 0 activates read mode; MODE = 1 activates write-read mode (see Digital Interface section). 6 8 D0 7, 8, 9 9, 10, 11 D1, D2, D3 Three-State Data Output (LSB) 10 12 RD Read Input. RD must be low to access data (see Digital Interface section). 11 13 INT Interrupt Output. INT goes low to indicate end of conversion (see Digital Interface section). 12 14 GND Ground 13 15 REF- Lower limit of reference span. REF- sets the zero-code voltage. Range is GND ≤ VREF- < VREF+. 14 16 REF+ Upper limit of reference span. REF+ sets the full-scale input voltage. Range is VREF- < VREF+ ≤ VDD. Internally hardwired to IN8 (Table 1). 15 17 WR/RDY Three-State Data Outputs Write-Control Input/Ready-Status Output (see Digital Interface section) 16 18 CS 17, 18, 19 19, 20, 21 D4, D5, D6 Chip-Select Input. CS must be low for the device to recognize WR or RD inputs. 20 22 D7 Three-State Data Output (MSB) Three-State Data Outputs — 23 A2 Multiplexer Channel Address Input (MSB) 21 24 A1 Multiplexer Channel Address Input 22 25 A0 Multiplexer Channel Address Input (LSB) 23 26 PWRDN 24 27 VDD Positive Supply, +3.0V to +3.6V — 28 IN7 Analog Input Channel 7 Power-Down Input. PWRDN reduces supply current when low. _______________________________________________________________________________________ +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down VDD RL = 3k DATA OUTPUTS DATA OUTPUTS CL RL = 3k a) HIGH-Z TO VOH MAX113/MAX117 VDD 3k DATA OUTPUTS DATA OUTPUTS CL 10pF 3k b) HIGH-Z TO VOL a) VOH TO HIGH-Z 10pF b) VOL TO HIGH-Z Figure 1. Load Circuits for Data-Access Time Test Figure 2. Load Circuits for Data-Hold Time Test _______________Detailed Description be started. If the power-down feature is not required, connect PWRDN to VDD. For minimum current consumption, keep digital inputs at the supply rails in power-down mode. Refer to the Reference section for information on reducing the reference current during power-down. Converter Operation The MAX113/MAX117 use a half-flash conversion technique (see Functional Diagram) in which two 4-bit flash ADC sections achieve an 8-bit result. Using 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper four data bits. An internal digital-to-analog converter (DAC) uses the four most significant bits (MSBs) to generate both the analog result from the first flash conversion and a residue voltage that is the difference between the unknown input and the DAC voltage. The residue is then compared again with the flash comparators to obtain the lower four data bits (LSBs). An internal analog multiplexer enables the devices to read four (MAX113) or eight (MAX117) different analog voltages under microprocessor (µP) control. One of the MAX117’s analog channels, IN8, is internally hardwired and always reads VREF+ when selected. Power-Down Mode In burst-mode or low-sample-rate applications, the MAX113/MAX117 can be shut down between conversions, reducing supply current to microamp levels (see Typical Operating Characteristics). A logic low on the PWRDN pin shuts the devices down, reducing supply current typically to 1µA when powered from a single +3V supply. A logic high on PWRDN wakes up the MAX113/MAX117, and the selected analog input enters the track mode. The signal is fully acquired after 900ns (this includes both the power-up delay and the track/hold acquisition time), and a new conversion can ___________________Digital Interface The MAX113/MAX117 have two basic interface modes, which are set by the MODE pin. When MODE is low, the converters are in read mode; when MODE is high, the converters are set up for write-read mode. The A0, A1, and A2 inputs control channel selection, as shown in Table 1. The address must be valid for a minimum time, tACQ, before the next conversion starts. Table 1. Truth Table for Input Channel Selection MAX113 MAX117 SELECTED CHANNEL A1 A0 A2 A1 A0 0 0 0 0 0 IN1 0 1 0 0 1 IN2 1 0 0 1 0 IN3 1 1 0 1 1 IN4 — — 1 0 0 IN5 — — 1 0 1 IN6 — — 1 1 0 IN7 — — 1 1 1 IN8 (reads VREF+ if selected) _______________________________________________________________________________________ 7 MAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down Read Mode (MODE = 0) In read mode, conversions and data access are controlled by the RD input (Figure 3). The comparator inputs track the analog input voltage for the duration of tACQ. A conversion is initiated by driving CS and RD low. With µPs that can be forced into a wait state, hold RD low until output data appears. The µP starts the conversion, waits, and then reads data with a single read instruction. In read mode, WR/RDY is configured as a status output (RDY), so it can drive the ready or wait input of a µP. RDY is an open-collector output (no internal pull-up) that goes low after the falling edge of CS and goes high at the end of the conversion. If not used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the rising edge of CS or RD. tUP PWRDN CS tCSH tCSS RD A0–A2 RDY tACQ ADDRESS VALID (N) tAH tACQ ADDRESS VALID (N + 1) tAH WITH EXTERNAL PULL-UP tRDY tINTH INT tCRD tDH VALID DATA (N) D0–D7 tACCO Figure 3. Read Mode Timing (Mode = 0) Write-Read Mode (MODE = 1) Figures 4 and 5 show the operating sequence for writeread mode. The comparator inputs track the analog input voltage for the duration of tACQ. The conversion is initiated by a falling edge of WR. When WR returns high, the result of the four-MSBs flash is latched into the output buffers and the conversion of the four-LSBs flash starts. INT goes low, indicating conversion end, and the lower four data bits are latched into the output buffers. The data is then accessible after RD goes low (see Timing Characteristics). A minimum acquisition time (tACQ) is required from INT going low to the start of another conversion (WR going low). Options for reading data from the converter include using internal delay, reading before delay, and pipelined operation (discussed in the following sections). Using Internal Delay The µP waits for the INT output to go low before reading the data (Figure 4). INT goes low after the rising edge of WR, indicating that the conversion is complete and the result is available in the output latch. With CS low, data outputs D0–D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD. Fastest Conversion: Reading Before Delay An external method of controlling the conversion time is shown in Figure 5. The internally generated delay (tINTL) varies slightly with temperature and supply voltage, and can be overridden with RD to achieve the fastest conversion time. RD is brought low after the rising edge of WR, but before INT goes low. This completes the conversion and enables the output buffers 8 CS tCSH tCSS tWR WR tACQ tACQ tAH ADDRESS VALID (N) A0–A2 ADDRESS VALID (N + 1) tCSH tCSS RD tREAD2 tINTH tRD INT tINTL VALID DATA (N) D0–D7 tACC2 tDH Figure 4. Write-Read Mode Timing (tRD > tINTL) (Mode = 1) CS tWR WR tCSS A0–A2 tCSH tRD tACQ tINTL tAH tACQ ADDRESS VALID (N) ADDRESS VALID (N + 1) tCSS RD tCSH tREAD1 tRI INT VALID DATA (N) D0–D7 tCWR tACC1 tINTH tDH Figure 5. Write-Read Mode Timing (tRD < tINTL) (Mode = 1) _______________________________________________________________________________________ +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down tCSS tCSH tWR RD, WR A0–A2 VIN+ IN_ VIN- GND VDD MAX113 REF+ MAX117 +3V tACQ tACQ tAH ADDRESS VALID (N) ADDRESS VALID (N + 1) REF- tIHWR INT 0.1µF 4.7µF Figure 7a. Power Supply as Reference tINTL VIN+ tID D0–D7 OLD DATA (N - 1) MAX113/MAX117 CS VINNEW DATA (N) GND VDD +3V Figure 6. Pipelined Mode Timing (WR = RD) (Mode = 1) 4.7µF 0.1µF 8 1 3 that contain the conversion result (D0–D7). INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: tWR + tRD + tACC1 = 1800ns. Pipelined Operation Besides the two standard write-read-mode options, “pipelined” operation can be achieved by connecting WR and RD together (Figure 6). With CS low, driving WR and RD low initiates a conversion and concurrently reads the result of the previous conversion. _____________Analog Considerations Reference Figures 7a, 7b, and 7c show typical reference connections. The voltages at REF+ and REF- set the ADC’s analog input range (Figure 10). The voltage at REFdefines the input that produces an output code of all zeros, and the voltage at REF+ defines the input that produces an output code of all ones. The internal resistance from REF+ to REF- can be as low as 1kΩ, and current will flow through it even when the MAX113/MAX117 are shut down. Figure 7d shows how an N-channel MOSFET can be connected to REFto break this current path during power-down. The FET should have an on-resistance of less than 2Ω with a 3V gate drive. When REF- is switched, as in Figure 7d, a new conversion can be initiated after waiting a time equal to the power-up delay (tUP) plus the N-channel FET’s turn-on time. Although REF+ is frequently connected to VDD, the circuit of Figure 7d uses a low-current, low-dropout, 2.5V voltage reference: the MAX872. Since the MAX872 cannot continuously furnish enough current for the ref- 7 +2.5V 6 34.8k 2 LM10 IN_ REF+ 0.1µF MAX113 MAX117 3.01k 4 REF- Figure 7b. External Reference, 2.5V Full Scale VIN+ IN_ GND +3V 4.7µF VDD 0.1µF MAX113 REF+ MAX117 +2.5V VINR* REF0.1µF 0.1µF * CURRENT PATH MUST STILL EXIST FROM VIN- TO GND Figure 7c. Input Not Referenced to GND erence resistance, this circuit is intended for applications where the MAX113/MAX117 are normally in standby and are turned on in order to make measurements at intervals greater than 100µs. C1 (the capacitor connected to REF+) is slowly charged by the MAX872 during the standby period, and furnishes the reference current during the short measurement period. The 4.7µF value of C1 ensures a voltage drop of less than 1/2LSB when performing four to eight successive conversions. Larger capacitors reduce the error still further. Use ceramic or tantalum capacitors for C1. _______________________________________________________________________________________ 9 MAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down +3V VDD 0.1µF MAX113 REF+ MAX117 MAX872 C1 4.7µF N-FET* RON VIN2 . . . RIN REFPWRDN MAX113 MAX117 MUX 0.1µF T/H PWRDN * IRML2402 Figure 7d. An N-channel MOSFET switches off the reference load during power-down Figure 8. Equivalent Input Circuit Initial Power-Up When power is first applied, perform a conversion to initialize the MAX113/MAX117. Disregard the output data. R VIN_ 1 VIN Bypassing 22pF Use a 4.7µF electrolytic in parallel with a 0.1µF ceramic capacitor to bypass VDD to GND. Minimize capacitor lead lengths. Bypass the reference inputs with 0.1µF capacitors, as shown in Figures 7a, 7b, and 7c. Analog Inputs Figure 8 shows the equivalent circuit of the MAX113/ MAX117 input. When a conversion starts and WR is low, VIN_ is connected to sixteen 0.6pF capacitors. During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches. In addition, about 22pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge. The typical 32pF input capacitance allows source resistance as high as 1.5kΩ without setup problems. For larger resistances, the acquisition time (tACQ) must be increased. Internal protection diodes, which clamp the analog input to VDD and GND, allow the channel input pins to swing from GND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale and zero scale the inputs must not exceed VDD by more than 50mV or be lower than GND by 50mV. 2k 10pF MAX113 MAX117 Figure 9. RC Network Equivalent Input Model OUTPUT CODE FULL-SCALE TRANSITION 11111111 11111110 11111101 1LSB = 00000011 00000010 00000001 VREF+ 00000000 VREF- 1 2 FS 3 INPUT VOLTAGE (LSBs) Figure 10. Transfer Function 10 VREF+ - VREF256 ______________________________________________________________________________________ FS - 1LSB +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down Track/Hold The track/hold enters hold mode when a conversion starts (RD low or WR low). INT goes low at the end of the conversion, at which point the track/hold enters track mode. The next conversion can start after the minimum acquisition time, tACQ. Transfer Function Figure 10 shows the MAX113/MAX117’s nominal transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary with 1LSB = (VREF+ - VREF-) / 256. Conversion Rate The maximum sampling rate (fMAX) for the MAX113/ MAX117 is achieved in write-read mode (tRD < tINTL) and is calculated as follows: 1 fMAX = t WR + tRD + tRI + tACQ fMAX = 1 600ns + 800ns + 300ns + 450ns fMAX = 465kHz where tWR = the write pulse width, tRD = the delay between write and read pulses, tRI = RD to INT delay, and tACQ = minimum acquisition time. Signal-to-Noise Ratio and Effective Number of Bits Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to all other ADC output signals. The output spectrum is limited to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 30.27kHz sinusoid at a 400kHz rate. This FFT plot of the output shows the output level in various spectral bands. The effective resolution (or “effective number of bits”) the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SINAD 1.76) / 6.02 (see Typical Operating Characteristics). Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + ...VN THD = 20log V1 where V1 is the fundamental RMS amplitude, and V2 through VN are the amplitudes of the 2nd through Nth harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADC’s noise floor. See the Signal-to-Noise Ratio graph in Typical Operating Characteristics. ______________________________________________________________________________________ 11 MAX113/MAX117 If the analog input exceeds 50mV beyond the supplies, limit the input current to no more than two milliamperes, as excessive current will degrade the conversion accuracy of the on channel. MAX113/MAX117 +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1µA Power-Down __Ordering Information (continued) PART TEMP. RANGE ___________________Chip Information PIN-PACKAGE MAX117CPI 0°C to +70°C 28 Wide Plastic DIP MAX117CAI MAX117C/D MAX117EPI 0°C to +70°C 0°C to +70°C -40°C to +85°C 28 SSOP Dice* 28 Wide Plastic DIP MAX117EAI MAX117MJI -40°C to +85°C -55°C to +125°C 28 SSOP 28 Wide CERDIP** TRANSISTOR COUNT: 2011 *Dice are specified at TA = +25°C, DC parameters only. **Contact factory for availability. __________________________________________________________Pin Configurations TOP VIEW IN4 1 24 VDD IN3 2 23 PWRDN IN2 3 22 A0 IN1 4 21 A1 MODE 5 MAX113 20 D7 D0 6 19 D6 D1 7 18 D5 D2 8 17 D4 D3 9 16 CS RD 10 15 WR/RDY INT 11 14 REF+ GND 12 13 REF- DIP/SSOP IN6 1 28 IN7 IN5 2 27 VDD IN4 3 26 PWRDN IN3 4 25 A0 IN2 5 IN1 6 MAX117 24 A1 23 A2 MODE 7 22 D7 D0 8 21 D6 D1 9 20 D5 D2 10 19 D4 D3 11 18 CS RD 12 17 WR/RDY INT 13 16 REF+ GND 14 15 REF- DIP/SSOP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.