For Communications Equipment MN86063 High-Speed CODEC LSI for Facsimile Images Overview The MN86063 is a high-speed LSI codec for compressing and decompressing facsimile images. Features include real-time printing to laser printers, built-in line memory, enlargement and reduction, and code conversion. Features Pixels per line: between 16 and 4864 bits, in word (16-bit) increments. Processing time per line: Individual pixels are processed within two system clock cycles. For a machine cycle of 10 MHz, processing the worst-case pattern for a 4096-bit line takes no more than 1 ms. Time-shared, multiplex processing Support for time-shared, multiplex processing allows image I/O, enlargement/reduction processing, and coding/decoding to proceed concurrently for a group of lines. Image bus DMA transfers can also proceed concurrently with command processing. Multiple channels If lines consist of 2432 bits or fewer, commands can be processed simultaneously on two channels using time-sharing. These commands may be issued asynchronously. Bus configuration There are separate system and image buses. The latter features two independent master DMA channels; the former, four slave DMA channel pins. Image data I/O Image data I/O can use either the image or system bus. Byte conversion When the system bus is 16 bits wide, the chip can swap the upper and lower bytes of image or coded data. It can also swap the MSB and LSB. Memory management The chip includes pointer management for the image buffer connected to the image bus. Machine cycle The limit is 10 MHz. This means that the maximum input clock is twice this, or 20 MHz. Function Message coding: MH, MR, MMR, and MG3. The chip also supports data transfers on the image and system buses and DMA transfers on the image bus alone. Coding conversion The chip converts between all supported message coding systems: MH, MR, MMR, and MG3. Enlargement/reduction These may be added to coding, decoding, code conversion, and data transfer operations. (1) In the primary scan direction, the chip uses multiplication on the change point address. The scaling factor can be anywhere between approximately 0.1% and 200% in increments of approximately 0.1%. Integral multiplication is also available beyond this (2) In the subscanning direction, the chip uses decimation and replication. The scaling factor can be anywhere between approximately 0.0015% and 200% in increments of approximately 0.0015%. Integral multiplication is also available from 2 to 65,535. White masks for both edges These may be added to coding, decoding, code conversion, and data transfer operations. They change all pixels within the margins, specified in bit increments, to white. Decoding error processing The chip offers a choice of replacing with the previous line or a white line. Applications Facsimile equipment MN86063 For Communications Equipment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IA0 IA1 IA2 IA3 IA4 IA5 IA6 IA7 IA8 IA9 IA10 IA11 IA12 IA13 IA14 IA15 VDD2 VSS2 DACK1 DACK0 DSTR0 DSTR1 IMLE IMUE DCMP0 Pin Assignment 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 HEX INTR0 INTR1 INTR2 2SYSCLK RD WR SYSCLK D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CS VSS3 VDD3 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 VSS4 VDD4 TEST3 TEST2 TEST1 TEST0 RESET QFP100-P-1818 DCMP1 IREADY IOW IMW IOR IMR DREQ0 DREQ1 IHACK IHREQ VDD1 VSS1 A0 A1 A2 A3 ACKD1 ACKD0 ACKC1 ACKC0 REQD1 REQD0 REQC1 REQC0 UBE For Communications Equipment MN86063 Pin Configuration The MN86063 features two buses: the system bus, which is primarily used for transferring coded data to and from a microprocessor and other components and the image bus, which is used for transferring image data to or from a scanner, printer, or the like. Pin Function Chart The chip has a total of 100 pins: 39 for the system bus, 49 for the image bus, and 12 for testing, power supply, and other purposes. Image bus pins System bus pins A0 to A3 IA0 to 15 D0 to D15 ID0 to 15 UBE RD WR CS HEX RESET INTR0 to 2 IHREQ IHACK IREADY IMUE IMLE MN8606X REQC0 IMR IMW REQC1 REQD0 DSTR0 REQD1 DSTR1 ACKC0 ACKC1 DREQ0 ACKD0 ACKD1 DACK0 DREQ1 DACK1 DCMP0 2SYSCLK SYSCLK DCMP1 IOR IOW TEST0 to 3 VDD0 to 3 VSS0 to 3 MN86063 For Communications Equipment Pin Descriptions System Bus Pin No. 35 Symbol A3 36 A2 37 A1 38 A0 I/O I Function Description Address. Address bus for accessing internal registers Data. Data bus for bidirectional transfers over system bus 9 D15 I/O 10 D14 Tristate 11 D13 12 D12 13 D11 14 D10 15 D9 16 D8 17 D7 18 D6 19 D5 20 D4 21 D3 22 D2 23 D1 24 D0 26 UBE I Upper byte enable. This input pin specifies whether the data from pins D15–D8 is effective. 6 RD I Read. This input pin specifies a read from the specified register. 7 WR I Write. This input pin specifies a write to the specified register. 25 CS I Chip select. This input pin specifies access to a register. 1 HEX I Data bus width selection. This input pin specifies the width of the system 100 RESET I Reset. This input pin resets the internal circuitry, clearing all registers. 2 INTR0 O Interrupt request 0. This output pin indicates an interrupt request data bus: "0" for 16 bits; "1" for 8 bits. Open triggered by the cause given in interrupt register 0 (STIR0) corrector 3 INTR1 O Open Interrupt request 1. This output pin indicates an interrupt request triggered by the cause given in interrupt register 1 (STIR1) corrector 4 INTR2 O Open Interrupt request 2. This output pin indicates an interrupt request triggered by the cause given in DMA transfer interrupt register (DMIR). corrector 27 REQC0 O 28 REQC1 O DMA transfer output request 0. This output pin indicates a request for data output on DMA channel 0. DMA transfer output request 1. This output pin indicates a request for data output on DMA channel 1. For Communications Equipment MN86063 Pin Descriptions (continued) System Bus (continued) Pin No. 29 Symbol REQD0 I/O O Function Description DMA transfer input request 0. This output pin indicates a request for data 30 REQD1 O 31 ACKC0 I 32 ACKC1 I 33 ACKD0 I 34 ACKD1 I DMA transfer input acknowledge 0. This input pin accepts the response 5 2SYSCLK I 2 system clock. This input pin accepts a clock signal with a frequency 8 SYSCLK O input on DMA channel 0. DMA transfer input request 1. This output pin indicates a request for data input on DMA channel 1. DMA transfer output acknowledge 0. This input pin accepts the response to a DMA transfer request with REQC0. DMA transfer output acknowledge 0. This input pin accepts the response to a DMA transfer request with REQC1. DMA transfer input acknowledge 0. This input pin accepts the response to a DMA transfer request with REQD0. to a DMA transfer request with REQD1. twice that of the system clock. System clock. This output pin provides a clock signal with half the frequency of 2SYSCLK. Image Bus Pin No. 60 Symbol IA15 I/O O 61 1A14 Tristate 62 IA13 63 IA12 64 IA11 65 IA10 66 IA9 67 IA8 68 IA7 69 IA6 70 IA5 71 IA4 72 IA3 73 IA2 74 IA1 75 IA0 Function Description Image address bus. These pins provide an address on the image data bus. MN86063 For Communications Equipment Pin Descriptions (continued) Image Bus (continued) Pin No. 78 Symbol ID15 I/O I/O 79 ID14 Tristate 80 ID13 81 ID12 82 ID11 83 ID10 84 ID9 85 ID8 86 ID7 87 ID6 88 ID5 89 ID4 90 ID3 91 ID2 92 ID1 93 ID0 41 IHREQ O 42 IHACK I 49 IREADY I 52 IMUE O 53 IMLE 45 IMR 47 IMW 55 DSTR0 54 DSTR1 O 44 DREQ0 I 43 DREQ1 I 56 DACK0 O 57 DACK1 O Function Description Image data. These pins form a bus for bidirectional transfers of image data. Image bus request. This output pin indicates a request for control of the image bus. Image bus acknowledge. This input pin indicates when the chip can seize control of the image bus. Image data acknowledge. This input pin indicates the end of the read/ write operation. Tristate O Tristate O Tristate O Tristate O Image memory upper byte enable. This output pin specifies whether the data from pins ID15–ID8 is effective. Image memory lower byte enable. This output pin specifies whether the data from pins ID7–ID0 is effective. Image memory read. This output pin indicates a read from the address on the image address bus. Image memory write. This output pin indicates a write to the address on the image address bus. DMA start 0. This output indicates that the chip is ready for a DMA transfer from an I/O device to memory. DMA start 1. This output indicates that the chip is ready for a DMA transfer from memory to an I/O device. DMA request 0. This input pin indicates a request for a DMA transfer from an I/O device to memory. DMA request 1. This input pin indicates a request for a DMA transfer from memory to an I/O device. DMA acknowledge 0. This output pin gives the response to the DREQ0 signal, initiating a DMA transfer from an I/O device to memory. DMA acknowledge 1. This output pin gives the response to the DREQ1 signal, initiating a DMA transfer from memory to an I/O device. For Communications Equipment MN86063 Pin Descriptions (continued) Image Bus (continued) Pin No. 51 Symbol DCMP0 I/O O Function Description DMA complete 0. This output pin indicates the successful completion of the DMA transfer of 1 line of data from an I/O device to memory. 50 DCMP1 O DMA complete 1. This output pin indicates the successful completion of the DMA transfer of 1 line of data from memory to an I/O device. 46 IOR O Tristate 48 IOW O Tristate I/O device read. This output pin indicates a read from an I/O device connected to the image address bus. I/O device write. This output pin indicates a write to an I/O device connected to the image address bus. Power on Reset Circuit Pin No. 96 Symbol TEST3 97 TEST2 98 TEST1 99 TEST0 40 VDD1 59 VDD2 77 VDD3 95 VDD4 39 VSS1 58 VSS2 76 VSS3 94 VSS4 I/O I Function Description Test mode. Connect all these pins to the ground. I 5 volt power supply. Connect all these pins to a 5 volt power supply. I Ground. Connect all these pins to the ground. MN86063 For Communications Equipment Application Circuit Example #1. Sample Connections to System Bus Address bus Data bus (MPU) BUFR/W BUFEN AD(0 to 15) 16 74HC245 G B DIR 16 A 2 pieces A(16 to 15) 4 3 BS(0 to 2) ASTB HDACK +5V 74HC573 D Q C OC 3 pieces MN86063 23 4 A(0 to 3) D(0 to 15) 16 A(0 to 3) D(0 to 15) UBE UBE IORD RD WT IOWR BS(0 to 2) +5V A(4 to 19) MRD Address Decoder MWT DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3 DMAAK3 CS HEX REQC0 ACKC0 REQC1 ACKC1 REQD0 ACKD0 REQD1 ACKD1 INTR0 INTR1 INTR2 INTR0 INTR1 INTR2 CLKIN RST 2SYSCLK RESET (Upper half of memory) 256-Kbit SRAM A(0 to 14) I/O(0 to 7) A(1 to 15) D(8 to 15) 15 8 CS WE Crystal oscillator circuit (20 MHz) OE Address Decoder (Lower half of memory) 256-Kbit SRAM A(0 to 14) I/O(0 to 7) CS WE OE A(1 to 15) 15 D(0 to 7) 8 BS(0 to 2) A(16 to 19) A0 Power on reset circuit For Communications Equipment MN86063 Application Circuit Example #2. Sample Connections to Image Bus Address bus Data bus MN86063 IHREQ Bus Arbiter IHACK IA(0 to 15) ID(0 to 15) DSTR0 DCMP0 DREQ0 DACK0 IOR Scanner 8 +5V SYSCLK IREADY Low-speed device Timing control DSTR1 DCMP1 DREQ1 DACK1 IOW Printer +5V 8 IMUE IMLE (Upper half of memory) IMR 256-Kbit SRAM IMW IA(1 to 15) 15 A(0 to 14) ID(8 to 15) 8 I/O(0 to 7) CS WE OE (Lower half of memory) 256-Kbit SRAM IA(1 to 15) 15 ID(0 to 7) 8 A(0 to 14) I/O(0 to 7) CS WE OE MN86063 For Communications Equipment Package Dimensions (Unit: mm) QFP100-P-1818 22.90±0.40 18.00±0.20 75 51 50 100 26 0.15 SEATING PLANE (1.30±0.20) (2.45±0.20) +0.10 0.15–0.05 0.30±0.10 2.90 max. 0.65 2.50±0.20 (1.20) 25 0.10±0.10 1 22.90±0.40 18.00±0.20 (1.20) 76 0 to 10°