19-0486; Rev 2; 2/00 +5V Microprocessor Supervisory Circuits These devices offer two pretrimmed reset threshold voltages for ±5% or ±10% power supplies: 4.65V for the L versions and 4.40V for the M versions. The MAX817/ MAX818/MAX819 are available in space-saving µMAX packages, as well as 8-pin DIP/SO. _____________________Selector Guide MAX817 L/M MAX818 L/M MAX819 L/M Active-Low Reset ✔ ✔ ✔ Backup-Battery Switchover ✔ ✔ ✔ Power-Fail Comparator ✔ Watchdog Input ✔ — ✔ Battery Freshness Seal ✔ ✔ — ✔ Manual Reset Input — Chip-Enable Gating — — ✔ — FEATURE Pin-Package ✔ ♦ 11µA Quiescent Supply Current ♦ 200ms Reset Time Delay ♦ Watchdog Timer with 1.6sec Timeout (MAX817/MAX818) ♦ Battery-Backup Power Switching; Battery Voltage Can Exceed VCC ♦ Battery Freshness Seal ♦ On-Board, 3ns Gating of Chip-Enable Signals (MAX818) ♦ Uncommitted Voltage Monitor for Power-Fail or Low-Battery Warning (MAX817/MAX819) ♦ Manual Reset Input (MAX819) ______________Ordering Information PART† — TEMP. RANGE PIN-PACKAGE MAX817_CPA 0°C to +70°C 8 Plastic DIP MAX817_CSA MAX817_CUA 0°C to +70°C 0°C to +70°C 8 SO 8 µMAX Ordering Information continued on last page. †These parts offer a choice of reset threshold voltage. From the table below, select the suffix corresponding to the desired threshold and insert it into the blank to complete the part number. ✔ SUFFIX RESET THRESHOLD (V) L 4.65 M 4.40 8-DIP/SO/ 8-DIP/SO/ 8-DIP/SO/ µMAX µMAX µMAX Low-Power, PinMAX690A/ Compatible Upgrades for: MAX692A MAX703/ MAX704 ________________________Applications Battery-Powered Computers and Controllers Embedded Controllers Intelligent Instruments Critical µP Monitoring Portable Equipment Typical Operating Circuit appears at end of data sheet. *Patents Pending ____________________________Features ♦ Precision Supply-Voltage Monitor: 4.65V (MAX81_L) 4.40V (MAX81_M) _________________Pin Configurations TOP VIEW OUT 1 8 BATT 7 RESET GND 3 6 WDI PFI 4 5 PFO VCC 2 MAX817 DIP/SO/µMAX Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX817L/M, MAX818L/M, MAX819L/M* General Description The MAX817/MAX818/MAX819 microprocessor (µP) supervisory circuits simplify power-supply monitoring, battery control, and chip-enable gating in µP systems by reducing the number of components required. These devices are designed for use in +5V-powered systems. Low supply current (11µA typical) and small package size make these devices ideal for portable applications. The MAX817/MAX818/MAX819 are specifically designed to ignore fast transients on VCC. Other supervisory functions include active-low reset, backupbattery switchover, watchdog input, battery freshness seal, and chip-enable gating. The Selector Guide below lists the specific functions available from each device. MAX817L/M, MAX818L/M, MAX819L/M* +5V Microprocessor Supervisory Circuits ABSOLUTE MAXIMUM RATINGS Input Voltage VCC, BATT ..........................................................-0.3V to +6.0V All Other Pins (Note 1).............................-0.3V to (VCC + 0.3V) Input Current VCC Peak ..............................................................................1A VCC Continuous .............................................................250mA BATT Peak .....................................................................250mA BATT Continuous .............................................................50mA GND .................................................................................25mA Output Current OUT................................................................................250mA All Other Outputs .............................................................25mA OUT Short-Circuit Duration.................................................10sec Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 9.09mW/°C above +70°C) .............727mW SO (derate 5.88mW/°C above +70°C) ..........................471mW µMAX (derate 4.10mW/°C above +70°C) .....................330mW Operating Temperature Ranges MAX81_ _C_A ......................................................0°C to +70°C MAX81_ _E_A ...................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Note 1: The input voltage limits on PFI and WDI may be exceeded (up to 12V VIN) if the current into these pins is limited to less than 10mA. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +4.75V to +5.5V for MAX81_L, VCC = +4.5V to +5.5V for MAX81_M, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN Operating Voltage Range, VCC, VBATT (Note 2) Supply Current (excluding IOUT) TYP 0 ISUPPLY As applicable; CE IN = 0V, WDI and MR unconnected Supply Current in BatteryBackup Mode (excluding IOUT) VCC = 0V BATT Standby Current (Note 3) 5.5V > VCC > (VBATT + 0.2V) BATT Leakage Current, Freshness Seal Enabled VCC = 0V, VOUT = 0V 5.5 V 11 45 MAX81_ _E 11 60 TA = +25°C 0.05 1.0 TA = TMIN to TMAX 5.0 TA = +25°C -0.10 0.02 TA = TMIN to TMAX -1.00 0.02 1 IOUT = 5mA VCC 0.05 VCC 0.025 IOUT = 50mA VCC 0.5 VCC 0.25 VCC to OUT On-Resistance 5 BATT to OUT On-Resistance 100 VOUT in Battery-Backup Mode IOUT = 250µA, VCC < (VBATT - 0.2V) Battery Switch Threshold (VCC - VBATT) VCC < VRST 2 UNITS MAX81_ _C VOUT Output Battery Switchover Hysteresis MAX VBATT - VBATT 0.1 0.02 Power-up 20 Power-down -20 40 _______________________________________________________________________________________ µA µA µA µA V 10 Ω Ω V mV mV +5V Microprocessor Supervisory Circuits (VCC = +4.75V to +5.5V for MAX81_L, VCC = +4.5V to +5.5V for MAX81_M, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX MAX81_L 4.50 4.65 4.75 MAX81_M 4.25 4.40 4.50 UNITS RESET AND WATCHDOG TIMER Reset Threshold VRST Reset Threshold Hysteresis Reset Timeout Period 25 tRP VOH RESET Output Voltage VOL VCC to RESET Delay tWD WDI Pulse Width tWDI VIL VIH 280 VCC < VRST(MIN), ISINK = 3.2mA 0.4 MAX81_ _C, VCC = 1V, VCC falling, VBATT = 0V, ISINK = 50µA 0.3 MAX81_ _E, VCC = 1.2V, VCC falling, VBATT = 0V, ISINK = 100µA 0.3 100 1.00 VIL = 0.4V, VIH = 0.8VCC VCC = 5V WDI = GND, time average 1.60 ms V µs 2.25 50 sec ns 0.8 3.5 WDI = VCC, time average WDI Input Current (Note 5) 200 mV VCC - 1.5 From VRST, VCC falling at 10V/ms Watchdog Timeout Period WDI Input Threshold (Note 4) 140 VCC > VRST(MAX), ISOURCE = 800µA V 120 -20 -15 VPFT 1.20 1.25 IPFI -25 0.01 160 V µA POWER-FAIL COMPARATOR (MAX817/MAX819 only) PFI Input Threshold PFI Input Hysteresis PFI Input Current PFO Output Voltage 1.30 4 VOL VPFI < 1.20V, ISINK = 3.2mA, VCC > 4.50V VOH VPFI > 1.30V, ISOURCE = 40µA, VCC > 4.5V PFO Short-Circuit Current mV 25 0.4 VCC - 1.5 V P FO = 0V 250 V 500 nA V µA MANUAL RESET INPUT (MAX819 only) MR Input Threshold MR Pulse Width VIL 0.8 VIH 2.0 1 MR Pulse that Would Not Cause a Reset µs 100 MR to Reset Delay ns 120 MR Pull-Up Resistance 45 V 63 ns 85 kΩ _______________________________________________________________________________________ 3 MAX817L/M, MAX818L/M, MAX819L/M* ELECTRICAL CHARACTERISTICS (continued) MAX817L/M, MAX818L/M, MAX819L/M* +5V Microprocessor Supervisory Circuits ELECTRICAL CHARACTERISTICS (continued) (VCC = +4.75V to +5.5V for MAX81_L, VCC = +4.5V to +5.5V for MAX81_M, VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CHIP-ENABLE GATING (MAX818 only) CE IN Leakage Current Disable mode ±0.005 ±1 µA CE IN to CE OUT Resistance (Note 6) Enable mode 40 150 Ω CE OUT Short-Circuit Current (Reset Active) Disable mode, CE OUT = 0V 0.75 2.0 mA CE IN to CE OUT Propagation Delay (Note 7) 50Ω source impedance driver, CLOAD = 50pF 3 8 ns CE OUT Output CE OUT Input Threshold RESET to CE OUT Delay VOH VIH VIL IOUT = -100µA, VCC = 0V IOUT = -1µA, VCC = 0V, VBATT = 2.8V VCC = 5V Power-down 0.1 VCC - 1V V 2.7 0.8 3.5 15 V µs Either VCC or VBATT can go to 0V if the other is greater than 2.0V. “-” = battery-charging current, “+” = battery-discharging current. WDI is internally serviced within the watchdog timeout period if WDI is left unconnected. WDI input is designed to be driven by a three-stated output device. To float WDI, the “high-impedance mode” of the output device must have a maximum leakage current of 10µA and a maximum output capacitance of 200pF. The output device must also be able to source and sink at least 200µA when active. Note 6: The chip-enable resistance is tested with VCC = +4.75V for the MAX818L and VCC = +4.5V for the MAX818M. V C E IN = V C E OUT = VCC/2. Note 7: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT. Note 2: Note 3: Note 4: Note 5: 4 _______________________________________________________________________________________ +5V Microprocessor Supervisory Circuits 12 10 8 -20 0 20 40 60 80 VBATT = 5.0V 120 100 80 VBATT = 2.8V 60 VBATT = 2.0V 40 20 100 VCE IN = 4V 80 70 60 VCE IN = 3V 50 40 VCE IN = 2V 30 20 10 0 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 TEMPERATURE (°C) TEMPERATURE (°C) BATT TO OUT ON-RESISTANCE vs. TEMPERATURE VCC TO OUT ON-RESISTANCE vs. TEMPERATURE RESET TIMEOUT PERIOD vs. TEMPERATURE 150 VBATT = 2.8V 100 VBATT = 5.0V 50 0 6 5 4 0 20 40 60 80 100 100 80 100 MAX817/18/19-06 210 200 190 180 3 -20 80 220 RESET TIMEOUT PERIOD (ms) VBATT = 2.0V 200 MAX817/18/19-05 250 7 VCC TO OUT ON-RESISTANCE (Ω) VCC = 0V -40 90 TEMPERATURE (°C) MAX817/18/19-04 300 -40 -20 0 20 40 60 80 -40 100 -20 0 20 40 60 TEMPERATURE (°C) TEMPERATURE (°C) VCC TO RESET PROPAGATION DELAY vs. TEMPERATURE WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE BATTERY FRESHNESS SEAL LEAKAGE CURRENT vs. TEMPERATURE 300 1V/ms 200 10V/ms 100 0 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 20 1.65 1.60 1.55 MAX817/18/19-09 400 1.70 MAX817/18/19-08 VCC FALLING AT: 0.25V/ms WATCHDOG TIMEOUT PERIOD (sec) 500 MAX817/18/19-07 TEMPERATURE (°C) LEAKAGE CURRENT (nA) BATT TO OUT ON-RESISTANCE (Ω) 140 100 0 -40 VCC TO RESET PROPAGATION DELAY (ms) VCC = 0V CE IN TO CE OUT ON-RESISTANCE (Ω) MAX817/18/19-01 14 160 BATTERY SUPPLY CURRENT (nA) SUPPLY CURRENT (µA) 16 CE IN TO CE OUT ON-RESISTANCE vs. TEMPERATURE MAX817/18/19-02 BATTERY SUPPLY CURRENT (BACKUP MODE) vs. TEMPERATURE MAX817/18/19-03 SUPPLY CURRENT vs. TEMPERATURE (NO LOAD) 15 10 5 0 1.50 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX817L/M, MAX818L/M, MAX819L/M* __________________________________________Typical Operating Characteristics (VCC = +5V, VBATT = 3.0V, TA = +25°C, unless otherwise noted.) ____________________________Typical Operating Characteristics (continued) (VCC = +5V, VBATT = 3.0V, TA = +25°C, unless otherwise noted.) 4.5 MAX81_M 4.3 -40 1000 800 RESET OCCURS ABOVE CURVE 600 400 200 0 20 60 40 1 80 6 5 4 3 2 1 0 0 -20 MAX817/18/19-12 MAX817/18/19-11 1200 7 10 100 1000 0 10,000 1 2 3 5 4 6 TEMPERATURE (°C) RESET COMPARATOR OVERDRIVE, VTH-VCC (mV) VCC (V) CE IN TO CE OUT PROPAGATION DELAY vs. TEMPERATURE MAX817/MAX819 PFI THRESHOLD vs. TEMPERATURE MAX817/MAX819 PFI TO PFO PROPAGATION DELAY vs. TEMPERATURE 5 tPD- 4 3 tPD+ 1.250 1.248 1.246 2 1.244 1 1.242 0 0 20 40 60 TEMPERATURE (°C) 80 100 32 31 30 29 28 1.240 -20 MAX817/18/19-15 1.252 33 PROPAGATION DELAY (µs) 6 MAX817/18/19-14 1.254 MAX817/18/19-13 7 -40 6 1400 8 BATTERY SUPPLY CURRENT (µA) 4.6 1600 THRESHOLD (V) RESET THRESHOLD (V) MAX81_L MAXIMUM TRANSIENT DURATION (µs) MAX817/18/19-10 4.7 4.4 BATTERY SUPPLY CURRENT vs. SUPPLY VOLTAGE MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE RESET THRESHOLD vs. TEMPERATURE CE IN TO CE OUT PROPAGATION DELAY (ns) MAX817L/M, MAX818L/M, MAX819L/M* +5V Microprocessor Supervisory Circuits -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 -40 -20 0 20 40 60 TEMPERATURE (°C) _______________________________________________________________________________________ 80 100 +5V Microprocessor Supervisory Circuits PIN NAME FUNCTION MAX817 MAX818 MAX819 1 1 1 OUT Supply Output for CMOS RAM. When VCC rises above the reset threshold or above VBATT, OUT is connected to VCC through an internal P-channel MOSFET switch. When VCC falls below VBATT, BATT connects to OUT. 2 2 2 VCC Input Supply Voltage, +5V input. 3 3 3 GND Ground. 0V reference for all signals. 4 — 4 PFI — 4 — CE IN 5 — 6 — — 5 6 — 5 — — 6 Power-Fail Comparator Input. When VPFI is below VPFT or when VCC is below VBATT, PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator section). Connect to ground if unused. Chip-Enable Input. The input to the chip-enable gating circuit. Connect to ground if unused. PFO Power-Fail Comparator Output. When PFI is less than VPFT or when VCC is below VBATT, PFO goes low; otherwise PFO remains high. PFO is also used to enable the battery freshness seal (see Battery Freshness Seal and Power-Fail Comparator sections). CE OUT Chip-Enable Output. CE OUT goes low only if CE IN is low while reset is not asserted. If CE IN is low when reset is asserted, CE OUT will remain low for 15µs or until CE IN goes high, whichever occurs first. CE OUT is pulled up to OUT in battery-backup mode. CE OUT is also used to enable the battery freshness seal (see Battery Freshness Seal section). WDI Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and a reset is triggered. If WDI is left unconnected or is connected to a high-impedance three-state buffer, the watchdog feature is disabled. The internal watchdog timer clears whenever reset is asserted, WDI is three-stated, or WDI sees a rising or falling edge. The WDI input is designed to be driven by a three-statedoutput device with a maximum high-impedance leakage current of 10µA and a maximum output capacitance of 200pF. The output device must also be capable of sinking and sourcing 200µA when active. MR Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted for as long as MR is held low and for 200ms after MR returns high. The activelow input has an internal 63kΩ pull-up resistor. It can be driven from a TTL- or CMOS-logic line or shorted to ground with a switch. Leave open, or connect to VCC if unused. 7 7 7 RESET Active-Low Reset Output. Pulses low for 200ms when triggered and remains low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for 200ms after VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes low to high. 8 8 8 BATT Backup-Battery Input. When VCC falls below VBATT, OUT switches from VCC to BATT. When VCC rises above VBATT, OUT reconnects to VCC. _______________________________________________________________________________________ 7 MAX817L/M, MAX818L/M, MAX819L/M* ______________________________________________________________Pin Description MAX817L/M, MAX818L/M, MAX819L/M* +5V Microprocessor Supervisory Circuits BATT OUT BATTERY SWITCHOVER CIRCUITRY VCC MAX817 MAX818 MAX819 RESET GENERATOR RESET 1.25V THIS PIN FOR MAX819 ONLY. MR BATTERY FRESHNESS SEAL CIRCUITRY WATCHDOG TIMER WDI THIS SECTION FOR MAX817/ MAX818 ONLY. THIS SECTION PFI FOR MAX817/ MAX819 ONLY. PFO 1.25V CHIP-ENABLE OUTPUT CONTROL THIS SECTION FOR MAX818 ONLY. CE IN CE OUT GND Figure 1. Functional Diagram 8 _______________________________________________________________________________________ +5V Microprocessor Supervisory Circuits General Timing Characteristics Designed for 5V systems, the MAX817/MAX818/ MAX819 provide a number of microprocessor (µP) supervisory functions (see the Selector Guide on the first page). Figure 2 shows the typical timing relationships of the various outputs during power-up and power-down with typical VCC rise and fall times. RESET Output A µP’s reset input starts the µP in a known state. The MAX817/MAX818/MAX819 µP supervisory circuits assert a reset to prevent code-execution errors during power-up, power-down, and brownout conditions. RESET is guaranteed to be a logic low for 0V < VCC < VRST if VBATT is greater than 1V. Without a backup battery (V BATT = GND) RESET is guaranteed valid for VCC ≥ 1V. Once VCC exceeds the reset threshold an internal timer keeps RESET low for the reset timeout period, t RP . After this interval RESET returns high (Figure 2). If a brownout condition occurs (VCC drops below the reset threshold), RESET goes low. Each time RESET is asserted it stays low for at least the reset timeout period. Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. RESET both sources and sinks current. Manual Reset Input (MAX819) Many µP-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. On the MAX819, a logic low on MR asserts reset. Reset remains asserted while MR is low, and for tRP (200ms) after it returns high. During the reset timeout period (t RP), MR’s state is ignored if the battery freshness seal is enabled. MR has an internal 63kΩ pull-up resistor, so it can be left open if not used. This input can be driven with TTL/CMOSlogic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. Note that MR must be high or open to enable the battery freshness seal. Once the battery freshness seal is enabled its operation is unaffected by MR. Battery Freshness Seal The MAX817/MAX818/MAX819 battery freshness seal disconnects the backup battery from internal circuitry and OUT until it is needed. This allows an OEM to ensure that the backup battery connected to BATT will be fresh when the final product is put to use. To enable the freshness seal on the MAX817 and MAX819: 1) Connect a battery to BATT. 2) Ground PFO. 3) Bring V CC above the reset threshold and hold it there until reset is deasserted following the reset timeout period. 4) Bring VCC down again (Figure 3). Use the same procedure for the MAX818, but ground CE OUT instead of PFO. Once the battery freshness seal is enabled (disconnecting the backup battery from internal circuitry and anything connected to OUT), it remains enabled until VCC is brought above VRST. VBATT VOUT VRST VRST VRST VCC VRST VBATT VCC VBATT tRP VRESET PFO FOLLOWS PFI VPFO* VCE OUT** VBATT CE OUT FOLLOWS CE IN *MAX817/MAX819 ONLY. ** MAX818 ONLY. Figure 2. Power-Up and Power-Down Timing RESET TO CE OUT DELAY** RESET tRP CE OUT (MAX818) (EXTERNALLY HELD AT 0V) CE OUT STATE LATCHED AT 1/2 tRP AND 3/4 tRP, FRESHNESS SEAL ENABLED PFO (MAX817/MAX819) (EXTERNALLY HELD AT 0V) PFO STATE LATCHED AT 1/2 tRP AND 3/4 tRP, FRESHNESS SEAL ENABLED Figure 3. Battery Freshness Seal Timing _______________________________________________________________________________________ 9 MAX817L/M, MAX818L/M, MAX819L/M* _______________Detailed Description MAX817L/M, MAX818L/M, MAX819L/M* +5V Microprocessor Supervisory Circuits On the MAX819, MR must be high or open to enable the battery freshness seal. Once the battery freshness seal is enabled its operation is unaffected by MR. Watchdog Input (MAX817/MAX818) In the MAX817/MAX818, the watchdog circuit monitors the µP’s activity. If the µP does not toggle the watchdog input (WDI) within tWD (1.6sec), reset asserts. The internal 1.6sec timer is cleared by either a reset pulse or by toggling WDI, which can detect pulses as short as 50ns. The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting (Figure 4). To disable the watchdog function, leave WDI unconnected or three-state the driver connected to WDI. The watchdog input is internally driven low during the first 7/8 of the watchdog timeout period, then momentarily pulses high, resetting the watchdog counter. When WDI is left open-circuited, this internal driver clears the 1.6sec timer every 1.4sec. When WDI is three-stated or left unconnected, the maximum allowable leakage current is 10µA and the maximum allowable load capacitance is 200pF. VCC tRP tWD RESET WDI Figure 4. Watchdog Timing BATTERY SWITCHOVER CIRCUITRY MAX817 MAX818 BATTERY FRESHNESS SEAL CIRCUITRY RESET GENERATOR Chip-Enable Gating (MAX818) Internal gating of the chip-enable (CE) signal prevents erroneous data from corrupting CMOS RAM in the event of an undervoltage condition. The MAX818 uses a series transmission gate from CE IN to CE OUT (Figure 5). During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short CE propagation delay from CE IN to CE OUT enables the MAX818 to be used with most µPs. If CE IN is low when reset asserts, CE OUT remains low for typically 15µs to permit the current write cycle to complete. OUT CHIP-ENABLE OUTPUT CONTROL P CE IN CE OUT N Figure 5. Chip-Enable Transmission Gate Chip-Enable Input (MAX818) The CE transmission gate is disabled and CE IN is high impedance (disabled mode) while reset is asserted. During a power-down sequence when VCC passes the reset threshold, the CE transmission gate disables and CE IN immediately becomes high impedance if the voltage at CE IN is high. If CE IN is low when reset asserts, the CE transmission gate will disable 15µs after reset asserts (Figure 6). This permits the current write cycle to complete during power-down. VRST VRST VRST VCC VCE OUT VBATT VBATT tRP 15µs tRP VRESET VCE IN Figure 6. Chip-Enable Timing 10 ______________________________________________________________________________________ VRST +5V Microprocessor Supervisory Circuits Chip-Enable Output (MAX818) When the CE transmission gate is enabled, the impedance of CE OUT is equivalent to a 40Ω resistor in series with the source driving CE IN. In the disabled mode, the transmission gate is off and an active pull-up connects CE OUT to OUT (Figure 5). This pull-up turns off when the transmission gate is enabled. +5V Power-Fail Comparator (MAX817/MAX819) The MAX817/MAX819 PFI input is compared to an internal reference. If PFI is less than the power-fail threshold (VPFT), PFO goes low. The power-fail comparator is intended for use as an undervoltage detector to signal a failing power supply (Figure 8). However, the comparator does not need to be dedicated to this function because it is completely separate from the rest of the circuitry. The power-fail comparator turns off and PFO goes low when VCC falls below VBATT. During the reset timeout period (tRP), PFO is forced high, regardless of the state of VPFI (see Battery Freshness Seal section). If the comparator is unused, connect PFI to ground and leave PFO unconnected. PFO can be connected to MR on the MAX819 so that a low voltage on PFI will generate a reset (Figure 9). In this configuration, when the monitored voltage causes PFI to fall below VPFT, PFO pulls MR low, causing a reset to be asserted. Reset remains asserted as long as PFO holds MR low, and for tRP (200ms) after PFO pulls MR high when the monitored supply is above the programmed threshold. When PFO is connected to MR, it is not possible to enable the battery freshness seal. Enabling the battery freshness seal requires MR to be high or open. Once the battery freshness seal is enabled, it is no longer affected by PFO’s connection to MR. VIN +5V REGULATOR POWER-FAIL-WARNING TRIP VOLTAGE R1 + R2 VWARN = 1.25 R2 VCC ( BATT VCC MAX818 CE IN 50Ω 50Ω ) MAX817 MAX819 R1 CE OUT RESET RESET PFI GND 50pF C L* PFO NMI µP R2 1.25V * CL INCLUDES LOAD CAPACITANCE, STRAY CAPACITANCE, AND SCOPE-PROBE CAPACITANCE. Figure 7. CE Propagation Delay Test Circuit Figure 8. Using the Power-Fail Comparator to Generate a Power-Fail Warning ______________________________________________________________________________________ 11 MAX817L/M, MAX818L/M, MAX819L/M* Any time a reset is generated, the CE transmission gate remains disabled and CE IN remains high impedance (regardless of CE IN activity) for the reset timeout period. When the CE transmission gate is enabled, the impedance of CE IN appears as a 40Ω resistor in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on VCC, the source impedance of the drive connected to CE IN, and the loading on CE OUT (see Typical Operating Characteristics). The CE propagation delay is production tested from the 50% point on CE IN to the 50% point on CE OUT using a 50Ω driver and a 50pF load capacitance (Figure 7). For minimum propagation delay, minimize the capacitive load at CE OUT and use a low-output-impedance driver. MAX817L/M, MAX818L/M, MAX819L/M* +5V Microprocessor Supervisory Circuits Backup-Battery Switchover In a brownout or power failure, it may be necessary to preserve the contents of RAM. With a backup battery installed at BATT, the MAX817/MAX818/MAX819 automatically switch RAM to backup power when VCC falls. These devices require two conditions before switching to battery-backup mode: 1) VCC must be below the reset threshold, and 2) V CC must be below V BATT . Table 1 lists the status of the inputs and outputs in battery-backup mode. As long as VCC exceeds the reset threshold, OUT connects to VCC through a 5Ω PMOS power switch. Once V CC falls below the reset threshold, V CC or V BATT (whichever is higher) switches to OUT. When VCC falls below VRST and VBATT, BATT switches to OUT through an 80Ω switch. When VCC exceeds the reset threshold, it is connected to the substrate, regardless of the voltage applied to BATT (Figure 10). During this time, the diode (D1) between BATT and the substrate will conduct current from BATT to VCC if VBATT is 0.6V greater than VCC. When BATT connects to OUT, backup mode is activated and the internal circuitry is powered from the battery (Table 1). When VCC is just below VBATT, the current draw from BATT is typically 6µA. When VCC drops to more than 1V below VBATT, the internal switchover comparator shuts off and the supply current falls to less than 1µA. __________Applications Information The MAX817/MAX818/MAX819 are protected for typical short-circuit conditions of 10sec or less. Shorting OUT to ground for longer than 10sec destroys the device. Decouple VCC, OUT, and BATT to ground by placing 0.1µF capacitors as close to the device as possible. Table 1. Input and Output Status in Battery-Backup Mode SIGNAL STATUS BATT VCC Disconnected from VOUT. VOUT Connected to VBATT through an internal 80Ω PMOS switch. VBATT Connected to VOUT. Current drawn from the battery is less than 1µA, as long as VCC < VBATT - 0.2V. V R ESET VWDI VCC SW2 SW1 D1 D2 SW3 SW4 SUBSTRATE Logic low Watchdog timer is disabled. V C E OUT V C E IN Logic high. The open-circuit voltage is equal to VOUT. High impedance D3 MAX817 MAX818 MAX819 OUT V1 ADDITIONAL SUPPLY RESET VOLTAGE R1 + R2 V2 (RESET) = 1.25 R2 ( VCC V2 MAX819 R1 RESET PFI R2 ) RESET MR PFO µP SW1/SW2 SW3/SW4 VCC > Reset Threshold Open Closed VCC < Reset Threshold and VCC > VBATT Open Closed VCC < Reset Threshold and VCC < VBATT Closed Open CONDITION RESET THRESHOLD = 4.65V IN MAX81_L RESET THRESHOLD = 4.4V IN MAX81_M Figure 9. Monitoring an Additional Supply by Connecting PFO to MR. 12 Figure 10. Backup-Battery-Switchover Block Diagram ______________________________________________________________________________________ +5V Microprocessor Supervisory Circuits Using a SuperCap™ as a Backup Power Source SuperCaps are capacitors with extremely high capacitance values (on the order of 0.47F) for their size. Since BATT has the same operating voltage range as VCC, and the battery switchover threshold voltages are typically ±30mV centered at V BATT, a SuperCap and simple charging circuit can be used as a backup power source. Figure 11 shows a SuperCap used as a backup source. If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to OUT and VCC from BATT until the voltage at BATT is less than 0.5V above VCC. For example, if a SuperCap is connected to BATT through a diode to VCC, and VCC quickly changes from 5.4V to 4.9V, the capacitor discharges through OUT and VCC until VBATT reaches 5.1V typical. Leakage current through the SuperCap charging diode and the internal power diode eventually discharges the SuperCap to VCC. Also, if VCC and VBATT start from 0.1V above the reset threshold and power is lost at VCC, the SuperCap on BATT discharges through VCC until VBATT reaches the reset threshold. Battery-backup mode is then initiated and the current through V CC goes to zero. Operation Without a Backup Power Source The MAX817/MAX818/MAX819 were designed for battery-backed applications. If a backup battery is not used, connect V CC to OUT, and connect BATT to ground. Replacing the Backup Battery The backup power source can be removed while VCC remains valid, without danger of triggering a reset pulse, if BATT is decoupled with a 0.1µF capacitor to ground. As long as VCC stays above the reset threshold, battery-backup mode cannot be entered. Adding Hysteresis to the Power-Fail Comparator (MAX817/MAX819) The power-fail comparator has a typical input hysteresis of 4mV. This is sufficient for most applications where a power-supply line is being monitored through an external voltage divider (see Monitoring an Additional Supply). For additional noise margin, connect a resistor between PFO and PFI, as shown in Figure 12. Select the ratio of R1 and R2 such that PFI sees VPFT when VIN falls to the +5V VIN VCC R1 PFI R2 MAX817 MAX819 R3 +5V C1* PFO OUT VCC BATT MAX817 MAX818 MAX819 RESET GND TO STATIC RAM TO µP TO µP +5V PFO 0V 100k 0.1F GND 0V SuperCap is a trademark of Baknor Industries. VL R2 VTRIP = 1.25V R1 + R2 ( VH = 1.25V Figure 11. Using a SuperCap™ as a Backup Power Source with a +5V ±10% Supply *OPTIONAL ( ) R2 || R3 R1 + R2 || R3 VL - 1.25 5 - 1.25 = + R1 R3 VTRIP VIN VH ) 1.25 R2 Figure 12. Adding Hysteresis to the Power-Fail Comparator ______________________________________________________________________________________ 13 MAX817L/M, MAX818L/M, MAX819L/M* Watchdog Input Current The MAX817/MAX818 WDI inputs are internally driven through a buffer and series resistor from the watchdog counter (Figure 1). When WDI is left unconnected, the watchdog timer is serviced within the watchdog timeout period by a low-high-low pulse from the counter chain. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog timeout period, pulsing it low-high-low once within 7/8 of the watchdog timeout period to reset the watchdog timer. If instead WDI is externally driven high for the majority of the timeout period, up to 150µA can flow into WDI. MAX817L/M, MAX818L/M, MAX819L/M* +5V Microprocessor Supervisory Circuits desired trip point (VTRIP). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1µA to ensure that the 25nA (max) PFI input leakage current does not shift the trip point. R3 should be larger than 200kΩ to prevent it from loading down the PFO pin. Capacitor C1 adds additional noise rejection. +5V VCC R1 MAX817 MAX819 PFI PFO R2 Monitoring an Additional Supply (MAX817/MAX819) The MAX817/MAX819 µP supervisors can monitor either positive or negative supplies using a resistor voltage divider to PFI. PFO can be used to generate an interrupt to the µP or to trigger a reset (Figures 9 and 13). GND V+5V Interfacing to µPs with Bidirectional Reset Pins µPs with bidirectional reset pins, such as the Motorola 68HC11 series, can contend with the MAX817/MAX818/ MAX819 RESET output. If, for example, the RESET output is driven high and the µP wants to pull it low, indeterminate logic levels may result. To correct this, connect a 4.7kΩ resistor between the RESET output and the µP reset I/O, as in Figure 14. Buffer the RESET output to other system components. PFO 0V VTRIP 0V V5 - 1.25 1.25 - VTRIP = R1 R2 NOTE: VTRIP IS NEGATIVE Figure 13. Monitoring a Negative Voltage Negative-Going VCC Transients These supervisors are relatively immune to short-duration, negative-going V CC transients (glitches) while issuing a reset to the µP during power-up, power-down, and brownout conditions. Therefore, resetting the µP when VCC experiences only small glitches is usually not desirable. The Typical Operating Characteristics show a graph of Maximum Transient Duration vs. Reset Threshold Overdrive for which reset pulses are not generated. The graph was produced using negative-going VCC pulses, starting at 3.3V and ending below the reset threshold by the magnitude indicated (reset threshold overdrive). The graph shows the maximum pulse width that a negativegoing VCC transient can typically have without triggering a reset pulse. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 135µs will not trigger a reset pulse. A 0.1µF bypass capacitor mounted close to the VCC pin provides additional transient immunity. BUFFERED RESET TO OTHER SYSTEM COMPONENTS VCC VCC MAX817 MAX818 MAX819 RESET 4.7k RESET GND GND Figure 14. Interfacing to µPs with Bidirectional Reset I/O 14 ______________________________________________________________________________________ +5V Microprocessor Supervisory Circuits To help the watchdog timer monitor software execution more closely, set and reset the watchdog input at different points in the program, rather than “pulsing” the watchdog input high-low-high or low-high-low. This technique avoids a “stuck” loop, in which the watchdog timer would continue to be reset within the loop, keeping the watchdog from timing out. Figure 15 shows an example of a flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should “hang” in any subroutine, the problem would quickly be corrected, since the I/O is continually set low and the watchdog timer is allowed to time out, triggering a reset or an interrupt. As described in the Watchdog Input Current section, this scheme results in higher average WDI input current than does the method of leaving WDI low for the majority of the timeout period and periodically pulsing it low-high-low. __________Typical Operating Circuit START SET WDI LOW SUBROUTINE OR PROGRAM LOOP, SET WDI HIGH RETURN END Figure 15. Watchdog Flow Diagram ____Pin Configurations (continued) TOP VIEW +5V VCC BATT 0.1µF REALTIME CLOCK CMOS RAM 0.1µF OUT 1 8 BATT 7 RESET GND 3 6 WDI CE IN 4 5 CE OUT 8 BATT 7 RESET GND 3 6 MR PFI 4 5 PFO VCC 2 MAX818 OUT MAX817 MAX818 MAX819 0.1µF DIP/SO/µMAX A0–A15 RESET RESET WDI** I/O µP CE IN* CE OUT* GND *CE IN AND CE OUT APPLY TO MAX818 ONLY. **WDI APPLIES TO MAX817/MAX818 ONLY. ADDRESS DECODE OUT 1 VCC 2 MAX819 DIP/SO/µMAX ______________________________________________________________________________________ 15 MAX817L/M, MAX818L/M, MAX819L/M* Watchdog Software Considerations (MAX817/MAX818) MAX817L/M, MAX818L/M, MAX819L/M* +5V Microprocessor Supervisory Circuits Ordering Information (continued) PART† TEMP. RANGE PIN-PACKAGE MAX817_EPA -40°C to +85°C 8 Plastic DIP MAX817_ESA MAX818_CPA MAX818_CSA -40°C to +85°C 0°C to +70°C 0°C to +70°C 8 SO 8 Plastic DIP 8 SO MAX818_CUA MAX818_EPA MAX818_ESA MAX819_CPA 0°C to +70°C -40°C to +85°C -40°C to +85°C 0°C to +70°C 8 µMAX 8 Plastic DIP 8 SO 8 Plastic DIP MAX819_CSA MAX819_CUA MAX819_EPA MAX819_ESA 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C 8 SO 8 µMAX 8 Plastic DIP 8 SO Chip Information TRANSISTOR COUNT: 719 †These parts offer a choice of reset threshold voltage. From the table below, select the suffix corresponding to the desired threshold and insert it into the blank to complete the part number. SUFFIX RESET THRESHOLD (V) L 4.65 M 4.40 ________________________________________________________Package Information DIM C α A 0.101mm 0.004 in e B A1 L A A1 B C D E e H L α INCHES MAX MIN 0.044 0.036 0.008 0.004 0.014 0.010 0.007 0.005 0.120 0.116 0.120 0.116 0.0256 0.198 0.188 0.026 0.016 6° 0° MILLIMETERS MIN MAX 0.91 1.11 0.10 0.20 0.25 0.36 0.13 0.18 2.95 3.05 2.95 3.05 0.65 4.78 5.03 0.41 0.66 0° 6° 21-0036D E H 8-PIN µMAX MICROMAX SMALL-OUTLINE PACKAGE D Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.