MICRONAS DDP3310B

ADVANCE INFORMATION
MICRONAS
Edition July 9, 1999
6251-464-1AI
DDP 3310B
Display and Deflection
Processor
MICRONAS
DDP 3310B
ADVANCE INFORMATION
Contents
Page
Section
Title
4
4
5
5
1.
1.1.
1.2.
1.3.
Introduction
Main Features
System Architecture
System Application
6
6
6
6
6
7
8
8
9
9
9
10
10
12
12
12
13
13
15
16
16
16
17
18
18
18
19
19
19
20
20
20
20
2.
2.1.
2.1.1.
2.1.2.
2.1.3.
2.1.4.
2.1.5.
2.1.6.
2.1.7.
2.1.8.
2.1.9.
2.1.10.
2.1.11.
2.2.
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.3.
2.3.1.
2.3.2.
2.3.3.
2.3.4.
2.3.5.
2.3.6.
2.3.7.
2.3.8.
2.3.9.
2.3.10.
2.3.11.
2.3.12.
2.3.13.
Functional Description
Display Part
Input Interface
Horizontal Scaler
Luma Processing
Dynamic Peaking
Soft Limiter
Chroma Input
Chroma Interpolation
Chroma Transient Improvement
Inverse Matrix and Digital RGB Processing
Picture Frame Generator
Scan Velocity Modulation
Analog Back-End
Analog RGB Insertion
Half-Contrast Control
Fast-Blank Monitor
CRT Measurement and Control
Average Beam Current Limiter
Synchronization and Deflection
Deflection Processing
Security Unit for H-Drive
Soft Start/Stop of Horizontal Drive
Horizontal Phase Adjustment
Vertical Synchronization
Vertical and East/West Deflection
Vertical Zoom
EHT Compensation
Protection Circuitry
Display Frequency Doubling
General-purpose D/A Converter
Clock and Reset
Reset and Power-On
21
21
21
22
34
3.
3.1.
3.2.
3.3.
3.3.1.
Serial Interface
I2C-Bus Interface
I2C Control and Status Registers
XDFP Control and Status Registers
Scaler Adjustment
2
Micronas
ADVANCE INFORMATION
DDP 3310B
Contents, continued
Page
Section
Title
35
35
35
38
41
42
44
44
44
45
45
45
46
46
47
47
48
49
49
49
50
50
50
51
51
51
52
53
56
56
4.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.6.1.
4.6.2.
4.6.3.
4.6.4.
4.6.4.1.
4.6.4.2.
4.6.4.3.
4.6.4.4.
4.6.4.5.
4.6.4.6.
4.6.4.7.
4.6.4.8.
4.6.4.9.
4.6.4.10.
4.6.4.11.
4.6.4.12.
4.6.4.13.
4.6.4.14.
4.6.4.15.
4.6.4.16.
4.6.4.17.
4.6.4.18.
4.6.4.19.
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Description
Pin Configuration
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Recommended Crystal Characteristics
Characteristics
General Characteristics
Line-locked Clock Inputs: LLC1, LLC2
Luma, Chroma Inputs
Reset Input, Test Input
Half-Contrast Input
I2C-Bus Interface
Horizontal and Vertical Sync Inputs and Clock and Freqency Select Pins
Horizontal Flyback Input
FIFO Control Signals
PWM Outputs
Horizontal Drive Output
Vertical Protection Input
Horizontal Safety Input
Vertical and East/West D/A Converter Output
Sense A/D Converter Input
Analog RGB and Fast-Blank Inputs
Analog RGB Outputs, D/A Converters
Scan Velocity Modulation Output
DAC Reference, Beam Current Safety
57
5.
Application Circuit
60
6.
Data Sheet History
Micronas
3
DDP 3310B
ADVANCE INFORMATION
Deflection processing
Display and Deflection Processor
– scan velocity modulation output
1. Introduction
– high-performance H/V deflection
The DDP 3310B is a single-chip digital Display and
Deflection Processor designed for high-quality backend applications in 100/120-Hz TV sets with 4:3- or
16:9 picture tubes. The IC can be combined with members of the DIGIT 3000 IC family (VPC 32xx,
TPU 3040), or it can be used with third-party products.
The IC contains the entire digital video component and
deflection processing and all analog interface components.
– EHT compensation for vertical / East/West
– soft start/stop of H-Drive
– vertical angle and bow
– differential vertical output
– vertical zoom via deflection
– horizontal and vertical protection circuit
1.1. Main Features
– adjustable horizontal frequency for VGA/SVGA display
Video processing
Miscellaneous
– linear horizontal scaling (0.25 … 4)
– selectable 4:1:1/4:2:2 YCrCb input
– selectable 27/32-MHz line-locked clock input
– non-linear horizontal scaling “panoramavision”
– crystal oscillator for horizontal protection
– dynamic peaking
– automatic picture tube adjustment (cutoff, whitedrive)
– soft limiter (gamma correction)
– color transient improvement
– single 5-V power supply
– programmable RGB matrix
– picture frame generator
– hardware for simple 50/60-Hz to 100/120-Hz conversion (display frequency doubling)
– two analog RGB/Fast-Blank inputs
– two I2C-controlled PWM outputs
– beam current limiter
YCrCb
4:2:2/4:1:1
Horizontal
Scaler
Line-locked
Clock
27/32 MHz
Clock
Gen.
SDA/SCL
I2C
Interface
Y Features
C Features
Digital
RGB
Matrix
3 x DAC
(10 Bit)
Tube Control
Picture
Frame
Generator
PWM
PWM
1&2
Measurement
ADC
Sense
Input
Analog
RGB
Switch
Scan
Velocity
Modulation
H/V
Deflection
Security
Unit
2H / 2V
(1H/1V)
DACs
Display
Frequency
Doubling
RGB
Out
2xRGB/FB
In
SVM
HDrive
V & E/W
FIFO
Controlling
HFlyback
Fig. 1–1: Block diagram of the DDP 3310B
4
Micronas
DDP 3310B
ADVANCE INFORMATION
– Europe: 15 kHz/ 50 Hz → 32 kHz/100 Hz interlaced
– US: 15 kHz/60 Hz → 31 kHz/120 Hz non-interlaced
VPC 32xxD
RGB
CVBS
VPC
32xx
CIP
3250A
IP
DDP
3310B
✔
✔
✔
✔
✔
✔
✔
IP
Note: The DDP 3310B and the VPC 32xx families
support memory-based applications through linelocked clocks, syncs, and data. The CIP 3250A may
run either with the native DIGIT3000 clock but also
with a line-locked clock system.
Scan Velocity Modulation
The VPC 32xx family processes all worldwide analog
video signals (including the European PALplus) and
allows non-linear Panorama aspect ratio conversion.
Thus, 4:3 and 16:9 systems can easily be configured
by software. The aspect ratio scaling is also used as a
sample rate converter to provide a line-locked digital
component output bus (YCrCb) compliant to ITU-R-601.
All video processing and line-locked clock/data gener-
Examples:
Fast Blank Mixing
Fig. 1–2 depicts several DDP applications. Since the
DDP functions as a video back-end, it must be complemented with additional functionality to form a complete
TV set.
The IP indicates memory-based image processing,
such as scan rate conversion, vertical processing
(Zoom), or PAL+ reconstruction.
RGB Saturation
1.3. System Application
The VPC 32xxD and the CIP 3250A provide a highquality analog RGB interface with character insertion
capability. This allows appropriate processing of external sources such as MPEG 2 set-top boxes in transparent (4:2:2) quality. Furthermore, it translates RGB/
Fast-Blank signals to the common digital video bus
and makes those signals available for 100-Hz processing. In some European countries (Italy), this feature is
mandatory.
16:9 Video
The DDP 3310B is a mixed-signal IC containing the
entire digital video component processing such as
chroma transient improvement (CTI), adaptive luma
peaking, and a non-linear ‘Panorama’ aspect ratio conversion. All deflection related signals can be adapted
to different scan rates. The analog section contains all
analog interface components and an ADC, to compensate long term changes of the picture tube parameters
and extreme high-tension effects. Fig. 1–1 shows the
block diagram of the single-chip Display and Deflection
Processor.
ation is derived from a single 20.25-MHz crystal. An
optional adaptive 2H/4H comb filter (VPC 32xx) performs Y/C separation for PAL and NTSC and all of their
substandards.
Comb Filter
1.2. System Architecture
PAL+
100 Hz
H/V
Defl.
RGB
RGB
CVBS
VPC
32xx
FIFO
DDP
3310B
✔
H/V
Defl.
Fig. 1–2: DDP 3310B applications
Micronas
5
DDP 3310B
ADVANCE INFORMATION
2. Functional Description
2.1.2. Horizontal Scaler
2.1. Display Part
The scaler block allows linear or non-linear horizontal
scaling of the digital input video signal in the range of
0.25 to 4. Non-linear scaling, also called “panorama
vision”, provides a geometrical distortion of the input
picture. It is used to fit a picture with 4:3 format on a
16:9 screen by stretching the picture geometry at the
borders. The inverse effect can be produced by the
scaler, also. The scaler consists of a programmable
decimation and interpolation filter and a 1/2H FIFO
memory.
The display part converts the digital YCrCb to analog
RGB (see Fig. 2–7) and provides contrast and saturation adjustment. In case of YCrCb 4:1:1 an interpolation filter is used, which converts the digital input signal
to YCrCb 4:2:2 standard. The 4:2:2 YCrCb signal is
processed by the horizontal scaler. In the luminance
processing path, a variety of features, such as
dynamic peaking and soft limiting, are provided. In the
chrominance path, the CrCb signals are converted to
4:4:4 format and filtered by a color transient improvement circuit. The YCrCb signal is converted by a programmable matrix to RGB color space.
A summary of scaler modes is given in Table 2–1.
Table 2–1: Scaler modes
2.1.1. Input Interface
The data inputs Y0…Y7 and C0…C7 are clocked with
the external clock LLC2. The clock frequency is selectable for 27 or 32 MHz. A clock generator converts the
different external line-locked clock rates to a common
internal sample rate of appr. 40.5 MHz in order to provide a fix bandwidth for all digital filters. The horizontal
scaler is used for conversion of scan rate and non-linear aspect ratio. The horizontal sync puls at the HS pin
should be an active video signal, which is not vertically
blanked.
The input interface signals are
Mode
Scale
Factor
Description
Panorama
4:3 → 16:9
nonlinear
compr.
4:3 source displayed on
a16:9 tube,
borders distorted
Waterglass
16:9 → 4:3
nonlinear
zoom
Letterbox source (PAL+)
displayed on a 4:3 tube,
vertical overscan,
borders distorted,
no cropping
27 → 40.5 MHz
1.5
linear
sample rate conversion
from external to internal
pixel clock
32 → 40 MHz
1.25
linear
sample rate conversion
from external to internal
pixel clock
– external clock (LLC2)
– luma / chroma inputs (Y0…Y7 / C0…C7)
– horizontal sync (HS) / vertical sync (VS, VS2)
2.1.3. Luma Processing
The blacklevel of the input signal is assumed to be 16
(ITU-R standard). The luminance signal is multiplied
by a factor between 0 and 2 subdivided into 64 steps.
With a contrast adjustment of 32 (gain=1) the signal
can be shifted by ±100 % of its maximal amplitude with
the digital brightness value. This is for adjustment of
the headrooms for under- and overshoot. After the
brightness addition, the negative going signals are limited to zero. It is desirable to keep a small positive offset with the signal to prevent undershoots produced by
the peaking from being cut.
6
Micronas
DDP 3310B
ADVANCE INFORMATION
2.1.4. Dynamic Peaking
Especially with decoded composite signals and notch
filter luminance separation as input signals, it is necessary to improve the luminance frequency characteristics. With transparent high-bandwidth signals, it is
sometimes desirable to soften the image.
The center frequency of the peaking filter is selectable
from 2.5 MHz to 3.2 MHz. For S-VHS and for notch filter color decoding, the total system frequency
responses for both PAL and NTSC are shown in Fig.
2–1 and Fig. 2–2. (All frequencies refer to a 50/60-Hz
video signal).
In the DDP 3310B, the luma frequency response is
improved by “dynamic” peaking. It adapts to the amplitude and the frequency of the input signal. Small AC
amplitudes are sharpened while large AC amplitudes
remain nearly unmodified.
The dynamic range can be adjusted from −14 to
+14 dB for small high-frequency signals. There is separate adjustment for signal overshoot and for signal
undershoot. For large signals, the dynamic range is
limited by a non-linear function that does not create
any visible alias components. The peaking can be
switched over to “softening” by inverting the peaking
term by software.
dB
20
15
10
5
0
-5
-10
-15
-20
0
dB
8
10
MHz
dB
CF= 2.5 MHz
15
CF= 3.2 MHz
10
10
5
5
0
S-VHS
0
-5
-5
-10
-10
-15
-15
0
2
4
6
8
10
MHz
-20
dB
0
2
4
6
8
10
MHz
dB
20
20
CF= 3.2 MHz
15
CF= 2.5 MHz
15
10
10
5
5
PAL/SECAM
0
0
-5
-5
-10
-10
-15
-15
0
2
4
6
8
10
MHz
-20
0
2
4
6
8
10
MHz
dB
dB
20
20
CF= 3.2 MHz
15
CF= 2.5 MHz
15
10
10
5
5
0
NTSC
0
-5
-5
-10
-10
-15
-15
-20
6
20
15
-20
4
Fig. 2–1: Dynamic peaking frequency response
20
-20
2
0
2
4
6
8
10
MHz
-20
0
2
4
6
8
10
MHz
Fig. 2–2: Total frequency response for peaking filter and S-VHS, PAL, NTSC
Micronas
7
DDP 3310B
ADVANCE INFORMATION
2.1.5. Soft Limiter
Table 2–2: 4:1:1 Chroma format
The dynamic range of the processed luma signal must
be limited to prevent the CRT from overload. An appropriate headroom for contrast, peaking, and brightness
can be adjusted by the TV manufacturer according to
the CRT characteristics. All signals above this limit will
be “soft”-clipped. A characteristic diagram of the soft
limiter is shown in Fig. 2–3. The total limiter consists of
three parts:
Pin Name
Part A includes adjustable tilt point and gain. The gain
before the tilt value is 1. Above the tilt value, a part
(0…15/16) of the input signal is subtracted from the
input signal itself. Therefore, the gain is adjustable
from 16/16 to 1/16, when the slope value varies from 0
to 15. The tilt value can be adjusted from 0 to 511.
Part B has the same characteristics as part A. The
subtracting part is also relative to the input signal, so
the total differential gain will become negative if the
sum of slope A and slope B is greater than 16 and the
input signal is above the both tilt values (see characteristics).
Pixel Number
1
2
3
4
C7
Cb17
Cb15
Cb13
Cb11
C6
Cb16
Cb14
Cb12
Cb10
C5
Cr17
Cr15
Cr13
Cr11
C4
Cr16
Cr14
Cr12
Cr10
Note: Cxy; x = pixel number, y = bit number
Table 2–3: 4:2:2 Chroma format
Pin Name
Pixel Number
1
2
3
4
C7
Cb17
Cr17
Cb37
Cr37
C6
Cb16
Cr16
Cb36
Cr36
C5
Cb15
Cr15
Cb35
Cr35
2.1.6. Chroma Input
C4
Cb14
Cr14
Cb34
Cr34
The chroma input signal can either be YCrCb in 4:1:1
or in 4:2:2 format. For the digital signal processing, the
time-multiplexed chroma samples will be demultiplexed and synchronized with the signal at the HS pin.
The input formatter accepts either two’s complement
or binary offset code. Also, the delay can be adjusted
within a range of ±2 input clocks relative to the luma
signal; this doesn’t affect the chroma multiplex.
C3
Cb13
Cr13
Cb33
Cr33
C2
Cb12
Cr12
Cb32
Cr32
C1
Cb11
Cr11
Cb31
Cr31
C0
Cb10
Cr10
Cb30
Cr30
Finally, the output signal of the soft limiter will be
clipped by a hard limiter adjustable from 256 to 511.
Part A
Output
511
Note: Cxy; x = pixel number, y = bit number
Part B
Hard limiter
0
2
Slope A [0...15]
4
6
8
10
12
0
2
4
400
200
Y Input
Range= 256...511 Black Level
Contrast
14
Dig. Brightness
Peaking
Slope B [0...15]
6
8
10
12
14
300
Calculation example for the softlimiter input amplitude.
16...235 (ITU-R 601)
16 (constant)
63
20
off
Limiter input signal:
(Yin-black level) × CTM/32‘+BRM
100
Tilt A [ 0...511]
(235-16) × 63/32 + 20 = 451
Tilt B [0...511]
0
0
100
200
300
400
500
600
700
800
900
Limiter Input
1023
Fig. 2–3: Characteristics of soft limiter A and B and hard limiter
8
Micronas
DDP 3310B
ADVANCE INFORMATION
2.1.7. Chroma Interpolation
In case of YCrCb 4:1:1 input format, an interpolation filter is used which converts the digital input signal to
4:2:2 format. This filter runs with the incoming pixel
clock frequency.
0
dB
-10
-20
-30
The signal is passed to the scaler in YCrCb 4:2:2 format in order to convert the incoming pixel clock frequency (27/32 MHz) to the internal frequency (40.5/
40 MHz). A linear phase interpolator is used to convert
the chroma sampling rate from 4:2:2 to 4:4:4.
The frequency response of the interpolator is shown in
Fig. 2–4. All further processing is carried out at the full
sampling rate.
2.1.8. Chroma Transient Improvement
The intention of this block is to enhance the chroma
resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be selected according to the signal bandwidth,
e.g. for PAL/NTSC/SECAM or digital component signals, respectively. The amplitude of the correction signal is adjustable. Small noise amplitudes in the correction signal are suppressed by an adjustable coring
circuit. To eliminate “wrong colors”, which are caused
by over and undershoots at the chroma transition, the
sharpened chroma signals are limited to a proper
value automatically.
-40
-50
MHz
0
4
8
12
16
20
Fig. 2–4: Frequency response of the chroma 4:2:2 to
4:4:4 interpolation filter
a)
Cr Cb
input
t
b)
Ampl.
t
2.1.9. Inverse Matrix and Digital RGB Processing
c)
Six multipliers in parallel perform the matrix multiplication to transform the Cr and Cb signals to R−Y, B−Y,
and G−Y. The initialization values for the matrix are
computed from the standard ITU-R (CCIR) matrix:
R
1
0
1,402
Y
=
×
G
1 –0,345 – 0,713
Cb
B
1 1,773
0
Cr
The multipliers are also used to adjust color saturation
and picture contrast. Since the multiplier allows ±4 as
the biggest coefficient, it is possible that the product of
CTM × SATM × MxxM will be clipped, which causes
wrong colors. SATLIM limits the product of contrast
times saturation to allow a maximum oversaturation.
The matrix computes:
Cr out
Cb out
a) CrCb input of DTI
b) CrCb input + correction signal
c) sharpened and limited CrCb
t
Fig. 2–5: Digital color transient improvement
After adding the post-processed luma, the digital RGB
signals are limited to 10 bits. Three multipliers are
used to digitally adjust the white-drive and to implement an average beam current limiter. See also Section 2.2.4. “CRT Measurement and Control”.
R
MR1M MR2M
1
CTM
CTM
SATM
SATLIM


----×
=
MIN
×
× Cb +  ------------- × Y
---------------------------------------------×
,
G
MG1M
MG2M


64
32
 32
32 
32
Cr
B
MB1M MB2M
Micronas
9
DDP 3310B
ADVANCE INFORMATION
2.1.10. Picture Frame Generator
2.1.11. Scan Velocity Modulation
When the picture does not fill the total screen (height
or width too small) it is surrounded with black areas.
These areas (and more) can be colored with the picture frame generator. Another possibility is the insertion of a vertical and a horizontal stripe into the picture.
This is done by switching over the RGB signal from the
matrix to the signal from the frame color register.
Picture tubes equipped with an appropriate yoke can
use the Scan Velocity Modulation signal to vary the
speed of the electron gun during the entire video scan
line depending on its content. Transitions from dark to
bright will first speed up and then slow down the scan;
vice-versa for the opposite transition (see Fig. 2–6).
The width of each area (left, right, upper, lower) can be
adjusted separately. The generator starts on the right,
respectively lower side of the screen and stops on the
left, respectively upper side of the screen. This means,
it runs during horizontal, respectively vertical flyback.The color of the complete border can be stored in
a programmable frame color register. The format is
3×4 bit RGB. The contrast can be adjusted separately.
If the start value for the generator is larger than the
stop value, the picture frame is inserted at the borders.
If the start value is smaller than the stop value a vertical or horizontal stripe is inserted.
The digital RGB input signal for the SVM is converted
to Y in a simple matrix. Then the Y signal is differentiated by a filter of the transfer function 1−Z−N, where N
is programmable from 1 to 6. With a coring some noise
can be suppressed. This is followed by a gain adjustment and an adjustable limiter. The analog output signal is generated by an 8-bit D/A converter. The signal
delay can be adjusted by ±3.5 clocks in half-clock
steps in respect to the analog RGB output signals.
This is useful to adjust the different group delays of
analog RGB amplifiers to the one for the SVM yoke
current.
Ampl.
Beam
Current
SVM Yoke
Current
t
Fig. 2–6: SVM signal wave form
10
Micronas
Y
C rC b
4:2:2/4:1:1
Line-locked
Clock
27/32 MHz
FIFO
Read Ctrl
H/V
FIFO
Intpl.
4:2:2
FIFO
Scaler
1
FIFO
Scaler
1
FIFO
40.5/40.0 MHz
Contrast
Scaler
2
Intpl.
4:4:4
Peaking
Soft Limiter
Cr
Y
Cr
CTI
Cb
Cb
3×DAC
int. Bright.
×White-Drive
int. H/V
XDFP
– H-PLL2/3, flyback control
and soft start/stop
– vertical, E/W deflection
with EHT compensation
and vertical zoom
– beam current limiter
– cutoff & drive control loop
I2C
Interface
Clk
Security
H-Drive
Gen.
HDrive
H/V
Protection
H/V Prot.
H-Flyb.
Skew
H-Flyb
V, E/W
V & E/W
Sense
SVM
Picture
Frame
Gen.
R,G,B
DAC
cutoff
DAC
black
RGB
out
R,G,B
Measurement
ADC
DAC
R,G,B
3×DAC
ext. Bright.
×White-Drive
2×DAC
5 MHz
CLK
digital R,G,B
RGB
Matrix
Saturation
White-Dr.
× BCL
3×DAC
RGB
H&V
Timing
Display
Frequency
Doubling
Scan.
Vel. Mod.
dig. Bright.
Y
Scaler
2
digital/analog
Cock
Generator
FIFO
Write Ctrl
SDA/
SCL
27/32 MHz
ADVANCE INFORMATION
Micronas
13.5/16 MHz
3×DAC
ext. Contr.
×White-drive
×BCL
FBL
Prio
FBL1/2
in
Clamping
RGB1
in
Clamping
RGB2
in
RSW1&2
Fig. 2–7: Detailed block diagram of the DDP 3310B
DDP 3310B
11
DDP 3310B
2.2. Analog Back-End
The digital RGB signals are converted to analog RGB
using three video digital to analog converters (DAC)
with 10-bit resolution. The analog RGB-outputs are
current outputs with current-sink characteristics. The
maximum current drawn by the output stage is
obtained with peak white RGB.
Each RGB signal has two additional DAC’s with 9-bit
resolution to adjust analog brightness (40 % of the full
RGB range) and cutoff / black level (60 % of the full
RGB range). An additional fixed current is applied for
the blanking level.
In order to define accurate color on different CRT displays, you must exactly adjust what color the CRT
phosphorous produces to display the color on screen.
To have the same colors for the life of the display, a
build-in automatic tube control loop checks and adjusts
the black level on every field and white point every third
field.
The back-end allows insertion of two external analog
RGB signals. The RGB signals are key-clamped and
inserted into the main RGB by the Fast-Blank switch.
The external RGB signals can be adjusted independently as regarding DC-level (brightness) and magnitude (contrast). An external Half-Contrast signal can
be used to reduce the output current of the internal
RGB outputs to 50 %.
The controlling of the white-drive/analog brightness
and also the external contrast and brightness adjustments is done via the internal processor.
2.2.1. Analog RGB Insertion
The DDP 3310B allows insertion of two external analog RGB signals. Each RGB signal is key-clamped and
inserted into the main RGB by the Fast-Blank switch.
The selected external RGB input can be overlaid or
underlaid to the digital picture. The external RGB signals can be adjusted independently as regards DC
level (brightness) and magnitude (contrast).
It depends on the Fast-Blank input signals and the programming of a number of I2C-register settings which
analog RGB input is selected. Both Fast-Blank inputs
must be either active-Low or active-High.
All signals for analog RGB insertion (RIN1/2, GIN1/2,
BIN1/2, FBLIN1/2, HCS) must be synchronized to the
horizontal flyback, otherwise a horizontal jitter will be
visible. The DDP 3310B has no means for timing correction of the analog RGB input signals.
12
ADVANCE INFORMATION
Table 2–4: RGB Input Selection
I2C Settings
Input Signals
Analog
RGB Outputs
FBLIN1
FBLIN2
FBPOL
FBPRIO
0
0
0
x
Video
0
1
0
x
RGB input 2
1
0
0
x
RGB input 1
1
1
0
0
RGB input 1
1
1
0
1
RGB input 2
0
0
1
0
RGB input 1
0
0
1
1
RGB input 2
0
1
1
x
RGB input 1
1
0
1
x
RGB input 2
1
1
1
x
Video
Note: with following I2C settings
FBFOH1 = FBFOH2 = FBFOL1 = FBFOL2 = 0
2.2.2. Half-Contrast Control
Insertion of transparent text pages or OSD onto the
video picture is often difficult to read, especially if the
video contrast is high. The DDP 3310B allows contrast
reduction of the video background by means of a HalfContrast input (HCS pin). This input can be supplied
with a fast switching signal (similar to the Fast-Blank
input), typically defining a rectangular box in which the
video picture is displayed with reduced contrast. The
analog RGB inputs are still displayed with full contrast.
HCSPOL
HCS
#
HCSEN
HCS intern
HCSFOH
Fig. 2–8: Half-Contrast switch logic
Micronas
DDP 3310B
ADVANCE INFORMATION
2.2.3. Fast-Blank Monitor
2.2.4. CRT Measurement and Control
The presence of external analog RGB sources can be
detected by means of a Fast-Blank monitor. The status
of the selected Fast-Blank input can be monitored via
an I2C register. There is a 2-bit information, giving
static and dynamic indication of a Fast-Blank signal.
The static bit is directly reading the Fast-Blank input
line, whereas the dynamic bit is reading the status of a
flip flop triggered by the negative edge of the FastBlank signal.
The display processor is equipped with an 8/12-bit
PDM-ADC for all picture tube measuring purposes.
This MADC is connected to the SENSE input pin, the
input range is 0 to 1.6V.
With this monitor logic it is possible to detect if there is
an external RGB source active and if it is a full-screen
insertion or only a box. The monitor logic is connected
directly to the FBLIN1 or FBLIN2 pin. Selection is done
via I2C register.
FBFOH1
FBFOL1
FBPOL
#
FBLIN1
FastBlank
Monitor
FastBlank
Selection
FBLIN2
#
FBFOH2
FBPRIO
FBFOL2
FastBlank
int
Cutoff and white-drive current measurement are carried out with 8-bit resolution during the vertical blanking interval. The current range for cutoff measurement
is set by connecting the resistor R1 to the SENSE
input. Due to the fact of a 1:10 relation between cutoff
and white-drive current, the range select 2 output
(RSW2) becomes active for the white-drive measurement and connects R3 in parallel to R1, thus determining the correct current range. During the active picture,
the MADC is used for the average beam current limiter
with a 12-bit resolution. Again, a different measurement range is selected with active range select 1&2
outputs (RSW1&RSW2) connecting R2 in parallel to
R3 and R1. See Fig. 2–10 and Fig. 2–11 for the corresponding timing. These measurements are typically
done at the summation point of the picture tube cathode currents.
Another method uses two different current measurements. The range switch 1 pin (RSW1) can be used as
a second Sense input, selectable by software. In this
case, the cutoff and white-drive currents are measured
as before at the SENSE input. The active picture measurement can be done with the second Sense input
(RSW1). The signal may come (via a proper interface)
from the low end of the EHT coil (CRT anode current).
In this case, the resistor R2 in Fig. 2–10 has to be
removed.
FBMON
Fig. 2–9: Fast-Blank selection logic
Beam Current 2
Beam Current 1
SENSE
A
D
MADC
RSW1
R2
RSW2
R3
R1
Fig. 2–10: MADC range switch
Micronas
13
DDP 3310B
ADVANCE INFORMATION
The picture tube measurement returns results on
every field for:
– The automatic mode is selected by setting
CUT(WDR)_GAIN > 0 and CUT(WDR)_DIS = 0. In
this mode, the registers CUT(WDR)_R/G/B are
used as reference for the measured values (CUTOFF(WDRIVE)_R/G/B). Due to the 8-bit resolution
of the ADC, only 8 LSB can be used as reference
values. The calculated error is used with a small
hysteresis (1,5 %) to adjust cutoff and drive. The
higher the loop gain (CUT(WDR)_GAIN), the
smaller the time constant for the adjustment.
– cutoff R
– cutoff G
– cutoff B
– white-drive R or G or B (sequentially)
Thus, a cutoff control cycle for RGB requires one field
only while a complete white-drive control cycle
requires three fields. During cutoff and white-drive
measurement the average beam current limiter function (see Section 2.2.5.) is switched off. The amplitude
of the cutoff and white-drive measurement lines can be
programmed separately with IBRM and WDRM (see
Fig. 2–11). The start line for the tube measurement
(cutoff red) can be programmed via I2C-bus (TML).
– If the automatic mode was once enabled
(CUT(WDR)_GAIN > 0), the control loop can be
stopped by setting CUT(WDR)_DIS = 1. In this
mode, the calculated cutoff and drive values will no
longer be modified and the measurement lines are
suppressed. Changes of the reference values
(CUT(WDR)_R/G/B) have no effect.
If one of the calculated red, green, or blue white-drive
values exceeds its maximal possible value (WDR_R/
G/B>511), the white balance gets misadjusted. An
automatic drive saturation avoidance prevents from
this effect (WDR_SAT = 1) from occurring. If one drive
value exceeds the maximum allowed threshold
(MAX_WDR), the amplitude of the white-drive measurement line will be increased and decreased if one
of them goes below the fixed threshold 475.
The built-in control loop for cutoff and white-drive can
operate in three different modes selected by
CUT(WDR)_GAIN and CUT(WDR)_DIS.
– The user control mode is selected by setting
CUT(WDR)_GAIN = 0. In this mode the registers
CUT(WDR)_R/G/B are used as direct control values
for cutoff and drive using the whole 9-bit range. If
the
measurement
lines
are
enabled
(CUT(WDR)_DIS = 0) the user can read the measured cutoff & white drive values in the CUTOFF(WDRIVE)_R/G/B registers. An external software can now control the settings of the
CUT(WDR)_R/G/B registers.
CUT_R + IBRM + WDRM×WDR_R
CUT_R + IBRM
WhiteDrive
Cutoff
R
Black
R
ROUT
Ultra Black
CUT_G + IBRM
Cutoff
G
GOUT
CUT_B + IBRM
Cutoff
B
BOUT
Active
Resistors
Measurement
Lines
R1||R3
R1
R1||R2||R3
BCL
OFFSET
VBSO
CUTOFF
TML
R1||R2||R3
R1
WDR
BCL
VBST
Fig. 2–11: MADC measurement timing
14
Micronas
DDP 3310B
ADVANCE INFORMATION
2.2.5. Average Beam Current Limiter
The average beam current limiter (BCL) works on both
the digital YUV input and the inserted analog RGB signals by using either the sense input or the RSW1 input
for the beam current measurement. The BCL uses a
different filter to average the beam current during the
active picture resulting in a 12-bit resolution. The filter
bandwidth is approximately 4 kHz.
Beam Current
The beam current limiter allows the setting of a threshold current, a gain and an additional time constant. If
the beam current is above the threshold, the excess
current is low-pass filtered with the according gain and
time constant. The result is used to attenuate the RGB
outputs by adjusting the white-drive multipliers for the
internal (digital) RGB signals and the analog contrast
multipliers for the analog RGB inputs, respectively. The
lower limit of the attenuator is programmable, thus a
minimum contrast can always be set. If the minimum
contrast is reached, the brightness will be decreased
down to a programmable minimum as well. Typical
characteristics of the BCL for different loop gains are
shown in Fig. 2–12; for this example the tube has been
assumed to have square-law characteristics.
gain = 0 %
gain = 10 %
gain = 60 %
Threshold
gain = 90 %
Drive
Fig. 2–12: Beam current limiter characteristics:
beam current output vs. drive
Micronas
15
DDP 3310B
ADVANCE INFORMATION
2.3. Synchronization and Deflection
2.3.2. Security Unit for H-Drive
2.3.1. Deflection Processing
The security unit observes the H-Drive output signal
with an external 5-MHz reference clock. For different
horizontal frequencies the security unit uses different
ranges to control the H-Drive signal. Selecting a specific horizontal frequency via I2C-register HFREQ
automatically switches to the corresponding security
range. The control ranges are listed in Table 2–5.
The deflection processing generates the signals for the
horizontal and vertical drive (see Fig. 2–13). This block
contains two numeric phase-locked loops and a security unit:
– PLL2 generates the horizontal and vertical timing,
e.g. blanking, clamping, and sync signals. Phase
and frequency are synchronized by the incoming
sync signals.
The window of the control range has to fit into a main
control window which is selectable with the FREQSEL
input pin. With a Low signal at this pin, the main control
range is 28.8…34.4 µs and with a High signal, the
main control range is 25.6…29.2 µs. This is to prevent
malfunctions if the horizontal deflection stage is prepared for VGA frequencies.
– PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal output stage.
– The security unit observes the H-Drive output signal. With an external 5-MHz reference clock, this
unit controls the H-Drive “off time” and period. In
case of an incorrect H-Drive signal the security unit
generates a free-running H-Drive signal divided
down from the 5-MHz reference clock.
The Horizontal Drive Output can be forced to the High
level during Flyback. This means, the falling edge of
the drive pulse occurs at the earliest to the end of the
flyback pulse. This function can be enabled via the I2C
bus (EFLB).
The DDP 3310B is able to synchronize various horizontal frequencies, even VGA frequencies. Allowed
horizontal frequencies are listed in Table 2–5. The horizontal drive uses a high-voltage (8 V) open-drain output transistor.
H
Flyback
PLL3
Phase
Comparator
&
Low-Pass
FREQSEL
Horizontal
Drive
Generator
DCO
Security
Unit
H
Drive
FIFORWR
FIFOWR
Blanking, Clamping, etc.
FIFORRD
FIFORD
HSYNC
1H or 2H
VSYNC
1 V or 2 V
Display
Timing
2H
Phase
Comparator
&
Low-Pass
PWM
15-Bit
E/W
Output
Sawtooth
PWM
15-Bit
V+
Output
V−
PLL2
FIFO control
Display
Frequency
Doubling
E/W
Correction
DCO
2V
Vertical Reset
Clock & Control
Fig. 2–13: Deflection processing block diagram
16
Micronas
DDP 3310B
ADVANCE INFORMATION
2.3.3. Soft Start/Stop of Horizontal Drive
In order to increase the energy supply of the horizontal
deflection stage smoothly, a soft start decreases the
drive frequency from 55 kHz to 31.25 kHz within
85 ms. The High time tH is always 14.4 µs. This
means, the duty factor decreases from 79.2 % to 45 %
(see Fig. 2–14).
The soft stop is needed, when the protection circuitry
wants to turn off the H-Drive. It has the inverse behavior of the soft start and ends with a High level at the
HOUT Pin.
85 ms
...
tH = 14.4 µs
...
...
T=1/55 kHz
tH = 14.4 µs
T = 1/31.25 kHz
Fig. 2–14: Soft start with a duty factor of 14.4/32
Table 2–5: Allowed Horizontal Frequencies
Supply
Clock
(MHz)
Pixels per
Line
Supply Clk
Main
Clock
(in MHz)
Pixels per
line
Main Clk
Horizontal
Frequency
(Hz)
Minimum
H-Drive
Period
(in µs)
Maximum
H-Drive
Period
(in µs)
HFREQ
(I2C)
27
864
40.5
1296
31.24968
29.60
34.40
000
27
858
40.5
1287
31.46853
29.60
34.40
010
27
800
40.5
1200
33.750
28.80
30.60
100
27
768
40.5
1152
35.15625
27.80
29.20
001
27
720
40.5
1080
37.500
25.60
28.00
101
27
712
40.5
1068
37.92135
25.60
28.00
110
32
1024
40.0
1280
31.24952
29.60
34.40
000
32
944
40.0
1180
33.89776
28.80
30.60
100
32
912
40.0
1140
35.08747
27.80
29.20
001
32
852
40.0
1065
37.55869
25.60
28.00
101
32
844
40.0
1055
37.91469
25.60
28.00
110
40.5
1296
40.5
1296
31.24968
29.60
34.40
000
Micronas
17
DDP 3310B
ADVANCE INFORMATION
2.3.4. Horizontal Phase Adjustment
This section describes a simple way to get a correct
horizontal frame position and clamp window for analog
RGB insertion.
1. For a correct scaler function in panorama/waterglass mode, the digital input data should be centered to the active video input signal.
recorder search mode when the number of lines per
field does not comply with the standard, or if you want
to use a common value of LPFD for PAL and NTSC
(e.g.: LPFD = 290; VSYNCWIN = 54).
2.3.6. Vertical and East/West Deflection
2. The clamping pulse for analog RGB insertion can be
adjusted to the pedestal of the input signal with
POFS2.
3. The horizontal raster position of the analog inserted
RGB1/2 signal can be set to the desired frame position with POFS3.
4. The horizontal position of the digital RGB signal can
be shifted to the left and right with NEWLIN. Following values allowed in respect to POFS2:
− 90 < (POFS2+NEWLIN) − (Clk × SFIF) < 580
− Clk = 3 @ LLC2 = 27 MHz
− Clk = 2.5 @ LLC2 = 32 MHz
5. Now the positioning of horizontal blanking and the
picture frame generator can be done.
2.3.5. Vertical Synchronization
The number of lines per field can be adjusted by software (LPFD). This number is used to calculate the vertical raster. The DDP synchronizes only to a vertical
sync within a programmable detection window (LPFD
± VSYNCWIN). If there is no vsync, the DDP runs with
maximum allowed lines and if the vertical frequency is
to high, it runs with minimum allowed lines. The
smaller the detection window, the slower the DDP gets
synchronized to the incoming vertical sync. In case of
an interlaced input signal, it is possible to display both
fields at the same raster position by setting R_MODE
to 1 or 2.
The vertical deflection waveform is calculated as follows (without EHT compensation):
2
3
V = vpos + ampl ⋅ ( x + lin ⋅ x + scorr ⋅ x )
–
–
–
–
VPOS
AMPL
LIN
SCORR
defines the vertical raster position
is the vertical raster amplitude (zoom ≥ 1)
is the linearity coefficient
is the coefficient for S-correction
The vertical sawtooth signal will be generated from a
differential current D/A converter and can drive a DC
coupled power stage. In order to get a faster vertical
retrace timing, the output current of the vertical D/Aconverter can be increased during the retrace for a
programmable number of lines (FLYBL). The range
between the end of the flyback and the beginning of
the raster is also programmable (HOLDL).
The East/West deflection waveform, generated from a
single-ended D/A converter, is given with the equation:
2
E ⁄ W = width + tcorr ⋅ x + cush ⋅ x + corner ⋅ x
–
–
–
–
–
WIDTH
TCORR
CUSH
CRNU
CRNL
4
is a DC value for the picture width
is the trapezoidal correction
is the pincushion correction
is the upper corner correction
is the lower corner correction
E / W Amplitude
Vertical Amplitude
An automatic field length adaptation can be selected
(VA_MODE). In this case, the vertical raster will be calculated according to the counted number of lines per
field instead from LPFD. This is useful for video
The calculations of the Vertical deflection and East/
West correction waveforms are done in the internal
processor. They are described as polynomials in x,
where x varies from −0.5 × zoom to +0.5 × zoom for one
field. For zoom>1 the range is limited between −0.5
and +0.5.
-0.5
-0.3
-0.1
0.1
0.3
0.5
x
-0.5
-0.3
-0.1
0.1
0.3
0.5
x
Fig. 2–15: Vertical and East/West deflection waveforms
18
Micronas
DDP 3310B
ADVANCE INFORMATION
2.3.7. Vertical Zoom
2.3.9. Protection Circuitry
With vertical zoom, the DDP 3310B is able to display
different aspect ratios of the source signal on tubes
with 4:3 or 16:9 aspect ratio by adapting the corresponding raster.
Picture tube and drive stage protection is provided
through the following measurements:
Vertical
Sawtooth
Start
Stop
– Vertical protection input: this pin watches the vertical sawtooth signal. In every field the sawtooth must
descend below the lower threshold A and ascend
above the upper threshold B. In this case the protection flag is set (sawtooth o.k.). If an error occurs the
protection flag is cleared.
After approx. 10 fields with cleared flag, the RGB
drive signals are blanked. The blanking is cancelled
if the flag is set for 40 fields (see Fig. 2–17).
– Drive shutoff during flyback: this feature can be
selected by software (EFLB)
East/West
Parabola
– Safety input pin: This pin has two thresholds. The
applied signal has to meet the following conditions:
1. threshold B must not be overshot
Normal
Zoom
2. threshold A has to be exceeded permanently or
at least once per line
Fig. 2–16: Vertical zoom
otherwise the RGB signals are blanked . Both
thresholds have a small hysteresis.
2.3.8. EHT Compensation
The vertical deflection waveform can be scaled
according to the average beam current. This is used to
compensate the effects of electric high-tension
changes due to beam current variations. EHT compensation for East/West deflection is done with an offset
corresponding to the average beam current. The time
constant of this process is freely programmable with a
resolution of 18 bit. Both corrections can be enabled
separately. The maximum scaling coefficient for vertical deflection is 1±x and the maximum offset for East/
West is y, where x, y are adjustable from 0 to 0.25. The
horizontal phase at the output HOUT can be influenced according to the average beam current in a
range of ±1.5 µs.
Vert. Protection Flag
1
Accu
−1
~10 fields
~40 fields
Blanking
t
Fig. 2–17: Protection timing
Micronas
19
DDP 3310B
ADVANCE INFORMATION
2.3.10. Display Frequency Doubling
2.3.12. Clock and Reset
The DDP 3310B handles single or double vertical and
horizontal input frequencies. The Display Frequency
Doubling is used when single H/V frequencies are
applied and a FIFO for video frequency doubling is
used. In this mode it is mandatory to supply an active
video signal to the HS pin, which is not vertical
blanked.
The DDP 3310B has the capability to accept different
line-locked clock rates: 27, 32, and 40.5 MHz.This
external clock rate is converted internally to a clock
rate of 40.5 or 40 MHz by means of a PLL. Selection of
external clock frequency is done with pins CM1 and
CM0. See Table 2–6 for clock frequency selection. To
ensure lock of PLL a reset pulse of at least 500 µs
must be applied after power-up.
Three different raster modes are selectable via I2C
bus:
Table 2–6: Clock Frequency Selection
A A‘ B‘ B (reduced line flicker)
A A B B (improved vertical resolution)
A A B‘ B‘ (non-interlaced)
A/B means field A/B in original raster position and A‘/B‘
means field A/B in the opposite raster position.
A minimum field length filter can be switched on (DFDFILT) to write only the smallest field length of the past
up to four fields into the memory. This prevents readbefore-write errors in signals with a strong changing
field length (e.g. VCR signals).
2.3.11. General-purpose D/A Converter
There are two D/A converters realized as pulse width
modulators. The resolution is 8 bit and the clock frequency is 20.25 MHz. The outputs are push-pull types.
For a ripple-free output voltage, a first-order low-pass
filter with a corner frequency <120 Hz should be
applied. The D/A converters will be adjusted via I2Cbus. They can be used to adjust two DC voltages, for
example for horizontal raster position, raster tilt, or just
as switching outputs when the values 0 and 255 are
selected.
20
CM1
CM0
LLC2
0
0
27 MHz
0
1
32 MHz
1
0
40.5 MHz
2.3.13. Reset and Power-On
The IC has its own voltage supervision to generate an
internal reset during power on or when the supply voltage (VSUPD) goes below ~4.5V. Also, a clock supervision of the 5-MHz clock keeps the internal reset active
until a proper clock signal is detected (e.g. three clock
cycles with the correct period). When the reset pin
RESQ or the internal reset becomes active, all
counters and registers are set to zero. When the reset
pins are released, the internal reset is still active for
approximately 4 µs. Then all registers are loaded with
their default values listed in Table 3–3. This initialization takes about 100 µs. During and after reset, the
HOUT signal remains High until a soft start (see Section 2.3.3.) will be performed by setting RAMP_EN.
Micronas
DDP 3310B
ADVANCE INFORMATION
3. Serial Interface
3.2. I2C Control and Status Registers
3.1. I2C-Bus Interface
The I2C-bus interface uses one level of subaddress.
First, the bus address selects the IC, then a subaddress selects one of the internal registers. They have
8- or 16-bit data size; 16-bit registers are accessed by
reading/writing two 8-bit data words.
Communication between the DDP 3310B and the
external controller is done via I2C-bus. The
DDP 3310B has an I2C-bus slave interface and uses
I2C clock synchronization to slow down the interface if
required.
Basically, there are two classes of registers in the
DDP 3310B:
– Writing is done by sending the device address first
followed by the subaddress byte and one or two
data bytes.
1. The first class are directly addressable I2C registers.
They are embedded in the hardware. These registers are 8 or 16 bit wide.
– For reading, the read address has to be transmitted
first by sending the device write address, followed
by the subaddress, a second start condition with the
device read address, and reading one or two bytes
of data.
2. The second class are “XDFP-REGISTERS”, which
are used by the “XDFP” on-chip controller. These
registers are all 16 bit wide and read- and writable.
Communication with these registers requires I2C
packets with a 16-bit XDFP-register address and
16-bit data.
Fig. 3–2 shows I2C protocol for read and write operations; the read operation requires an extra start condition and repetition of the chip address with read command set. Table 3–2 gives definitions of the I2C control
and status registers.
Communication with both classes of registers (I2C and
XDFP-REGISTERS) are performed via I2C; but the format of the I2C telegram depends on which type of register is being accessed.
The I2C-bus chip address of the DDP 3310B is given
below:
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
1
0
1
1/0
SDA
SCL
1
0
S
S
P
P
= I2C-Bus Start Condition
= I2C-Bus Stop Condition
Fig. 3–1: I2C-Bus protocol (MSB first, data must be stable while clock is High)
Write to I2C Control Register :
S 1000 101 W Ack Sub-Addr. Ack 1- or 2-Byte Data Ack
P
Read from I2C Control Register :
S 1000 101 W Ack
W = 0 (Write Bit)
R = 1 (Read Bit)
Sub-Addr. Ack S
S = Start Condition
P = Stop Condition
1000 101
R Ack High-Byte Data Ack Low-Byte Data Nak P
Ack = 0 (Acknowledge Bit from DDP 3310B=gray
or controller=hatched)
Nak = 1 (Not Acknowledge Bit from controller=hatched
or indicating an error state from DDP 3310B=gray)
Fig. 3–2: I2C-Bus protocol
Micronas
21
DDP 3310B
ADVANCE INFORMATION
3.3. XDFP Control and Status Registers
Table 3–1: XDFP read/write address
The second class are “XDFP-REGISTERS”, which are
used by the XDFP on-chip controller. Access to these
registers is achieved by subaddressing.
– Writing to these registers is done by sending the
device write address first, followed by the XDFPwrite subaddress, two address bits for the desired
XDFP-register, and the two data bytes.
– For reading, the XDFP-register address has to be
transmitted first by sending the device write
address, followed by the XDFP-read subaddress
and the two XDFP-register address bytes. Without
sending a stop condition, reading of the addressed
data is done by sending the device read address
and reading two bytes of data.
Fig. 3–3 shows I2C protocol for read and write operations. Table 3–3 gives definitions of the XDFP control
and status registers. If these registers are smaller than
16 bit, the remaining bits should be 0 on write and read
operations. Due to the internal architecture, the IC cannot react immediately to an I2C request, which interacts with the on-chip controller. The maximum
response timing is approximately 20 ms. If the
addressed controller is not ready for further transmissions on the I2C-bus, the clock line SCL is pulled low.
This puts the current transmission into a wait state.
After a certain period of time, the clock line will be
released and the interrupted transmission is carried
on.
XDFP Read address
h’13
XDFP Write address
h’12
The register modes are
8/16r
w
r/w
bit width
read only register
write only register
write/read data register
Note: set unused bits to ‘0‘!
The mnemonics used in the DDP 3310B demo software are given in the last column.
A hardware reset initializes all control registers to 0.
The automatic chip initialization loads a selected set of
registers with the default values given in Table 3–3.
Write to XDFP Control Register:
S 1000101 W Ack XDFP Write Addr. Ack High-Byte Addr. Ack Low-Byte Addr. Ack
High-Byte data Ack
Low-Byte Data Ack P
Read from XDFP Control Register:
S 1000101 W Ack XDFP Read Addr. Ack High-Byte Addr. Ack Low-Byte Addr. Ack S 1000101
W = 0 (Write Bit)
R = 1 (Read Bit)
S = Start Condition
P = Stop Condition
R Ack High-Byte Data Ack Low-Byte Data Nak P
Ack = 0 (Acknowledge Bit from DDP 3310B=gray
or Controller = hatched)
Nak = 1 (Not Acknowledge Bit from Controller=hatched or
indicating an error state from DDP 3310B=gray)
Fig. 3–3: XDFP protocol
22
Micronas
DDP 3310B
ADVANCE INFORMATION
Table 3–2: I2C Control Registers
I2C Control and Status Registers
Subaddr.
Mode
Function
Default
Name
XDFP INTERFACE
h’13
16-w
XDFP read address
bit[[9:0]
bit[15:10]
h’12
16-w
DFPRD
10-bit XDFP RAM address
0
reserved, set to zero
XDFP write address
DFPWR
bit[[9:0]
10-bit XDFP RAM address
bit[15:10]
reserved, set to zero
ANALOG FAST-BLANK MONITOR
h’1E
8-r
Fast-Blank signal status
bit[0]
h’11
16-r/w
0/1
FBLSTAT
FBLIN level Low/High
FBLEV
bit[1]
FBLIN slope: 1 = falling edge occurred
FBSLO
bit[7:2]
not used
picture frame color, 12 bit wide
bit[3:0]
PFC
0..15
blue amplitude
0
PFCB
bit[7:4]
0..15
green amplitude
0
PFCG
bit[11:8]
0..15
red amplitude
0
PFCR
bit[15:12]
0
not used
0
OUTPUT PINS
h’10
Micronas
8-r/w
output pin configuration
PSTR
bit[2:0]
pin driver strength, FIFO control
7 = output tristate
6 = minimum strength
0 = maximum strength
0
PSTSY
bit[3]
0/1
strong/weak driver strength PWM1
0
PSTPR1
bit[4]
0/1
strong/weak driver strength PWM2
0
PSTPR2
bit[5]
0/1
disable/enable internal resistor for vertical
and East/West drive output
0
VEWXR
bit[6]
0/1
High/Low-active horizontal flyback input
0
FLYPOL
bit[7]
0/1
disable/enable following I/O pin:
FIFO -controll signals, PWM1&2, HCS,
R/G/BIN2, and VS2.
0
OSDOFF
23
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
INPUT FORMATTER
h’1B0
16-r/w
Input format
INFMT
bit [0]
0/1
4:2:2 / 4:1:1 mode
1
M411
bit [1]
0/1
binary offset / 2‘s complement
1
COB
bit [2]
0/1
enable / disable blanking to black ( for luma
and chroma input when HS = 0 )
1
BLNK
bit [4:3]
0...3
select color multiplex
0
CMUX
0
SCMODE
PANO
SCALER CONTROL REGISTER
h’1C1
16-r/w
scaler mode register
bit[1:0]
h’1C2
16-r/w
bit[2]
reserved, set to 0
bit[13:3]
reserved, set to 0
bit[14]
0
scaler update command, set to 1 to update
only scaler mode register
0
SCMODUP
bit[15]
0
scaler update command, set to 1 to update
all scaler control registers
0
SCUPDATE
active video length for 1-h FIFO
bit[11:0]
h’1C3
16-r/w
16-r/w
h’1C5
16-r/w
h’1C6
...
h’1CA
16-r/w
h’1CB
...
h’1CF
16-r/w
24
0...1295
720
bit[11:0]
256..1024 expansion by a factor c,
the value 1/c*1024 is required
bit[11:0]
0...4095
scaler1/2 non-linear scaling coefficient
scaler1 window controls (see Table 3–4)
0...4095
5 registers for control of the non-linear
scaling
scaler2 window controls (see Table 3–4)
bit[11:0]
FFLIM
1024
SCINC1
682
SCINC2
1024..4095 compression by a factor c,
the value c*1024 is required
scaler2 coefficient; this scaler expands the signal.
bit[11:0]
720
length in pixels
LLC mode (864/h)
scaler1 coefficient; this scaler compresses the signal.
bit[11:0]
h’1C4
scaler mode
0
linear scaling mode
1
non-linear scaling mode, ’panorama’
2
non-linear scaling mode, ’waterglass’
3
reserved
0...4095
5 registers for control of the non-linear
scaling
0
SCINC
0
...
0
SCW1_1
...
SCW1_5
0
...
0
SCW2_1
...
SCW2_5
Micronas
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
CHROMA CHANNEL
h’1AF
16-r/w
luma/chroma matching delay
bit [2:0]
−2...2
bit [3]
bit [4]
0/1
bit [5]
h’1AB
16-r/w
CRCTRL
variable chroma delay
0
not used, set to “0”
0
CB (U) sample first / CR (V) sample first
0
CDEL
ENVU
not used, set to “0”
digital transient improvement
DTICTRL
bit [3:0]
0..15
coring value
1
DTICO
bit [7:4]
0..15
DTI gain
5
DTIGA
bit [8]
0/1
narrow/wide bandwidth mode
1
DTIMO
LUMA CHANNEL
h’1B1
16-r/w
bit [14:9]
0..63
h’19A
16-r/w
bit [8:0]
−256..255 luma DC-offset
h’1AA
16-r/w
luma peaking filter, the gain at high frequencies and small
signal amplitudes is: 1 + (k1+k2)/8
h’1AE
16-r/w
16-r/w
h’196
Micronas
16-r/w
PK1
PKUN
bit [7:4]
0..15
k2: peaking level overshoot
4
PKOV
bit [8]
0/1
peaking value normal/inverted
(peaking/softening)
0
PKINV
luma peaking filter, coring
PK2
0..31
coring level
3
COR
peaking reduction
100 %
80 %
60 %
50 %
40 %
30 %
0
PKRD
000
001
01x
100
101
11x
0/1
peaking filter center frequency High/Low
0
PFS
luma soft limiter, slope A and B
LSLS
bit [3:0]
slope segment A
0
LSLSA
bit [7:4]
slope segment B
0
LSLSB
luma soft limiter, limit A
bit [8]
16-r/w
BRM
4
bit [7:0]
h’192
0
k1: peaking level undershoot
bit [8]
h’18E
CTM
0..15
bit [7:5]
16-r/w
32
bit [3:0]
bit [4:0]
h’18A
picture contrast in steps of 1/32
LSLA
luma soft limiter absolute limit (unsigned)
0/1
modulation off/on
(resolution enhancement)
luma soft limiter, limit B
bit [8:0]
luma soft limiter segment B tilt point
(unsigned)
bit [8:0]
luma soft limiter segment A tilt point
(unsigned)
255
0
LSLAL
LSLM
300
LSLTB
250
LSLTA
25
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
INVERSE MATRIX
h’1B9
h’1B8
h’1B7
h’1B6
h’1B5
h’1B4
16-r/w
16-r/w
16-r/w
picture matrix coefficient R−Y = MR1M/64*CB + MR2M/64*CR
bit [15:7]
−256... 255
0
MR1M
bit [15:7]
−256... 255
86
MR2M
picture matrix coefficient G−Y = MG1M/64*CB + MG2M/64*CR
bit [15:7]
−256... 255
−22
MG1M
bit [15:7]
−256... 255
−44
MG2M
picture matrix coefficient B−Y = MB1M/64*CB + MB2M/64*CR
bit [15:7]
−256... 255
113
MB1M
bit [15:7]
−256... 255
0
MB2M
h’1B2
16-r/w
bit [15:9]
0...63
−1
picture saturation in steps of 1/32;
reserved mode to use old MATRIX
coefficients and CTM addresses from B1
−1
SATM
h’1B3
16-r/w
bit [14:8]
0...127
limit for picture contrast × saturation in
steps of 1/32
80
SATLIM
8
PFRCT
8
PFGCT
PICTURE FRAME GENERATOR
h’197
16-r/w
picture frame insertion contrast R (amplitude range:0 to 255)
bit [7:4]
h’193
16-r/w
h’1D5
16-r/w
16-r/w
R amplitude = PFCR · (PFRCT + 4)
invalid
picture frame insertion contrast G (amplitude range:0 to 255)
bit [7:4]
h’18F
0..13
14,15
0..13
14,15
G amplitude = PFCG · (PFGCT + 4)
invalid
picture frame insertion contrast B (amplitude range:0 to 255)
bit [7:4]
0..13
14,15
B amplitude = PFCB · (PFBCT + 4)
invalid
8
PFBCT
bit [10:0]
0...1295
horizontal picture frame begin
(see Table 2–5 for max. pixels per line)
horizontally disabled
full frame
0
PFGHB
0
7FF
h’1D6
16-r/w
bit [10:0]
0...1295
horizontal picture frame end
(see Table 2–5 for max. pixels per line)
0
PFGHE
h’1AC
16-r/w
bit [8:0]
0...511
0
vertical picture frame start line (+128)
vertically disabled
0
PFGVB
h’1A8
16-r/w
bit [8:0]
0...511
vertical picture frame end line
57
PFGVE
h’198
16-r/w
bit [7:0]
0/1:
disable/enable analog FastBlank input1/2
if bit[x] is set to 1, then the function is active
for the respective signal priority
0
PBFB1
h’194
16-r/w
bit [2:0]
0...7
picture frame generator priority id
7
PFGID
bit [8]
0/1
enable prio id for picture frame generator
1
PFGEN
26
Micronas
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
SCAN VELOCITY MODULATION
h’1A7
h’19F
h’19B
16-r/w
16-r/w
16-r/w
video mode coefficients
SVM1
bit [5:0]
0...63
gain
60
SVG
bit [8:6]
0...6
differentiator delay (0= filter off)
1
SVD
bit [7:0]
0...255
limit value
bit [8:5]
0
not used, set to”0”
0
delay of SVMOUT in steps of 12.5 ns
(7 = SVMOUT vs. RGBOUT is 60ns)
7
SVDEL
0
SVCOR
limiter
100
delay and coring
bit [3:0]
0...15
SVLIM
SVM2
bit [7:4]
0...15
coring value
bit [8]
0
not used, set to”0”
TUBE MEASUREMENT
h’19C
16-r/w
h’15F
16-r/w
h’186
16-r/w
tube measurement line
10
bit [8:0]
0..511
start line for tube measurement (+2 lines)
bit[10:0]
0... 1295
Latch timing of madc data in pixels before
the begin of horiz. blanking HBST
white drive measurement control
bit [8:0]
0..511
RGB amplitude for white-drive beam current measurement
0..511
Amplitude for cutoff measurement.
It can be set to measure at higher cutoff
current.
h’168
16-r/w
bit[14:6]
h’171
16-r/w
measurement control word
Micronas
TML
128
MADCLAT
384
WDRM
256
IBRM
MCTRL
bit [8]
0/1
enable/disable ultra black blanking
0
ULBLK_DIS
bit [9]
0/1
0: all outputs blanked (video mute)
1: normal mode
0
BLANK_DIS
bit [10]
0/1
78/156 kHz bandwidth for cutoff and drive
measurement
0
BW_SEL
bit [11]
0/1
enable/disable white drive measurement
0
WDR_DIS
bit [12]
0/1
enable/disable cutoff measurement
0
CUT_DIS
bit [13]
0/1
disable/enable horizontal blanking during
measurement
0
MBLANK
bit [14]
0/1
disable/enable RSW1 Pin as input for beam
current measurement
0
SMODE
27
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
BRIGHTNESS and CONTRAST
h’165
16-r/w
bit[14:6]
h’166
16-r/w
h’167
16-r/w
0..511
analog contrast for external RGB
360
EXT_CONTR
bit[15:6]
−256..255 analog brightness for external RGB
The range allows for both increase and reduction of brightness.
128
EXT_BRT
bit[15:6]
−256..255 internal analog brightness
The range allows for both increase and reduction of brightness.
24
INT_BRT
BCL
h’D7
16-r/w
bit[14:3]
0..4095
measured beam current, latched every line
except during vertical blanking
0
h’160
16-r/w
bit[15:4]
0... 2047
0...−2048
BCL threshold current if SENSE input used
BCL threshold current if RSW1 input used
(max. ADC output ~2047)
64
h’161
16-r/w
bit[8:0]
0...511
BCL time constant;
0 = off
0
BCL_TC
h’162
16-r/w
bit[14:6]
0...511
BCL loop gain
0
BCL_GAIN
h’163
16-r/w
bit[14:6]
0...511
BCL minimum contrast; (= 0..max contrast)
256
BCL_MIN_C
h’164
16-r/w
bit[14:6]
0...511
BCL minimum brightness; (= 0..max
bright.)
256
BCL_MIN_B
28
BC
BCL_THRES
Micronas
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
CUTOFF and DRIVE
h’169
16-r/w
bit[12:4]
0...511
reference for cutoff Red
511
CUT_R
h’16A
16-r/w
bit[12:4]
0...511
reference for cutoff Green
511
CUT_G
h’16B
16-r/w
bit[12:4]
0...511
reference for cutoff Blue
511
CUT_B
h’D3
16-r
bit[11:4]
0...255
measured cutoff Red
0
CUTOFF_R
h’D4
16-r
bit[11:4]
0...255
measured cutoff Green
0
CUTOFF_G
h’D5
16-r
bit[11:4]
0...255
measured cutoff Blue
0
CUTOFF_B
h’16C
16-r/w
bit[14:6]
0...511
0
gain for cutoff control loop;
the reference values are taken directly as
cutoff values
0
CUT_GAIN
h’16D
16-r/w
bit[12:4]
0...511
reference for White Drive Red
511
WDR_R
h’16E
16-r/w
bit[12:4]
0...511
reference for White Drive Green
511
WDR_G
h’16F
16-r/w
bit[12:4]
0...511
reference for White Drive Blue
511
WDR_B
h’D0
16-r
bit[11:4]
0...255
measured White Drive Red
0
WDRIVE_R
h’D1
16-r
bit[11:4]
0...255
measured White Drive Green
0
WDRIVE_G
h’D2
16-r
bit[11:4]
0...255
measured White Drive Blue
0
WDRIVE_B
h’170
16-r/w
bit[14:6]
0...511
0
gain for White Drive control loop;
the reference values are taken directly as
white drive values
0
WDR_GAIN
h’172
16-r/w
bit[14:6]
475 ...511 threshold for automatic drive saturation
avoidance
491
MAX_WDR
h’1E9
16-r/w
bit[0]
0/1
Micronas
disable/enable automatic drive saturation
avoidance
0
WDR_SAT
29
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
DISPLAY FREQUENCY DOUBLING
h’176
16-r/w
display frequency doubling control word
DFDCTRL
bit[1:0]
display raster mode (A’ = field A in raster B)
0 = A A‘ B‘ B
1=AA B B
2 = A A B‘ B‘
3=not used
0
DFDMODE
bit[3:2]
minimum field length filter
0 = off
1 = 2 fields
2 = 3 fields
3 = 4 fields
0
DFDFILT
bit[5:4]
input sync doubling switch
0 = leave H and V sync unchanged
1 = double VSYNC and leave HSYNC unchanged
2 = double HSYNC and leave VSYNC unchanged
3 = double H and V sync
0
DFDSW
bit[6]
clock switch
0 = Clock from LLC2 pin divided by 2
1 = Clock from LLC1 pin
0
DFDCLK
bit[7]
test bit, set to 0
0
bit[8]
0
1
automatic VS/VS2 polarity detection
Low-active VS/VS2 input
0
VSYPOL
bit[9]
0/1
High/Low-active HS input
0
HSYPOL
bit[10]
0/1
VS / VS2 Pin is source of VSYNC
0
VSYSRC
bit[11]
0/1
dis-/enable still picture (only available if
display frequency doubling is enabled)
0
STILL
bit[12]
0/1
High / Low-active FIFO controll signals
0
FIFOPOL
TIMING
h’1A4
16-r/w
vertical blanking start
bit [8:0]
h’1A0
16-r/w
0..511
182
VBST
22
VBSO
first line of vertical blanking (+ 128 offset)
vertical blanking stop
bit [8:0]
0..511
last line of vertical blanking
h’1D3
16-r/w
bit[10:0]
0..1295
horizontal blanking start
(see Table 2–5 for max. pixels per line)
253
HBST
h’1D4
16-r/w
bit[10:0]
0..1295
horizontal blanking stop
(see Table 2–5 for max. pixels per line)
331
HBSO
h’1D2
16-r/w
bit[10:0]
0..1295
Start at active video relative to pixel
counter.
(see Table 2–5 for max. pixels per line)
330
NEWLIN
h’18b
16-r/w
bit [8:0]
0...511
start point of active video relative to incoming HS signal in steps of 2 LLC2 clocks; can
be used e.g. for panning
30
0
SFIF
Micronas
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
30
HDRV
HORIZONTAL DEFLECTION
h’1D1
16-r/w
h’140
16-r/w
bit [5:0]
20..35
horizontal deflection control register
16-r/w
0
reserved, set to 0
0
bit [1]
0/1
enable/disable vertical protection
0
VPROT_DIS
bit [2]
0/1
enable/disable H-safety protection
0
HPROT_DIS
bit [3]
0/1
disable/enable drive high during flyback
0
EFLB
bit [4]
1
start ramp up/down
0
RAMP_EN
bit [7:5]
0..7
horizontal frequency
H-Freq.
pixels per line @LLC
in kHz
27 MHz
32 MHz
31.25
864
1024
35.1
768
912
31.46
858
1024
33.8
800
944
37.5
720
852
37.9
712
844
0
HFREQ
5
POFS2
0
POFS3
adjustable delay of PLL2, clamping, and blanking (relative to
incoming hsync) adjust clamping pulse for analog RGB input
bit [15:1]
h’144
16-r/w
16-r/w
Range ±600, 1 step = 1 pixel clock
adjustable delay of flyback, H/VSYNC and analog RGB (relative to PLL2) adjust horizontal drive or H/VSYNC
bit [15:1]
h’145
h’142
HCTRL
bit [0]
000
001
010
100
101
110
h’141
horizontal drive pulse duration (High time)
Range ±600, 1 step = 1 pixel clock
PLL2/3 filter coefficients
bit [14:6]
0...511
proportional coefficient PLL3, c*2^−9
102
PKP3
bit [14:6]
0...511
proportional coefficient PLL2, c*2^−9
184
PKP2
h’14A
16-r/w
bit[15:6]
−512...511 vertical angle
0
ANGLE
h’14B
16-r/w
bit[15:6]
−512...511 vertical bow
0
BOW
0
VS_MODE
0
R_MODE
0
VA_MODE
VERTICAL MODES
h’1E2
16-r/w
bit [0]
h’1E3
16-r/w
raster mode
h’1E8
Micronas
16-r/w
0/1
VSYNC synchronized/ free running
bit [1:0]
0
1
2
3
same input and output raster
field 2 is delayed (only A raster is written)
field 1 is delayed (only B raster is written)
not used
bit [0]
0/1
automatic lines-per-field adaption (constant
raster amplitude) off/on
31
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
VERTICAL PARAMETERS
h’152
16-r/w
bit [6:0]
0... 127
window (LPFD±VSYNWIN) for sync
detection
h’153
16-r/w
bit [9:0]
0... 1023
lines per field
h’154
16-r/w
bit [9:0]
0... 1023
number of hold lines
h’155
16-r/w
bit [9:0]
0... 1023
number of flyback lines
(flyback booster active)
32
312
VSYNWIN
LPFD
10
HOLDL
5
FLYBL
0
AMPL
256
ZOOM
VERTICAL SAWTOOTH CORRECTION (%-values according to DAC range)
h’14D
16-r/w
bit [15:8]
−128...127 vertical amplitude (±25 %)
h’14E
16-r/w
bit [14:6]
0...510
h’14F
16-r/w
bit [15:8]
−128...127 vertical picture position (± 50 %)
(DC offset of Sawtooth output). This offset
is independent of EHT compensation.
0
VPOS
h’150
16-r/w
bit [15:8]
−128...127 linearity (±10 %)
0
LIN
h’151
16-r/w
bit [15:8]
−128...127 S-correction (±8 %)
0
SCORR
51
WIDTH
zoom (0...100...200 %)
EAST-WEST PARABOLA (%-values according to DAC range)
h’157
16-r/w
bit [15:7]
−256..255 picture width (0...100 %)
h’158
16-r/w
bit [15:8]
−128...127 trapez correction (±100 %)
0
TCORR
h’159
16-r/w
bit [15:8]
−128...127 cushion correction (±100 %)
0
CUSH
h’15A
16-r/w
bit [15:8]
−128...127 upper corner correction (±100 %)
0
CRNU
h’15B
16-r/w
bit [15:8]
−128...127 lower corner correction (±100 %)
0
CRNL
EXTREME HIGH-TENSION (EHT) COMPENSATION (%-values according to DAC range)
h’148
16-r/w
bit[15:6]
−512...511 EHT compensation coefficient for
horizontal phase (±1.5µs)
0
EHTHP
h’149
16-r/w
bit[14:6]
0...511
0
EHTH_TC
h’147
16-r/w
bit[15:6]
−512...511 EHT compensation coefficient for
horizontal amplitude (±100 %)
0
EHTH
h’15C
16-r/w
bit [15:6]
−512...511 EHT compensation coefficient for
vertical amplitude (±25 %)
0
EHTV
h’15D
16-r/w
bit [14:6]
0...511
0
EHTV_TC
32
EHT time constant for horizontal phase
compensation
0 = off
time constant for control of vertical and
horizontal amplitude EHT compensation
0 = off
Micronas
DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
ANALOG RGB INSERTION
h’17A
16-r/w
Fast-Blank interface mode
FBLMODE
bit [0]
0
1
Fast-Blank from FBLIN1 pin
force internal Fast-Blank signal to High
0
FBFOH1
bit [1]
0/1
Fast-Blank active High/Low at FBLIN pin
0
FBPOL
bit [2]
0
1
Fast-Blank from FBLIN1 pin
force internal Fast-Blank signal to Low
0
FBFOL1
Fast-Blank priority
FBLIN1>FBLIN2
FBLIN1<FBLIN2
0
FBPRIO
0
1
bit [4]
0
1
Fast-Blank from FBLIN2 pin
force internal Fast-Blank signal to Low
0
FBFOL2
bit [5]
0
1
Fast-Blank from FBLIN2 pin
force internal Fast-Blank signal to High
0
FBFOH2
bit[6]
0/1
Fast-Blank monitor input select FBLIN1/2
0
FBMON
bit[7]
0/1
disable/enable clamping for RGBIN1&2
0
CLAMP
bit[8]
0/1
half contrast signal active High/Low
at HCS pin
0
HCSPOL
bit[9]
0/1
disable/enable half contrast switching
0
HCSEN
bit[10]
0
1
half contrast signal from HCS pin
force internal half contrast signal to High
0
HCSFOH
bit[11]
0
1
clamp RGBIN1 to black (if CLAMP =1)
clamp RGBIN1 to bias (if CLAMP =1)
0
C1_B
bit[12]
0
1
clamp RGBIN2 to black (if CLAMP =1)
clamp RGBIN2 to bias (if CLAMP =1)
0
C2_B
bit[3]
I2C-CONTROLLED 8-BIT PWM
h’178
16-r/w
bit[7:0]
0..255
PWM1 data word
0
PWM1
h’179
16-r/w
bit[7:0]
0..255
PWM2 data word
0
PWM2
XDFP STATUS REGISTER
h’0
Micronas
16-r/w
firmware version number
VER
bit[7:0]
firmware release
−
FW_REL
bit[15:8]
hardware version number (TC)
−
HW_VER
33
DDP 3310B
ADVANCE INFORMATION
3.3.1. Scaler Adjustment
Fig. 3–4. It shows the scaling of the input signal and
the variation of the scaling factor during the active
video line. The scaling factor starts below 1, i.e. for the
borders the video data is expanded and after it
exceeds 1 it is compressed. When the picture center is
reached, the scaling factor is kept constant. At the second border the scaling factor changes back symmetrically.
In case of linear scaling, most of the scaler registers
need not be set. Only the scaler mode, active video
length, and the fixed scaler increments (SCINC1 /
SCINC2) must be written.
For adjustment of the scaler for non-linear scaling, the
parameters given in Table 3–4 should be used. An
example for “panorama vision” mode is depicted in
Center
Border
Border
Compression
Ratio
Zoom
Compression
Zoom
1
t
Input Signal
Output Signal
Fig. 3–4: Scaler operation for “panorama” mode
Table 3–4: Setup values for non-linear scaler modes
Mode
27 MHz
‘waterglass’
border 35 %
Register
center 3/4
32 MHz
‘panorama’
border 30 %
center 5/6
center 4/3
‘waterglass’
border 35 %
center 6/5
center 3/4
‘panorama’
border 30 %
center 5/6
center 4/3
center 6/5
SCINC1
1099
1064
1024
1024
1195
1122
1024
1024
SCINC2
1024
1024
259
407
1024
1024
305
489
SCINC
60
65
56
38
54
42
68
46
FFLIM
715
717
758
796
833
845
831
871
SCW1 - 0
20
10
106
106
51
37
109
126
SCW1 - 1
156
123
106
106
161
166
125
126
SCW1 - 2
202
236
273
292
256
257
291
310
SCW1 - 3
338
349
273
292
366
386
307
310
SCW1 - 4
358
359
379
398
417
423
416
436
SCW2 - 0
20
10
186
177
51
37
168
175
SCW2 - 1
156
123
186
177
161
166
184
175
SCW2 - 2
384
417
354
363
373
368
350
359
SCW2 - 3
520
530
354
363
483
497
366
359
SCW2 - 4
540
540
540
540
534
534
534
534
34
Micronas
DDP 3310B
ADVANCE INFORMATION
4. Specifications
4.1. Outline Dimensions
1
1.27
1.1 x 45°
61
60
26
44
27
43
16 x 1.27 = 20.32
24.2
23.1
0.23
25.14
0.74
1.27
10
0.46
9
16 x 1.27 = 20.32
1.0
1.2 x 45 °
1.7
3.8
25.14
4.4
24.2
0.1
SPGS0027-2(K)/1E
Fig. 4–1:
68-Pin Plastic Leaded Chip Carrier with heat spreader
(PLCC68K)
Weight approximately 4.8 g
Dimensions in mm
4.2. Pin Connections and Short Descriptions
NC = not connected
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
Pin No.
Pin Name
Type
PLCCK
68-pin
IN = Input
OUT = Output
SUPPLY = Supply Pin
Connection
Short Description
(If not used)
1
VSUPP
SUPPLY
X
Supply Voltage, Output Pin Driver
2
GNDP
SUPPLY
X
Ground, Output Pin Driver
3
VS2
IN
GNDD
Additional VSYNC input
4
FIFORRD
OUT
LV
FIFO Read counter Reset
5
FIFORD
OUT
LV
FIFO Read Enable
6
FIFOWR
OUT
LV
FIFO Write Enable
7
FIFORWR
OUT
LV
FIFO Write counter Reset
8
HOUT
OUT
X
Horizontal Drive Output
9
HFLB
IN
HOUT
Horizontal Flyback Input
10
SAFETY
IN
GNDO
Safety Input
11
VPROT
IN
GNDO
Vertical Protection Input
Micronas
35
DDP 3310B
Pin No.
Pin Name
ADVANCE INFORMATION
Type
PLCCK
68-pin
Connection
Short Description
(If not used)
12
FREQSEL
IN
X
Selection of H-Drive Frequency Range
13
CM1
IN
X
Clock Select 40.5 or 27/32 MHz
14
CM0
IN
X
Clock select 27/32 MHz
15
RSW2
OUT
LV
Range Switch2, Measurement ADC
16
RSW1
IN/OUT
LV
Range Switch1, Measurement ADC
17
SENSE
IN
GNDO
Sense ADC Input
18
GNDM
SUPPLY
X
Ground, MADC Input
19
VERT+
OUT
GNDO
Differential Vertical Sawtooth Output
20
VERT−
OUT
GNDO
Differential Vertical Sawtooth Output
21
EW
OUT
GNDO
Vertical Parabola Output
22
XREF
IN
X
Reference Input for RGB DACs
23
SVM
OUT
VSUPO
Scan Velocity Modulation
24
ROUT
OUT
VSUPO
Analog Output Red
25
GOUT
OUT
VSUPO
Analog Output Green
26
BOUT
OUT
VSUPO
Analog Output Blue
27
GNDO
SUPPLY
X
Ground, Analog Back-end
28
VSUPO
SUPPLY
X
Supply Voltage, Analog Back-end
29
VRD/BCS
IN
X
DAC Reference, Beam Current Safety
30
FBLIN1
IN
GNDO
Fast-Blank1 Input
31
RIN1
IN
GNDO
Analog Red1 Input
32
GIN1
IN
GNDO
Analog Green1 Input
33
BIN1
IN
GNDO
Analog Blue1 Input
34
FBLIN2
IN
GNDO
Fast-Blank2 Input
35
RIN2
IN
GNDO
Analog Red2 Input
36
GIN2
IN
GNDO
Analog Green2 Input
37
BIN2
IN
GNDO
Analog Blue2 Input
38
TEST
IN
GNDD
Test Pin
39
RESQ
IN
X
Reset Input, active low
40
PWM1
OUT
LV
I2C-controlled DAC
41
PWM2
OUT
LV
I2C-controlled DAC
42
HCS
IN
GNDD
Half-Contrast
36
Micronas
DDP 3310B
ADVANCE INFORMATION
Pin No.
Pin Name
Type
PLCCK
68-pin
Connection
Short Description
(If not used)
43
C0
IN
GNDD
Picture Bus Chroma (LSB)
44
C1
IN
GNDD
Picture Bus Chroma
45
C2
IN
GNDD
Picture Bus Chroma
46
C3
IN
GNDD
Picture Bus Chroma
47
C4
IN
GNDD
Picture Bus Chroma
48
C5
IN
GNDD
Picture Bus Chroma
49
C6
IN
GNDD
Picture Bus Chroma
50
C7
IN
GNDD
Picture Bus Chroma (MSB)
51
VSUPD
SUPPLY
X
Supply Voltage, Digital Circuitry
52
GNDD
SUPPLY
X
Ground, Digital Circuitry
53
LLC2
IN
X
System Clock Input (27/32/40.5 MHz)
54
Y0
IN
GNDD
Picture Bus Luma (LSB)
55
Y1
IN
GNDD
Picture Bus Luma
56
Y2
IN
GNDD
Picture Bus Luma
57
Y3
IN
GNDD
Picture Bus Luma
58
Y4
IN
GNDD
Picture Bus Luma
59
Y5
IN
GNDD
Picture Bus Luma
60
Y6
IN
GNDD
Picture Bus Luma
61
Y7
IN
GNDD
Picture Bus Luma (MSB)
62
LLC1
IN
VSUPD
Single Line-Locked Clock Input (13.5/16 MHz)
63
HS
IN
X
Horizontal Sync Input
64
VS
IN
GNDD
Vertical Sync Input
65
XTAL2
OUT
X
Analog Crystal Output (5-MHz Security Clock)
66
XTAL1
IN
X
Analog Crystal Input (5-MHz Security Clock)
67
SDA
IN/OUT
X
I2C-Bus Data
68
SCL
IN/OUT
X
I2C-Bus Clock
Micronas
37
DDP 3310B
4.3. Pin Description
Pin 1 – Supply Voltage, Output Pin Driver VSUPP*
This pin is used as supply for the following digital output pins: FIFORRD, FIFORD, FIFOWR, FIFORWR.
Pin 2 – Ground, Output Pin Driver GNDP*
Output Pin Driver Reference
Pin 3 – Sync Signal Input VS2 (Fig. 4–3)
Additional pin for the vertical sync information. Via I2CRegister the used vertical sync can be switched
between the inputs VS2 and VS (Pin 64)
Pin 4 – Reset for FIFO Read Counter FIFORRD
(Fig. 4–4)
This signal is active-High and resets the read counter
in the display frequency doubling FIFO.
Pin 5 – Read Enable for FIFO FIFORD (Fig. 4–4)
This signal is active-High and enables the read counter
in the display frequency doubling FIFO.
Pin 6 – Write Enable for FIFO FIFOWR (Fig. 4–4)
This signal is active-High and enables the write
counter in the display frequency doubling FIFO.
Pin 7 – Reset for FIFO Write Counter FIFORWR (Fig.
4–4)
This signal is active-High and resets the write counter
in the display frequency doubling FIFO.
Pin 8 – Horizontal Drive HOUT (Fig. 4–5)
This open-drain output supplies the drive pulse for the
horizontal output stage. A pull-up resistor has to be
used (see Section 2.3.).
Pin 9 – Horizontal Flyback Input HFLB (Fig. 4–6)
Via this pin, the horizontal flyback pulse is supplied to
the DDP 3310B (see Section 2.3.).
Pin 10 – Safety Input SAFETY (Fig. 4–6)
This input has two thresholds. A signal between the
lower and upper threshold means normal function.
Other signals are detected as malfunction (see Section
2.3.9.).
Pin 11 – Vertical Protection Input VPROT (Fig. 4–7)
The vertical protection circuitry prevents the picture
tube from burn-in in the event of a malfunction of the
vertical deflection stage. If the peak-to-peak value of
the vertical sawtooth signal is too small, the RGB output signals are blanked (see Section 2.3.9.).
Pin 12 – H-Drive Frequency Range Select FREQSEL
(Fig. 4–3)
This pin selects the frequency range for the horizontal
drive signal (see Section 2.3.2.).
38
ADVANCE INFORMATION
Pin 13 – Clock Select 40.5 or 27/32 MHz CM1
(Fig. 4–3)
Low level selects 27/32 MHz, High level selects
40.5 MHz (see Section 2.3.12.).
Pin 14 – Clock Select 27 or 32 MHz CM0 (Fig. 4–3)
Low level selects 27 MHz, High level selects 32 MHz
(see Section 2.3.12.).
Pin 15 – Range Switch2 for Measuring ADC RSW2
(Fig. 4–8)
This pin is an open-drain pull-down output. During cutoff measurement the switch is off. During white drive
measurement the switch is on. Also during the rest of
time it is on. (see Section 2.2.4.).
Pin 16 – Range Switch1 or Second Input for Measuring ADC RSW1 (Fig. 4–9)
This pin is an open-drain pull-down output. During cutoff and white-drive measurement, the switch is off.
During the rest of time it is on. The RSW1 pin can be
used as second measurement ADC input (see Section
2.2.4.).
Pin 17 – Measurement ADC Input SENSE (Fig. 4–10)
This is the input of the analog to digital converter for
the picture and tube measurement. Three measurement ranges are selectable with RSW1 and RSW2
(see Section 2.2.4.).
Pin 18 – Measurement ADC Reference Input MGND
This is the ground reference for the measurement
A/D converter.
Pin 19 – Vertical Sawtooth Output VERT+ (19)
(Fig. 4–11)
This pin supplies the drive signal for the vertical output
stage. The drive signal is generated with 15-bit precision. The analog voltage is generated by a 4-bit current DAC with external resistor (6 kΩ for proper operation) and uses digital noise-shaping.
Pin 20 – Vertical Sawtooth Output inverted VERT−
(Fig. 4–11)
This pin supplies the inverted signal of VERT+.
Together with this pin, it can be used to drive symmetrical deflection amplifiers.
Pin 21 – East/West Parabola Output EW (Fig. 4–12)
This pin supplies the parabola signal for the East/West
correction. The drive signal is generated with 15-bit
precision. The analog voltage is generated by a 4-bit
current DAC with external resistor and uses digital
noise-shaping.
Micronas
ADVANCE INFORMATION
Pin 22 – DAC Current Reference XREF (Fig. 4–13)
External reference resistor for DAC output currents,
typical 10 kΩ, to adjust the output current of the D/A
converters. (see recommended operating conditions).
This resistor has to be connected to analog ground as
closely as possible to the pin.
Pin 23 – Scan Velocity Modulation Output SVM
(Fig. 4–14)
This output delivers the analog SVM signal (see Section 2.1.11.). The D/A converter is a current sink like
the RGB D/A converters. At zero signal the output current is 50 % of the maximum output current.
Pin 24, 25, 26 – Analog RGB Output ROUT, GOUT,
BOUT (Fig. 4–14)
These pins are the analog Red/Green/Blue outputs of
the back-end. The outputs are current sinks.
Pin 27 – Ground, Analog Back-end GNDO*
This pin has to be connected to the analog ground. No
supply current for the digital stages should flow
through this line.
Pin 28 – Supply Voltage, Analog Back-end VSUPO*
This pin has to be connected to the analog supply voltage. No supply current for the digital stages should
flow through this line.
Pin 29 – DAC Reference Decoupling/Beam Current
Safety VRD/BCS (Fig. 4–13)
Via this pin, the DAC reference voltage is decoupled by
an external capacitor. The DAC output currents
depend on this voltage, therefore a pull-down transistor can be used to shut off all beam currents. A decoupling capacitor of 4.7 µF in parallel to 100 nF (low
inductance) is required.
Pin 30, 34 – Fast-Blank Input FBLIN1/2 (Fig. 4–7)
These pins are used to switch the RGB outputs to the
external analog RGB inputs. FBLIN1 switches the
RIN1, GIN1 and BIN1 inputs, FBLIN2 switches the
RIN2, GIN2 and BIN2 inputs. The active level (Low or
High) can be selected by software.
Pin 31, 32, 33 – Analog RGB Input1 RIN1, GIN1, BIN1
(Fig. 4–15)
These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector which can by
switched to the analog RGB outputs with the FastBlank signal. The analog back-end provides separate
brightness and contrast settings for the external analog RGB signals (see Section 2.2.1. and Fig. ).
Micronas
DDP 3310B
Pin 35, 36, 37 – Analog RGB Input2 RIN2, GIN2, BIN2
(Fig. 4–15)
These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector which can by
switched to the analog RGB outputs with the FastBlank signal. The analog back-end provides separate
brightness and contrast settings for the external analog RGB signals (see Section 2.2.1. and Fig. ).
Pin 38 – Test Input TEST (Fig. 4–16)
This pin enables factory test modes. For normal operation it must be connected to ground.
Pin 39 – Reset Input RESQ (Fig. 4–16)
A low level on this pin resets the DDP 3310B.
Pin 40 – Adjustable DC Output 1 PWM1 (Fig. 4–17)
This output delivers a DC voltage with a resolution of
8 bit, adjustable over the I2C bus. The output is driven
by a push-pull stage. The PWM frequency is appr.
79.4 kHz. For a ripple-free voltage a first order lowpass
filter with a corner frequency <120 Hz should be
applied.
Pin 41 – Adjustable DC Output 2 PWM2 (Fig. 4–17)
See pin 40.
Pin 42 – Half-Contrast Input HCS (Fig. 4–18)
Via this input pin the output level of the D/A-converted
internal RGB signals can be reduced by 6 dB. Inserted
external analog RGB signals remain unchanged.
Pin 43...50 – Picture Bus Chroma C0...C7 (Fig. 4–3)
The Picture Bus Chroma lines carry the multiplexed
color component data. For the 4:1:1 input signal (4-bit
chroma) the pins C4...C7 are used.
Pin 51 – Supply Voltage, Digital Circuitry VSUPD*
Pin 52 – Ground, Digital Circuitry GNDD*
Digital Circuitry Input Reference
Pin 53 – Main Clock Input LLC2 (53) (Fig. 4–16)
This is the input for the line-locked clock signal. The
frequency can be 27, 32, or 40.5 MHz.
Pin 54...61 – Picture Bus Luma Y0...Y7 (Fig. 4–3)
The Picture Bus Luma lines carry the digital luminance
data.
Pin 62 – Line-Locked Clock Input LLC1 (Fig. 4–16)
This is the reference clock for the single frequency
input sync signals required in a FIFO application. The
frequency can be 13.5, 16, or 20.25 MHz.
39
DDP 3310B
Pin 63 – Sync Signal Input HS (Fig. 4–3)
This pin gets the horizontal sync information. Either
single or double horizontal frequency or VGA horizontal sync signal.
Pin 64 – Sync Signal Input VS (Fig. 4–3)
This pin gets the vertical sync information. Either single or double vertical frequency or VGA vertical sync
signal.
ADVANCE INFORMATION
* Application Note:
All ground pins should be connected separately with
short and low-resistive lines to a central power supply
ground. Accordingly, all supply pins should be connected separately with short and low-resistive lines to
the power supply. Decoupling capacitors from VSUPP
to GNDP, VSUPD to GNDD, and VSUPO to GNDO are
recommended to be placed as closely as possible to
the pins.
Pin 65, 66 – Crystal Output / Input XTAL2 / XTAL1
(Fig. 4–19)
These pins are connected to an 5-MHz crystal oscillator. The security unit for the HOUT signal uses this
clock signal as reference.
Pin 67 – I2C Data Input/Output SDA (Fig. 4–20)
Via this pin the I2C-bus data are written to or read from
the DDP 3310B.
Pin 68 – I2C Clock Input SCL (Fig. 4–20)
Via this pin, the clock signal for the I2C-bus will be supplied. The signal can be pulled down by an internal
transistor.
40
Micronas
DDP 3310B
ADVANCE INFORMATION
4.4. Pin Configuration
VSUPP
GNDP
SCL
VS2
SDA
FIFORRD
XTAL1
FIFORD
XTAL2
FIFOWR
VS
FIFORWR
HS
HOUT
LLC1
HFLB
Y7
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
SAFETY
10
60
Y6
VPROT
11
59
Y5
FREQSEL
12
58
Y4
CM1
13
57
Y3
CM0
14
56
Y2
RSW2
15
55
Y1
RSW1
16
54
Y0
SENSE
17
53
LLC2
GNDM
18
52
GNDD
VERT+
19
51
VSUPD
VERT−
20
50
C7
EW
21
49
C6
XREF
22
48
C5
SVM
23
47
C4
ROUT
24
46
C3
GOUT
25
45
C2
BOUT
26
44
C1
DDP 3310B
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
C0
GNDO
VSUPO
HCS
VRD/BCS
PWM2
FBLIN1
PWM1
RIN1
RESQ
GIN1
TEST
BIN1
BIN2
FBLIN2
GIN2
RIN2
Fig. 4–2: 68-pin PLCCK package
Micronas
41
DDP 3310B
ADVANCE INFORMATION
4.5. Pin Circuits
VSUPD
P
N
GNDO
N
Fig. 4–8: Output pin 15 (RSW2)
GNDD
Fig. 4–3: Input pins 3, 12, 13, 14, 43 to 50, 54 to 61,
63, and 64 (VS2, FREQSEL, CM1, CM0, C[7:0],
Y[7:0], HS, VS)
P
to ADC
N
N
VSUPP
VSUPO
P
Fig. 4–9: Input/Output pin 16 (RSW1)
N
GNDP
P
Fig. 4–4: Output pins 4 to 7
(FIFORRD, FIFORD, FIFOWR, FIFORWR)
N
Fig. 4–10: Input pin 17 (SENSE)
N
VSUPO
GNDP
P
Fig. 4–5: Output pin 8 (HOUT)
VEWXR
VREF
Fig. 4–6: Input pins 9 to 11
(HFLB, SAFETY, VPROT)
P
P
N
N
Flyback
+
N
GNDO
Fig. 4–11: Output pins 19 and 20 (VERT+, VERT−)
VREF
Fig. 4–7: Input pins 30 and 34
(FBLIN1, FBLIN2)
42
Micronas
DDP 3310B
ADVANCE INFORMATION
VSUPD
VSUPO
P
P
P
N
VEWXR
GNDD
N
Fig. 4–17: Output pins 40 and 41 (PWM1, PWM2)
GNDO
Fig. 4–12: Output pin 21 (EW)
VSUPO
P
VSUPO
VRD/BCS
+
-
ref. current
int. ref.
voltage
XREF
N
GNDO
Fig. 4–18: Input pin 42 (HCS)
GNDO
Fig. 4–13: Input pins 22 and 29 (XREF, VDR/BCS)
VSUPD
N
P
XTAL1
XTAL2
N
Bias
N
N
P
GNDO
Fig. 4–14: Output pins 23 to 26
(SVM, ROUT, GOUT, BOUT)
GNDD
Fig. 4–19: Input pin 66 (XTAL1), Output pin 65 (XTAL2)
N
Clamping
N
N
GNDO
GNDD
Fig. 4–15: Input pins 31 to 33 and 35 to 37
(R/G/BIN1, R/G/BIN2)
Fig. 4–20: Input/Output pins 67 and 68 (SDA, SCL)
Fig. 4–16: Input pins 38, 39, 53, and 62
(TEST, RESQ, LLC2, LLC1)
Micronas
43
DDP 3310B
ADVANCE INFORMATION
4.6. Electrical Characteristics
4.6.1. Absolute Maximum Ratings
Symbol
Parameter
Pin Name
Min.
Max.
Unit
TA
Ambient Operating Temperature
−
0
65
°C
TC
Case Temperature
−
0
105
°C
TS
Storage Temperature
−
−40
125
°C
VSUP
Supply Voltage
All Supply
Pins
−0.3
6
V
VI
Input Voltage
All Inputs
−0.3
VSUP(P/D/O)+0.3
V
VO
Output Voltage
All Outputs
(except
HOUT)
−0.3
VSUP(P/D/O)+0.3
V
VGD
Voltage between different ground pins
All Ground
Pins
−
0.3
V
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
4.6.2. Recommended Operating Conditions
Symbol
Parameter
TA
Min.
Typ.
Max.
Unit
Ambient Operating Temperature
0
−
65
°C
VSUP
Supply Voltages, all Supply Pins
(except output pin driver supply)
4.75
5.0
5.25
V
VSUPP
Output Pin Driver Supply Voltage
VSUPP
3.0
5.0
5.25
V
fsys
Clock Frequency
LLC2
25.1
−
43.3
MHz
Rxref
RGB − DAC Current Defining Resistor
XREF
9.5
10
10.5
kΩ
44
Pin Name
Micronas
DDP 3310B
ADVANCE INFORMATION
4.6.3. Recommended Crystal Characteristics
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
fP
Parallel Resonance Frequency
@ CL=16 pF
XTAL1
−
5
−
MHz
XTAL2
RR
Series Resonance Resistance
@ CL=16 pF, fP=5 MHz
−
−
150
Ω
C0
Shunt (Parallel) Capacitance
−
−
6
pF
CLext
External Load Capacitances (from both
crystal pins connected to GNDD)
−
27
−
pF
see
Remarks!
Remarks:
External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load
capacitance (including the capacitance of the printed circuit board and the IC package) to the required load
capacitance CL of the crystal. A higher capacitance will result in a lower clock frequency. The exact value of the
matching capacitor should be determined in the actual application (PCB layout).
CLext = 2 (CL − CPCB − CPACK)
4.6.4. Characteristics
Min./Max. values at: TA = 0 to 65 °C, VSUP(P/D/O) = 4.75 to 5.25 V, Rxref = 10 kΩ, f = 27 MHz
Typical values at:
TC = 70 °C,
VSUP(P/D/O) = 5 V,
Rxref = 10 kΩ, f = 27 MHz
4.6.4.1. General Characteristics
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
IVSUPO
Current Consumption
Analog Back-end
VSUPO
−
65
−
mA
IVSUPD
Current Consumption
Digital Processing
VSUPD
−
225
−
mA
IVSUPP
Current Consumption
Output Pin Driver
VSUPP
−
10
−
mA
PTOT
Total Power Dissipation
−
1.5
−
W
IL
Input and Output Leakage Current
(if not otherwise specified)
−
−
0.1
µA
Micronas
45
DDP 3310B
ADVANCE INFORMATION
4.6.4.2. Line-locked Clock Inputs: LLC1, LLC2 (see Fig. 4–21)
Symbol
Parameter
VIL
Input Low Voltage
Pin Name
Min.
Typ.
Max.
Unit
LLC1
−
−
0.8
V
2.0
−
−
V
LLC2
VIH
Input High Voltage
tSK
Clock skew
−
−
±6
ns
tR, tF
Clock Rise / Fall Time
−
−
5
ns
CIN
Input Capacitance
−
5
−
pF
1/TLLC1
Clock Frequency
12.0
−
17.2
MHz
tWL1
Clock Low Time
26
−
−
ns
tWH1
Clock High Time
26
−
1/TLLC2
Clock Frequency
25.1
−
43.3
MHz
tWL2
Clock Low Time
7
−
−
ns
tWH2
Clock High Time
7
−
−
ns
LLC1
LLC2
Test Conditions
ns
4.6.4.3. Luma, Chroma Inputs (see Fig. 4–21)
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
Y[0...7]
−
−
0.8
V
2.0
−
−
V
C[0...7]
VIH
Input High Voltage
tIS
Input Setup Time
7
−
−
ns
tIH
Input Hold Time
6
−
−
ns
CIN
Input Capacitance
−
5
−
pF
Test Conditions
TLLC1
tWH1
tWL1
VIH
LLC1
VIL
tR1
tSK tF1
tSK
TLLC2
tWH2
tWL2
VIH
LLC2
VIL
tR2
tF2
tIS
tIH
Y,C Inputs
VIH
VIL
Fig. 4–21: Line-locked clock input pins and luma/chroma bus input timing
46
Micronas
DDP 3310B
ADVANCE INFORMATION
4.6.4.4. Reset Input, Test Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
RESQ
TEST
−
−
2.0
V
VIH
Input High Voltage
3.2
−
−
V
CIN
Input Capacitance
−
5
−
pF
Test Conditions
4.6.4.5. Half-Contrast Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
HCS
−
−
0.8
V
VIH
Input High Voltage
2.0
−
−
V
CIN
Input Capacitance
−
5
−
pF
Micronas
Test Conditions
47
DDP 3310B
ADVANCE INFORMATION
4.6.4.6. I2C-Bus Interface
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
SDA
SCL
−
−
1.5
V
VIH
Input High Voltage
3.0
−
−
V
VOL
Output Low Voltage
−
−
0.6
V
IOL
Output Low Current
−
−
10
mA
CIN
Input Capacitance
−
−
5
pF
tF
Signal Fall Time
−
−
300
ns
CL = 400 pF
tR
Signal Rise Time
−
−
300
ns
CL = 400 pF
fSCL
Clock Frequency
0
−
400
kHz
tLOW
Low Period of SCL
1.3
−
−
µs
tHIGH
High Period of SCL
0.6
−
−
µs
tIS
Input Data Set Up Time
to SCL high
55
−
−
ns
tIH
Input Data Hold Time
to SCL Low
55
−
tOS
Output Data Set Up Time
to SCL High
100
−
−
ns
tOH
Output Data Hold Time
to SCL Low
15
−
900
ns
SCL
SDA
Test Conditions
IOL = 6 mA
ns
1/fSCL
tHIGH
tLOW
VIH
SCL
VIL
tR
tIS
tF
tIS
SDA as
input
VIH
VIL
tOS
SDA as
output
tOH
VIH
VIL
Fig. 4–22: I2C bus timing
48
Micronas
DDP 3310B
ADVANCE INFORMATION
4.6.4.7. Horizontal and Vertical Sync Inputs and Clock and Freqency Select Pins
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
−
−
0.8
V
VIH
Input High Voltage
2.0
−
−
V
CIN
Input Capacitance
HS
VS
VS2
CM0
CM1
FREQSEL
−
5
−
pF
tIS
Input Setup Time
6
−
−
ns
tIH
Input Hold Time
7
−
−
ns
HS
VS
VS2
Test Conditions
VIH
LLC1
VIL
tIH
tIS
VIH
HS, VS, VS2 Inputs
VIL
Fig. 4–23: Sync Inputs referenced to line-locked clock
4.6.4.8. Horizontal Flyback Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
HFLB
−
−
1.8
V
VIH
Input High Voltage
2.6
−
−
V
VIHST
Input Hysteresis
0.1
−
−
V
Test Conditions
4.6.4.9. FIFO Control Signals
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VOL
Output Low Voltage
FIFORRD
−
−
0.4
V
IOL = 1.6 mA
I2C[PSTSY] = 6
FIFORD
VOH
tOT
Output High Voltage
FIFORWR
FIFOWR
Output Transition Time
VSUPP
− 0.4
−
−
10
VSUPP
V
−IOL = 1.6 mA
I2C[PSTSY] = 6
20
ns
CLOAD = 30pF
I2C[PSTSY] = 6
IOL
Micronas
Output Current
−10
−
10
mA
49
DDP 3310B
ADVANCE INFORMATION
4.6.4.10. PWM Outputs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VOL
Output Low Voltage
PWM1
−
−
0.4
V
tOT
Output High Voltage
Output Transition Time
IOL = 1.6 mA
I2C[PSTPR1/2] = 0
PWM2
VOH
Test Conditions
VSUPD
− 0.4
−
−
−
VSUPD
V
−IOL = 1.6 mA
I2C[PSTPR1/2] = 0
20
ns
CLOAD = 10 pF
Rlp = 4.7 kΩ
Clp = 100 nF
I2C[PSTPR1/2] = 0
4.6.4.11. Horizontal Drive Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VOL
Output Low Voltage
HOUT
−
−
0.4
V
IOL = 10 mA
VOH
Output High Voltage
(Open-Drain Stage)
−
−
8
V
external pull-up resistor
tOF
Output Fall Time
−
8
20
ns
CLOAD = 30 pF
IOL
Output Low Current
−
−
10
mA
4.6.4.12. Vertical Protection Input (see Section 2.3.9.)
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIA
Input Threshold A
VPROT
1.2
1.0
0.8
V
VIB
Input Threshold B
1.7
1.5
1.3
V
VIHST
Input Hysteresis A and B
0.1
−
−
V
50
Test Conditions
Micronas
DDP 3310B
ADVANCE INFORMATION
4.6.4.13. Horizontal Safety Input (see Section 2.3.9.)
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIA
Input Threshold A
SAFETY
2.5
2.2
1.9
V
VIB
Input Threshold B
3.8
3.5
3.2
V
VIHST
Input Hysteresis A and B
0.1
−
−
V
Test Conditions
4.6.4.14. Vertical and East/West D/A Converter Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Resolution
EW
VERT+
VERT−
−
15
−
bit
−
0
−
V
Rload = 6.8 kΩ
Rxref = 10 kΩ
VOMIN
Minimum Output Voltage
VOMAX
Maximum Output Voltage
2.82
3
3.2
V
Rload = 6.8 kΩ
Rxref = 10 kΩ
IDACN
Full scale DAC Output
Current
415
440
465
µA
Rxref = 10 kΩ
PSRR
Power Supply Rejection
Ratio
−
20
−
dB
4.6.4.15. Sense A/D Converter Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VI255
Input Voltage for code 255
SENSE
RSW1
1.4
1.54
1.7
V
C0
Digital Output for zero Input
−
−
16
LSB
RI
Input Impedance
1
−
−
MΩ
−
−
50
Ω
Test Conditions
Range Switch Outputs
RON
Output On Resistance
IMax
Maximum Current
−
−
15
mA
ILEAK
Leakage Current
−
−
600
nA
Micronas
RSW1
RSW2
IOL = 10 mA
RSW High Impedance
51
DDP 3310B
ADVANCE INFORMATION
4.6.4.16. Analog RGB and Fast-Blank Inputs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VRGBIN
External RGB Input
Voltage Range
RIN1
GIN1
BIN1
−0.3
−
1.1
V
VRGBIN
Nominal RGB Input Voltage
Peak-to-Peak
0.5
0.7
1.0
VPP
VRGBIN
RGB Input Voltage for
Maximum Output Current
−
0.44
−
Contrast setting: 511
−
0.7
−
Contrast setting: 323
−
1.1
−
Contrast setting: 204
External RGB Input
Coupling Capacitor
−
10
−
nF
Clamp Pulse Width
1.6
−
−
µs
CIN
Input Capacitance
−
−
13
pF
IIL
Input Leakage Current
−0.5
−
0.5
µA
VCLIP
RGB Input Voltage for
Clipping Current
−
2
−
V
VCLAMP
Clamp Level at Input
40
60
80
mV
Clamping ON
VINOFF
Offset Level at Input
−10
−
10
mV
Extrapolated from
VIN = 100 and 200 mV
VINOFF
Offset Level Match at Input
−10
−
10
mV
Extrapolated from
VIN = 100 and 200 mV
RCLAMP
Clamping-ON-Resistance
−
140
−
Ω
VFBLOFF
FBLIN Low Level
−
−
0.5
V
VFBLON
FBLIN High Level
0.9
−
−
V
VFBLTRIG
Fast-Blanking Trigger
Level typical
−
0.7
−
tPID
Delay Fast Blanking to
RGBOUT from midst of
FBLIN-transition
to 90% of RGBOUT- transition
−
8
15
ns
Difference of Internal Delay
to External RGBin Delay
−5
−
+5
ns
Switch-Over-Glitch
−
0.5
−
pAs
CRGBIN
52
RIN2
GIN2
BIN2
FBLIN1
FBLIN2
Test Conditions
SCART Spec:
0.7 V ±3 dB
Clamping OFF,
VIN = −0.3...3 V
Internal RGB = 3.75 mA
(Full Scale)
Internal Brightness = 0
External Brightness =
1.5 mA (Full Scale)
RGBin = 0
VFBLOFF = 0.4 V
VFBLON = 1.0 V
Rise and fall time = 2 ns
Switch from 3.75 mA
(int.) to 1.5 mA (ext.)
Micronas
DDP 3310B
ADVANCE INFORMATION
4.6.4.17. Analog RGB Outputs, D/A Converters
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
−
10
−
bit
3.6
3.75
3.9
mA
Test Conditions
Internal RGB Signal D/A Converter Characteristics
Resolution
ROUT
GOUT
BOUT
IOUT
Full Scale Output Current
Rref = 10 kΩ
IOUT
Differential Non-Linearity
−
−
1
LSB
IOUT
Integral Non-Linearity
−
−
2
LSB
IOUT
Glitch Pulse Charge
−
0.5
−
pAs
Ramp signal, 25 Ω output
termination
IOUT
Rise and Fall Time
−
3
−
ns
10 % to 90 %, 90 % to
10 %
IOUT
Intermodulation
−
−
−50
dB
2/2.5 MHz full scale
IOUT
Signal to Noise
+50
−
−
dB
Signal: 1MHz full scale
Bandwidth: 10MHz
IOUT
Matching R-G, R-B, G-B
−2
−
2
%
R/B/G Crosstalk
one channel talks
two channels talk
−
−
−46
dB
Passive channel:
IOUT =1.88 mA
Crosstalk-Signal: 1.25
MHz, 3.75 mAPP
RGB Input Crosstalk from
external RGB
one channel talks
two channels talk
three channels talk
−
−
−
−
−
−
−50
−50
−50
dB
dB
dB
−
9
−
bit
39.2
40
40.8
%
Internal RGB Brightness D/A Converter Characteristics
Resolution
ROUT
GOUT
BOUT
IBR
Full Scale Output Current
relative
IBR
Full Scale Output Current
absolute
−
1.5
−
mA
IBR
Differential Non-Linearity
−
−
1
LSB
IBR
Integral Non-Linearity
−
−
2
LSB
IBR
Match R-G, R-B, G-B
−2
−
2
%
IBR
Match to digital RGB
R-R, G-G, B-B
−2
−
2
%
Micronas
Ref to max. digital RGB
53
DDP 3310B
Symbol
Parameter
ADVANCE INFORMATION
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
−
9
−
bit
58.8
60
61.2
%
Full Scale Output Current
absolute
−
2.25
−
mA
Differential Non-Linearity
−
−
1
LSB
Integral Non-Linearity
−
−
2
LSB
Matching to digital RGB
R-R, G-G, B-B
−2
−
2
%
−
1
−
bit
19.6
20
20.4
%
−
0.75
−
mA
−
9
−
bit
96
100
104
%
Ref. to max. Digital RGB
VIN = 0.7 VPP, contrast =
323
Full Scale Output Current
absolute
−
3.75
−
mA
Same as Digital RGB
Contrast Adjust Range
−
16:511
−
Gain Match R-G, R-B, G-B
−2
−
2
%
Measured at RGB
Outputs VIN = 0.7 V,
contrast = 323
Gain Match to RGB-DACs
R-R, G-G, B-B
−3
−
3
%
Measured at RGB
Outputs VIN = 0.7 V,
contrast = 323
R/B/G Input Crosstalk
one channel talks
two channels talk
−
−
−46
dB
Passive channel:
VIN = 0.7 V, contrast =
323 Crosstalk signal:
1.25 MHz, 3.75 mAPP
RGB Input Crosstalk from
Internal RGB
one channel talks
two channels talk
tree channels talk
−
−
−50
dB
RGB Output Cutoff D/A Converter Characteristics
Resolution
ICUT
Full Scale Output Current
relative
ROUT
GOUT
BOUT
Ref to max. digital RGB
RGB Output Ultrablack D/A Converter Characteristics
Resolution
IUB
Full Scale Output Current
relative
ROUT
GOUT
BOUT
Full Scale Output Current
absolute
Ref to max. digital RGB
External RGB Voltage/Current Converter Characteristics
Resolution
IEXOUT
CR
54
Full Scale Output Current
relative
ROUT
GOUT
BOUT
Micronas
DDP 3310B
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
RGB Input Noise and
Distortion
ROUT
GOUT
BOUT
−
−
−50
dB
VIN=0.7 VPP at 1 MHz
contrast = 323
Bandwidth: 10 MHz
15
−
MHz
VIN = 0.7 VPP,
contrast =323
RGB Input Bandwidth -3 dB
VRGBO
VOUTC
RGB Input THD
−
−
−50
−40
−
−
dB
dB
Input signal 1 MHz
Input signal 6 MHz
VIN = 0.7 VPP
contrast =323
Differential Non-Linearity of
Contrast Adjust
−
−
1.0
LSB
VIN = 0.44V
Integral Non-Linearity of
Contrast Adjust
−
−
7
LSB
R,G,B Output Voltage
−1.0
−
0.3
V
Referred to VSUPO
R,G,B Output Load
Resistance
−
−
100
Ω
Ref. to VSUPO
RGB Output Compliance
−1.5
−1.3
−1.2
V
Ref. to VSUPO Sum of
max. Current of RGBDACs and max. Current
of Int. Brightness DACs is
2 % degraded
−
9
−
bit
39.2
40
40.8
%
Full Scale Output Current
absolute
−
1.5
−
mA
Differential Non-Linearity
−
−
1
LSB
Integral Non-Linearity
−
−
2
LSB
Matching R-G, R-B, G-B
−2
−
2
%
Matching to digital RGB
R-R, G-G, B-B
−2
−
2
%
External RGB Brightness D/A Converter Characteristics
Resolution
IEXBR
Micronas
Full-Scale Output Current
relative
ROUT
GOUT
BOUT
Ref to max. digital RGB
55
DDP 3310B
ADVANCE INFORMATION
4.6.4.18. Scan Velocity Modulation Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Resolution
SVMOUT
−
8
−
bit
Test Conditions
IOUT
Full-Scale Output Current
1.55
1.875
2.25
mA
IOUT
Differential Non-Linearity
−
−
0.5
LSB
IOUT
Integral Non-Linearity
−
−
1
LSB
IOUT
Glitch Pulse Charge
−
0.5
−
pAs
Ramp, output line is
terminated on both ends
with 50 Ω
IOUT
Rise and Fall Time
−
3
−
ns
10 % to 90 %, 90 % to
10 %
Test Conditions
4.6.4.19. DAC Reference, Beam Current Safety
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VDACREF
DAC-Ref. Voltage
VRD/BCS
2.38
2.50
2.67
V
DAC-Ref. Output
resistance
VRD/BCS
18
25
32
kΩ
DAC-Ref. Voltage
Bias Current Generation
XREF
2.25
2.34
2.43
V
VXREF
56
Rxref = 10 kΩ
Micronas
DDP 3310B
ADVANCE INFORMATION
+5 V
+5 V
+5 V
+5 V
+5 V
+5 V
+5 V
5. Application Circuit
Micronas
57
DDP 3310B
58
ADVANCE INFORMATION
Micronas
ADVANCE INFORMATION
Micronas
DDP 3310B
59
DDP 3310B
ADVANCE INFORMATION
6. Data Sheet History
1. Advance Information: “DDP 3310B Display and
Deflection Processor, July 9, 1999, 6251-464-1AI. First
release of the advance information.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-464-1AI
60
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas