19-0876; Rev 1; 5/96 CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs ________________________Applications Digital Signal Processing High-Speed Data Acquisition Telecommunications Audio Systems High-Speed Servo Loops Low-Power Data Loggers _________________Pin Configurations ____________________________Features ♦ Fast Conversion Time: 5µs (MX7575) 10µs (MX7576) ♦ Built-In Track/Hold Function (MX7575) ♦ Low Total Unadjusted Error (±1LSB max) ♦ 50kHz Full-Power Signal Bandwidth (MX7575) ♦ Single +5V Supply Operation ♦ 8-Bit µP Interface ♦ 100ns Data-Access Time ♦ Low Power: 15mW ♦ Small-Footprint Packages ______________Ordering Information PART TEMP. RANGE MX7575JN 0°C to +70°C PIN-PACKAGE 18 Plastic DIP MX7575KN 0°C to +70°C 18 Plastic DIP MX7575JCWN 0°C to +70°C 18 Wide SO MX7575KCWN 0°C to +70°C 18 Wide SO MX7575JP 0°C to +70°C 20 PLCC MX7575KP 0°C to +70°C 20 PLCC MX7575J/D 0°C to +70°C Dice* MX7575AQ -25°C to +85°C 18 CERDIP** MX7575BQ -25°C to +85°C 18 CERDIP** Ordering Information continued at end of data sheet. * Contact factory for dice specifications. ** Contact factory for availability. INL (LSB) ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1 ±1/2 _______________Functional Diagrams VDD 18 TOP VIEW CS 1 18 VDD RD 2 TP (MODE) 3 17 REF MX7575 MX7576 BUSY 4 16 AIN 15 AGND CLK 5 13 D1 D6 7 12 D2 8 11 D3 DGND 9 10 D4 ( ) ARE FOR MX7576 ONLY. 16 MX7575 TRACK/ HOLD DIP/SO Pin Configurations continued at end of data sheet. COMP AGND 15 REF 17 DAC 14 D0 (LSB) D7 (MSB) 6 D5 AIN CLK CS RD TP 5 1 2 3 CLOCK OSCILLATOR SAR 6 CONTROL LOGIC 4 BUSY Functional Diagrams continued at end of data sheet. LATCH AND THREE-STATE OUTPUT DRIVERS .. D7 D0 14 9 DGND ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MX7575/MX7576 _______________General Description Maxim’s MX7575/MX7576 are high-speed (5µs/10µs), microprocessor (µP) compatible, 8-bit analog-to-digital converters (ADCs). The MX7575 provides an on-chip track/hold function that allows full-scale signals up to 50kHz (386mV/µs slew rate) to be acquired and digitized accurately. Both ADCs use a successive-approximation technique to achieve their fast conversions and low power dissipation. The MX7575/MX7576 operate with a +5V supply and a 1.23V external reference. They accept input voltages ranging from 0V to 2VREF. The MX7575/MX7576 are easily interfaced to all popular 8-bit µPs through standard CS and RD control signals. These signals control conversion start and data access. A BUSY signal indicates the beginning and end of a conversion. Since all the data outputs are latched and three-state buffered, the MX7575/MX7576 can be directly tied to a µP data bus or system l/O port. Maxim also makes the MAX165, a plug-in replacement for the MX7575 with an internal 1.23V reference. For applications that require a differential analog input and an internal reference, the MAX166 is recommended. MX7575/MX7576 CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to AGND...............................................................-0.3V, +7V VDD to DGND ..............................................................-0.3V, +7V AGND to DGND ...............................................-0.3V, VDD + 0.3V Digital Input Voltage to DGND (CS, RD, TP, MODE) ......................................-0.3V, VDD + 0.3V Digital Output Voltage to DGND (BUSY, D0–D7) ..............................................-0.3V, VDD + 0.3V CLK Input Voltage to DGND ............................-0.3V, VDD + 0.3V REF to AGND ...................................................-0.3V, VDD + 0.3V AIN to AGND....................................................-0.3V, VDD + 0.3V Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 11.11mW/°C above +70°C) ...............889mW Wide SO (derate 9.52mW/°C above +70°C)..................762mW CERDIP (derate 10.53mW/°C above +70°C) .................842mW PLCC (derate 10.00mW/°C above +70°C) ....................800mW Operating Temperature Ranges MX757_J/K ............................................................0°C to +70°C MX757_A/B ........................................................-25°C to +85°C MX757_JE/KE ....................................................-40°C to +85°C MX757_S/T.......................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering,10sec) ..............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V DD = +5V; V REF = 1.23V; AGND = DGND = 0V; f CLK = 4MHz external for MX7575; f CLK = 2MHz external for MX7576; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY Resolution 8 Total Unadjusted Error TUE Relative Accuracy INL Bits MX757_K/B/T ±1 MX757_J/A/S ±2 MX757_K/B/T ±1/2 MX757_J/A/S ±1 No-Missing-Codes Resolution 8 ±1 ±5 Offset Error (Note 1) LSB ppm/°C ±1/2 Offset Tempco LSB Bits Full-Scale Error Full-Scale Tempco LSB ±5 LSB ppm/°C ANALOG INPUT Voltage Range 1LSB = 2VREF/256 0 DC Input Impedance Slew Rate, Tracking Signal-to-Noise Ratio (Note 2) 2VREF 10 MX7575 0.386 SNR MX7575, VIN = 2.46Vp-p at 10kHz, Figure 13 Reference Voltage VREF ±5% variation for specified performance Reference Current IREF V MΩ 45 V/µs dB REFERENCE INPUT LOGIC INPUTS CS, RD, MODE Input Low Voltage VINL Input High Voltage VINH Input Current IIN Input Capacitance (Note 2) CIN 2 1.23 V 500 µA 0.8 V 2.4 VIN = 0V or VDD V TA = +25°C ±1 TA = TMIN to TMAX ±10 _______________________________________________________________________________________ 10 µA pF CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs (V DD = +5V; V REF = 1.23V; AGND = DGND = 0V; f CLK = 4MHz external for MX7575; f CLK = 2MHz external for MX7576; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.8 V CLOCK Input Low Voltage VINL Input High Voltage VINH 2.4 Input Low Current IINL VIN = 0V Input High Current IINH VIN = VDD Output Low Voltage VOL ISINK = 1.6mA Output High Voltage VOH ISOURCE = 40µA V MX757_J/A/K/B 700 MX757_S/T 800 MX757_J/A/K/B 700 MX757_S/T 800 µA µA LOGIC OUTPUTS (D0–D7, BUSY) Floating State Leakage Current VOUT = 0V to VDD, D0–D7 Floating State Output Capacitance (Note 2) D0–D7 0.4 4.0 V V TA = +25°C ±1 TA = TMIN to TMAX ±10 10 µA pF CONVERSION TIME (Note 3) Conversion Time with External Clock MX7575: fCLK = 4MHz MX7576: fCLK = 2MHz Conversion Time with Internal Clock Using recommended clock components: RCLK = 100kΩ, CCLK = 100pF; TA = +25°C POWER REQUIREMENTS (Note 4) Supply Voltage VDD Supply Current IDD Power Dissipation Power-Supply Rejection Note 1: Note 2: Note 3: Note 4: 5 10 µs MX7575 5 15 MX7576 10 30 µs ±5% for specified performance MX757_J/A/K/B MX757_S/T 5 3 V 6 7 15 4.75V < VDD < 5.25V ±1/4 mA mW LSB Offset Error is measured with respect to an ideal first-code transition that occurs at 1/2LSB. Sample tested at +25°C to ensure compliance. Accuracy may degrade at conversion times other than those specified. Power-supply current is measured when MX7575/MX7576 are inactive, i.e.: For MX7575 CS = RD = BUSY = high; For MX7576 CS = RD = BUSY = MODE = high. _______________________________________________________________________________________ 3 MX7575/MX7576 ELECTRICAL CHARACTERISTICS (continued) MX7575/MX7576 CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs TIMING CHARACTERISTICS (Note 5) (VDD = +5V, VREF = 1.23V, AGND = DGND = 0V.) TA = +25°C PARAMETER SYMBOL TA = TMIN to TMAX ALL CONDITIONS MIN J/K/A/B MAX MIN MAX S/T MIN CS to RD Setup Time t1 RD to BUSY Propagation Time t2 Data-Access Time after RD t3 RD Pulse Width t4 100 100 120 CS to RD Hold Time t5 0 0 0 Data-Access Time after BUSY t6 (Note 6) Data-Hold Time t7 (Note 7) BUSY to CS Delay t8 0 (Note 6) 0 0 0 ns 100 100 120 ns 100 100 120 ns 80 10 UNITS MAX 80 80 10 0 80 10 ns ns 100 ns 100 ns 0 ns Note 5: Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tr = tf = 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V. Note 6: t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Note 7: t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. ______________________________________________________________Pin Description PIN NAME FUNCTION DIP/SO PLCC 1 2 CS Chip Select Input. CS must be low for the device to be selected or to recognize the RD input. 2 3 RD Read Input. RD must be low to access data. RD is also used to start conversions. See the Microprocessor Interface section. 3 4 4 5 BUSY 5 6 CLK 6 7 D7 7, 8 8, 9 D6, D5 Three-State Data Outputs, bits 6 and 5 9 10 DGND Digital Ground 10–13 12–15 D4–D1 Three-State Data Outputs, bits 4–1 14 16 D0 15 17 AGND 16 18 AIN Analog Input. 0V to 2VREF input range. 17 19 REF Reference Input. +1.23V nominal. 18 20 VDD Power-Supply Voltage. +5V nominal. — 1, 11 N.C. No Connect 4 TP Test Point. Connect to VDD. (MX7575) MODE Mode Input. MODE = low puts the ADC into its asynchronous conversion mode. MODE has to be (MX7576) tied high for the synchronous conversion mode and the ROM interface mode. BUSY Output. BUSY going low indicates the start of a conversion. BUSY going high indicates the end of a conversion. External Clock Input/Internal Oscillator Pin for frequency setting RC components. Three-State Data Output, bit 7 (MSB) Three-State Data Output, bit 0 (LSB) Analog Ground _______________________________________________________________________________________ CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs +5V 3k D_ D_ 3k D_ 100pF 100pF DGND DGND a) HIGH-Z TO VOH 3k b) HIGH-Z TO VOL NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS D_ 3k 10pF DGND a) VOH TO HIGH-Z 10pF DGND b) VOL TO HIGH-Z NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS Figure 1. Load Circuits for Data-Access Time Test Figure 2. Load Circuits for Data-Hold Time Test _______________Detailed Description are performed. In the slow-memory interface mode, CS and RD are taken low to start a conversion and they remain low until the conversion ends, at which time the conversion result is latched. This mode is designed for µPs that can be forced into a wait state. In the ROM interface mode, however, the µP is not forced into a wait state. A conversion is started by taking CS and RD low, and data from the previous conversion is read. At the end of the most recent conversion, the µP executes a read instruction and starts another conversion. For the MX7575, TP should be hard-wired to V DD to ensure proper operation of the device. Spurious signals may occur on TP, or excessive currents may be drawn from VDD if TP is left open or tied to a voltage other than VDD. Converter Operation The MX7575 and MX7576 use the successive-approximation technique to convert an unknown analog input voltage to an 8-bit digital output code (see Functional Diagrams). The MX7575 samples the input voltage on an internal capacitor once (at the beginning of the conversion), while the MX7576 samples the input signal eight times during the conversion (see MX7575 Track/Hold and MX7576 Analog Input sections). The internal DAC is initially set to half scale, and the comparator determines whether the input signal is larger than or smaller than half scale. If it is larger than half scale, the DAC MSB is kept. But if it is smaller, the MSB is dropped. At the end of each comparison phase, the SAR (successive-approximation register) stores the results of the previous decision and determines the next trial bit. This information is then loaded into the DAC after each decision. As the conversion proceeds, the analog input is approximated more closely by comparing it to the combination of the previous DAC bits and a new DAC trial bit. After eight comparison cycles, the eight bits stored in the SAR are latched into the output latches. At the end of the conversion, the BUSY signal goes high, and the data in the output latches is ready for microprocessor (µP) access. Furthermore, the DAC is reset to half scale in preparation for the next conversion. Microprocessor Interface The CS and RD logic inputs are used to initiate conversions and to access data from the devices. The MX7575 and MX7576 have two common interface modes: slowmemory interface mode and ROM interface mode. In addition, the MX7576 has an asynchronous conversion mode (MODE pin = low) where continuous conversions Slow-Memory Mode Figure 3 shows the timing diagram for slow-memory interface mode. This is used with µPs that have a waitstate capability of at least 10µs (such as the 8085A), where a read instruction is extended to accommodate slow-memory devices. A conversion is started by executing a memory read to the device (taking CS and RD low). The BUSY signal (which is connected to the µP READY input) then goes low and forces the µP into a wait state. The MX7575 track/hold, which had been tracking the analog input signal, holds the signal on the third falling clock edge after RD goes low (Figure 12). The MX7576, however, samples the analog input eight times during a conversion (once before each comparator decision). At the end of the conversion, BUSY returns high, the output latches and buffers are updated with the new conversion result, and the µP completes the memory read by acquiring this new data. The fast conversion time of the MX7575/MX7576 ensures that the µP is not forced into a wait state for an excessive amount of time. Faster versions of many µPs, _______________________________________________________________________________________ 5 MX7575/MX7576 +5V MX7575/MX7576 CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs CS CS t5 t1 RD t1 t5 RD t2 t8 t2 tCONV BUSY t4 BUSY t3 DATA HIGHIMPEDANCE BUS t6 t7 NEW DATA OLD DATA HIGHIMPEDANCE BUS Figure 3. Slow-Memory Interface Timing Diagram A8–A15 ADDRESS BUS TP/MODE ADDRESS DECODE S0 ALE AD0–AD7 ADDRESS LATCH CS MX7575* RD MX7576 BUSY t3 t7 OLD DATA t7 NEW DATA HIGH-IMPEDANCE BUS HIGHIMPEDANCE BUS Figure 5. ROM Interface Timing Diagram A0–A15 +5V 8085A-2 t3 HIGHDATA IMPEDANCE BUS ADDRESS BUS +5V TP/MODE 6502-6809 R/W ADDRESS EN DECODE Φ 2 OR E CS MX7575* MX7576 RD D0–D7 D0–D7 DATA BUS READY * SOME CIRCUITRY OMITTED FOR CLARITY S0 IS LOW FOR READ CYCLES D0–D7 DATA BUS * SOME CIRCUITRY OMITTED FOR CLARITY Figure 4. MX7575/MX7576 to 8085A-2 Slow-Memory Interface Figure 6. MX7575/MX7576 to 6502/6809 ROM Interface including the 8085A-2, test the status of the READY input immediately after the start of an instruction cycle. Therefore, if the MX7575/MX7576 are to be effective in placing the µP in a wait state, their BUSY output should go low very early in the cycle. When using the 8085A-2, the earliest possible indication of an upcoming read operation is provided by the S0 status signal. Thus, S0, which is low for a read cycle, should be connected to the RD input of the MX7575/MX7576. Figure 4 shows the connection diagram for the 8085A-2 to the MX7575/MX7576 in slow-memory interface mode. external clock period of BUSY going high, then the second conversion is not started. Furthermore, for correct operation in this mode, RD and CS should not go low before BUSY returns high. Figures 6 and 7 show the connection diagrams for interfacing the MX7575/MX7576 in the ROM interface mode. Figure 6 shows the connection diagram for the 6502/6809 µPs, and Figure 7 shows the connections for the Z-80. Due to their fast interface timing, the MX7575/MX7576 will interface to the TMS32010 running at up to 18MHz. Figure 8 shows the connection diagram for the TMS32010. In this example, the MX7575/MX7576 are mapped as a port address. A conversion is initiated by using an IN A and a PA instruction, and the conversion result is placed in the TMS32010 accumulator. ROM Interface Mode Figure 5 shows the timing diagram for ROM interface mode. In this mode, the µP does not need to be placed in a wait state. A conversion is started with a read instruction (RD and CS go low), and old data is accessed. The BUSY signal then goes low to indicate the start of a conversion. As before, the MX7575 track/hold acquires the signal on the third falling clock edge after RD goes low, while the MX7576 samples it eight times during a conversion. At the end of a conversion (BUSY going high), another read instruction always accesses the new data and normally starts a second conversion. However, if RD and CS go low within one 6 Asynchronous Conversion Mode (MX7576) Tying the MODE pin low places the MX7576 into a continuous conversion mode. The RD and CS inputs are only used for reading data from the converter. Figure 9 shows the timing diagram for this mode of operation, and Figure 10 shows the connection diagram for the 8085A. In this mode, the MX7576 looks like a ROM to _______________________________________________________________________________________ CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs +5V DEFER UPDATING TP/MODE MREQ CS ADDRESS EN DECODE CS MX7575* MX7576 RD RD D7 D0 DB7 DB0 t1 t5 t4 RD BUSY t3 HIGHDATA IMPEDANCE BUS DATA BUS t7 VALID DATA VALID DATA HIGH-IMPEDANCE BUS HIGHIMPEDANCE BUS * SOME CIRCUITRY OMITTED FOR CLARITY Figure 7. MX7575/MX7576 to Z-80 ROM Interface PA2 PA0 A0–A15 ADDRESS BUS TP/MODE ADDRESS EN DECODE CS MX7575* MX7576 MODE 8085A ADDRESS ENCODE RD RD DEN D7 D0 DB7 DB0 ADDRESS BUS +5V TMS32010 MEN Figure 9. MX7576 Asynchronous Conversion Mode Timing Diagram DATA BUS * SOME CIRCUITRY OMITTED FOR CLARITY ALE AD0–AD7 CS MX7576* RD ADDRESS LATCH D0–D7 DATA BUS * SOME CIRCUITRY OMITTED FOR CLARITY Figure 8. MX7575/MX7576 to TMS32010 ROM Interface Figure 10. MX7576 to 8085A Asynchronous Conversion Mode Interface the µP, in that data can be accessed independently of the clock. The output latches are normally updated on the rising edge of BUSY. But if CS and RD are low when BUSY goes high, the data latches are not updated until one of these inputs returns high. Additionally, the MX7576 stops converting and BUSY stays high until RD or CS goes high. This mode of operation allows a simple interface to the µP. the CLK input to the ADC (both should be derived from the same source), because the sampling instants occur three clock cycles after CS and RD go low. Therefore, the sampling instants occur at exactly equal intervals if the conversions are started at equal intervals. In this scheme, the output data is fed into a FIFO latch, which allows the µP to access data at its own rate. This guarantees that data is not read from the ADC in the middle of a conversion. If data is read from the ADC during a conversion, the conversion in progress may be disturbed, but the accessed data that belonged to the previous conversion will be correct. The track/hold starts holding the input on the third falling edge of the clock after CS and RD go low. If CS and RD go low within 20ns of a falling clock edge, the ADC may or may not consider this falling edge as the first of the three edges that determine the sampling instant. Therefore, the CS and RD should not be allowed to go low within this period when sampling accuracy is required. Processor Interface for Signal Acquisition (MX7575) In many applications, it is necessary to sample the input signal at exactly equal intervals to minimize errors due to sampling uncertainty or jitter. In order to achieve this objective with the previously discussed interfaces, the user must match software delays or count the number of elapsed clock cycles. This becomes difficult in interrupt-driven systems where the uncertainty in interrupt servicing delays is another complicating factor. The solution is to use a real-time clock to control the start of a conversion. This should be synchronous with _______________________________________________________________________________________ 7 MX7575/MX7576 UPDATE LATCH ADDRESS BUS Z-80 MX7575/MX7576 CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs MX7575 Track/Hold MX7576 Analog Input The track/hold consists of a sampling capacitor and a switch to capture the input signal. The simplified diagram of this block is shown in Figure 11. At the beginning of the conversion, switch S1 is closed, and the input signal is tracked. The input signal is held (switch S1 opens) on the third falling edge of clock after CS and RD go low (Figure 12). This allows a minimum of two clock cycles for the input capacitor to be charged to the input voltage through the switch resistance. The time required for the hold capacitor to settle to ±1/4LSB is typically 7ns. Therefore, the input signal is allowed ample time to settle before it is acquired by the track/hold. When a conversion ends, switch S1 closes, and the input signal is tracked. The track/hold is capable of acquiring signals with slew rates of up to 386mV/µs (or equivalently a 50kHz sine wave with 2.46Vp-p amplitude). Figure 13 shows the signal-to-noise ratio (SNR) versus input frequency for the ADC. The SNR plot is generated at a sampling rate of 200kHz using sinusoidal inputs with a peak-to-peak amplitude of 2.46V. The reconstructed sine wave is passed through a 50kHz 8th-order Chebychev filter. The improvement in SNR at high frequencies is due to the filter cutoff. The switching nature of the analog input results in transient currents that charge the input capacitance of the track/hold. Keep the driving source impedance low (below 2kΩ), so that the settling characteristics of the track/hold are not degraded. A low driving impedance also minimizes undesirable noise pickup and reduces DC errors caused by transient currents at the analog input. As with any ADC, it is important to keep external sources of noise to a minimum during a conversion. Therefore, keep the data bus as quiet as possible during a conversion, especially when the track/hold is making the transition to the hold mode. For conversion times that are significantly longer than 5µs, the device’s accuracy may degrade slightly, as shown in Figure 14. This degradation is due to the charge that is lost from the hold capacitor in the presence of small on-chip leakage currents. The MX7576 analog input can also be modeled with the switch and capacitor as shown in Figure 11. However, unlike the MX7575, the MX7576 samples the input voltage eight times during a conversion (once before each comparator decision). Therefore, the precautions that apply to the MX7575 also apply to the MX7576. These include minimizing the analog source impedance and reducing noise coupling from the digital circuitry during a conversion, especially near a sampling instant. Reference Input The high speed of this ADC can be partially attributed to the “inverted voltage output” topology of the DAC that it uses. This topology provides low offset and gain errors and fast settling times. The input current to the DAC, however, is not constant. During a conversion, as different DAC codes are tried, the DC impedance of the DAC can vary between 6kΩ and 18kΩ. Furthermore, when the DAC codes change, small amounts of transient current are drawn from the reference input. These characteristics require a low DC and AC driving impedance for the reference circuitry to minimize conversion errors. Figure 15 shows the reference circuitry recommended to drive the reference input of the MX7575/MX7576. CS RD BUSY EXTERNAL CLOCK a) WITH EXTERNAL CLOCK INPUT SIGNAL HELD HERE CS RD BUSY RON 500Ω S1 VIN CS 0.5pF CH 2pF INTERNAL CLOCK INPUT SIGNAL HELD HERE b) WITH INTERNAL CLOCK Figure 11. Equivalent Input Circuit 8 Figure 12. MX7575 Track/Hold (Slow-Memory Interface) Timing Diagrams _______________________________________________________________________________________ CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs The decoupling capacitors are necessary to provide a low AC source impedance. MX7575/6 FIG13 TA = +25°C 42 Internal/External Clock The MX7575/MX7576 can be run with either an externally applied clock or their internal clock. In either case, the signal appearing at the clock pin is internally divided by two to provide an internal clock signal that is relatively insensitive to the input clock duty cycle. Therefore, a single conversion takes 20 input clock cycles, which corresponds to 10 internal clock cycles. SNR (dB) 44 46 48 50 52 Internal Clock The internal oscillator frequency is set by an external capacitor, CCLK, and an external resistor, RCLK, which are connected as shown in Figure 16a. During a conversion, a sawtooth waveform is generated on the CLK pin by charging CCLK through RCLK and discharging it through an internal switch. At the end of a conversion, the internal oscillator is shut down by clamping the CLK pin to VDD through an internal switch. The circuit for the internal oscillator can easily be overdriven with an external clock source. The internal oscillator provides a convenient clock source for the MX7575. Figure 17 shows typical conversion times versus temperature for the recommended RCLK and CCLK combination. Due to process variations, the oscillation frequency for this RCLK/CCLK combination may vary by as much as ±50% from the nominal value shown in Figure 17. Therefore, an external clock should be used in the following situations: 1) Applications that require the conversion time to be within 50% of the minimum conversion time for the specified accuracy (5µs MX7575/10µs MX7576). 2) Applications in which time-related software constraints cannot accommodate conversion-time differences that may occur from unit to unit or over temperature for a given device. 54 100 10k 1k 100k INPUT FREQUENCY (Hz) RELATIVE ACCURACY (LSB) 2.5 2.0 MX7575/6 FIG14 Figure 13. MX7575 SNR vs. Input Frequency A: TA = +125°C B: TA = +85°C C: TA = +25°C 1.5 1.0 A B C 0.5 0 10 100 1000 10000 CONVERSION TIME (µs) Figure 14. MX7575 Accuracy vs. Conversion Time +5V 3.3k 1.23V REF + ICL8069 _ + 47µF 0.1µF External Clock The CLK input of the MX7575/MX7576 may be driven directly by a 74HC or 4000B series buffer (e g., 4049), or by an LS TTL output with a 5.6kΩ pull-up resistor. At the end of a conversion, the device ignores the clock input and disables its internal clock signal. Therefore, the external clock may continue to run between conversions without being disabled. The duty cycle of the external clock may vary from 30% to 70%. As discussed previously, in order to maintain accuracy, clock rates significantly lower than the data sheet limits (4MHz for MX7575 and 2MHz for MX7576) should not be used. Figure 15. External Reference Circuit _______________________________________________________________________________________ 9 MX7575/MX7576 40 MX7575/MX7576 CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs OUTPUT CODE +5V 47µF 0.1µF +5V +5V 3.3k 2.46V(max) +1.23V + - 47µF 16 RCLK 100k, 2% 18 VDD CLK AIN BUSY 17 0.1µF 15 CS REF AGND 1111 1111 1111 1110 1111 1101 5 4 1 2 RD TP/ 3 MODE MX7575 MX7576 CCLK 100pF, 1% CONTROL INPUTS D7–D0 DATA OUT 0000 0011 0000 0010 0000 0001 0000 0000 FS - 1LSB 1LSB 3LSBs 2LSBs AIN, INPUT VOLTAGE (IN TERMS OF LSBs) Figure 16b. Nominal Transfer Characteristic for Unipolar Operation ______________ Typical Applications Unipolar Operation Figure 16a shows the analog circuit connections for unipolar operation, and Figure 16b shows the nominal transfer characteristic for unipolar operation. Since the offset and full-scale errors of the MX7575/MX7576 are very small, it is not necessary to null these errors in most cases. If calibration is required, follow the steps in the sections below. Offset Adjust The offset error can be adjusted by using the offset trim capability of an op amp (when it is used as a voltage follower) to drive the analog input, AIN. The op amp should have a common-mode input range that includes 0V. Set its initial input to 4.8mV (1/2LSB), while varying its offset until the ADC output code flickers between 0000 0000 and 0000 0001. Full-Scale Adjustment Make the full-scale adjustment by forcing the analog input, AIN, to 2.445V (FS - 3/2LSB). Then vary the reference input voltage until the ADC output code flickers between 1111 1110 and 1111 1111. Bipolar Operation Figure 18a shows an example of the circuit connection for bipolar operation, and Figure 18b shows the nominal transfer characteristic for bipolar operation. The output code provided by the MX7575 is offset binary. The analog input range for this circuit is ±2.46V (1LSB = 19.22mV), even though the voltage appearing at AIN is in the 0V to 2.46V range. In most cases, the MX7575 is accurate enough that calibration will not be necessary. If calibration is not needed, resistors R1–R7 should have a 0.1% tolerance, with R4 and R5 replaced by one 10kΩ resistor, and R2 and R3 with one 1kΩ resistor. If calibration is required, follow the steps in the sections below. Offset Adjust Adjust the offset error by applying an analog input voltage of 2.43V (+FS - 3/2LSB). Then adjust resistor R5 until the output code flickers between 1111 1110 and 1111 1111. Full-Scale Adjust Null the full-scale error by applying an analog input voltage of -2.45V (-FS + 1/2LSB). Then adjust resistor R3 until the output code flickers between 0000 0000 and 0000 0001. 14 13 CONVERSION TIME (µs) Figure 16a. Unipolar Configuration FS = 2VREF 2FS 1LSB = ––– 256 0 9 10 FULL-SCALE TRANSITION (FS - 3/2LSB) MX7576 MX7575 12 11 10 9 8 RCLK = 100kΩ CCLK = 100pF 7 -55 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE (°C) Figure 17. Typical Conversion Times vs. Temperature Using Internal Clock ______________________________________________________________________________________ CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs +5V 47µF 0.1µF 47µF + OUTPUT CODE 0.1µF +5V R6 3.3k 18 VDD 5 17 CLK REF +5V TLC271 RCLK 111...111 111...110 CL 100pF 2% 100...010 MX7575 ICL8069 1.2V REFERENCE 100...001 R5 5k R4 8.2k R7 10k MX7575/MX7576 +5V R1 1k 16 100...000 -FS 2 -1/2LSB 011...111 AIN D7–D0 AGND DGND DATA OUT R2 9 15 820Ω 1/2LSB FS -1LSB 2 AIN 011...110 R3 500Ω 000...001 FS = 2VREF 000...000 1LSB = 2FS 256 INPUT VOLTAGE Figure 18a. MX7575 Bipolar Configuration Figure 18b. Nominal Transfer Characteristic for Bipolar Operation __________Applications Information __Functional Diagrams (continued) Noise To minimize noise coupling, keep both the input signal lead to AIN and the signal return lead from AGND as short as possible. If this is not possible, a shielded cable or a twisted-pair transmission line is recommended. Additionally, potential differences between the ADC ground and the signal-source ground should be minimized, since these voltage differences appear as errors superimposed on the input signal. To minimize system noise pickup, keep the driving source resistance below 2kΩ. Proper Layout For PC board layouts, take care to keep digital lines well separated from any analog lines. Establish a single-point, analog ground (separate from the digital system ground) near the MX7575/MX7576. This analog ground point should be connected to the digital system ground through a single-track connection only. Any supply or reference bypass capacitors, analog input filter capacitors, or input signal shielding should be returned to the analog ground point. VDD 18 AIN AGND 16 15 MX7576 COMP REF 17 CLK CS RD MODE 5 1 2 3 DAC CLOCK OSCILLATOR SAR 6 CONTROL LOGIC LATCH AND THREE-STATE OUTPUT DRIVERS .. D7 D0 14 4 BUSY 9 DGND ______________________________________________________________________________________ 11 ____Pin Configurations (continued) _Ordering Information (continued) PART RD CS N.C. VDD REF TOP VIEW 3 2 1 20 19 TP (MODE) 4 BUSY 5 CLK 6 D7 (MSB) 7 15 D1 D6 8 14 9 10 11 12 13 D5 N.C. D4 D3 MX7575 MX7576 DGND MX7575/MX7576 CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs 18 AIN 17 AGND 16 D0 (LSB) TEMP. RANGE PIN-PACKAGE MX7575JEWN -40°C to +85°C 18 Wide SO MX7575KEWN -40°C to +85°C 18 Wide SO MX7575JEQP -40°C to +85°C 20 PLCC MX7575KEQP -40°C to +85°C 20 PLCC MX7575SQ -55°C to +125°C 18 CERDIP** MX7575TQ -55°C to +125°C 18 CERDIP** MX7576JN 0°C to +70°C 18 Plastic DIP MX7576KN 0°C to +70°C 18 Plastic DIP MX7576JCWN 0°C to +70°C 18 Wide SO MX7576KCWN 0°C to +70°C 18 Wide SO MX7576JP 0°C to +70°C 20 PLCC MX7576KP 0°C to +70°C 20 PLCC MX7576J/D 0°C to +70°C Dice* MX7576AQ -25°C to +85°C 18 CERDIP** MX7576BQ -25°C to +85°C 18 CERDIP** MX7576JEWN -40°C to +85°C 18 Wide SO MX7576KEWN -40°C to +85°C 18 Wide SO MX7576JEQP -40°C to +85°C 20 PLCC MX7576KEQP -40°C to +85°C 20 PLCC MX7576SQ -55°C to +125°C 18 CERDIP** MX7576TQ -55°C to +125°C 18 CERDIP** * Contact factory for dice specifications. ** Contact factory for availability. D2 PLCC ( ) ARE FOR MX7576 ONLY. INL (LSB) ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 __________________________________________________________Chip Topographies MX7575 D6 D7 MX7576 CLK D6 N.C. BUSY D5 D7 (MSB) CLK MODE BUSY D5 DGND TP DGND D4 RD D4 CS 0.081" (2.057mm) V DD N.C. RD CS 0.081" (2.057mm) V DD REF D3 REF D3 D2 D1 D0 AGND* AIN AGND* 0.130" (3.302mm) D2 D1 D0 (LSB) AGND* AIN AGND* 0.130" (3.302mm) *The two AGND pads must both be used (bonded together). *The two AGND pads must both be used (bonded together). TRANSISTOR COUNT: 768 SUBSTRATE CONNECTED TO VDD TRANSISTOR COUNT: 768 SUBSTRATE CONNECTED TO VDD Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.