19-1172; Rev 0; 12/96 +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface ______________________________Features The +3V MAX5251 combines four low-power, voltageoutput, 10-bit digital-to-analog converters (DACs) and four precision output amplifiers in a space-saving, 20pin package. In addition to the four voltage outputs, each amplifier’s negative input is also available to the user. This facilitates specific gain configurations, remote sensing, and high output drive capacity, making the MAX5251 ideal for industrial-process-control applications. Other features include software shutdown, hardware shutdown lockout, an active-low reset that clears all registers and DACs to zero, a user-programmable logic output, and a serial-data output. ♦ Four 10-Bit DACs with Configurable Output Amplifiers ♦ +3.0V to +3.6V Single-Supply Operation ♦ Low Supply Current: 0.8mA Normal Operation 3µA Shutdown Mode ♦ Available in 20-Pin SSOP ♦ Power-On Reset Clears all Registers and DACs to Zero ♦ SPI/QSPI and Microwire Compatible ♦ Simultaneous or Independent Control of DACs via 3-Wire Serial Interface ♦ User-Programmable Digital Output Each DAC has a double-buffered input organized as an input register followed by a DAC register. A 16-bit serial word loads data into each input/DAC register. The 3-wire serial interface is compatible with SPI™/QSPI™ and Microwire™. It allows the input and DAC registers to be updated independently or simultaneously with a single software command. All logic inputs are TTL/CMOSlogic compatible. ♦ Schmitt-Trigger Digital Inputs for Direct Optocoupler Interface ♦ 12-Bit Upgrade Available: MAX5253 _________________Ordering Information ________________________Applications PART Digital Offset and Gain Adjustment TEMP. RANGE PIN-PACKAGE Automatic Test Equipment MAX5251ACPP 0°C to +70°C 20 Plastic DIP MAX5251BCPP 0°C to +70°C 20 Plastic DIP MAX5251ACAP 0°C to +70°C 20 SSOP MAX5251BCAP 0°C to +70°C 20 SSOP Ordering Information continued on last page. Remote Industrial Controls Pin Configuration appears at end of data sheet. Microprocessor-Controlled Systems Industrial Process Controls INL (LSB) ±1/2 ±1 ±1/2 ±1 Motion Control _________________________________________________________________________Functional Diagram DOUT CL PDL DGND AGND SR CONTROL LOGIC OUTPUT CS DIN SCLK UPO REFAB FBA DECODE CONTROL 16-BIT SHIFT REGISTER VDD MAX5251 OUTA INPUT REGISTER A DAC REGISTER A DAC A INPUT REGISTER B DAC REGISTER B DAC B INPUT REGISTER C DAC REGISTER C DAC C INPUT REGISTER D DAC REGISTER D DAC D FBB OUTB FBC OUTC FBD OUTD REFCD SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX5251 __________________General Description MAX5251 +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface ABSOLUTE MAXIMUM RATINGS VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND ..................................................................±0.3V REFAB, REFCD to AGND ...........................-0.3V to (VDD + 0.3V) OUT_, FB_ to AGND...................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND.............................................-0.3V to +6V DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V) Continuous Current into Any Pin.......................................±20mA Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 8.00mW/°C above +70°C) .................640mW SSOP (derate 8.00mW/°C above +70°C) ......................640mW CERDIP (derate 11.11mW/°C above +70°C) .................889mW Operating Temperature Ranges MAX5251_C_P ......................................................0°C to +70°C MAX5251_E_P ...................................................-40°C to +85°C MAX5251BMJP ................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. Output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE—ANALOG SECTION Resolution Integral Nonlinearity (Note 1) N 10 MAX5251AC/E INL Differential Nonlinearity DNL Offset Error VOS ±0.25 ±1.0 MAX5251BMJP ±2.0 Guaranteed monotonic ±1.0 ±6.0 6 ±2.4 1 PSRR VDD = +3.0V to +3.6V LSB LSB mV ppm/°C GE Gain-Error Tempco Power-Supply Rejection Ratio ±0.5 MAX5251BC/E Offset-Error Tempco Gain Error (Note 1) Bits LSB ppm/°C 100 800 µV/V REFERENCE INPUT MATCHING PERFORMANCE (TA = +25°C) Reference Input Range VREF Reference Input Resistance RREF 2 0 Code dependent, minimum at code 554 hex VDD - 1.4 10 _______________________________________________________________________________________ V kΩ +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface (VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. Output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MULTIPLYING-MODE PERFORMANCE Reference -3dB Bandwidth VREF = 0.67Vp-p 650 kHz Reference Feedthrough Input code = all 0s, VREF = 1.6Vp-p at 1kHz -84 dB VREF = 1Vp-p at 25kHz, code = full scale 72 dB Signal-to-Noise Plus Distortion Ratio SINAD DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIN Input Capacitance CIN 2.0 VIN = 0V or VDD V 0.01 0.6 V ±1.0 µA 8 pF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA VDD - 0.5 V 0.13 0.4 V DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time To ±1/2LSB, VSTEP = 1.25V Output Voltage Swing Rail-to-rail (Note 2) RL = ∞ Start-Up Time Exiting Shutdown Mode CS = VDD, DIN = 100kHz Digital Feedthrough V/µs 12 µs 0 to VDD Current into FB_ OUT_ Leakage Current in Shutdown 0.6 Digital Crosstalk V 0 0.1 µA 0.01 ±1 µA 20 µs 5 nV-s 5 nV-s POWER SUPPLIES Supply Voltage VDD (Note 3) Supply Current IDD (Note 4) (Note 4) Supply Current in Shutdown Reference Current in Shutdown Note 1: Note 2: Note 3: Note 4: 3.0 3.6 V 0.82 0.98 mA 3 20 µA 0.01 ±1 µA Guaranteed from code 5 to code 1023 in unity-gain configuration. Accuracy is better than 1LSB for VOUT = 6mV to VDD - 80mV, guaranteed by PSR test at the endpoints. Remains operational with supply voltage as low as +2.7V. RL = ∞, digital inputs at DGND or VDD. _______________________________________________________________________________________ 3 MAX5251 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. Output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS (Figure t6) SCLK Clock Period CP 100 ns SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns DIN Setup Time tDS 40 ns DIN Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tD01 CL = 200pF 120 ns SCLK Fall to DOUT Valid Propagation Delay tD02 CL = 200pF 120 ns SCLK Rise to CS Fall Delay tCS0 40 ns CS Rise to SCLK Rise Hold Time tCS1 40 ns CS Pulse Width High tCSW 100 ns __________________________________________Typical Operating Characteristics (VDD = +3.3V, TA = +25°C, unless otherwise noted.) RELATIVE OUTPUT (dB) -4 -0.25 -0.50 -0.75 -1.00 -8 -12 -16 -20 4 0.5 MAX5251-04 950 900 850 800 750 700 650 600 550 RL = 5kΩ -1.25 0 1000 SUPPLY CURRENT (µA) 0 REFAB SWEPT 0.67Vp-p RL = 5kΩ CL = 100pF MAX5251-06 0 MAX5251-01 0.25 SUPPLY CURRENT vs. TEMPERATURE REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE INL (LSB) MAX5251 +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface 1.0 1.5 2.0 REFERENCE VOLTAGE (V) 2.5 0 500k 1.0M 1.5M 2.0M 2.5M 3.0M FREQUENCY (Hz) CODE = FFC hex 500 -55 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) _______________________________________________________________________________________ +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY 850 0.35 750 700 650 600 0.30 0.25 0.20 0.15 -40 -60 -80 0.10 0.05 CODE = FFC hex 500 -100 0.5 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 0.1 SUPPLY VOLTAGE (V) 1 10 100 0 SIGNAL AMPLITUDE (dB) -0.5 -1.0 -1.5 -2.5 1 LOAD (kΩ) 10 100 REFAB INPUT SIGNAL -20 4.9 6.0 VREF = 1.6Vp-p @ 1kHz RL = 5kΩ CL = 100pF -40 -60 -80 -2.0 0.1 3.8 2.7 FREQUENCY (kHz) REFERENCE FEEDTHROUGH AT 1kHz MAX5251-03 0 0.01 1.6 FREQUENCY (kHz) FULL-SCALE ERROR vs. LOAD FULL-SCALE ERROR (LSB) VREF = 1kHz, 0.006V TO 1.6V RL = 5kΩ CL = 100pF -20 MAX5251-11 550 SIGNAL AMPLITUDE (dB) 0.40 THD + NOISE (%) 900 800 DAC CODE = FULL SCALE REFAB = 1Vp-p RL = 5kΩ CL = 100pF 0.45 OUTPUT FFT PLOT 0 MAX5251-02 950 SUPPLY CURRENT (µA) 0.50 MAX5251-05 1000 MAX5251-10 SUPPLY CURRENT vs. SUPPLY VOLTAGE -100 0.5 OUTA FEEDTHROUGH 1.2 1.9 2.6 3.3 4.0 FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX5251 ____________________________Typical Operating Characteristics (continued) (VDD = +3.3V, TA = +25°C, unless otherwise noted.) MAX5251 +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface ____________________________Typical Operating Characteristics (continued) (VDD = +3.3V, VREF = 1.25V, RL = 5kΩ, CL = 100pF, TA = +25°C, unless otherwise noted.) MAJOR-CARRY TRANSITION DIGITAL FEEDTHROUGH (SCLK = 100kHz) MAX5251-07 MAX5251-08 CS 5V/div SCLK, 2V/div OUTB, AC COUPLED 50mV/div OUTA, AC COUPLED 10mV/div 10µs/div 2µs/div CS = PDL = CL = 3.3V, DIN = 0V DAC A CODE SET TO 800 hex ANALOG CROSSTALK DYNAMIC RESPONSE MAX5251-12 MAX5251-13 OUTA, 500mV/div OUTA, 500mV/div GND OUTB, AC COUPLED 10mV/div 10µs/div DAC A CODE SWITCHING FROM 00C hex TO FFC hex DAC B CODE SET TO 800 hex 6 10µs/div SWITCHING FROM CODE 000 hex TO FB4 hex OUTPUT AMPLIFIER GAIN = +2.6 _______________________________________________________________________________________ +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface PIN NAME FUNCTION 1 AGND 2 FBA 3 OUTA DAC A Output Voltage 4 OUTB DAC B Output Voltage 5 FBB 6 REFAB 7 CL Clears All DACs and Registers. Resets all outputs (OUT_, UPO, DOUT) to 0, active low. 8 CS Chip-Select Input. Active low. 9 DIN Serial-Data Input 10 SCLK Serial-Clock Input 11 DGND Digital Ground 12 DOUT Serial-Data Output 13 UPO User-Programmable Logic Output 14 PDL Power-Down Lockout. Active low. Locks out software shutdown if low. 15 REFCD 16 FBC 17 OUTC DAC C Output Voltage 18 OUTD DAC D Output Voltage 19 FBD DAC D Output Amplifier Feedback 20 VDD Positive Power Supply Analog Ground DAC A Output Amplifier Feedback DAC B Output Amplifier Feedback Reference Voltage Input for DAC A and DAC B Reference Voltage Input for DAC C and DAC D DAC C Output Amplifier Feedback _______________________________________________________________________________________ 7 MAX5251 ______________________________________________________________Pin Description MAX5251 +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface FB_ R 2R 2R S0 R 2R S1 OUT_ R 2R 2R D0 D9 REF_ AGND The impedance at each reference input is code dependent, ranging from a low value of 10kΩ when both DACs connected to the reference have an input code of 554 hex, to a high value exceeding several giga ohms (leakage current) with an input code of 000 hex. Because the input impedance at the reference pins is code dependent, load regulation of the reference source is important. The REFAB and REFCD reference inputs have a 10kΩ guaranteed minimum input impedance. When the two reference inputs are driven from the same source, the effective minimum impedance is 5kΩ. Driving the REFAB and REFCD pins separately improves reference accuracy. In shutdown mode, the MAX5251’s REFAB and REFCD inputs enter a high-impedance state with a typical input leakage current of 0.01µA. SHOWN FOR ALL 1s ON DAC Figure 1. Simplified DAC Circuit Diagram _______________Detailed Description The MAX5251 contains four voltage-output digital-toanalog converters (DACs) that are easily addressed using a simple 3-wire serial interface. It includes a 16-bit data-in/data-out shift register, and each DAC has a doubled-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition to the four voltage outputs, each amplifier’s negative input is available to the user. The DACs are inverted R-2R ladder networks that convert a digital input (10 data bits plus 2 sub-bits) into equivalent analog output voltages in proportion to the applied reference voltage inputs. DACs A and B share the REFAB reference input, while DACs C and D share the REFCD reference input. The two reference inputs allow different full-scale output voltage ranges for each pair of DACs. Figure 1 shows a simplified circuit diagram of one of the four DACs. Reference Inputs The two reference inputs accept positive DC and AC signals. The voltage at each reference input sets the full-scale output voltage for its two corresponding DACs. The reference input voltage range is 0V to (VDD - 1.4V). The output voltages (VOUT_) are represented by a digitally programmable voltage source as: The reference input capacitance is also code dependent and typically ranges from 20pF with an input code of all 0s to 100pF at full scale. Output Amplifiers All MAX5251 DAC outputs are internally buffered by precision amplifiers with a typical slew rate of 0.6V/µs. Access to each output amplifier’s inverting input provides the user greater flexibility in output gain setting/ signal conditioning (see the Applications Information section). With a full-scale transition at the MAX5251 output, the typical settling time to ±1/2LSB is 12µs when loaded with 5kΩ in parallel with 100pF (loads less than 2kΩ degrade performance). The MAX5251 output amplifier’s output dynamic responses and settling performances are shown in the Typical Operating Characteristics. Power-Down Mode The MAX5251 features a software-programmable shutdown that reduces supply current to a typical value of 3µA. The power-down lockout pin (PDL) must be high to enable shutdown mode. Writing 1100XXXXXXXXXXXX as the input-control word puts the MAX5251 in shutdown mode (Table 1). VOUT_ = (VREF x NB / 1024 ) x Gain where NB is the numeric value of the DAC’s binary input code (0 to 1023), VREF is the reference voltage, and Gain is the externally set voltage gain. 8 _______________________________________________________________________________________ +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5251 SCLK SK DIN SO DOUT* SI* CS I/O Serial-Interface Configurations The MAX5251’s 3-wire serial interface is compatible with both Microwire™ (Figure 2) and SPI™/QSPI™ (Figure 3). The serial input word consists of two address bits and two control bits followed by 10+2 data bits (MSB first), as shown in Figure 4. The 4-bit address/ control code determines the MAX5251’s response outlined in Table 1. The connection between DOUT and the serial-interface port is not necessary, but may be used for data echo. Data held in the MAX5251’s shift register can be shifted out of DOUT and returned to the microprocessor (µP) for data verification. The MAX5251’s digital inputs are double buffered. Depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all four DAC registers can be updated simultaneously from the input registers (Table 1). • The state of the user-programmable logic output (UPO) • If the part is to go into shutdown mode (assuming PDL is high) • How the part is configured when exiting shutdown mode. MICROWIRE PORT *THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5251, BUT MAY BE USED FOR READBACK PURPOSES. Figure 2. Connections for Microwire +3.3V DOUT* MISO* DIN MAX5251 Serial-Interface Description The MAX5251 requires 16 bits of serial data. Table 1 lists the serial-interface programming commands. For certain commands, the 10+2 data bits are “don’t cares.” Data is sent MSB first and can be sent in two 8-bit packets or one 16-bit word (CS must remain low until 16 bits are transferred). The serial data is composed of two DAC address bits (A1, A0) and two control bits (C1, C0), followed by the 10+2 data bits D9…D0, S1, S0 (Figure 4). Set both sub-bits (S0, S1) to zero. The 4-bit address/control code determines: • The register(s) to be updated • The clock edge on which data is to be clocked out via the serial-data output (DOUT) MAX5251 In shutdown mode, the MAX5251 output amplifiers and the reference inputs enter a high-impedance state. The serial interface remains active. Data in the input registers is retained in shutdown, allowing the MAX5251 to recall the output states prior to entering shutdown. Exit shutdown mode either by recalling the previous configuration or by updating the DACs with new data. When powering up the device or bringing it out of shutdown, allow 20µs for the outputs to stabilize. SS MOSI SCLK SCK CS SPI/QSPI PORT I/O CPOL = 0, CPHA = 0 *THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5251, BUT MAY BE USED FOR READBACK PURPOSES. Figure 3. Connections for SPI/QSPI MSB ..................................................................................LSB 16 Bits of Serial Data Address Bits A1 A0 Control Bits C1 C0 Data Bits MSB.................................LSB D9 ...................................D0 S1 S0 4 Address/ Control Bits 10+2 Data Bits Figure 4. Serial-Data Format _______________________________________________________________________________________ 9 MAX5251 +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD FUNCTION A1 A0 C1 C0 D9.................D0 MSB.............LSB S1 S0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data 0 0 0 0 0 0 0 0 Load input register A; DAC registers unchanged. Load input register B; DAC registers unchanged. Load input register C; DAC registers unchanged. Load input register D; DAC registers unchanged. 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data 0 0 0 0 0 0 0 0 Load input register A; all DAC registers updated. Load input register B; all DAC registers updated. Load input register C; all DAC registers updated. Load input register D; all DAC registers updated. 0 1 0 0 XXXXXXXXXX X X Update all DAC registers from their respective input registers (also exit shutdown mode). 1 0 0 0 10-bit DAC data 0 0 Load all DAC registers from shift register (also exit shutdown mode). 1 1 0 0 XXXXXXXXXX X X Enter shutdown mode (provided PDL = 1). 0 0 1 0 XXXXXXXXXX X X UPO goes low (default). 0 1 1 0 XXXXXXXXXX X X UPO goes high. 0 0 0 0 XXXXXXXXXX X X No operation (NOP) to DAC registers 1 1 1 0 XXXXXXXXXX X X Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers updated. 1 0 1 0 XXXXXXXXXX X X Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers updated (default). “X” = Don’t care Figure 5 shows the serial-interface timing requirements. The chip-select pin (CS) must be low to enable the DAC’s serial interface. When CS is high, the interface control circuitry is disabled. CS must go low at least tCSS before the rising serial clock (SCLK) edge to properly clock in the first bit. When CS is low, data is clocked into the internal shift register via the serial-data input pin (DIN) on SCLK’s rising edge. The maximum guaranteed clock frequency is 10MHz. Data is latched into the appropriate MAX5251 input/DAC registers on CS’s rising edge. The programming command Load-All-DACs-From-ShiftRegister allows all input and DAC registers to be simultaneously loaded with the same digital code from the input shift register. The no operation (NOP) command leaves the register contents unaffected and is useful when the MAX5251 is configured in a daisy chain (see the Daisy Chaining Devices section). The command to 10 change the clock edge on which serial data is shifted out of DOUT also loads data from all input registers to their respective DAC registers. Serial-Data Output (DOUT) The serial-data output, DOUT, is the internal shift register’s output. The MAX5251 can be programmed so that data is clocked out of DOUT on SCLK’s rising edge (Mode 1) or falling edge (Mode 0). In Mode 0, output data at DOUT lags input data at DIN by 16.5 clock cycles, maintaining compatibility with Microwire, SPI/QSPI, and other serial interfaces. In Mode 1, output data lags input data by 16 clock cycles. On power-up, DOUT defaults to Mode 0 timing. User-Programmable Logic Output (UPO) The user-programmable logic output, UPO, allows an external device to be controlled via the MAX5251 serial interface (Table 1). ______________________________________________________________________________________ +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5251 CS COMMAND EXECUTED SCLK 1 DIN 8 A0 A1 C1 D9 C0 D6 D7 D8 9 D5 16 D4 D3 D2 D1 D0 S1 S0 D4 D3 D2 D1 D0 S1 S0 DATA PACKET (N) DOUT (MODE 0) A0 A1 C1 D9 C0 D6 D7 D8 D5 A1 MSB FROM PREVIOUS WRITE DATA PACKET (N) DATA PACKET (N-1) DOUT (MODE 1) A0 A1 C1 C0 D9 D8 D6 D7 D5 D4 D3 D2 D1 D0 S1 S0 A1 MSB FROM PREVIOUS WRITE DATA PACKET (N) DATA PACKET (N-1) Figure 5. Serial-Interface Timing Diagram tCSW CS tCSO tCSS tCL tCP tCH tCSH tCS1 SCLK tDS tDH DIN tDO1 tDO2 DOUT Figure 6. Detailed Serial-Interface Timing Diagram Power-Down Lockout (PDL) The power-down lockout pin PDL disables software shutdown when low. When in shutdown, transitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL could also be used to wake up the device asynchronously. Daisy Chaining Devices Any number of MAX5251s can be daisy chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7). Since the MAX5251’s DOUT pin has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the serial-data-out VOH and VOL specifications in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several MAX5251s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC. ______________________________________________________________________________________ 11 MAX5251 +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5251 SCLK SCLK DIN DIN CS CS MAX5251 SCLK DOUT MAX5251 SCLK DOUT DIN CS DOUT DIN CS TO OTHER SERIAL DEVICES Figure 7. Daisy-Chaining MAX5251s DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 CS CS MAX5251 CS MAX5251 MAX5251 SCLK SCLK SCLK DIN DIN DIN Figure 8. Multiple MAX5251s Sharing a Common DIN Line 12 ______________________________________________________________________________________ +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface Unipolar Output For a unipolar output, the output voltages and the reference inputs have the same polarity. Figure 9 shows the MAX5251 unipolar output circuit, which is also the typical operating circuit. Table 2 lists the unipolar output codes. For rail-to-rail outputs, see Figure 10. This circuit shows the MAX5251 with the output amplifiers configured with a closed-loop gain of +2.6 to provide 0V to 3.25V fullscale range when a 1.25V reference is used. REFERENCE INPUTS REFAB ANALOG OUTPUT +3.3V VDD REFCD FBA DAC A OUTA 1111 1111 11(00) 1023 +VREF ( ——— ) 1024 1000 0000 513 +VREF ( ——— ) 1024 1000 0000 00(00) 512 +VREF +VREF ( ——— ) = ———— 1024 2 0111 1111 11(00) 511 +VREF ( ——— ) 1024 0000 0000 01(00) 1 +VREF ( ——— ) 1024 0000 0000 00(00) 0V 01(00) VOUT = VREF [(2NB / 1024) - 1] where NB is the numeric value of the DAC’s binary input code. Table 3 shows digital codes (offset binary) and corresponding output voltages for Figure 11’s circuit. MAX5251 Table 2. Unipolar Code Table DAC CONTENTS MSB LSB Bipolar Output The MAX5251 outputs can be configured for bipolar operation using Figure 11’s circuit: FBB DAC B OUTB FBC DAC C OUTC FBD DAC D OUTD AGND DGND Table 3. Bipolar Code Table DAC CONTENTS MSB LSB Figure 9. Unipolar Output Circuit ANALOG OUTPUT 511 +VREF ( ——— ) 512 1111 1111 11(00) 1000 0000 1000 0000 00(00) 0111 1111 11(00) 1 ) -VREF ( ——— 512 0000 0000 01(00) 511 -VREF ( ——— ) 512 0000 0000 00(00) 512 -VREF ( ——— ) = -VREF 512 01(00) 1 +VREF ( ——— ) 512 0V ( ) Sub-bits ______________________________________________________________________________________ 13 MAX5251 __________Applications Information +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5251 Using an AC Reference REFERENCE INPUTS In applications where the reference has AC signal components, the MAX5251 has multiplying capability within the reference input range specifications. Figure 12 shows a technique for applying a sine-wave signal to the reference input where the AC signal is offset before being applied to REFAB/REFCD. The reference voltage must never be more negative than DGND. +3.3V MAX5251 REFAB FBA 10k VDD REFCD 16k DAC A OUTA FBB 10k The MAX5251’s total harmonic distortion plus noise (THD + N) is typically less than -72dB (full-scale code), given a 1Vp-p signal swing and input frequencies up to 25kHz. The typical -3dB frequency is 650kHz, as shown in the Typical Operating Characteristics graphs. 16k DAC B OUTB FBC 10k 16k Digitally Programmable Current Source DAC C The circuit of Figure 13 places an NPN transistor (2N3904 or similar) within the op-amp feedback loop to implement a digitally programmable, unidirectional current source. This circuit can be used to drive 4–20mA current loops, which are commonly used in industrialcontrol applications. The output current is calculated with the following equation: IOUT = (VREF / R) x (NB / 1024) where NB is the numeric value of the DAC’s binary input code and R is the sense resistor shown in Figure 13. OUTC FBD 10k 16k DAC D OUTD AGND DGND VREFAB = VREFCD = 1.25V AV = 1 + 16k = 2.6 10k Figure 10. Unipolar Rail-to-Rail Output Circuit +3.3V R1 AC REFERENCE INPUT R2 26k 1/2 MAX492 REF_ +3.3V 500mVp-p 10k VDD REF_ FB_ VOUT DAC DAC_ OUT_ OUT_ -3.3V MAX5251 MAX5251 R1 = R2 = 10kΩ ± 0.1% AGND Figure 11. Bipolar Output Circuit 14 Figure 12. AC Reference Input Circuit ______________________________________________________________________________________ DGND +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface TOP VIEW VL MAX5251 IOUT DAC_ OUT_ 2N3904 FB_ AGND 1 20 VDD FBA 2 19 FBD OUTA 3 18 OUTD OUTB 4 17 OUTC FBB 5 R Figure 13. Digitally Programmable Current Source Power-Supply Considerations On power-up, all input and DAC registers are cleared (set to zero code) and DOUT is in Mode 0 (serial data is shifted out of DOUT on the clock’s falling edge). For rated MAX5251 performance, limit REFAB/REFCD to less than 1.4V below VDD. Bypass VDD with a 4.7µF capacitor in parallel with a 0.1µF capacitor to AGND. Use short lead lengths and place the bypass capacitors as close to the supply pins as possible. MAX5251 16 FBC 15 REFCD REFAB 6 CL 7 14 PDL CS 13 UPO 8 DIN 9 12 DOUT SCLK 10 11 DGND DIP/SSOP Grounding and Layout Considerations Digital or AC transient signals between AGND and DGND can create noise at the analog outputs. Tie AGND and DGND together at the DAC, then tie this point to the highest-quality ground available. Good printed circuit board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. Wire-wrapped boards are not recommended. ______________________________________________________________________________________ 15 MAX5251 __________________Pin Configuration REF_ MAX5251 +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface _Ordering Information (continued) PART MAX5251AEPP MAX5251BEPP MAX5251AEAP MAX5251BEAP MAX5251BMJP TEMP. RANGE ___________________Chip Information TRANSISTOR COUNT: 4337 INL (LSB) PIN-PACKAGE -40°C to +85°C 20 Plastic DIP -40°C to +85°C 20 Plastic DIP -40°C to +85°C 20 SSOP -40°C to +85°C 20 SSOP -55°C to +125°C 20 CERDIP* ±1/2 ±1 ±1/2 ±1 ±2 *Contact factory for availability and processing to MIL-STD-883. ________________________________________________________Package Information DIM α E H C L A A1 B C D E e H L α INCHES MILLIMETERS MIN MAX MIN MAX 0.068 0.078 1.73 1.99 0.002 0.008 0.05 0.21 0.010 0.015 0.25 0.38 0.004 0.008 0.09 0.20 SEE VARIATIONS 0.205 0.209 5.20 5.38 0.0256 BSC 0.65 BSC 0.301 0.311 7.65 7.90 0.025 0.037 0.63 0.95 0˚ 8˚ 0˚ 8˚ DIM PINS e SSOP SHRINK SMALL-OUTLINE PACKAGE A B A1 D D D D D 14 16 20 24 28 INCHES MILLIMETERS MAX MIN MAX MIN 6.33 0.239 0.249 6.07 6.33 0.239 0.249 6.07 7.33 0.278 0.289 7.07 8.33 0.317 0.328 8.07 0.397 0.407 10.07 10.33 21-0056A D Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.