19-1684; Rev 0; 5/00 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference The MAX1280/MAX1281 are available in 20-pin TSSOP packages. These devices are higher-speed versions of the MAX146/MAX147 (for more information, see the respective data sheet). Applications Portable Data Logging Features ♦ 8-Channel Single-Ended or 4-Channel Pseudo-Differential Inputs ♦ Internal Multiplexer and Track/Hold ♦ Single-Supply Operation +4.5V to +5.5V (MAX1280) +2.7V to +3.6V (MAX1281) ♦ Internal +2.5V Reference ♦ 400ksps Sampling Rate (MAX1280) ♦ Low Power 2.5mA (400ksps) 1.3mA (Reduced-Power Mode) 0.9mA (Fast Power-Down Mode) 2µA (Full Power-Down) ♦ SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire Serial Interface ♦ Software-Configurable Unipolar or Bipolar Inputs ♦ 20-Pin TSSOP Package Ordering Information TEMP. RANGE PART MAX1280BCUP MAX1280BEUP 0°C to +70°C -40°C to +85°C PINPACKAGE INL (LSB) 20 TSSOP 20 TSSOP ±1 ±1 Ordering Information continued at end of data sheet. Pin Configuration TOP VIEW CH0 1 20 VDD1 Data Acquisition CH1 2 19 VDD2 Medical Instruments CH2 3 Battery-Powered Instruments CH3 4 Pen Digitizers CH4 5 Process Control CH5 6 15 SSTRB CH6 7 14 DOUT CH7 8 13 GND COM 9 12 REFADJ SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. 18 SCLK MAX1280 MAX1281 17 CS 16 DIN 11 REF SHDN 10 TSSOP ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX1280/MAX1281 General Description The MAX1280/MAX1281 12-bit ADCs combine an 8-channel analog-input multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. The MAX1280 operates from a single +4.5V to +5.5V supply; the MAX1281 operates from a single +2.7V to +3.6V supply. Both devices’ analog inputs are software configurable for unipolar/bipolar and singleended/pseudo-differential operation. The 4-wire serial interface connects directly to SPI™/QSPI™/MICROWIRE™ devices without external logic. A serial strobe output allows direct connection to TMS320-family digital signal processors. The MAX1280/ MAX1281 use an external serial-interface clock to perform successive-approximation analog-to-digital conversions. Both parts feature an internal +2.5V reference and a reference-buffer amplifier with a ±1.5% voltageadjustment range. An external reference with a 1V to VDD1 range may also be used. The MAX1280/MAX1281 provide a hard-wired SHDN pin and four software-selectable power modes (normal operation, reduced power, fast power-down, and full power-down). These devices can be programmed to automatically shut down at the end of a conversion or to operate with reduced power. When using the powerdown modes, accessing the serial interface automatically powers up the devices, and the quick turn-on time allows them to be powered down between all conversions. This technique can cut supply current to under 100µA at reduced sampling rates. MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference ABSOLUTE MAXIMUM RATINGS VDD_ to GND ............................................................ -0.3V to +6V VDD1 to VDD2 ........................................................ -0.3V to +0.3V CH0–CH7, COM to GND.......................... -0.3V to (VDD1 + 0.3V) REF, REFADJ to GND .............................. -0.3V to (VDD1 + 0.3V) Digital Inputs to GND .............................................. -0.3V to +6V Digital Outputs to GND ............................ -0.3V to (VDD2 + 0.3V) Digital Output Sink Current .................................................25mA Continuous Power Dissipation (TA = +70°C) 20-Pin TSSOP (derate 7.0mW/°C above +70°C) .........559mW Operating Temperature Ranges MAX128_BCUP .................................................. 0°C to +70°C MAX128_BEUP ............................................... -40°C to +85°C Storage Temperature Range ............................ -60°C to +150°C Lead Temperature (soldering, 10s) ................................ +300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX1280 (VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1.0 LSB DC ACCURACY (Note 1) 12 Resolution Relative Accuracy (Note 2) INL Differential Nonlinearity DNL Bits ±1.0 LSB Offset Error ±6.0 LSB Gain Error (Note 3) ±6.0 LSB No missing codes over temperature Gain-Error Temperature Coefficient ±0.8 ppm/°C Channel-to-Channel Offset-Error Matching ±0.1 LSB DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Up to the 5th harmonic 70 dB -81 dB 80 dB fIN1 = 99kHz, fIN2 = 102kHz 76 dB Channel-to-Channel Crosstalk (Note 4) fIN = 200kHz, VIN = 2.5Vp-p -78 dB Full-Power Bandwidth -3dB point 6 MHz Full-Linear Bandwidth SINAD > 68dB 350 kHz Intermodulation Distortion IMD CONVERSION RATE Conversion Time (Note 5) tCONV Track/Hold Acquisition Time tACQ 2.5 10 Aperture Delay Duty Cycle 2 fSCLK ns ns <50 Aperture Jitter Serial Clock Frequency µs 468 ps 0.5 6.4 MHz 40 60 % _______________________________________________________________________________________ 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference (VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUTS (CH7–CH0, COM) Input Voltage Range, SingleEnded and Differential (Note 6) VREF Unipolar, VCOM = 0 VCH_ Multiplexer Leakage Current Bipolar, VCOM or VCH_ = VREF/2, referenced to COM or CH_ ±VREF/2 On/off leakage current, VCH_ = 0 or VDD1 ±0.001 Input Capacitance ±1 18 V µA pF INTERNAL REFERENCE REF Output Voltage VREF TA = +25°C 2.480 REF Short-Circuit Current REF Output Temperature Coefficient TC VREF Load Regulation (Note 7) 2.500 V 30 mA ±15 ppm/°C 0.1 0 to 1mA output load 2.520 2.0 mV/mA Capacitive Bypass at REF 4.7 10 µF Capacitive Bypass at REFADJ 0.01 10 µF REFADJ Output Voltage REFADJ Input Range For small adjustments, from 1.22V REFADJ Buffer Disable Threshold To power down the internal reference 1.22 V ±100 mV 1.4 VDD1 2.05 Buffer Voltage Gain V V/V EXTERNAL REFERENCE (Reference buffer disabled, reference applied to REF) REF Input Voltage Range (Note 8) 1.0 VREF = 2.500V, fSCLK = 6.4MHz REF Input Current VDD1 + 50mV 200 V 350 VREF = 2.500V, fSCLK = 0 320 In power-down, fSCLK = 0 5 µA mA DIGITAL INPUTS (DIN, SCLK, CS, SHDN) Input High Voltage VINH Input Low Voltage VINL Input Hysteresis 3.0 VHYST Input Leakage IIN Input Capacitance CIN V 0.8 V ±1 µA 0.2 VIN = 0 or VDD2 V 15 pF DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low VOL ISINK = 5mA Output Voltage High VOH ISOURCE = 1mA Three-State Leakage Current Three-State Output Capacitance IL CS = 5V COUT CS = 5V 0.4 V ±10 µA 4 V 15 pF _______________________________________________________________________________________ 3 MAX1280/MAX1281 ELECTRICAL CHARACTERISTICS—MAX1280 (continued) MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference ELECTRICAL CHARACTERISTICS—MAX1280 (continued) (VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 V POWER SUPPLY Positive Supply Voltage (Note 9) Supply Current VDD1, VDD2 IVDD1 + IVDD2 4.5 VDD1 = VDD2 = 5.5V Supply Current Power-Supply Rejection PSR Operating mode (Note 10) 2.5 4.0 Reduced-power mode (Note 11) 1.3 2.0 Fast power-down (Note 11) 0.9 1.5 Full power-down (Note 11) 2 10 µA ±0.5 ±2.0 mV VDD1 = VDD2 = 5V ±10%, midscale input mA ELECTRICAL CHARACTERISTICS—MAX1281 (VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1.0 LSB ±1.0 LSB Offset Error ±6.0 LSB Gain Error (Note 3) ±6.0 LSB DC ACCURACY (Note 1) 12 Resolution Relative Accuracy (Note 2) INL Differential Nonlinearity DNL Bits No missing codes over temperature Gain-Error Temperature Coefficient ±1.6 ppm/°C Channel-to-Channel OffsetError Matching ±0.2 LSB DYNAMIC SPECIFICATIONS (75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Up to the 5th harmonic 70 dB -81 dB 80 dB fIN1 = 73kHz, fIN2 = 77kHz 76 dB Channel-to-Channel Crosstalk (Note 4) fIN = 150kHz, VIN = 2.5Vp-p -78 dB Full-Power Bandwidth -3dB point 3 MHz Full-Linear Bandwidth SINAD > 68dB 250 kHz Intermodulation Distortion 4 IMD _______________________________________________________________________________________ 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference (VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVERSION RATE Conversion Time (Note 5) tCONV Normal operating mode Track/Hold Acquisition Time tACQ Normal operating mode 3.3 µs 625 ns Aperture Delay 10 ns Aperture Jitter <50 ps Serial Clock Frequency fSCLK Normal operating mode Duty Cycle 0.5 4.8 MHz 40 60 % ANALOG INPUTS (CH7–CH0, COM) Input Voltage Range, SingleEnded and Differential (Note 6) VREF Unipolar, VCOM = 0 VCH_ Multiplexer Leakage Current Bipolar, VCOM or VCH_ = VREF/2, referenced to COM or CH_ ±VREF/2 On/off leakage current, VCH_ = 0 or AVDD ±0.001 Input Capacitance ±1 18 V µA pF INTERNAL REFERENCE REF Output Voltage VREF TA = +25°C 2.480 REF Short-Circuit Current REF Output Temperature Coefficient TC VREF Load Regulation (Note 7) 4.7 Capacitive Bypass at REFADJ 0.01 REFADJ Output Voltage For small adjustments, from 1.22V REFADJ Buffer Disable Threshold To power down the internal reference 2.520 mA ±15 ppm/°C 2.0 mV/mA 10 µF 10 µF 1.22 V ±100 mV 1.4 VDD1 - 1 2.05 Buffer Voltage Gain V 15 0.1 0 to 0.75mA output load Capacitive Bypass at REF REFADJ Input Range 2.500 V V/V EXTERNAL REFERENCE (Reference buffer disabled, reference applied to REF) REF Input Voltage Range (Note 8) 1.0 200 VREF = 2.500V, fSCLK = 4.8MHz REF Input Current VDD1 + 50mV V 350 VREF = 2.500V, fSCLK = 0 320 In power-down, fSCLK = 0 5 µA DIGITAL INPUTS (DIN, SCLK, CS, SHDN) Input High Voltage VINH Input Low Voltage VINL Input Hysteresis 2.0 0.2 VHYST Input Leakage IIN Input Capacitance CIN V 0.8 V ±1 VIN = 0 or VDD2 15 V µA pF _______________________________________________________________________________________ 5 MAX1280/MAX1281 ELECTRICAL CHARACTERISTICS—MAX1281 (continued) MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference ELECTRICAL CHARACTERISTICS—MAX1281 (continued) (VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V ±10 µA DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low VOL ISINK = 5mA Output Voltage High VOH ISOURCE = 0.5mA Three-State Leakage Current Three-State Output Capacitance IL CS = 3V COUT CS = 3V VDD2 - 0.5V V 15 pF POWER SUPPLY Positive Supply Voltage (Note 9) VDD1, VDD2 Supply Current IVDD1 + IVDD2 2.7 Operating mode (Note 10) Power-Supply Rejection PSR Reduced-power mode (Note 11) VDD1 = VDD2 = 3.6V Fast power-down (Note 11) Full power-down (Note 11) VDD1 = VDD2 = 2.7V to 3.6V, midscale input 3.6 V 2.5 3.5 1.3 2.0 0.9 1.5 2 ±0.5 10 ±2.0 µA mV TYP MAX UNITS mA TIMING CHARACTERISTICS—MAX1280 (Figures 1, 2, 6, 7; VDD1 = VDD2 = +4.5V to +5.5V; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN SCLK Period tCP 156 ns SCLK Pulse Width High tCH 62 ns SCLK Pulse Width Low tCL 62 ns DIN to SCLK Setup tDS 35 ns DIN to SCLK Hold tDH 0 ns CS Fall to SCLK Rise Setup tCSS 35 ns SCLK Rise to CS Rise Hold tCSH 0 ns SCLK Rise to CS Fall Ignore tCSO 35 ns CS Rise to SCLK Rise Ignore tCS1 35 ns SCLK Rise to DOUT Hold tDOH CLOAD = 20pF 10 20 SCLK Rise to SSTRB Hold tSTH CLOAD = 20pF 10 20 SCLK Rise to DOUT Valid tDOV CLOAD = 20pF SCLK Rise to SSTRB Valid tSTV CLOAD = 20pF CS Rise to DOUT Disable tDOD CLOAD = 20pF 10 CS Rise to SSTRB Disable tSTD CLOAD = 20pF 10 CS Fall to DOUT Enable tDOE CLOAD = 20pF CS Fall to SSTRB Enable tSTE CLOAD = 20pF CS Pulse Width High tCSW 6 100 _______________________________________________________________________________________ ns ns 80 ns 80 ns 65 ns 65 ns 65 ns 65 ns ns 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference (Figures 1, 2, 6, 7; VDD1 = VDD2 = +2.7V to +3.6V; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Period tCP 208 ns SCLK Pulse Width High tCH 83 ns SCLK Pulse Width Low tCL 83 ns DIN to SCLK Setup tDS 45 ns DIN to SCLK Hold tDH 0 ns CS Fall to SCLK Rise Setup tCSS 45 ns SCLK Rise to CS Rise Hold tCSH 0 ns SCLK Rise to CS Fall ignore tCSO 45 ns CS Rise to SCLK Rise Ignore tCS1 45 ns SCLK Rise to DOUT Hold tDOH CLOAD = 20pF 13 20 SCLK Rise to SSTRB Hold tSTH CLOAD = 20pF 1 20 SCLK Rise to DOUT Valid tDOV CLOAD = 20pF SCLK Rise to SSTRB Valid tSTV CLOAD = 20pF CS Rise to DOUT Disable tDOD CLOAD = 20pF 13 CS Rise to SSTRB Disable tSTD CLOAD = 20pF 13 CS Fall to DOUT Enable tDOE CS Fall to SSTRB Enable tSTE CS Pulse Width High tCSW ns ns 100 ns 100 ns 85 ns 85 ns CLOAD = 20pF 85 ns CLOAD = 20pF 85 ns 100 ns Note 1: MAX1280 tested at VDD1 = VDD2 = +5V, MAX1281 tested at VDD1 = VDD2 = +3V; COM = GND; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. Note 3: Offset nulled. Note 4: Ground “on” channel; sine wave applied to all “off” channels. Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The absolute voltage range for the analog inputs (CH7–CH0, and COM) is from GND to VDD1. Note 7: External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is a result of production test limitations. Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. Note 9: Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) to VDD1(MAX) = VDD2(MAX). For operations beyond this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory. Note 10: AIN = midscale. Unipolar mode. MAX1280 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz, 0 to 5V. MAX1281 tested with same loads, fSCLK = 4.8MHz, 0 to 3V. DOUT = FFF hex. Note 11: SCLK = DIN = GND, CS = VDD1. _______________________________________________________________________________________ 7 MAX1280/MAX1281 TIMING CHARACTERISTICS—MAX1281 Typical Operating Characteristics (MAX1280: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1281: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF, 0.01µF capacitor at REFADJ, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE SUPPLY CURRENT vs. SUPPLY VOLTAGE (CONVERTING) DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.4 SUPPLY CURRENT (mA) 0.2 DNL (LSB) 0.1 0 0 -0.2 -0.1 2.5 2.0 -0.4 -0.2 -0.3 -0.6 0 500 1000 1500 2000 2500 3000 3500 4000 4500 1.5 0 500 1000 1500 2000 2500 3000 3500 4000 4500 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. SUPPLY VOLTAGE (STATIC) SUPPLY CURRENT vs. TEMPERATURE (STATIC) 2.8 2.6 2.4 MAX1281 2.2 1.5 MAX1280 (PD1 = 1, PD0 = 1) 2.0 SUPPLY CURRENT (mA) MAX1280 NORMAL OPERATION (PD1 = PD0 = 1) 2.0 SUPPLY CURRENT (mA) 3.0 2.5 MAX1280/1-05 2.5 MAX1280/1-04 3.2 SUPPLY CURRENT (mA) 3.0 REDP (PD1 = 1, PD0 = 0) 1.0 FASTDP (PD1 = 0, PD0 = 1) MAX1280/1-06 INL (LSB) 0.3 0.2 3.5 MAX1280/1-03 0.4 MAX1280/1-02 0.6 MAX1280/1-01 0.5 MAX1281 (PD1 = 1, PD0 = 1) 1.5 MAX1280 (PD1 = 1, PD0 = 0) MAX1281 (PD1 = 1, PD0 = 0) 1.0 0.5 0.5 0 0 MAX1280 (PD1 = 0, PD0 = 1) MAX1281 (PD1 = 0, PD0 = 1) 2.0 -20 0 20 40 60 80 100 3.0 3.5 4.0 4.5 5.0 5.5 -20 0 20 40 60 TEMPERATURE (°C) SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE REFERENCE VOLTAGE vs. SUPPLY VOLTAGE 3 2 MAX1280 2.0 1.5 MAX1281 1.0 0.5 1 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 5.0 5.5 2.5003 2.5001 2.4999 2.4997 0 0 100 MAX1280/1-09 SHUTDOWN CURRENT (µA) 4 (PD1 = PD0 = 0) 80 2.5005 MAX1280/1-08 2.5 MAX1280/1-07 (PD1 = PD0 = 0) 2.5 -40 SUPPLY VOLTAGE (V) 5 8 2.5 TEMPERATURE (°C) REFERENCE VOLTAGE (V) -40 SHUTDOWN CURRENT (µA) MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference 2.4995 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference REFERENCE VOLTAGE vs. TEMPERATURE OFFSET ERROR vs. SUPPLY VOLTAGE 2.4994 -1.0 -1.5 2.4992 -2.0 -2.5 -20 0 20 40 60 80 100 MAX1280/1-12 -1.5 -2.5 2.7 3.0 3.3 3.6 -40 -15 VDD (V) TEMPERATURE (°C) 35 60 85 GAIN ERROR vs. TEMPERATURE GAIN ERROR vs. SUPPLY VOLTAGE 1 10 TEMPERATURE (°C) 0.5 MAX1280/1-13 MAX1281 0 0 GAIN ERROR (LSB) -40 -1.0 -2.0 2.4990 2.4988 -0.5 MAX1280/1-14 MAX1281 0 OFFSET ERROR (LSB) -0.5 OFFSET ERROR (LSB) 2.4998 GAIN ERROR (LSB) REFERENCE VOLTAGE (V) MAX1280 OFFSET ERROR vs. TEMPERATURE 0.5 MAX1280/1-11 2.5000 2.4996 0 MAX1280/1-10 2.5002 -1 -2 -0.5 -1.0 -1.5 -2.0 -3 2.7 3.0 3.3 VDD (V) 3.6 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 9 MAX1280/MAX1281 Typical Operating Characteristics (continued) (MAX1280: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1281: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF, 0.01µF capacitor at REFADJ, TA = +25°C, unless otherwise noted.) 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference MAX1280/MAX1281 Pin Description PIN NAME FUNCTION 1–8 CH0–CH7 9 COM Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be stable to ±0.5LSB. 10 SHDN Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA (typ). Sampling Analog Inputs 11 REF Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the reference buffer provides a +2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD1. 12 REFADJ Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD1. 13 GND Analog and Digital Ground 14 DOUT Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high. 15 SSTRB Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high. 16 DIN Serial Data Input. Data is clocked in at SCLK’s rising edge. 17 CS Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and SSTRB are high impedance. 18 SCLK Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty cycle must be 40% to 60%.) 19 VDD2 Positive Supply Voltage 20 VDD1 Positive Supply Voltage VDD2 VDD2 DOUT DOUT CLOAD 20pF 6k CLOAD 20pF GND GND a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL Figure 1. Load Circuits for Enable Time 10 6k 6k DOUT DOUT CLOAD 20pF 6k GND a) VOH to High-Z Figure 2. Load Circuits for Disable Time ______________________________________________________________________________________ CLOAD 20pF GND b) VOL to High-Z 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference The MAX1280/MAX1281 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors (µPs). Figure 3 shows a functional diagram of the MAX1280/MAX1281. Pseudo-Differential Input The equivalent input circuit of Figure 4 shows the MAX1280/MAX1281’s input architecture, which is composed of a T/H, input multiplexer, input comparator, switched-capacitor DAC, and reference. In single-ended mode, the positive input (IN+) is connected to the selected input channel and the negative input (IN-) is set to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels according to Tables 2 and 3. The MAX1280/MAX1281 input configuration is pseudodifferential in that only the signal at IN+ is sampled. The return side (IN-) is connected to the sampling capacitor while converting and must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to GND during a conversion. If a varying signal is applied to the selected IN-, its amplitude and frequency must be limited to maintain accuracy. The following equations determine the relationship between the maximum signal amplitude and its frequency CS SCLK DIN SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM in order to maintain ±0.5LSB accuracy. Assuming a sinusoidal signal at IN-, the input voltage is determined by: ( The maximum voltage variation is determined by: max 10 1 2 3 4 5 6 7 8 dνIN1LSB VREF = VIN- 2πf ≤ = 12 dt t CONV 2 t CONV ( ) A 650mVp-p 60Hz signal at IN- will generate ±0.5LSB of error when using a +2.5V reference voltage and a 2.5µs conversion time (15/fSCLK). When a DC reference voltage is used at IN-, connect a 0.1µF capacitor to GND to minimize noise at the input. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from IN+ to IN-. This unbalances node ZERO at the comparator’s input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to V DD1 /2 within the limits of 12-bit resolution. This action is equivalent to transferring a 12pF x (VIN+ - VIN-) charge from CHOLD to the binaryweighted capacitive DAC, which in turn forms a digital representation of the analog input signal. GND 17 18 16 ) νIN- = VIN- sin(2πft) INPUT SHIFT REGISTER REF INT CLOCK CONTROL LOGIC CH0 CH1 OUTPUT SHIFT REGISTER ANALOG INPUT MUX 14 15 DOUT SSTRB T/H CLOCK IN 12-BIT SAR ADC OUT REF 9 +1.22V REFERENCE REFADJ 12 REF 11 17k A ≈ 2.05* Figure 3. Functional Diagram CH6 CH7 20 19 13 +2.500V MAX1280 MAX1281 CH2 CH3 CH4 CH5 VDD1 CH8 INPUT MUX CAPACITATIVE DAC CHOLD 12pF CSWITCH* 6pF RIN 800Ω HOLD TRACK AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. VDD2 GND COMPARATOR ZERO VDD1/2 SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM. PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7. *INCLUDES ALL INPUT PARASITICS Figure 4. Equivalent Input Circuit ______________________________________________________________________________________ 11 MAX1280/MAX1281 Detailed Description MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference Track/Hold Input Bandwidth The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM and the converter converts the “+” input. If the converter is set up for differential inputs, the difference of [(IN+) - (IN-)] is converted. At the end of the conversion, the positive input connects back to IN+ and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal and is also the minimum time needed for the signal to be acquired. It is calculated by the following equation: The ADC’s input tracking circuitry has a 6MHz (MAX1280) or 3MHz (MAX1281) small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, antialias filtering is recommended. tACQ = 9 ✕ (RS + RIN) ✕ 12pF where RIN = 800Ω, RS = the source impedance of the input signal; tACQ is never less than 468ns (MAX1280) or 625ns (MAX1281). Note that source impedances below 2kΩ do not significantly affect the ADC’s AC performance. Analog Input Protection Internal protection diodes, which clamp the analog input to VDD1 and GND, allow the channel input pins to swing from GND - 0.3V to VDD1 + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD1 by more than 50mV or be lower than GND by 50mV. If the analog input exceeds 50mV beyond the supplies, do not allow the input current to exceed 2mA. Quick Look To quickly evaluate the MAX1280/MAX1281’s analog performance, use the circuit of Figure 5. The MAX1280/ MAX1281 require a control byte to be written to DIN before each conversion. Connecting DIN to VDD2 feeds in control bytes of $FF (HEX), which trigger singleended unipolar conversions on CH7 without powering down between conversions. The SSTRB output pulses OSCILLOSCOPE MAX1280 MAX1281 0V TO 2.500V ANALOG INPUT 0.01µF CH7 VDD1 VDD2 +3V or +5V 0.1µF SCLK 10µF GND COM SSTRB CS REFADJ 0.01µF DOUT* SCLK TO VDD2 DIN 2.5V EXTERNAL CLOCK DOUT REF 4.7µF SSTRB SHDN TO VDD2 CH1 CH2 CH3 CH4 *FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX) Figure 5. Quick-Look Circuit 12 ______________________________________________________________________________________ 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference MAX1280/MAX1281 CS tACQ SCLK 1 4 8 9 12 16 20 24 SEL SEL SEL UNI/ SGL/ PD1 PD0 2 1 0 BIP DIF DIN START SSTRB HIGH-Z HIGH-Z RB2 RB1 RB3 HIGH-Z HIGH-Z DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ACQUISITION IDLE CONVERSION IDLE Figure 6. Single-Conversion Timing high for one clock period before the MSB of the 12-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence of bits from DOUT. A total of 16 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs typically occur 20ns after the rising edge of SCLK. clock frequency from 500kHz to 6.4MHz (MAX1280) or 4.8MHz (MAX1281). 1) Set up the control byte and call it TB1. TB1 should be of the format 1XXXXXXX binary, where the Xs denote the particular channel, selected conversion mode, and power mode. Starting a Conversion 2) Use a general-purpose I/O line on the CPU to pull CS low. Start a conversion by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1280/MAX1281’s internal shift register. After CS falls, the first arriving logic “1” bit defines the control byte’s MSB. Until this first “start” bit arrives, any number of logic “0” bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The MAX1280/MAX1281 are compatible with SPI/QSPI and MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 12-bit conversion result). See Figure 17 for MAX1280/MAX1281 QSPI connections. Simple Software Interface Make sure the CPU’s serial interface runs in master mode, so the CPU generates the serial clock. Choose a 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3. 6) Pull CS high. Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion, padded with three leading zeros and one trailing zero. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120µs. Digital Output In unipolar input mode, the output is straight binary (Figure 14). For bipolar input mode, the output is two’s complement (Figure 15). Data is clocked out on the rising edge of SCLK in MSB-first format. ______________________________________________________________________________________ 13 MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference Table 1. Control-Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0 BIT NAME 7 (MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte. DESCRIPTION 6 5 4 SEL2 SEL1 SEL0 These three bits select which of the eight channels are used for the conversion (Tables 2 and 3). 3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the differential signal can range from -VREF/2 to +VREF/2. 2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2 and 3). 1 0 (LSB) PD1 PD0 Select operating mode. PD1 PD0 Mode 0 0 Full power-down 0 1 Fast power-down 1 0 Reduced Power 1 1 Normal Operation Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1) SEL2 0 SEL1 0 SEL0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 CH0 + CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM – + – + – + – + – + – + – + – Table 3. Channel Selection in Psuedo-Differential Mode (SGL/DIF = 0) SEL2 SEL1 SEL0 CH0 CH1 0 0 0 + – 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 14 – CH2 CH3 + – CH4 CH5 + – CH6 CH7 + – – + + – + – + ______________________________________________________________________________________ 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference MAX1280/MAX1281 CS tCSW tCSS tCH tCP tCL tCSO tCSH tCS1 SCLK tDS tDH tDOH DIN tDOV tDOD tDOE DOUT tSTE tSTH tSTV tSTD SSTRB Figure 7. Detailed Serial-Interface Timing Serial Clock The external serial clock not only shifts data in and out, but also drives the analog-to-digital conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approximation bit decisions are made and appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS rising edge, SSTRB outputs a logic low. Figure 7 shows the detailed serial-interface timing. The conversion must complete in 120µs or less, or droop on the sample-and-hold capacitors may degrade conversion results. Data Framing The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on SCLK’s falling edge after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as follows: The first high bit clocked into DIN with CS low any time the converter is idle, e.g., after VDD1 and VDD2 are applied. OR The first high bit clocked into DIN after bit 6 of a conversion in progress is clocked onto the DOUT pin. Once a start bit has been recognized, the current conversion may only be terminated by pulling SHDN low. The fastest the MAX1280/MAX1281 can run with CS held low between conversions is 16 clocks per conversion. Figure 8 shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles. If CS is tied low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. Applications Information Power-On Reset When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX1280/MAX1281 in normal operating mode, ready to convert with SSTRB = low. The MAX1280/MAX1281 require 10µs to reset after the power supplies stabilize; no conversions should be initiated during this time. If CS is low, the first logic 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros. Additionally, wait for the reference to stabilize when using the internal reference. Power Modes You can save power by placing the converter in one of the two low-current operating modes or in full powerdown between conversions. Select the power mode through bit 1 and bit 0 of the DIN control byte (Tables 1 and 4), or force the converter into hardware shutdown by driving SHDN to GND. The software power-down modes take effect after the conversion is completed; SHDN overrides any software power mode and immediately stops any conversion in ______________________________________________________________________________________ 15 MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference CS DIN S S CONTROL BYTE 0 1 8 12 CONTROL BYTE 1 16 1 5 S 8 12 CONTROL BYTE 2 16 1 5 S 8 12 16 1 B11 B6 ETC 5 SCLK DOUT HIGH-Z B11 B6 B0 B11 CONVERSION RESULT 0 SSTRB B6 B0 CONVERSION RESULT 1 HIGH-Z Figure 8. Continuous 16-Clock/Conversion Timing Table 4. Software-Controlled Power Modes TOTAL SUPPLY CURRENT PD1/PD0 MODE CIRCUIT SECTIONS* CONVERTING AFTER CONVERSION INPUT COMPARATOR REFERENCE 00 Full Power-Down (FULLPD) 2.5mA 2µA Off Off 01 Fast Power-Down (FASTPD) 2.5mA 0.9mA Reduced Power On 10 Reduced-Power Mode (REDPD) 2.5mA 1.3mA Reduced Power On 11 Operating Mode 2.5mA 2.0mA Full Power On *Circuit operation between conversions; during conversion, all circuits are fully powered up. progress. In software power-down mode, the serial interface remains active, waiting for a new control byte to start conversion and switch to full-power mode. Once the conversion is completed, the device goes into the programmed power mode until a new control byte is written. The power-up delay is dependent on the power-down state. Software low-power modes will be able to start conversion immediately when running at decreased clock rates (see Power-Down Sequencing). During power-on reset, when exiting software full power-down mode or exiting hardware shutdown, the device goes immediately into full-power mode and is ready to convert after 2µs when using an external reference. When using the internal reference, wait for the typical power16 up delay from a full power-down (software or hardware), as shown in Figure 9. Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. When software shutdown is asserted, the ADC completes the conversion in progress and powers down into the specified lowquiescent-current state (2µA, 0.9mA, or 1.3mA). The first logic 1 on DIN is interpreted as a start bit and puts the MAX1280/MAX1281 into their full-power mode. Following the start bit, the data input word or control byte also determines the next power-down state. For example, if the DIN word contains PD1 = 0 and PD0 = 1, a 0.9mA power-down starts after the conversion. ______________________________________________________________________________________ 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference Hardware Power-Down Pulling SHDN low places the converter in hardware power-down. Unlike software power-down mode, the conversion is terminated immediately. When returning to normal operation from SHDN with an external reference, the MAX1280/MAX1281 can be considered fully powered-up within 2µs of actively pulling SHDN high. When using the internal reference, the conversion should be initiated only after the reference has settled; its recovery time depends on the external bypass capacitors and shutdown duration. Power-Down Sequencing The MAX1280/MAX1281’s automatic power-down modes can save considerable power when operating at REFERENCE POWER-UP DELAY (ms) 1.50 1.25 1.00 0.75 0.50 0.25 0 0.0001 0.001 0.01 0.1 1 10 TIME IN SHUTDOWN (s) Figure 9. Reference Power-Up Delay vs. Time in Shutdown Using Full Power-Down Mode Full power-down mode (FULLPD) achieves the lowest power consumption at up to 1000 conversions per channel per second. Figure 10a shows the MAX1281’s power consumption for 1- or 8-channel conversions using full power-down mode (PD1 = PD0 = 0), with the internal reference and the maximum clock speed. A 0.01µF bypass capacitor plus the internal 17kΩ reference resistor at REFADJ forms an RC filter with a 200µs time constant. To achieve full 12-bit accuracy, 10 time constants or 2ms are required after power-up if the bypass capacitor is fully discharged between conversions. Waiting this 2ms in FASTPD mode or reducedpower mode (REDP) instead of full power-down mode can further reduce power consumption. This is achieved by using the sequence shown in Figure 12a. Figure 10b shows the MAX1281’s power consumption for 1- or 8-channel conversions using FULLPD mode (PD1 = PD0 = 0), an external reference, and the maximum clock speed. One dummy conversion to power-up the device is needed, but no wait-time is necessary to start the second conversion, thereby achieving lower power consumption at up to the full sampling rate. Using Fast Power-Down and Reduced-Power Modes FASTPD and REDP modes achieve the lowest power consumption at speeds close to the maximum sample rate. Figure 11 shows the MAX1281’s power consumption in FASTPD mode (PD1 = 0, PD0 = 1), REDP mode (PD1 = 1, PD0 = 0), and (for comparison) normal operating mode (PD = 1, PD0 = 1). The figure shows 10,000 1000 MAX1281 VDD1 = VDD2 = 3.0V CLOAD = 20pF CODE = 101010000000 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) less than maximum sample rates. Figures 10 and 11 show the average supply current as a function of the sampling rate. 100 8 CHANNELS 10 1 CHANNEL MAX1281 VDD1 = VDD2 = 3.0V CLOAD = 20pF CODE = 101010000000 1000 8 CHANNELS 100 1 CHANNEL 10 1 1 0.1 1 10 100 1k 10k SAMPLING RATE (sps) Figure 10a. Average Supply Current vs. Sample Rate (Using FULLPD and Internal Reference) 1 10 100 1k 10k 100k SAMPLING RATE (sps) Figure 10b. Average Supply Current vs. Sampling Rate (Using FULLPD and External Reference) ______________________________________________________________________________________ 17 MAX1280/MAX1281 Table 4 details the four power modes with the corresponding supply current and operating sections. For data rates achievable in software power-down modes, see Power-Down Sequencing. power consumption using the specified power-down mode, with the internal reference and the maximum clock speed. The clock speed in FASTPD or REDP should be limited to 4.8MHz for the MAX1280/ MAX1281. FULLPD mode may provide increased power savings in applications where the MAX1280/ MAX1281 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. Internal and External References The MAX1280/MAX1281 can be used with an internal or external reference. An external reference can be connected directly at REF or at the REFADJ pin. 2.5 NORMAL OPERATION SUPPLY CURRENT (mA) MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference An internal buffer is designed to provide 2.5V at REF for both the MAX1280/MAX1281. The internally trimmed 1.22V reference is buffered with a gain of +2.05V/V. 2.0 REDP FASTPD 1.5 Internal Reference The MAX1280/MAX1281’s full-scale range with the internal reference is 2.5V for unipolar inputs and ±1.25V for bipolar inputs. The internal reference voltage is adjustable to ±100mV with the circuit of Figure 13. 1.0 MAX1281, VDD1 = VDD2 = 3.0V CLOAD = 20pF CODE = 101010000000 0.5 0 50 200 150 100 250 300 External Reference An external reference can be placed at either the input (REFADJ) or the output (REF) of the internal referencebuffer amplifier. The REFADJ input impedance is typically 17kΩ. At REF, the DC input resistance is a minimum of 350 SAMPLING RATE (sps) Figure 11. Average Supply Current vs. Sampling Rate (Using REPD, FASTPD, and Normal Operation and Internal Reference) WAIT 2ms (10 x RC) 0 0 1 DIN 1 0 1 REDP FULLPD 0 0 1 FULLPD DUMMY CONVERSION 1.22V 1 1.22V RE FADJ 0V γ = RC = 17kΩ x 0.01µF 2.5V 2.5V REF 0V 2.5mA IVDD1 + IVDD2 2.5mA 2.5mA 1.3mA OR 0.9mA 0mA 0mA Figure 12a. Full Power-Down Timing 1 0 1 DIN REF 0 1 1 REDP REDPD FASTPD 2.5V (ALWAYS ON) 2.5mA IVDD1 + IVDD2 1 0 1 2.5mA 0.9mA 2.5mA 0.9mA 1.3mA Figure 12b. Reduced-Power/Fast Power-Down Timing 18 ______________________________________________________________________________________ 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference MAX1280/MAX1281 +3.3V OUTPUT CODE 24k MAX1281 510k 100k 12 011 . . . 111 FS = VREF + VCOM 2 011 . . . 110 ZS = COM REFADJ -VREF + VCOM 2 V 1LSB = REF 4096 -FS = 000 . . . 010 0.01µF 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 Figure 13. MAX1281 Reference-Adjust Circuit 111 . . . 101 OUTPUT CODE 100 . . . 001 100 . . . 000 FULL-SCALE TRANSITION 11 . . . 111 - FS 11 . . . 110 COM* +FS - 1LSB INPUT VOLTAGE (LSB) 11 . . . 101 *VCOM ≤ VREF / 2 FS = VREF + VCOM ZS = VCOM V 1LSB = REF 4096 00 . . . 011 00 . . . 010 tions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = 610µV for unipolar and bipolar operation. Layout, Grounding, and Bypassing 00 . . . 001 00 . . . 000 0 1 (COM) Figure 15. Bipolar Transfer Function, Full Scale (FS) = VREF / 2 + VCOM, Zero Scale (ZS) = VCOM 2 3 INPUT VOLTAGE (LSB) FS FS - 3/2LSB Figure 14. Unipolar Transfer Function, Full Scale (FS) = VREF + VCOM, Zero Scale (ZS) = VCOM 18kΩ. During conversion, an external reference at REF must deliver up to 350µA DC load current and have 10Ω or less output impedance. If the reference has a higher output impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor. Using the REFADJ input makes buffering the external reference unnecessary. To use the direct REF input, disable the internal buffer by connecting REFADJ to VDD1. Transfer Function Table 5 shows the full-scale voltage ranges for unipolar and bipolar modes. Figure 14 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 15 shows the bipolar I/O transfer function. Code transi- For best performance, use printed circuit boards; wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 16 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at GND. Connect all analog grounds to the star ground. Connect the digital system ground to star ground at this point only. For lowest-noise operation, the ground return to the star ground’s power supply should be low impedance and as short as possible. High-frequency noise in the VDD1 power supply may affect the high-speed comparator in the ADC. Bypass the supply to the star ground with 0.1µF and 10µF capacitors, located close to pin 20 of the MAX1280/ MAX1281. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10Ω resistor can be connected as a lowpass filter (Figure 16). ______________________________________________________________________________________ 19 MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference Table 5. Full Scale and Zero Scale UNIPOLAR MODE BIPOLAR MODE Full Scale Zero Scale Positive Full Scale Zero Scale Negative Full Scale VREF + VCOM COM VREF / 2 + VCOM VCOM -VREF / 2 + VCOM connected with the MAX1280/MAX1281’s SCLK input. SUPPLIES VDD1 VDD2 GND R* = 10Ω VDD1 GND COM VDD2 VDD DGND DIGITAL CIRCUITRY MAX1280 MAX1281 *OPTIONAL Figure 16. Power-Supply Grounding Connection 2) The MAX1280/MAX1281’s CS pin is driven low by the TMS320’s XF_ I/O port to enable data to be clocked into the MAX1280/MAX1281’s DIN pin. 3) An 8-bit word (1XXXXX11) should be written to the MAX1280/MAX1281 to initiate a conversion and place the device into normal operating mode. See Table 1 to select the proper XXXXX bit values for your specific application. 4) The MAX1280/MAX1281’s SSTRB output is monitored through the TMS320’s FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX1280/MAX1281. 5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) Pull CS high to disable the MAX1280/MAX1281 until the next conversion is initiated. High-Speed Digital Interfacing with QSPI The MAX1280/MAX1281 can interface with QSPI using the circuit in Figure 17 (fSCLK = 4.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own microsequencer. TMS320LC3x Interface Figure 18 shows an application circuit that interfaces the MAX1280/MAX1281 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 19. Use the following steps to initiate a conversion in the MAX1280/MAX1281 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and with CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are 20 Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1280/MAX1281 are measured using the endpoint method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. ______________________________________________________________________________________ 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference ANALOG INPUTS VDD1 +3V OR +5V 1 CH0 VDD1 20 2 CH1 VDD2 19 (POWER SUPPLIES) 3 CH2 SCLK 18 SCK 4 CH3 MAX1280 MAX1281 0.1µF 10µF CS 17 PCS0 DIN 16 MOSI 5 CH4 6 CH5 SSTRB 15 7 CH6 DOUT 14 8 CH7 GND 13 9 COM REFADJ 12 10 SHDN REF 11 MAX1280/MAX1281 +3V OR +5V MC683XX MISO 4.7µF 0.01µF (GND) Figure 17. QSPI Connections Signal-to-Noise Ratio XF CLKX For a waveform perfectly reconstructed from digital samples, Signal-to-noise ratio (SNR) is the ratio of fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): CS SCLK TMS320LC3x MAX1280 MAX1281 CLKR DX DIN DR DOUT FSR SSTRB SNR = (6.02 ✕ N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Figure 18. MAX1280/MAX1281-to-TMS320 Serial Interface Signal-to-noise ratio plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to RMS equivalent of all other ADC output signals. SINAD (dB) = 20 ✕ log (SignalRMS / NoiseRMS) Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken. ______________________________________________________________________________________ 21 MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference CS SCLK DIN SSTRB START SEL2 SEL1 SEL0 UNI/BIP SGI/DIF PD1 PD0 HIGH IMPEDANCE DOUT MSB B10 B1 B0 HIGH IMPEDANCE Figure 19. MAX1280/MAX1281-to-TMS320 Serial Interface Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: Ordering Information (continued) TEMP. RANGE PART MAX1281BCUP MAX1281BEUP ENOB = (SINAD - 1.76) / 6.02 0°C to +70°C -40°C to +85°C Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: 20 TSSOP 20 TSSOP ±1 ±1 +5V OR +3V CH0 0 TO +2.5V ANALOG INPUTS where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics, respectively. 4.7µF Spurious-Free Dynamic Range 0.01µF Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. INL (LSB) Typical Operating Circuit Total Harmonic Distortion (THD) 2 2 2 2 2 V2 + V3 + V4 + V4 + V5 THD = 20 × log V1 PINPACKAGE VDD1 VDD 0.1µF VDD2 MAX1280 GND MAX1281 CH8 COM REF CS SCLK DIN REFADJ DOUT SSTRB SHDN CPU I/O SCK (SK) MOSI (SO) MISO (SI) VSS ___________________Chip Information TRANSISTOR COUNT: 4286 PROCESS: BiCMOS 22 ______________________________________________________________________________________ 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference TSSOP.EPS ______________________________________________________________________________________ 23 MAX1280/MAX1281 ________________________________________________________Package Information MAX1280/MAX1281 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.