LT1002 Dual, Matched Precision Operational Amplifier U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ The LT ®1002 dual, matched precision operational amplifiers combine excellent individual amplifier performance with tight matching and temperature tracking between amplifiers. Guaranteed low offset voltage LT1002A 60µV max LT1002 100µV max Guaranteed offset voltage match LT1002A 40µV max LT1002 80µV max Guaranteed low drift LT1002A 0.9µV/°C max LT1002 1.3µV/°C max Guaranteed CMRR LT1002A 110dB min LT1002 110dB min Guaranteed channel separation LT1002A 132dB min LT1002 130dB min Guaranteed maching characteristics Low noise 0.35µV p-p In the design, processing, and testing of the device, particular attention has been paid to the optimization of the entire distribution of several key parameters and their matching. Consequently, the specifications of even the low cost commercial grade (the LT1002C) have been spectacularly improved compared to presently available devices. Essentially, the input offset voltage of all units is less than 80µV, and matching between amplifiers is consistently beter than 60µV (see distribution plot below). Input bias and offset currents, channel separation, common mode and power suply rejections of the LT1002C are all specified at levels which were previsouly attainable only on very expensive, selected grades of other dual devices. Power dissipation is nearly halved compared to the most popular precision duals, without adversely affecting noise or speed performance. A by-product of lower dissipation is decreased warm-up drift. For even better performance in a single precision op amp, refer to the LT1001 data sheet. A bridge signal conditioning application is shown below. This circuit illustrates the requirement for both excellent matching and individual amplifier specifications. U APPLICATIONS ■ ■ ■ ■ ■ ■ Thermocouple Amplifiers Strain Gauge Amplifiers Low level signal processing Medical instrumentation Precision dual limit threshold detection Instrumentation amplifiers , LTC and LT are registered trademarks of Linear Technology Corporation. Strain Gauge Signal Conditioner with Bridge Excitation Distribution of Offset Voltage Match +15V +15V LM329 4 4.99k* / LT1002 1 2 3 70 100Ω 5W + 13 2k – REFERENCE OUT TO MONITORING A/D CONVERTER 2N2219 3 * 301k – + + 6 6 LT1001 – 1µF GAIN TRIM IN4148 / LT1002 1 2 11 10k ZERO 2 2N2907 0 TO 10V OUT 340k* 1.1k* 50 40 30 20 10 0 –100 –80 –60 –40 –20 0 20 40 60 80 100 INPUT OFFSET VOLTAGE MATCH (µV) 2k 100Ω 5W *RN60C FILM RESISTORS –15V VS = ±15V TA = 25°C 287 UNITS TESTED IN4148 350Ω BRIDGE 10 60 NUMBER OF UNITS 8.2k 2.0K* 1002 TA01 1002 TA02 1 LT1002 W U U W W W Supply Voltage (Note 6)......................................... ±22V Differential Input Voltage ...................................... ±30V Input Voltage Equal to Supply Voltage Output Short Circuit Duration ......................... Indefinite Operating Temperature Range LT1002AM/LT1002M ....................... – 55°C to 125°C LT1002AC/LT1002C ............................... 0°C to 70°C Storage Temperature Range All Grades ......................................... – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)................. 300°C U ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION ORDER PART NO. OFFSET VOLTAGE MAX at 25°C LT1002AMJ LT1002MJ LT1002ACJ LT1002CJ LT1002ACN LT1002CN 60µV 100µV 60µV 100µV 60µV 100µV TOP VIEW 14 V+ (A) NULL (A) 1 13 OUT (A) NULL (A) 2 –IN (A) 3 +IN (A) 4 – 12 V– (A) A + V– (B) 5 + B – 11 +IN (B) 10 –IN (B) 9 NULL (B) OUT (B) 6 8 NULL (B) V+ (B) 7 J PACKAGE 14 PIN HERMETIC N PACKAGE 14 PIN PLASTIC NOTE: Device may be operated even if insertion is reversed; this is due to inherent symmetry of pin locations of amplifiers A and B. (Note 6) U W ELECTRICAL CHARACTERISTICS, I DIVIDUAL A PLIFIERS VS = ±15V, TA = 25°C, unless otherwise noted LT1002AM/LT1002AC MIN TYP MAX 20 60 LT1002M/LT1002C MIN TYP MAX 25 100 SYMBOL VOS PARAMETER Input Offset Voltage CONDITIONS Note 1 ∆VOS ∆Time IOS Long Term Input Offset Voltage Stability Notes 2 and 3 IB Input Bias Current en Input Noise Voltage 0.1Hz to 10Hz (Note 2) 0.35 0.7 0.38 0.75 µVp-p en Input Noise Voltage Density fO = 10Hz (Note 5) fO = 1000Hz (Note 2) 10.3 9.6 20.0 11.5 10.5 9.8 20.0 12.0 nV√Hz AVOL Large Signal Voltage Gain RL ≥ 2kΩ, VO = ±12V RL ≥ 1kΩ, VO = ±10V CMRR Common Mode Rejection Ratio VCM = ±13V 110 126 110 126 dB PSRR Power Supply Rejection Ratio VS = ±3V to ±18V 108 123 105 123 dB Rin Input Resistance Differential Mode Note 4 0.3 Input Offset Current Input Voltage Range RL ≥ 2kΩ RL ≥ 1kΩ 400 250 20 1.5 0.4 2.0 UNITS µV µV/month 0.3 2.8 0.4 4.2 nA ±0.6 ±3.0 ±0.7 ±4.5 nA 800 500 350 220 100 800 500 V/mV 13 80 MΩ ±13 ±14 ±13 ±14 V ±13 ±12 ±14 ±13.5 ±13 ±12 ±14 ±13.5 V VOUT Maximum Output Voltage Swing SR Slew Rate RL ≥ 2kΩ (Note 4) 0.1 0.25 0.1 0.25 V/µs GBW Gain Bandwidth Product Note 4 0.4 0.8 0.4 0.8 MHz Pd Power Dissipation per amplifier No load No load, VS = ±3V 2 46 4 75 7 48 4 85 8 mW LT1002 U W ELECTRICAL CHARACTERISTICS, I DIVIDUAL A PLIFIERS VS = ±15V, – 55°C ≤ TA ≤ 125°C, unless otherwise noted SYMBOL VOS PARAMETER Input Offset Voltage CONDITIONS Note 1 MIN ● LT1002AM TYP MAX 30 150 MIN LT1002M TYP MAX 45 230 UNITS µV Average Input Offset Voltage Drift ● 0.2 0.9 0.3 1.3 µV/°C IOS Input Offset Current ● 0.8 5.6 1.2 8.5 nA IB Input Bias Current ±1.0 ±6.0 ±1.5 ±9.0 AVOL Large Signal Voltage Gain CMRR PSRR ∆VOS ∆Temp ● nA RL ≥ 2kΩ, VO = ±10V ● 300 700 200 700 V/mV Common Mode Rejection Ratio VCM = ±13V ● 106 122 104 120 dB Power Supply Rejection Ratio VS = ±3V to ±18V ● 102 117 96 117 dB ● ±13 VOUT Output Voltage Swing RL ≥ 2kΩ ● ±12.5 ±13.5 Pd Power Dissipation per amplifier No load ● Input Voltage Range ±14 55 ±13 ±14 V ±12.0 ±13.5 V 90 60 100 mW LT1002C TYP MAX 30 160 UNITS µV VS = ±15V, 0°C ≤ TA ≤ 70°C, unless otherwise noted SYMBOL VOS ∆VOS ∆Temp PARAMETER Input Offset Voltage CONDITIONS Note 1 MIN ● LT1002AC TYP MAX 20 100 Average Input Offset Voltage Drift ● 0.2 IOS Input Offset Current ● 0.5 4.2 IB Input Bias Current ● ±0.7 ±4.5 MIN 0.9 1.3 µV/°C 0.6 5.7 nA ±1.0 ±6.0 nA 0.3 AVOL Large Signal Voltage Gain RL ≥ 2kΩ, VO = ±10V ● 350 750 250 750 V/mV CMRR Common Mode Rejection Ratio VCM = ±13V ● 108 124 106 123 dB PSRR Power Supply Rejection Ratio VS = ±3V to ±18V ● 105 120 100 120 dB ● ±13 ±14 ±13 ±14 V ±12.5 ±13.8 Input Voltage Range VOUT Output Voltage Swing RL ≥ 2kΩ ● Pd Power Dissipation per amplifier No Load ● The ● denotes the specifications which apply over the full operating temperature range. For MIL-STD components, please refer to LTC 883C data sheet for test listing and parameters. Note 1: Offset voltage measured with high speed test equipment, approximately 1second after power is applied. Note 2: This parameter is tested on a sample basis only. Note 3: Long Term Input Offset Voltage Stability refers to the averaged trend line of VOS versus Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5µV. ±12.5 ±13.8 50 85 55 V 90 mW Note 4: Parameter is guaranteed by design. Note 5: 10Hz noise voltage density is sample tested on every lot. Devices 100% tested at 10Hz are available on request. Note 6: The V + supply terminals are completely independent and may be powered by separate supplies if desired (this approach, however, would sacrifice the advantages of the power supply rejection ratio matching). The V – supply terminals are both connected to the common substrate and must be tied to the same voltage. Both V – pins should be used. 3 LT1002 W U ATCHI G CHARACTERISTICS at VS = ±15V, TA = 25°C, unless otherwise noted SYMBOL PARAMETER Input Offset Voltage Match IB+ Average Non-Inverting Bias Current LT1002AM/AC MIN TYP MAX – 15 40 CONDITIONS ±0.6 – ±3.5 MIN – – LT1002M/C TYP MAX 25 80 ±0.7 ±4.8 UNITS µV nA IOS+ IOS– Non-Inverting Offset Current – 0.6 3.5 – 0.7 6.0 nA Inverting Offset Current – 0.6 3.5 – 0.7 6.0 nA ∆CMRR Common Mode Rejection Ratio Match VCM = ±13V 110 132 – 108 132 – dB Power Supply Rejection Ratio Match VS = ±3V to ±18V 108 130 – 102 128 – dB Channel Seperation f ≤ 10Hz (Note 4) 132 148 – 130 146 – dB ∆PSRR W U ATCHI G CHARACTERISTICS at VS = ±15V, – 55°C ≤ TA ≤ 125°C, unless otherwise noted SYMBOL ● ● – 0.3 1.0 – 0.4 Average Non-Inverting Bias Current ● – ±1.5 ±6.0 – ±1.8 ±10.0 nA IOS+ IOS– Non-Inverting Offset Current ● – 1.5 6.5 – 1.8 12.0 nA Inverting Offset Current ● – 1.5 6.5 – 1.8 12.0 nA ∆CMRR Common Mode Rejection Ratio Match VCM = ±13V ● 106 126 102 124 – dB Power Supply Rejection Ratio Match VS = ±3V to ±18V ● 102 122 94 120 – dB ∆PSRR MIN – LT1002M TYP MAX 60 230 Input Offset Voltage Tracking IB CONDITIONS LT1002AM TYP MAX 50 140 MIN – + PARAMETER Input Offset Voltage Match 1.5 UNITS µV µV/°C W U ATCHI G CHARACTERISTICS at VS = ±15V, 0°C ≤ TA ≤ 70°C, unless otherwise noted SYMBOL ● ● – 0.3 1.0 – 0.4 1.5 µV/°C Average Non-Inverting Bias Current ● – ±1.0 ±4.5 – ±1.2 ±7.0 nA IOS+ IOS– Non-Inverting Offset Current ● – 1.0 5.0 – 1.2 8.5 nA Inverting Offset Current ● – 1.0 5.0 – 1.2 8.5 nA ∆CMRR Common Mode Rejection Ratio Match VCM = ±13V ● 108 130 – 105 128 – dB ∆PSRR Power Supply Rejection Ratio Match VS = ±3V to ±18V ● 105 126 – 98 124 – dB 4 MIN – LT1002C TYP MAX 45 150 Input Offset Voltage Tracking IB CONDITIONS LT1002AC TYP MAX 30 85 MIN – + PARAMETER Input Offset Voltage Match UNITS µV LT1002 U W TYPICAL PERFORMANCE CHARACTERISTICS Distribution of Offset Voltage Drift with Temperature (Individual Amplifiers) Distribution of Offset Voltage of Individual Amplifiers 70 VS = ±15V TA = 25°C 60 VS = ±15V 30 260 UNITS TESTED 574 UNITS TESTED NUMBER OF UNITS NUMBER OF UNITS 80 35 VS = ±15V 60 40 130 UNITS TESTED 50 25 NUMBER OF UNITS 100 Distribution of Offset Voltage Match Drift with Temperature 40 30 20 20 15 10 20 10 5 0 –1.2 0 –100 –80 –60 –40 –20 0 20 40 60 80 100 INPUT OFFSET VOLTAGE (µV) 1002 G01 100 80 80 LT1002M 40 02AM LT1002AM LT10 20 002AM 0 LT1 –20 LT1002M –40 LT1002M –60 60 VS = ±15V LT1002M LT1002AM AM 1002 40 LT 20 2M T100 0 L –20 LT1002AM –40 LT1002M –60 –80 –80 –100 –50 50 25 0 75 TEMPERATURE (°C) –25 100 125 –100 –50 –25 50 25 0 75 TEMPERATURE (°C) Long Term Stability of Four Representative Units VS = ±15V TA = 25°C 4 N14 PLASTIC PACKGE 3 J14 HERMETIC DIP PACKGE 2 1 0 0 1002 G04 1002 G04 0.1Hz to 10Hz Noise 1 3 4 2 TIME AFTER POWER ON – BOTH AMPLIFIERS (MINUTES) 5 1002 G06 Noise Spectrum 100 10 10 0 –5 VOLTAGE NOISE nV/√Hz 5 30 3 1/f CORNER 4Hz VOLTAGE 10 1 1/f CORNER 70Hz 3 0.3 CURRENT NOISE pA/√Hz TA = 25°C VS = ±3 TO ±18V NOISE VOLTAGE 100nV/DIV OFFSET VOLTAGE CHANGE (µV) Warm-Up Drift 125 100 0 +0.4 +0.8 +1.2 –0.8 –0.4 OFFSET VOLTAGE MATCH DRIFT WITH TEMPERATURE (µV/°C) 1002 G03 5 CHANGE IN OFFSET VOLTAGE (MICROVOLTS) 100 60 –1.2 Offset Voltage Tracking with Temperature of Six Representative Units OFFSET VOLTAGE MATCH (µV) INDIVIDUAL AMPLIFIER OFFSET VOLTAGE (µV) Offset Voltage Drift with Temperature of Six Representative Units 0 +0.4 +0.8 +1.2 –0.8 –0.4 INPUT OFFSET VOLTAGE DRIFT WITH TEMPERATURE (µV/°C) 1002 G02 CURRENT –10 0 1 3 2 TIME (MONTHS) 4 5 1001 G07 0 2 6 4 TIME (SECONDS) 8 10 1001 G08 1 1 10 100 FREQUENCY (Hz) 0.1 1000 1002 G09 5 LT1002 U W TYPICAL PERFORMANCE CHARACTERISTICS 30 1.5 VS = ±15V 1.0 1.6 1.4 MATCHING: NON INVERTING BIAS CURRENT 1.2 1.0 M N O ATC N -I H I N G N V . : IN V IV I DU OFFS ERING & AL ET CU A RRENT M IND P BI AS C IV I DU URRE AL A NT MP O FFS E T C U R RENT IN D 0.8 0.6 0.4 0.2 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 Ib VCM 0.5 DEVICE WITH POSITIVE INPUT CURRENT VS = ±15V TA = 25°C 0 –.5 DEVICE WITH NEGATIVE INPUT CURRENT –1.0 –1.5 –15 125 – + IB ≈ 1 nA 10 –5 0 5 –10 COMMON-MODE INPUT VOLTAGE 0 0.1 15 Gain, Phase Shift vs. Frequency 200k 120 100 80 VS = ±15V 60 40 VS = ±3V 20 100 –20 0.1 125 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 1002 G13 0.6 0.4 PERCENT GAIN MISMATCH = OUTPUT A – OUTPUT B × 100% 1/2 (OUTPUT A + OUTPUT B) 10k 100k 1002 G16 6 180 VS = ±15V 200 PHASE MARGIN –55°C = 63° 125°C = 57° –8 0.1 220 2 1 0.5 FREQUENCY (MHz) 0.2 1002 G15 Power Supply Rejection and PSRR Match vs Frequency 10 AV = 1000 1 AV = +1 0.1 IO = ±1mA VS = ±15V TA = 25°C 0.001 1k 100 FREQUENCY (Hz) 160 160 0.01 0 10 0 100 OUTPUT IMPEDANCE (Ω) OPEN LOOP GAIN MISMATCH (PERCENT) 0.8 1 GAIN 125°C 140 GAIN 25°C & –55°C Closed Loop Output Impedance VS = ±15V TA = 25°C 0.2 4 25°C PHASE MARGIN = 60° 1002 G14 Open Loop Gain Mismatch vs Frequency 1.0 120 8 POWER SUPPLY REJECTION (dB) 50 25 75 0 TEMPERATURE (°C) 100 PHASE 25°C 12 –4 0 0 –50 –25 80 16 TA = 25°C VOLTAGE GAIN (dB) 400k OPEN LOOP VOLTAGE GAIN (dB) OPEN LOOP VOLTAGE GAIN (V/V) VS = ±3V, VO = ±1V 600k 30 20 140 800k 0.3 1.0 3.0 10 ± DIFFERENTIAL INPUT (VOLTS) 1002 G12 Open Loop Voltage Gain Frequency Response VS = ±15V, VO = ±12V 10 1002 G11 Open Loop Voltage Gain vs Temperature 1000k 20 COMMON-MODE INPUT RESISTANCE = 28V = 280G Ω 0.1nA 1001 G10 1200k VS = ±15V TA = 25°C INVERTING OR NON-INVERTING INPUT BIAS CURRENT (mA) 1.8 INPUT BIAS CURRENT (nA) INPUT BIAS AND OFFSET CURRENTS (nA) 2.0 Input Bias Current vs. Differential Input Voltage Input Bias Current Over the Common Mode Range PHASE SHIFT (DEGREES) Matching and Individual Amplifier Bias and Offset Currents vs Temperature 1 10 1k 100 FREQUENCY (Hz) 10k 100k 1002 G17 VS = ±15V ±2V pp TA = 25°C MATCH (NEGATIVE SUPPLY) 140 120 100 80 60 NEGATIVE SUPPLY POSITIVE SUPPLY 40 MATCH (POSITIVE SUPPLY) 20 0 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1002 G18 LT1002 U W TYPICAL PERFORMANCE CHARACTERISTICS Common Mode Rejection and CMRR Match vs Frequency Channel Separation vs Frequency CHANNEL SEPARATION (dB) 150 RS =10Ω 140 130 120 RS =100Ω 110 100 RS =1k 90 160 VS = ±15V TA = 25°C 140 120 MATCH (< CMRR) 100 CMRR 80 60 40 20 0 80 100 1k 100k 10k FREQUENCY (Hz) 1 1M 10 100 1k 10k FREQUENCY (Hz) 100k 1M Supply Churrent vs. Supply Voltage For Each Amplifier V + = 12 to 18V V – = –12 to –18V V – = –1.2 to –4V 50 25 75 0 TEMPERATURE (°C) 125°C 1.0 0.5 100 125 1002 G21 Maximum Undistorted Output vs. Frequency OUTPUT VOLTAGE, PEAK-TO-PEAK (VOLTS) 25°C 1.5 ±3 V + = 1.2 to 4V +1.0 +.8 +.6 +.4 +.2 V– –50 –25 Large Signal Transient Response 2.0 –55°C V+ –0.2 –0.4 –0.6 –0.8 –1.0 1002 G20 1002 G19 28 VS = ±15V TA = +25°C 24 20 16 12 8 4 0 ± 6 ± 9 ± 12 ± 15 ± 18 ± 21 SUPPLY VOLTAGE (V) 1002 G23 1 10 100 FREQUENCY (kHz) 1000 1002 G24 1002 G22 Voltage Follower Overshoot vs Capacitive Load Small Signal Transient Response Small Signal Transient Response 100 80 PERCENT OVERSHOOT SUPPLY CURRENT (mA) COMMON MODE LIMIT (VOLTS) REFERRED TO POWER SUPPLY VS = ±15V TA = 25°C COMMON MODE REJECTION (dB) 160 Common Mode Limit vs Temperature VS = ±15V TA = 25°C VIN = 100mV RL > 50k 60 40 20 0 100 AV = +1, CL = 50pF 1002 G25 10,000 1000 CAPACITIVE LOAD (PICOFARADS) 100,000 AV = +1, CL = 1000pF 1002 G27 1002 G26 7 LT1002 U W TYPICAL PERFORMANCE CHARACTERISTICS Output Short Circuit Current vs Time Output Swing vs. Load Resistance 16 SHORT CIRCUIT CURRENT (mA) SINKING SOURCING 50 OUTPUT SWING (VOLTS) NEGATIVE SWING 12 POSITIVE SWING 8 4 VS = ±15V TA = 25°C 0 100 1000 3k 300 LOAD RESISTANCE (Ω) 10k 40 –55°C 30 20 25°C 125°C 10 VS = ±15V –10 125°C –20 25°C –30 –55°C –40 –50 0 1 3 2 TIME FROM OUTPUT SHORT (MINUTES) 1002 G28 4 1002 G29 U W U U APPLICATIONS INFORMATION The LT1002 dual amplifier may be inserted directly into OP-10, OP207, OP227 sockets with or without removal of external nulling potentiometers. nately, the guaranteed offset voltage match of the LT1002 is very low, in most applications offset adjustment will be unnecessary. Standard Adjustment Offset Voltage Adjustment The input offset voltage of the LT1002, and its drift with temperature, are permanently trimmed at wafer testing to a low level. However, if further adjustment of VOS is necessary, nulling with a 10k or 20k potentiometer will not degrade drift with temperature. Trimming to a value other than zero creates a drift of (VOS/ 300)µV/°C, e.g. if VOS is adjusted to 300µV, the change in drift will be 1µV/°C. The adjustment range with a 10k or 20k pot is approximately ±2.5mV. If less adjustment range is needed, the sensitivity and resolution of the nulling can be improved by using a smaller pot in conjunction with fixed resistors. The example has an approximate null range of ±100µV. 10k or 20k 1 (8) 2 3 – +15V (9) 14 (7) (10) 1/2 LT1002 INPUT 4 (11) + –15V 1002 TA03 Improved Sensitivity Adjustment 7.5k 7.5k (8) 2 (9) 3 – 14 (7) (10) 1/2 LT1002 INPUT 13 (6) 4 + 12 (5) (11) +15V 1 –15V 8 OUTPUT 12 (5) 1k In matching applications, both amplifiers can be trimmed to zero, or the offset of one amplifier can be trimmed to match the offset of the other. Offset adjustment, however, slightly degrades the gain, common-mode and powersupply rejection match between the two op amps. Fortu- 13 (6) OUTPUT 1002 TA04 LT1002 U W U U APPLICATIONS INFORMATION 0.1Hz to 10Hz Noise Test Circuit Test Circuit for Offset Voltage and its Drift with Temperature The device under test should be warmed up for three minutes and shielded from air currents. Turn the device 180° to measure the noise of side B. *50k 0.1µF +15V 3 – 14 (7) (10) 100Ω * 4 + 100kΩ 10Ω – 1/2 LT1002 * –15V *RESISTORS MUST HAVE LOW THERMOELECTRIC POTENTIAL. VO = 1000 VOS VOLTAGE GAIN = 50,000 VO 12 (5) (11) 50k 13 (6) 1/2 LT1002 1002 TA05 + 2kΩ A DEVICE UNDER TEST + 1/2 LT1002 4.7 µF – 22µF B 100k 24.3k 4.3k 2.2µF 0.1 µF SCOPE ×1 RIN = 1MΩ 110k 1002 TA06 This circuit is also used as burn-in configuration for the LT1002, with supply voltages increased to ±20V. Unless proper care is exercised, thermocouple effects, caused by temperature gradients across dissimilar metals at the contacts to the input terminals, can exceed the inherent drift of the amplifier. Air currents should be minimized, package leads should be short, the two input leads should be as close together as possible and maintained at the same temperature. Channel Separation This parameter is defined as the ratio of the change in input offset voltage of one amplifier to the change in output voltage of the other amplifier causing the offset change. At low frequencies the LT1002’s channel separation is an almost unmeasurable 148dB. As frequency increases, pin to pin capacitance of the package, between the output of one amplifier and the inputs of the other, becomes dominant. Since these pins are non-adjacent, the capacitance is only 0.02pF. To maintain the LT1002’s excellent channel separation at higher frequencies, the socket and PC board capacitances should be minimized. (Peak to Peak noise measured in 10 Sec interval) Power supplies The LT1002 is specified over a wide range of power supply voltages from ±3V to ±18V. Operation with lower supplies is possible, down to ±1.2V (two Ni-Cad batteries). However, with ±1.2V supplies, the device is stable only in closed loop gains of + 2 or higher (or inverting gain of one or higher). The V+ supply terminals are completely independent and may be powered by separate supplies if desired (this approach, however, would sacrifice the advantages of the power supply rejection ratio matching). The V– supply terminals are both connected to the common substrate and must be tied to the same voltage. Both V – pins should be used. 9 LT1002 U W U U APPLICATIONS INFORMATION Advantages of Matched Dual Op Amps In many applications the performance of a system depends on the matching between two operational amplifiers rather than the individual characteristics of the two op amps. Two or three op amp instrumentation amplifiers, tracking voltage references and low drift active filters are some of the circuits requiring matching between two op amps. The well-known triple op amp configuration illustrates these concepts. Output offset is a function of the difference between the offsets of the two halves of the LT1002. This error cancellation principle holds for a considerable number of input referred parameters in addition to offset voltage and its drift with temperature. Input bias current will be the average of the two non-inverting input currents (IB+). The difference between these two currents (IOS+) is the offset current of the instrumentation amplifier. The difference between the inverting input currents (IOS–) will cause errors flowing through R1, R2, and R3. Commonmode and power supply rejections will be dependent only on the match between the two amplifiers (assuming perfect resistor matching). The concepts of common mode and power supply rejection ratio match (∆CMRR and ∆PSRR) are best demonstrated with a numerical example: Assume CMRRA = + 1.0µV/V or 120dB, and CMRRB = + 0.75µV/V or 122.5dB, then ∆CMRR = 0.25µV/V or 132dB; if CMRRB = – 0.75µV/V which is still 122.5dB, then ∆CMRR = 1.75µV/V or 115dB. Clearly, the LT1002, by specifying and guaranteeing all of these matching parameters, can significantly improve the performance of matching dependent circuits. 10 Three Op Amp Instrumentation Amplifier INPUT – + A 1/2 LT1002 – R1 10k 1% R3 2.1k 1% R8 R4 R6 100Ω 1% 10k 1% – R10 100k 200Ω C1 100pF – R2 B 1/2 LT1002 INPUT + + LT1037 OUTPUT + Gain = 1000 10k 1% R5 100Ω 1% R7 9.76k 1% R9 200Ω 1002 TA07 Trim R8 for gain Trim R9 for DC common mode rejection Trim R10 for AC common mode rejection Typical performance of the instrumentation amplifier: Input offset voltage = 25µV Input bias current = 0.7nA Input resistance = 200 GΩ Input offset current = 0.6nA Input noise = 0.5µV p-p Power bandwidth (V0 = ±10V) = 80kHz LT1002 U U W U APPLICATIONS INFORMATION Precision ±10V Reference +15V 130k 5% 3.3k 4 0.1% 14 + 10k 13 1/2 LT1002 3 10 0.1% – 12 LM129A OUT 1 10.000V 10k 1% 7 – 6 1/2 LT1002 11 + OUT 2 –10.000V 5 3.3k 8.2k 1% 1% 1k –15V 1002 TA08 The LT1002 contributes less than 5% of the total drift with temperature, noise and long term drift of the reference. The accuracy of the –10V output is limited by the matching of the two 10k resistors. Dual Limit Microvolt Comparator +15V 430k 14 UPPER LIMIT 3 1% – 1 1/2 LT1002 4 39.2Ω 1% 1k 5% FLV117 15k 1% 13 1/4 CA3118 20k 5% + 12 1/4 CA3118 –15V INPUT 430k 10 1% 7 – 8 1/2 LT1002 LOWER LIMIT 11 + 39.2Ω 1% 15k 1% 6 5 1/4 CA3118 1/4 CA3118 –15V 1002 TA09 When the upper or lower limit is exceeded the LED lights up. Positive feedback to one of the nulling terminals creates 5 to 20µV of hysteresis on both amplifiers. This feedback changes the offset voltage of the LT1002 by less than 5µV. Therefore, the basic accuracy of the comparator is limited only by the low offset voltage of the LT1002. 11 LT1002 U U W U APPLICATIONS INFORMATION Two Op Amp Instrumentation Amplifier R5 2.2k+ R1 R2 R4 100k* 10k 100k – R3 1/2 LT1002 – – 10k + 1/2 LT1002 OUTPUT + INPUTS + 1002 TA10 * TRIM FOR COMMON-MODE REJECTION + TRIM FOR GAIN Gain = R4 1 1+ R3 2 ( ) R2 R3 R2 + R3 + + ≈ 100 R1 R4 R5 Precision Amplifier Drives 500Ω Load to ±10V 1.1Rf + 0.1RS 110k RS This application utilizes the guaranteed 10mA load driving capability of the LT1002. The offset voltage of amplifier A is the offset of the configuration. Amplifier B provides the additional 10mA load current. When load resistor RL is removed, amplifier A sinks this current without affecting accuracy. In the gain of 1000 configuration shown, approximately 0.3% gain accuracy can be realized. +15 – B 1/2 LT1002 100Ω + –15V 100Ω 0.2RL Rf 100k RS +15V – A 100Ω OUTPUT 1/2 LT1002 + INPUT 12 –15V 500Ω RL 1002 TA11 LT1002 U U W U APPLICATIONS INFORMATION Dead Zone Generator INPUT Q4 ** 100k ** 100k 2 BIPOLAR SYMMETRY IS EXCELLENT BECAUSE ONE DEVICE, Q2, SETS BOTH LIMITS 6 8 + 100k Q3 Q2 – LM301A 3 VSET DEAD ZONE CONTROL INPUT 0 to 5V 10k* 47pF 10k* 4.7k 2k 1 3 30pF 2N4393 Q1 10k** – 1/2 LT1002 4 IN914 10k** 10 13 + – 1/2 LT1002 10k 11 10k 15pF 2 – LM301A 3 2N4393 Q6 4.7k 15pF 6 + VOUT + +15V 100k 6 4.7k 3.3k IN914 Q5 VSET VOUT 1k –15V VIN * 1% FILM ** RATIO MATCH 0.05% Q2, 3, 4, 5 CA 3096 TRANSISTOR ARRAY VSET 1002 TA12 Precision Absolute Value Circuit 10k 0.1% INPUT –10 to 10V 10k 3 0.1% 1/2 LT1002 4 0.1% 0.1% IN4148 – 10k 10k 10 13 1/2 LT1002 11 + – + 6 OUTPUT 0 to 10V IN4148 10k 1002 TA13 0.1% 13 LT1002 U U W U APPLICATIONS INFORMATION 22k* 100Ω 43k* (select) 3 +15 100Ω 5W – 2k 1/2 LT1002 +15V 4 Dual Precision Power Supply (1) 0 to 10V in 100µV Steps (2) 0 to 100V in 1mV Steps 2N2219 13 + OUTPUT 1 0-10V 25mA IN914 8.2k TRIAD TY-90 VN-46 LM399 DIODES = SEMTECH # FF-15 KVD 00000 – 99999 + 1 –15V KVD= ESI#DP311 *= JULIE RSCH. LABS #R-44 25k + KELVIN-VARLEY DIVIDER ESI#DP311 4 VN-46 0.1 2.2 TRIM–100V 100Ω – LT301A 3 + D CLK 6 Q 2N6533 33k + 22µf 6 IN914 10 1/2 LT1002 + 11 15Ω 33k +15 – 2k Q 74C74 33k OUTPUT 2 0-100V, 25mA 10k* (select) + 680pF 2 90k* +15 +15V 1.8k CLAMP SET 2N2907 5k IN914 1002 TA14 14 LT1002 W W SCHE ATIC DIAGRA V+ 6k 6k Q29 Q27 NULL Q24 Q25 Q28 NULL 40k 40k 1.5k Q13 Q11 Q5 Q14 25k Q12 Q6 3k Q8 Q7 Q31 Q4 Q3 55pF 20pF Q33 20 + 500 Q1A Q2B Q1B 30pF Q2A Q26 3k IN – OUT Q21 20 Q34 Q16 Q10 500 Q15 IN 2k 180 Ω 1/2 LT1002 Q20 2k Q17 Q23 Q18 Q30 Q9 120 8k Q19 V– Q32 Q22 T1 240 1002 SS U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package 14-Lead PDIP (Narrow 0.300) J Package 14-Lead CERDIP (Narrow 0.300, Hermetic) (LTC DWG # 05-08-1510) (LTC DWG # 05-08-1110) CORNER LEADS OPTION (4 PLCS) 0.770* (19.558) MAX 14 13 11 12 10 9 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 1 0.130 ± 0.005 (3.302 ± 0.127) 2 3 4 0.005 (0.125) +0.635 8.255 MIN –0.381 0.100 ± 0.010 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) ) 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 7 0.125 (3.175) MIN LT1002ACN LT1002CN 13 12 11 10 9 8 0.220 – 0.310 (5.588 – 7.874) 0.025 (0.635) RAD TYP 2 1 3 4 5 6 7 0.200 (5.080) MAX 0.300 BSC (0.762 BSC) 0.015 – 0.060 (0.381 – 1.524) 0.065 (1.651) TYP 0.009 – 0.015 (0.229 – 0.381) ( 6 14 0.045 – 0.065 (1.143 – 1.651) 0.015 (0.380) MIN +0.025 0.325 –0.015 5 0.785 (19.939) MAX 8 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.005 (0.127) MIN 0.018 ± 0.003 (0.457 ± 0.076) N14 0695 0.008 – 0.018 (0.203 – 0.457) 0° – 15° 0.385 ± 0.025 (9.779 ± 0.635) 0.100 ± 0.010 (2.540 ± 0.254) 0.045 – 0.068 (1.143 – 1.727) 0.014 – 0.026 (0.360 – 0.660) 0.125 (3.175) MIN J14 0694 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS. TJMAX θJA LT1002ACJ LT1002CJ 125°C 100°C/W LT1002AMJ LT1002MJ TJMAX θJA 125°C 100°C/W 125°C 100°C/W Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT1002 16 Linear Technology Corporation LT/GP 0396 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1985