19-3244; Rev 0; 10/05 KIT ATION EVALU E L B A AVAIL TFT-LCD DC-DC Converter with Operational Amplifiers The MAX1518B includes a high-performance step-up regulator, two linear-regulator controllers, and high-current operational amplifiers for active-matrix, thin-film transistor (TFT), liquid-crystal displays (LCDs). Also included is a logic-controlled, high-voltage switch with adjustable delay. The step-up DC-DC converter provides the regulated supply voltage for the panel source driver ICs. The converter is a high-frequency (1.2MHz) current-mode regulator with an integrated 14V n-channel MOSFET that allows the use of ultra-small inductors and ceramic capacitors. It provides fast transient response to pulsed loads while achieving efficiencies over 85%. The gate-on and gate-off linear-regulator controllers provide regulated TFT gate-on and gate-off supplies using external charge pumps attached to the switching node. The MAX1518B includes five high-performance operational amplifiers. These amplifiers are designed to drive the LCD backplane (VCOM) and/or the gammacorrection divider string. The device featureS high output current (±150mA), fast slew rate (13V/µs), wide bandwidth (12MHz), and rail-to-rail inputs and outputs. The MAX1518B is available in a 32-pin thin QFN package with a maximum thickness of 0.8mm for ultra-thin LCD panels. Applications Features ♦ 2.6V to 6.5V Input Supply Range ♦ 1.2MHz Current-Mode Step-Up Regulator Fast Transient Response to Pulsed Load High-Accuracy Output Voltage (1.5%) Built-In 14V, 2.4A, 0.16Ω n-Channel MOSFET High Efficiency (90%) ♦ Linear-Regulator Controllers for VGON and VGOFF ♦ High-Performance Operational Amplifiers ±150mA Output Short-Circuit Current 13V/µs Slew Rate 12MHz, -3dB Bandwidth Rail-to-Rail Inputs/Outputs ♦ Logic-Controlled, High-Voltage Switch with Adjustable Delay ♦ Timer-Delay Fault Latch for All Regulator Outputs ♦ Thermal-Overload Protection ♦ 0.6mA Quiescent Current Minimal Operating Circuit VCN VCP VIN VMAIN LX Notebook Computer Displays LCD Monitor Panels IN FB STEP-UP CONTROLLER PGND Automotive Displays COMP AGND VCP MAX1518B DRVP GATE-ON CONTROLLER FBP VGON SRC DEL Ordering Information COM SWITCH CONTROL CTL VCN DRN PART TEMP RANGE PIN-PACKAGE PKG CODE DRVN GATE-OFF CONTROLLER VGOFF SUP MAX1518BETJ -40°C to 32 Thin QFN 5mm x 5mm +100°C T3255-4 NEG1 OUT1 FBN OP1 REF POS1 NEG2 OUT2 REF NEG4 OP2 OP4 POS2 OUT4 POS4 NEG5 OUT3 OP3 OP5 POS3 OUT5 POS5 BGND Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1518B General Description MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers ABSOLUTE MAXIMUM RATINGS IN, CTL to AGND ......................................................-0.3V to +7V COMP, FB, FBP, FBN, DEL, REF to AGND ....-0.3V to (VIN + 0.3V) PGND, BGND to AGND ......................................................±0.3V LX to PGND ............................................................-0.3V to +14V SUP to AGND .........................................................-0.3V to +14V DRVP, SRC to AGND..............................................-0.3V to +30V POS_, NEG_, OUT_ to AGND ...................-0.3V to (VSUP + 0.3V) DRVN to AGND ...................................(VIN - 30V) to (VIN + 0.3V) DRN to AGND...........................................-0.3V to (VSRC + 0.3V) DRN to COM............................................................-30V to +30V OUT_ Maximum Continuous Output Current....................±75mA LX Switch Maximum Continuous RMS Output Current .........1.6A Continuous Power Dissipation (TA = +70°C) 32-Pin Thin QFN (derate 21.2mW/°C above +70°C) ..1702mW Operating Temperature Range .........................-40°C to +100°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER IN Supply Range IN Undervoltage-Lockout Threshold SYMBOL CONDITIONS VIN VUVLO MIN VIN rising, typical hysteresis = 200mV 2.25 VFB = VFBP = 1.4V, VFBN = 0, LX not switching IN Quiescent Current IIN TYP MAX UNITS 6.5 V 2.5 2.70 V 0.6 0.8 6 11 2.6 mA VFB = 1.1V, VFBP = 1.4V, VFBN = 0, LX switching Duration to Trigger Fault Condition 200 REF Output Voltage -2µA < IREF < 50µA, VIN = 2.6V to 5.5V 1.231 Temperature rising Thermal Shutdown 1.250 ms 1.269 +160 Hysteresis V °C 15 MAIN STEP-UP REGULATOR Output Voltage Range VMAIN VIN Operating Frequency fOSC 1020 84 TA = +25°C to +85°C TA = 0°C to +85°C Oscillator Maximum Duty Cycle FB Regulation Voltage VFB No load FB Fault Trip Level VFB falling FB Load Regulation 0 < IMAIN < full load, transient only 13 V 1200 1380 kHz 87 90 % 1.221 1.233 1.245 1.218 1.233 1.247 1.12 1.16 1.19 -1.6 FB Line Regulation VIN = 2.6V to 5.5V FB Input Bias Current VFB = 1.4V -40 FB Transconductance ∆ICOMP = 5µA 75 FB Voltage Gain FB to COMP 2 +0.04 160 600 _______________________________________________________________________________________ V V % ±0.15 %/ V +40 nA 280 µS V/ V TFT-LCD DC-DC Converter with Operational Amplifiers (VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER LX On-Resistance SYMBOL CONDITIONS MIN RLX(ON) LX Leakage Current ILX VLX = 13V LX Current Limit ILIM VFB = 1V, duty cycle = 65% Current-Sense Transconductance Soft-Start Period TYP MAX UNITS 160 250 mΩ 0.02 40 µA 2.5 3.0 3.5 A 3.0 3.8 5.0 S tSS Soft-Start Step Size 14 ms ILIM / 8 A OPERATIONAL AMPLIFIERS SUP Supply Range VSUP SUP Supply Current ISUP Buffer configuration, VPOS_ = 4V, no load Input Offset Voltage VOS Input Bias Current IBIAS Input Common-Mode Range Common-Mode Rejection Ratio 4.5 13.0 V 2.4 3.8 mA (VNEG_, VPOS_, VOUT_) ≅ VSUP / 2, TA = +25°C 0 12 mV (VNEG_ , VPOS_, VOUT_) ≅ VSUP / 2 +1 ±50 nA VCM CMRR 0 0 ≤ (VNEG_, VPOS_) ≤ VSUP VSUP 45 Open-Loop Gain 125 Output Voltage Swing, High Output Voltage Swing, Low IOUT_ = 100µA VSUP 15 VSUP 3 IOUT_ = 5mA VSUP 150 VSUP 80 dB mV VOH VOL V dB IOUT_ = -100µA 2 15 IOUT_ = -5mA 80 150 Short-Circuit Current To VSUP / 2, source or sink 50 Output Source and Sink Current (VNEG_ , VPOS_, VOUT_) ≅ VSUP / 2, |∆VOS| < 10mV (|∆VOS| < 30mV for OUT3) 40 mA DC, 6V ≤ VSUP ≤ 13V, (VNEG_, VPOS_) ≅ VSUP/2 60 dB Power-Supply Rejection Ratio PSRR Slew Rate -3dB Bandwidth Gain-Bandwidth Product GBW 150 mV mA 13 V/µs RL = 10kΩ, CL = 10pF, buffer configuration 12 MHz Buffer configuration 8 MHz GATE-ON LINEAR-REGULATOR CONTROLLER FBP Regulation Voltage VFBP FBP Fault Trip Level FBP Input Bias Current FBP Effective Load-Regulation Error (Transconductance) IFBP IDRVP = 100µA 1.231 1.250 1.269 V VFBP falling 0.96 1.00 1.04 V VFBP = 1.4V -50 +50 nA -1.5 % VDRVP = 10V, IDRVP = 50µA to 1mA -0.7 _______________________________________________________________________________________ 3 MAX1518B ELECTRICAL CHARACTERISTICS (continued) MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.) FBP Line (IN) Regulation Error DRVP Sink Current IDRVP = 100µA, 2.6V < VIN < 5.5V IDRVP DRVP Off-Leakage Current Soft-Start Period VFBP = 1.1V, VDRVP = 10V ±1.5 1 VFBP = 1.4V, VDRVP = 28V 0.01 tSS Soft-Start Step Size ±5 5 mV mA 10 µA 14 ms VREF / 128 V GATE-OFF LINEAR-REGULATOR CONTROLLER FBN Regulation Voltage VFBN FBN Fault Trip Level FBN Input Bias Current IFBN IDRVN = 100µA 235 250 265 mV VFBN rising 370 420 470 mV VFBN = 0 -50 +50 nA 11 25 mV ±0.7 ±5 mV FBN Effective Load-Regulation Error (Transconductance) VDRVN = -10V, IDRVN = 50µA to 1mA FBN Line (IN) Regulation Error IDRVN = 0.1mA, 2.6V < VIN < 5.5V DRVN Source Current IDRVN DRVN Off-Leakage Current Soft-Start Period VFBN = 500mV, VDRVN = -10V 1 VFBN = 0V, VDRVN = -25V 4 -0.01 tSS Soft-Start Step Size mA -10 µA 14 ms VREF / 128 V POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES DEL Capacitor Charge Current DEL Turn-On Threshold During startup, VDEL = 1V VTH(DEL) 4 5 6 µA 1.19 1.25 1.31 V DEL Discharge Switch OnResistance During UVLO, VIN = 2.2V CTL Input Low Voltage VIN = 2.6V to 5.5V CTL Input High Voltage VIN = 2.6V to 5.5V 2 CTL Input Leakage Current CTL = AGND or IN -1 CTL-to-SRC Propagation Delay 0.6 +1 100 µA ns 28 ISRC V V SRC Input Voltage Range SRC Input Current Ω 20 VDEL = 1.5V, CTL = IN 50 100 VDEL = 1.5V, CTL = AGND 15 30 V µA SRC to COM Switch OnResistance RSRC(ON) VDEL = 1.5V, CTL = IN 6 12 Ω DRN to COM Switch OnResistance RDRN(ON) VDEL = 1.5V, CTL = AGND 35 70 Ω 4 _______________________________________________________________________________________ TFT-LCD DC-DC Converter with Operational Amplifiers (VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER IN Supply Range SYMBOL CONDITIONS VIN IN Undervoltage-Lockout Threshold VUVLO VIN rising, typical hysteresis = 150mV MIN MAX UNITS 2.6 5.5 V 2.250 2.715 V VFB = VFBP = 1.4V, VFBN = 0, LX not switching IN Quiescent Current IIN REF Output Voltage 0.8 mA VFB = 1.1V, VFBP = 1.4V, VFBN = 0, LX switching -2µA < IREF < 50µA, VIN = 2.6V to 5.5V 11 1.222 1.269 V VIN 13 V 1020 1380 kHz 1.212 1.250 V ±0.15 %/ V nA MAIN STEP-UP REGULATOR Output Voltage Range VMAIN Operating Frequency fOSC FB Regulation Voltage VFB No load FB Line Regulation VIN = 2.6V to 5.5V FB Input Bias Current VFB = 1.4V -40 +40 FB Transconductance ∆ICOMP = 5µA 75 300 µS 250 mΩ 2.5 3.5 A 4.5 LX On-Resistance RLX(ON) LX Current Limit ILIM VFB = 1V, duty cycle = 65% OPERATIONAL AMPLIFIERS SUP Supply Range VSUP 13.0 V SUP Supply Current ISUP Buffer configuration, VPOS_ = 4V, no load 3.8 mA Input Offset Voltage VOS (VNEG_, VPOS_, VOUT_) ≅ VSUP / 2 12 mV Input Common-Mode Range VCM VSUP V Output Voltage Swing, High Output Voltage Swing, Low 0 IOUT_ = 100µA VSUP 15 IOUT_ = 5mA VSUP 150 VOH VOL mV IOUT_ = -100µA 15 IOUT_ = -5mA 150 Source 50 Sink 50 Short-Circuit Current To VSUP / 2 Output Source-and-Sink Current (VNEG_ , VPOS_, VOUT_) ≅ VSUP / 2, |∆VOS| < 10mV (|VOS| < 30mV for OUT3) mV mA 40 mA GATE-ON LINEAR-REGULATOR CONTROLLER FBP Regulation Voltage VFBP IDRVP = 100µA 1.218 1.269 V _______________________________________________________________________________________ 5 MAX1518B ELECTRICAL CHARACTERISTICS MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VIN = 3V, VSUP = 8V, PGND = AGND = BGND = 0, IREF = 25µA, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) FBP Effective Load-Regulation Error (Transconductance) VDRVP = 10V, IDRVP = 50µA to 1mA -2 % FBP Line (IN) Regulation Error IDRVP = 100µA, 2.6V < VIN < 5.5V 5 mV DRVP Sink Current IDRVP VFBP = 1.1V, VDRVP = 10V 1 mA GATE-OFF LINEAR-REGULATOR CONTROLLER FBN Regulation Voltage VFBN IDRVN = 100µA 235 265 mV FBN Effective Load-Regulation Error (Transconductance) VDRVN = -10V, IDRVN = 50µA to 1mA 25 mV FBN Line (IN) Regulation Error IDRVN = 0.1mA, 2.6V < VIN < 5.5V 5 mV DRVN Source Current IDRVN VFBN = 500mV, VDRVN = -10V 1 mA POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES DEL Capacitor Charge Current DEL Turn-On Threshold During startup, VDEL = 1V VTH(DEL) CTL Input Low Voltage VIN = 2.6V to 5.5V CTL Input High Voltage VIN = 2.6V to 5.5V 4 6 µA 1.19 1.31 V 0.6 2 SRC Input Voltage Range SRC Input Current 28 ISRC V V VDEL = 1.5V, CTL = IN 100 VDEL = 1.5V, CTL = AGND 30 V µA SRC-to-COM Switch OnResistance RSRC(ON) VDEL = 1.5V, CTL = IN 12 Ω DRN-to-COM Switch OnResistance RDRN(ON) VDEL = 1.5V, CTL = AGND 70 Ω Note 1: Specifications to -40°C are guaranteed by design, not production tested. 6 _______________________________________________________________________________________ TFT-LCD DC-DC Converter with Operational Amplifiers 70 60 50 40 1.3 NO LOAD, SUP DISCONNECTED, R1 = 95.3kΩ, R2 = 10.2kΩ 8 1.2 CURRENT INTO INDUCTOR 6 4 1.1 MAX1518B toc03 MAX1518B toc02 10 SUPPLY CURRENT (mA) VIN = 3.3V 1.4 SWITCHING FREQUENCY (MHz) VIN = 5.0V 80 CURRENT INTO IN PIN 2 VOUT = 13V 0 1.0 30 100 1000 2.5 3.0 3.5 4.0 4.5 5.0 2.5 5.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) INPUT VOLTAGE (V) LOAD CURRENT (mA) STEP-UP REGULATOR SOFT-START (HEAVY LOAD) STEP-UP REGULATOR PULSED LOAD-TRANSIENT RESPONSE MAX1518B toc04 MAX1518B toc05 A 0V A 200mA B 0V 13V B C 0A C 0A 10µs/div 2ms/div A: VIN, 5V/div B: VMAIN, 5V/div C: INDUCTOR CURRENT, 1A/div A: LOAD CURRENT, 1A/div B: VMAIN, 200mV/div, AC-COUPLED C: INDUCTOR CURRENT, 1A/div REF VOLTAGE LOAD REGULATION TIMER DELAYED OVERLOAD PROTECTION 1.253 220ms A MAX1518B toc07 10 1.252 REF VOLTAGE (V) 1 MAX1518B toc06 EFFICIENCY (%) MAX1518B toc01 100 90 STEP-UP SUPPLY CURRENT vs. SUPPLY VOLTAGE SWITCHING FREQUENCY vs. INPUT VOLTAGE STEP-UP EFFICIENCY vs. LOAD CURRENT 1.251 1.250 1.249 B 1.248 1.247 40ms/div A: VMAIN, 2V/div B: INDUCTOR CURRENT, 1A/div 0 10 20 30 40 50 LOAD CURRENT (µA) _______________________________________________________________________________________ 7 MAX1518B Typical Operating Characteristics (Circuit of Figure 1. VIN = 5V, VMAIN = 13V, VGON = 24V, VGOFF = -8V, VOUT1 = VOUT2 = VOUT3 = VOUT4 = VOUT5 = 6.5V, TA = +25°C unless otherwise noted.) Typical Operating Characteristics (continued) (Circuit of Figure 1. VIN = 5V, VMAIN = 13V, VGON = 24V, VGOFF = -8V, VOUT1 = VOUT2 = VOUT3 = VOUT4 = VOUT5 = 6.5V, TA = +25°C unless otherwise noted.) GATE-ON REGULATOR LOAD REGULATION -0.2 -0.4 -0.6 VGON = 23.5V IGON = 20mA -0.8 -0.10 -0.15 -0.20 -0.30 24 25 26 27 28 0 5 INPUT VOLTAGE (V) 0.50 0.25 0 10 20 15 -16 -14 LOAD CURRENT (mA) GATE-OFF REGULATOR LOAD REGULATION -12 INPUT VOLTAGE (V) POWER-UP SEQUENCE MAX1518B toc12 MAX1518B toc11 0 -0.2 VOLTAGE ERROR (%) 0.75 -0.25 30 29 VGOFF = -8V IGOFF = 50mA -0.25 -1.0 23 GATE-OFF REGULATOR LINE REGULATION 1.00 OUTPUT VOLTAGE ERROR (%) -0.05 VOLTAGE ERROR (%) 0 MAX1518B toc09 MAX1518B toc08 0 MAX1518B toc10 GATE-ON REGULATOR LINE REGULATION 0.2 OUTPUT VOLTAGE ERROR (%) A 0V B -0.4 0V -0.6 0V C -0.8 D 0V -1.0 0 10 20 30 40 50 LOAD CURRENT (mA) VPOS = VSUP/2 BUFFER CONFIGURATON 2.3 C: VGOFF, 10V/div D: VGON, 20V/div MAX1518B toc14 MAX1518B toc13 2.5 4ms/div A: VMAIN, 10V/div B: VSRC, 20V/div OPERATIONAL-AMPLIFIER RAIL-TO-RAIL INPUT/OUTPUT SUP SUPPLY CURRENT vs. SUP VOLTAGE ISUP (mA) MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers VSUP = 6V A 2.1 0V 1.9 B 1.7 0V 1.5 4.5 6.5 8.5 VSUP (V) 8 10.5 12.5 40µs/div A: INPUT SIGNAL, 2V/div B: OUTPUT SIGNAL, 2V/div _______________________________________________________________________________________ -10 -8 TFT-LCD DC-DC Converter with Operational Amplifiers OPERATIONAL-AMPLIFIER LARGE-SIGNAL STEP RESPONSE OPERATIONAL-AMPLIFIER LOAD-TRANSIENT RESPONSE OPERATIONAL-AMPLIFIER SMALL-SIGNAL STEP RESPONSE MAX1518B toc16 MAX1518B toc15 MAX1518B toc17 VSUP = 6V 0V A A A 0V +50mA B 0 0V B B -50mA 0V 1µs/div 400ns/div A: OUTPUT VOLTAGE, 1V/div, AC-COUPLED B: OUTPUT CURRENT, 50mA/div 0V 400ns/div A: INPUT SIGNAL, 2V/div B: OUTPUT SIGNAL, 2V/div A: INPUT SIGNAL, 100mV/div B: OUTPUT SIGNAL, 100mV/div Pin Description PIN NAME FUNCTION 1 SRC Switch Input. Source of the internal high-voltage p-channel MOSFET. Bypass SRC to PGND with a minimum 0.1µF capacitor close to the pins. 2 REF Reference Bypass Terminal. Bypass REF to AGND with a minimum of 0.22µF close to the pins. 3 AGND Analog Ground for Step-Up Regulator and Linear Regulators. Connect to power ground (PGND) underneath the IC. 4 PGND Power Ground. PGND is the source of the main step-up n-channel power MOSFET. Connect PGND to the output-capacitor ground terminals through a short, wide PC board trace. Connect to analog ground (AGND) underneath the IC. 5 OUT1 Operational-Amplifier 1 Output 6 NEG1 Operational-Amplifier 1 Inverting Input 7 POS1 Operational-Amplifier 1 Noninverting Input 8 OUT2 Operational-Amplifier 2 Output 9 NEG2 Operational-Amplifier 2 Inverting Input 10 POS2 Operational-Amplifier 2 Noninverting Input 11 BGND Analog Ground for Operational Amplifiers. Connect to power ground (PGND) underneath the IC. 12 POS3 Operational-Amplifier 3 Noninverting Input 13 OUT3 14 SUP Operational-Amplifier 3 Output Operational-Amplifier Power Input. Positive supply rail for the operational amplifiers. Typically connected to VMAIN. Bypass SUP to BGND with a 0.1µF capacitor. 15 POS4 Operational-Amplifier 4 Noninverting Input 16 NEG4 Operational-Amplifier 4 Inverting Input _______________________________________________________________________________________ 9 MAX1518B Typical Operating Characteristics (continued) (Circuit of Figure 1. VIN = 5V, VMAIN = 13V, VGON = 24V, VGOFF = -8V, VOUT1 = VOUT2 = VOUT3 = VOUT4 = VOUT5 = 6.5V, TA = +25°C unless otherwise noted.) TFT-LCD DC-DC Converter with Operational Amplifiers MAX1518B Pin Description (continued) PIN NAME 17 OUT4 Operational-Amplifier 4 Output 18 POS5 Operational-Amplifier 5 Noninverting Input 19 NEG5 Operational-Amplifier 5 Inverting Input 20 OUT5 Operational-Amplifier 5 Output 21 LX n-Channel Power MOSFET Drain and Switching Node. Connect the inductor and Schottky diode to LX and minimize the trace area for lowest EMI. 22 IN Supply Voltage Input. IN can range from 2.6V to 6.5V. 23 FB Step-Up Regulator Feedback Input. Regulates to 1.236V (nominal). Connect a resistive voltage-divider from the output (VMAIN) to FB to analog ground (AGND). Place the divider within 5mm of FB. 24 COMP 25 FBP Gate-On Linear-Regulator Feedback Input. FBP regulates to 1.25V (nominal). Connect FBP to the center of a resistive voltage-divider between the regulator output and AGND to set the gate-on linearregulator output voltage. Place the resistive voltage-divider close to the pin. 26 DRVP Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channel MOSFET. Connect DRVP to the base of an external pnp pass transistor. See the Pass-Transistor Selection section. 27 FBN 28 DRVN 29 DEL High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to set the high-voltage switch startup delay. 30 CTL High-Voltage Switch Control Input. When CTL is high, the high-voltage switch between COM and SRC is on and the high-voltage switch between COM and DRN is off. When CTL is low, the high-voltage switch between COM and SRC is off and the high-voltage switch between COM and DRN is on. CTL is inhibited by the undervoltage lockout and when the voltage on DEL is less than 1.25V. 31 DRN Switch Input. Drain of the internal high-voltage back-to-back p-channel MOSFETs connected to COM. COM Internal High-Voltage MOSFET Switch Common Terminal. Do not allow the voltage on COM to exceed VSRC. 32 10 FUNCTION Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RC from COMP to AGND. See the Loop Compensation section for component selection guidelines. Gate-Off Linear-Regulator Feedback Input. FBN regulates to 250mV (nominal). Connect FBN to the center of a resistive voltage-divider between the regulator output and REF to set the gate-off linearregulator output voltage. Place the resistive voltage-divider close to the pin. Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channel MOSFET. Connect DRVN to the base of an external npn pass transistor. See the Pass-Transistor Selection section. ______________________________________________________________________________________ TFT-LCD DC-DC Converter with Operational Amplifiers The MAX1518B Typical Operating Circuit (Figure 1) is a complete power-supply system for TFT LCDs. The circuit generates a +13V source-driver supply and +24V and -8V gate-driver supplies. The input voltage range for the IC is from +2.6V to +6.5V. The listed load currents in Figure 1 are available from a +4.5V to +5.5V supply. Table 1 lists some recommended components, and Table 2 lists the contact information of component suppliers. Table 1. Component List DESIGNATION Detailed Description Main Step-Up Regulator V −V D ≈ MAIN IN VMAIN DESCRIPTION C1 22µF, 6.3V X5R ceramic capacitor (1210) TDK C3225X5R0J227M C2 22µF, 16V X5R ceramic capacitor (1812) TDK C4532X5X1C226M D1 3A, 30V Schottky diode (M-flat) Toshiba CMS02 D2, D3 The MAX1518B contains a high-performance step-up switching regulator, two low-cost linear-regulator controllers, multiple high-current operational amplifiers, and startup timing and level-shifting functionality useful for active-matrix TFT LCDs. Figure 2 shows the MAX1518B Functional Diagram. The main step-up regulator employs a current-mode, fixed-frequency PWM architecture to maximize loop bandwidth and provide fast transient response to pulsed loads typical of TFT-LCD panel source drivers. The 1.2MHz switching frequency allows the use of lowprofile inductors and ceramic capacitors to minimize the thickness of LCD panel designs. The integrated high-efficiency MOSFET and the IC’s built-in digital soft-start functions reduce the number of external components required while controlling inrush currents. The output voltage can be set from VIN to 13V with an external resistive voltage-divider. To generate an output voltage greater than 13V, an external cascoded MOSFET is needed. See the Generating Output Voltages > 13V section in the Design Procedures. The regulator controls the output voltage and the power delivered to the output by modulating the duty cycle (D) of the internal power MOSFET in each switching cycle. The duty cycle of the MOSFET is approximated by: MAX1518B Typical Operating Circuit 200mA, 100V, dual ultra-fast diodes (SOT23) Fairchild MMBD4148SE L1 3.0µH, 3A inductor Sumida CDRH6D28-3R0 Q1 200mA, 40V pnp bipolar transistor (SOT23) Fairchild MMBT3906 Q2 200mA, 40V npn bipolar transistor (SOT23) Fairchild MMBT3904 Figure 3 shows the Functional Diagram of the step-up regulator. An error amplifier compares the signal at FB to 1.236V and changes the COMP output. The voltage at COMP sets the peak inductor current. As the load varies, the error amplifier sources or sinks current to the COMP output accordingly to produce the inductor peak current necessary to service the load. To maintain stability at high duty cycles, a slope-compensation signal is summed with the current-sense signal. On the rising edge of the internal clock, the controller sets a flip-flop, turning on the n-channel MOSFET and applying the input voltage across the inductor. The current through the inductor ramps up linearly, storing energy in its magnetic field. Once the sum of the current-feedback signal and the slope compensation exceeds the COMP voltage, the controller resets the flip-flop and turns off the MOSFET. Since the inductor current is continuous, a transverse potential develops across the inductor that turns on the diode (D1). The voltage across the inductor then becomes the difference between the output voltage and the input voltage. Table 2. Component Suppliers SUPPLIER PHONE FAX WEBSITE Fairchild 408-822-2000 408-822-2102 www.fairchildsemi.com Sumida 847-545-6700 847-545-6720 www.sumida.com TDK 847-803-6100 847-390-4405 www.component.tdk.com Toshiba 949-455-2000 949-859-3963 www.toshiba.com/taec ______________________________________________________________________________________ 11 MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers LX L1 3.0µH VIN 4.5V TO 5.5V D1 C2 22µF C1 22µF R10 10Ω R1 95.3kΩ 1% LX IN FB C18 0.1µF LX R1 10.2kΩ 1% 180kΩ 0.1µF AGND COMP PGND 220µF 0.1µF D2 LX 0.1µF MAX1518B 6.8kΩ D3 6.8kΩ DRVP 0.1µF Q2 R7 332kΩ 1% VGOFF -8V/50mA DRVN R4 192kΩ 1% Q1 FBP R5 10.0kΩ 1% FBN 0.22µF R8 40.2kΩ 1% 0.47µF SRC REF VGON 24V/20mA COM 0.22µF DRN DEL CTL 0.033µF SUP 0.1µF BGND NEG1 OUT1 NEG2 OUT2 TO VCOM BACKPLANE POS1 POS2 OUT3 POS3 NEG4 POS4 OUT4 POS5 NEG5 OUT5 Figure 1. Typical Operating Circuit 12 ______________________________________________________________________________________ VMAIN 13V/500mA TFT-LCD DC-DC Converter with Operational Amplifiers MAX1518B VCN VCP VIN VMAIN LX IN FB STEP-UP CONTROLLER PGND COMP AGND VCP MAX1518B DRVP GATE-ON CONTROLLER FBP VGON SRC DEL COM SWITCH CONTROL CTL VCN DRN DRVN GATE-OFF CONTROLLER VGOFF SUP NEG1 OUT1 FBN OP1 REF POS1 NEG2 OUT2 REF NEG4 OP2 OP4 POS2 OUT4 POS4 NEG5 OUT3 OP3 OP5 POS3 OUT5 POS5 BGND Figure 2. MAX1518B Functional Diagram ______________________________________________________________________________________ 13 MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers LX RESET DOMINANT CLOCK S R PGND Q ILIM COMPARATOR SOFTSTART VLIMIT SLOPE COMP PWM COMPARATOR Σ CURRENT SENSE OSCILLATOR FAULT COMPARATOR TO FAULT LATCH 1.0V ERROR AMP FB 1.236V COMP Figure 3. Step-Up Regulator Functional Diagram This discharge condition forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and the load. The MOSFET remains off for the rest of the clock cycle. Gate-On Linear-Regulator Controller, REG P The gate-on linear-regulator controller (REG P) is an analog gain block with an open-drain n-channel output. It drives an external pnp pass transistor with a 6.8kΩ base-to-emitter resistor (Figure 1). Its guaranteed basedrive sink current is at least 1mA. The regulator including Q1 in Figure 1 uses a 0.47µF ceramic output capacitor and is designed to deliver 20mA at 24V. Other output voltages and currents are possible with the proper pass transistor and output capacitor. See the Pass-Transistor Selection and Stability Requirements sections. 14 REG P is typically used to provide the TFT-LCD gate drivers’ gate-on voltage. Use a charge pump with as many stages as necessary to obtain a voltage exceeding the required gate-on voltage (see the Selecting the Number of Charge-Pump Stages section). Note the voltage rating of the DRVP is 28V. If the charge-pump output voltage can exceed 28V, an external cascode npn transistor should be added as shown in Figure 4. Alternately, the linear regulator can control an intermediate charge-pump stage while regulating the final charge-pump output (Figure 5). REG P is enabled after the REF voltage exceeds 1.0V. Each time it is enabled, the controller goes through a soft-start routine that ramps up its internal reference DAC in 128 steps. ______________________________________________________________________________________ TFT-LCD DC-DC Converter with Operational Amplifiers MAX1518B LX FROM CHARGE-PUMP OUTPUT VMAIN 0.1µF VMAIN 13V 0.1µF DRVP NPN CASCODE TRANSISTOR PNP PASS TRANSISTOR 6.8kΩ VGON MAX1518B Q1 DRVP MAX1518B VGON 35V 0.47µF 0.22µF 267kΩ 1% FBP FBP 10.0kΩ 1% Figure 4. Using Cascoded npn for Charge-Pump Output Voltages > 28V Figure 5. The linear regulator controls the intermediate chargepump stage. Gate-Off Linear-Regulator Controller, REG N SUP or to BGND. If the short-circuit condition persists, the junction temperature of the IC rises until it reaches the thermal-shutdown threshold (+160°C typ). Once the junction temperature reaches the thermal-shutdown threshold, an internal thermal sensor immediately sets the thermal fault latch, shutting off all the IC’s outputs. The device remains inactive until the input voltage is cycled. The gate-off linear-regulator controller (REG N) is an analog gain block with an open-drain p-channel output. It drives an external npn pass transistor with a 6.8kΩ base-to-emitter resistor (Figure 1). Its guaranteed basedrive source current is at least 1mA. The regulator including Q2 in Figure 1 uses a 0.47µF ceramic output capacitor and is designed to deliver 50mA at -8V. Other output voltages and currents are possible with the proper pass transistor and output capacitor (see the PassTransistor Selection and Stability Requirements sections). REG N is typically used to provide the TFT-LCD gate drivers’ gate-off voltage. A negative voltage can be produced using a charge-pump circuit as shown in Figure 1. REG N is enabled after the voltage on REF exceeds 1.0V. Each time it is enabled, the control goes through a soft-start routine that ramps down its internal reference DAC from VREF to 250mV in 128 steps. Operational Amplifiers The MAX1518B has five operational amplifiers. The operational amplifiers are typically used to drive the LCD backplane (VCOM) or the gamma-correction divider string. They feature ±150mA output short-circuit current, 13V/µs slew rate, and 12MHz bandwidth. The rail-to-rail input and output capability maximizes system flexibility. Short-Circuit Current Limit The operational amplifiers limit short-circuit current to approximately ±150mA if the output is directly shorted to Driving Pure Capacitive Load The operational amplifiers are typically used to drive the LCD backplane (VCOM) or the gamma-correction divider string. The LCD backplane consists of a distributed series capacitance and resistance, a load that can be easily driven by the operational amplifier. However, if the operational amplifier is used in an application with a pure capacitive load, steps must be taken to ensure stable operation. As the operational amplifier’s capacitive load increases, the amplifier’s bandwidth decreases and gain peaking increases. A 5Ω to 50Ω small resistor placed between OUT_ and the capacitive load reduces peaking but also reduces the gain. An alternative method of reducing peaking is to place a series RC network (snubber) in parallel with the capacitive load. The RC network does not continuously load the output or reduce the gain. Typical values of the resistor are between 100Ω and 200Ω, and the typical value of the capacitor is 10nF. ______________________________________________________________________________________ 15 MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers Undervoltage Lockout (UVLO) The undervoltage-lockout (UVLO) circuit compares the input voltage at IN with the UVLO threshold (2.5V rising, 2.30V falling, typ) to ensure the input voltage is high enough for reliable operation. The 200mV (typ) hysteresis prevents supply transients from causing a restart. Once the input voltage exceeds the UVLO rising threshold, startup begins. When the input voltage falls below the UVLO falling threshold, the controller turns off the main step-up regulator, turns off the linear-regulator outputs, and disables the switch control block; the operationalamplifier outputs are high impedance. VIN 2.5V VREF 1.05V VMAIN VGON Reference Voltage (REF) The reference output is nominally 1.25V and can source at least 50µA (see the Typical Operating Characteristics). Bypass REF with a 0.22µF ceramic capacitor connected between REF and AGND. Power-Up Sequence and Soft-Start Once the voltage on IN exceeds approximately 1.7V, the reference turns on. With a 0.22µF REF bypass capacitor, the reference reaches its regulation voltage of 1.25V in approximately 1ms. When the reference voltage exceeds 1.0V, the ICs enable the main step-up regulator, the gate-on linear-regulator controller, and the gate-off linear-regulator controller simultaneously. The IC employs soft-start for each regulator to minimize inrush current and voltage overshoot and to ensure a well-defined startup behavior. During the soft-start, the main step-up regulator directly limits the peak inductor current. The current-limit level is increased through the soft-start period from zero up to the full current-limit value in eight equal current steps (ILIM / 8). The maximum load current is available after the output voltage reaches regulation (which terminates soft-start), or after the soft-start timer expires. Both linear-regulator controllers use a 7-bit soft-start DAC. For the gate-on linear regulator, the DAC output is stepped in 128 steps from zero up to the reference voltage. For the gate-off linear regulator, the DAC output steps from the reference down to 250mV in 128 steps. The soft-start duration is 14ms (typ) for all three regulators. A capacitor (CDEL) from DEL to AGND determines the switch-control-block startup delay. After the input voltage exceeds the UVLO threshold (2.5V typ) and the soft-start routine for each regulator is complete and there is no fault detected, a 5µA current source starts charging CDEL. Once the capacitor voltage exceeds 16 12ms INPUT SOFT- SOFTVOLTAGE START START OK BEGINS ENDS 1.25V VGOFF VDEL SWITCH CONTROL ENABLED Figure 6. Power-Up Sequence 1.25V (typ), the switch-control block is enabled as shown in Figure 6. After the switch-control block is enabled, COM can be connected to SRC or DRN through the internal p-channel switches, depending upon the state of CTL. Before startup and when IN is less than VUVLO, DEL is internally connected to AGND to discharge CDEL. Select CDEL to set the delay time using the following equation: CDEL = DELAY _ TIME × 5µA 1.25V Switch-Control Block The switch-control input (CTL) is not activated until all four of the following conditions are satisfied: the input voltage exceeds VUVLO, the soft-start routine of all the regulators is complete, there is no fault condition detected, and VDEL exceeds its turn-on threshold. Once activated and if CTL is high, the 5Ω internal p-channel switch (Q1) between COM and SRC turns on and the 30Ω p-channel switch (Q2) between DRN and COM turns off. If CTL is low, Q1 turns off and Q2 turns on. ______________________________________________________________________________________ TFT-LCD DC-DC Converter with Operational Amplifiers MAX1518B IN MAX1518B 5µA 2.5V FB OK FBP OK FBN OK Q1 SRC DEL REF COM CTL Q2 DRN Figure 7. Switch-Control Block Fault Protection Thermal-Overload Protection During steady-state operation, if the output of the main regulator or any of the linear-regulator outputs does not exceed its respective fault-detection threshold, the MAX1518B activates an internal fault timer. If any condition or combination of conditions indicates a continuous fault for the fault-timer duration (200ms typ), the MAX1518B sets the fault latch to shut down all the outputs except the reference. Once the fault condition is removed, cycle the input voltage (below the UVLO falling threshold) to clear the fault latch and reactivate the device. The fault-detection circuit is disabled during the soft-start time. Thermal-overload protection prevents excessive power dissipation from overheating the MAX1518B. When the junction temperature exceeds TJ = +160°C, a thermal sensor immediately activates the fault protection, which shuts down all outputs except the reference, allowing the device to cool down. Once the device cools down by approximately 15°C, cycle the input voltage (below the UVLO falling threshold) to clear the fault latch and reactivate the device. The thermal-overload protection protects the controller in the event of fault conditions. For continuous operation, do not exceed the absolute maximum junction temperature rating of TJ = +150°C. ______________________________________________________________________________________ 17 MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers Design Procedure Main Step-Up Regulator Inductor Selection The minimum inductance value, peak current rating, and series resistance are factors to consider when selecting the inductor. These factors influence the converter’s efficiency, maximum output load capability, transient-response time, and output voltage ripple. Size and cost are also important factors to consider. The maximum output current, input voltage, output voltage, and switching frequency determine the inductor value. Very high inductance values minimize the current ripple and therefore reduce the peak current, which decreases core losses in the inductor and conduction losses in the entire power path. However, large inductor values also require more energy storage and more turns of wire, which increases size and can increase conduction losses in the inductor. Low inductance values decrease the size but increase the current ripple and peak current. Finding the best inductor involves choosing the best compromise between circuit efficiency, inductor size, and cost. The equations used here include a constant LIR, which is the ratio of the inductor peak-to-peak ripple current to the average DC inductor current at the full load current. The best trade-off between inductor size and circuit efficiency for step-up regulators generally has an LIR between 0.3 and 0.5. However, depending on the AC characteristics of the inductor core material and ratio of inductor resistance to other power-path resistances, the best LIR can shift up or down. If the inductor resistance is relatively high, more ripple can be accepted to reduce the number of turns required and increase the wire diameter. If the inductor resistance is relatively low, increasing inductance to lower the peak current can decrease losses throughout the power path. If extremely thin high-resistance inductors are used, as is common for LCD-panel applications, the best LIR can increase to between 0.5 and 1.0. Once a physical inductor is chosen, higher and lower values of the inductor should be evaluated for efficiency improvements in typical operating regions. Calculate the approximate inductor value using the typical input voltage (VIN), the maximum output current (IMAIN(MAX)), the expected efficiency (ηTYP) taken from an appropriate curve in the Typical Operating Characteristics section, and an estimate of LIR based on the above discussion: 18 η V 2 VMAIN − VIN TYP L = IN VMAIN IMAIN(MAX) × fOSC LIR Choose an available inductor value from an appropriate inductor family. Calculate the maximum DC input current at the minimum input voltage (VIN(MIN)) using conservation of energy and the expected efficiency at that operating point (ηMIN) taken from the appropriate curve in the Typical Operating Characteristics: IIN(DCMAX , )= IMAIN(MAX) × VMAIN VIN(MIN) × ηMIN Calculate the ripple current at that operating point and the peak current required for the inductor: IRIPPLE = VIN(MIN) × (VMAIN − VIN(MIN) ) L × VMAIN × fOSC IRIPPLE IPEAK = IIN(DCMAX , )+ 2 The inductor’s saturation current rating and the MAX1518B’s LX current limit (ILIM) should exceed IPEAK, and the inductor’s DC current rating should exceed IIN(DC,MAX). For good efficiency, choose an inductor with less than 0.1Ω series resistance. Considering the Typical Operating Circuit, the maximum load current (IMAIN(MAX)) is 500mA with a 13V output and a typical input voltage of 5V. Choosing an LIR of 0.5 and estimating efficiency of 85% at this operating point: 5V 2 13V − 5V 0.85 L= ≈ 3.3µH 13V 0.5A × 1.2MHz 0.5 Using the circuit’s minimum input voltage (4.5V) and estimating efficiency of 80% at that operating point: IIN(DCMAX , )= 0.5A × 13V ≈ 1.8A 4.5V × 0.8 The ripple current and the peak current are: 4.5V × (13V − 4.5V) ≈ 0.74A 3.3µH × 13V × 1.2MHz 0.74A IPEAK = 1.8A + ≈ 2.2A 2 IRIPPLE = ______________________________________________________________________________________ TFT-LCD DC-DC Converter with Operational Amplifiers VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) V I −V VRIPPLE(C) ≈ MAIN MAIN IN , and COUT VMAINfOSC VRIPPLE(ESR) ≈ IPEAKRESR(COUT) where I PEAK is the peak inductor current (see the Inductor Selection section). For ceramic capacitors, the output voltage ripple is typically dominated by VRIPPLE(C). The voltage rating and temperature characteristics of the output capacitor must also be considered. Input-Capacitor Selection The input capacitor (CIN) reduces the current peaks drawn from the input supply and reduces noise injection into the IC. A 22µF ceramic capacitor is used in the Typical Applications Circuit (Figure 1) because of the high source impedance seen in typical lab setups. Actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. Typically, CIN can be reduced below the values used in the Typical Applications Circuit. Ensure a low-noise supply at IN by using adequate C IN . Alternately, greater voltage variation can be tolerated on CIN if IN is decoupled from CIN using an RC lowpass filter (see R10 and C18 in Figure 1). Rectifier Diode The MAX1518B’s high switching frequency demands a high-speed rectifier. Schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. In general, a 2A Schottky diode complements the internal MOSFET well. Output-Voltage Selection The output voltage of the main step-up regulator can be adjusted by connecting a resistive voltage-divider from the output (VMAIN) to AGND with the center tap connected to FB (see Figure 1). Select R2 in the 10kΩ to 50kΩ range. Calculate R1 with the following equation: V R1 = R2 × MAIN − 1 VFB where VFB, the step-up regulator’s feedback set point, is 1.236V. Place R1 and R2 close to the IC. Generating Output Voltages >13V The maximum output voltage of the step-up regulator is 13V, which is limited by the absolute maximum rating of the internal power MOSFET. To achieve higher output voltages, an external n-channel MOSFET can be cascoded with the internal FET (Figure 8). Since the gate of the external FET is biased from the input supply, use a logiclevel FET to ensure that the FET is fully enhanced at the minimum input voltage. The current rating of the FET needs to be higher than the IC’s internal current limit. Loop Compensation Choose RCOMP to set the high-frequency integrator gain for fast transient response. Choose CCOMP to set the integrator zero to maintain loop stability. For low-ESR output capacitors, use the following equations to obtain stable performance and good transient response: RCOMP ≈ 315 × VIN × VOUT × COUT L × IMAIN(MAX) CCOMP ≈ VOUT × COUT 10 × IMAIN(MAX) × RCOMP To further optimize transient response, vary RCOMP in 20% steps and CCOMP in 50% steps while observing transient-response waveforms. Charge Pumps Selecting the Number of Charge-Pump Stages For highest efficiency, always choose the lowest number of charge-pump stages that meet the output requirement. Figures 9 and 10 show the positive and negative charge-pump output voltages for a given VMAIN for one-, two-, and three-stage charge pumps. The number of positive charge-pump stages is given by: V +V −V nPOS = GON DROPOUT MAIN VMAIN − 2 × VD where nPOS is the number of positive charge-pump stages, VGON is the gate-on linear-regulator REG P output, VMAIN is the main step-up regulator output, VD is the forward-voltage drop of the charge-pump diode, and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 0.3V. ______________________________________________________________________________________ 19 MAX1518B Output-Capacitor Selection The total output voltage ripple has two components: the capacitive ripple caused by the charging and discharging of the output capacitance, and the ohmic ripple due to the capacitor’s equivalent series resistance (ESR). MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers VMAIN >13V VIN LX has a negligible effect on output-current capability because the internal switch resistance and the diode impedance place a lower limit on the source impedance. A 0.1µF ceramic capacitor works well in most low-current applications. The flying capacitor’s voltage rating must exceed the following: FB VCX > n × VMAIN STEP-UP CONTROLLER PGND MAX1518B Figure 8. Operation with Output Voltages >13V Using Cascoded MOSFET where n is the stage number in which the flying capacitor appears, and VMAIN is the output voltage of the main step-up regulator. Charge-Pump Output Capacitor Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-topeak transient voltage. With ceramic capacitors, the output voltage ripple is dominated by the capacitance value. Use the following equation to approximate the required capacitor value: The number of negative charge-pump stages is given by: −V + VDROPOUT nNEG = GOFF VMAIN − 2 × VD where nNEG is the number of negative charge-pump stages, VGOFF is the gate-off linear-regulator REG N output, VMAIN is the main step-up regulator output, VD is the forward-voltage drop of the charge-pump diode, and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 0.3V. The above equations are derived based on the assumption that the first stage of the positive charge pump is connected to VMAIN and the first stage of the negative charge pump is connected to ground. Sometimes fractional stages are more desirable for better efficiency. This can be done by connecting the first stage to VIN or another available supply. If the first charge-pump stage is powered from V IN , then the above equations become: V +V +V nPOS = GON DROPOUT IN VMAIN − 2 × VD −VGOFF + VDROPOUT + VIN nNEG = VMAIN − 2 × VD Flying Capacitors Increasing the flying-capacitor (CX) value lowers the effective source impedance and increases the outputcurrent capability. Increasing the capacitance indefinitely 20 COUT _ CP ≥ ILOAD _ CP 2fOSC VRIPPLE _ CP where COUT_CP is the output capacitor of the charge pump, I LOAD_CP is the load current of the charge pump, and VRIPPLE_CP is the peak-to-peak value of the output ripple. Charge-Pump Rectifier Diodes Use low-cost silicon switching diodes with a current rating equal to or greater than two times the average charge-pump input current. If it helps avoid an extra stage, some or all of the diodes can be replaced with Schottky diodes with an equivalent current rating. Linear-Regulator Controllers Output-Voltage Selection Adjust the gate-on linear-regulator (REG P) output voltage by connecting a resistive voltage-divider from the REG P output to AGND with the center tap connected to FBP (Figure 1). Select the lower resistor of the divider R5 in the range of 10kΩ to 30kΩ. Calculate the upper resistor R4 with the following equation: V R4 = R5 × GON − 1 V FBP where VFBP = 1.25V (typ). ______________________________________________________________________________________ TFT-LCD DC-DC Converter with Operational Amplifiers MAX1518B POSITIVE CHARGE-PUMP OUTPUT VOLTAGE vs. VMAIN NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE vs. VMAIN 60 -0 VD = 0.3V TO 1V 3-STAGE CHARGE PUMP 1-STAGE CHARGE PUMP -5 50 -10 -15 G_OFF (V) G_ON (V) 40 2-STAGE CHARGE PUMP 30 20 -20 2-STAGE CHARGE PUMP -25 -30 3-STAGE CHARGE PUMP -35 10 -40 1-STAGE CHARGE PUMP 0 VD = 0.3V TO 1V -45 2 4 6 8 10 12 14 VMAIN (V) 2 4 6 8 10 12 14 VMAIN (V) Figure 9. Positive Charge-Pump Output Voltage vs. VMAIN Figure 10. Negative Charge-Pump Output Voltage vs. VMAIN Adjust the gate-off linear-regulator REG N output voltage by connecting a resistive voltage-divider from VGOFF to REF with the center tap connected to FBN (Figure 1). Select R8 in the range of 20kΩ to 50kΩ. Calculate R7 with the following equation: Therefore, transistors with current gain over 100 at the maximum output current can be difficult to stabilize and are not recommended unless the high gain is needed to meet the load-current requirements. The transistor’s saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator can support. Also, the package’s power dissipation limits the usable maximum input-to-output voltage differential. The maximum power-dissipation capability of the transistor’s package and mounting must exceed the actual power dissipated in the device. The power dissipated equals the maximum load current (ILOAD(MAX)_LR) multiplied by the maximum input-to-output voltage differential: V −V R7 = R8 × FBN GOFF VREF − VFBN where VFBN = 250mV, VREF = 1.25V. Note that REF can only source up to 50µA; using a resistor less than 20kΩ for R8 results in higher bias current than REF can supply. Pass-Transistor Selection The pass transistor must meet specifications for current gain (hFE), input capacitance, collector-emitter saturation voltage and power dissipation. The transistor’s current gain limits the guaranteed maximum output current to: V ILOAD(MAX) = IDRV − BE × hFE(MIN) RBE where IDRV is the minimum guaranteed base-drive current, VBE is the transistor’s base-to-emitter forward voltage drop, and RBE is the pullup resistor connected between the transistor’s base and emitter. Furthermore, the transistor’s current gain increases the linear regulator’s DC loop gain (see the Stability Requirements section), so excessive gain destabilizes the output. P = ILOAD(MAX)_ LR × (VIN(MAX)_ LR − VOUT _ LR ) where VIN(MAX)_LR is the maximum input voltage of the linear regulator, and VOUT_LR is the output voltage of the linear regulator. Stability Requirements The MAX1518B linear-regulator controllers use an internal transconductance amplifier to drive an external pass transistor. The transconductance amplifier, the pass transistor, the base-emitter resistor, and the output capacitor determine the loop stability. The following applies to both linear-regulator controllers in the MAX1518B. ______________________________________________________________________________________ 21 MAX1518B TFT-LCD DC-DC Converter with Operational Amplifiers The transconductance amplifier regulates the output voltage by controlling the pass transistor’s base current. The total DC loop gain is approximately: 10 I ×h A V _ LR ≅ × 1+ BIAS FE × VREF VT ILOAD _ LR where VT is 26mV at room temperature, and IBIAS is the current through the base-to-emitter resistor (RBE). For the MAX1518B, the bias currents for both the gate-on and gate-off linear-regulator controllers are 0.1mA. Therefore, the base-to-emitter resistor for both linear regulators should be chosen to set 0.1mA bias current: RBE = 0.7V VBE = ≈ 6.8kΩ 0.1mA 0.1mA The output capacitor and the load resistance create the dominant pole in the system. However, the internal amplifier delay, pass transistor’s input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capacitor’s ESR generates a zero. For proper operation, use the following equations to verify the linear regulator is properly compensated: 1) First, determine the dominant pole set by the linear regulator’s output capacitor and the load resistor: fPOLE _ LR = ILOAD(MAX)_ LR 2π × COUT _ LR × VOUT _ LR The unity-gain crossover of the linear regulator is: fCROSSOVER = AV_LR ✕ fPOLE_LR 2) The pole created by the internal amplifier delay is approximately 1MHz: fPOLE_AMP = 1MHz 3) Next, calculate the pole set by the transistor’s input capacitance, the transistor’s input resistance, and the base-to-emitter pullup resistor: fPOLE _ IN = 1 2π × CIN × (RBE || RIN ) where CIN = 22 gm is the transconductance of the pass transistor, and fT is the transition frequency. Both parameters can be found in the transistor’s data sheet. Because RBE is much greater than RIN, the above equation can be simplified: fPOLE _ IN = 1 2π × CIN × RIN Substituting for CIN and RIN yields: f fPOLE _ IN = T hFE 4) Next, calculate the pole set by the linear regulator’s feedback resistance and the capacitance between FB_ and AGND (including stray capacitance): fPOLE _ FB = 1 2π × CFB × (RUPPER || RLOWER ) where C FB is the capacitance between FB_ and AGND, RUPPER is the upper resistor of the linear regulator’s feedback divider, and RLOWER is the lower resistor of the divider. 5) Next, calculate the zero caused by the output capacitor’s ESR: fPOLE _ ESR = 1 2π × COUT _ LR × RESR where RESR is the equivalent series resistance of COUT_LR. To ensure stability, choose COUT_LR large enough so the crossover occurs well before the poles and zero calculated in steps 2 to 5. The poles in steps 3 and 4 generally occur at several megahertz, and using ceramic capacitors ensures the ESR zero occurs at several megahertz as well. Placing the crossover below 500kHz is sufficient to avoid the amplifier-delay pole and generally works well, unless unusual component choices or extra capacitances move one of the other poles or the zero below 1MHz. gm h , RIN = FE , 2πfT gm ______________________________________________________________________________________ TFT-LCD DC-DC Converter with Operational Amplifiers Power Dissipation An IC’s maximum power dissipation depends on the thermal resistance from the die to the ambient environment and the ambient temperature. The thermal resistance depends on the IC package, PC board copper area, other thermal mass, and airflow. The MAX1518B, with its exposed backside pad soldered to 1in 2 of PC board copper, can dissipate approximately 1.7W into +70°C still air. More PC board copper, cooler ambient air, and more airflow increase the possible dissipation, while less copper or warmer air decreases the IC’s dissipation capability. The major components of power dissipation are the power dissipated in the step-up regulator and the power dissipated by the operational amplifiers. Step-Up Regulator The largest portions of power dissipation in the step-up regulator are the internal MOSFET, the inductor, and the output diode. If the step-up regulator has 90% efficiency, approximately 3% to 5% of the power is lost in the internal MOSFET, approximately 3% to 4% in the inductor, and approximately 1% in the output diode. The remaining 1% to 3% is distributed among the input and output capacitors and the PC board traces. If the input power is about 5W, the power lost in the internal MOSFET is approximately 150mW to 250mW. Operational Amplifier The power dissipated in the operational amplifiers depends on their output current, the output voltage, and the supply voltage: PDSOURCE = IOUT _(SOURCE) × (VSUP − VOUT _ ) PDSINK = IOUT _(SINK) × VOUT _ where IOUT_(SOURCE) is the output current sourced by the operational amplifier, and IOUT_(SINK) is the output current that the operational amplifier sinks. In a typical case where the supply voltage is 13V and the output voltage is 6V with an output source current of 30mA, the power dissipated is 180mW. PC Board Layout and Grounding Careful PC board layout is important for proper operation. Use the following guidelines for good PC board layout: • Minimize the area of high-current loops by placing the inductor, the output diode, and the output capacitors near the input capacitors and near the LX and PGND pins. The high-current input loop goes from the positive terminal of the input capacitor to the inductor, to the IC’s LX pin, out of PGND, and to the input capacitor’s negative terminal. The highcurrent output loop is from the positive terminal of the input capacitor to the inductor, to the output diode (D1), and to the positive terminal of the output capacitors, reconnecting between the output capacitor and input capacitor ground terminals. Connect these loop components with short, wide connections. Avoid using vias in the high-current paths. If vias are unavoidable, use many vias in parallel to reduce resistance and inductance. • Create a power-ground island (PGND) consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all of these together with short, wide traces or a small ground plane. Maximizing the width of the powerground traces improves efficiency and reduces output voltage ripple and noise spikes. Create an analog ground plane (AGND) consisting of the AGND pin, all the feedback-divider ground connections, the operational-amplifier divider ground connections, the COMP and DEL capacitor ground connections, and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes. • Place all feedback voltage-divider resistors as close to their respective feedback pins as possible. The divider’s center trace should be kept short. Placing the resistors far away causes their FB traces to become antennas that can pick up switching noise. Take care to avoid running any feedback trace near LX or the switching nodes in the charge pumps. • Place the IN pin and REF pin bypass capacitors as close to the device as possible. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace. • Minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. • Minimize the size of the LX node while keeping it wide and short. Keep the LX node away from feedback nodes (FB, FBP, and FBN) and analog ground. Use DC traces to shield if necessary. Refer to the MAX1518B evaluation kit for an example of proper PC board layout. Chip Information TRANSISTOR COUNT: 4608 ______________________________________________________________________________________ 23 MAX1518B Applications Information TFT-LCD DC-DC Converter with Operational Amplifiers COM DRN CTL DEL DRVN FBN DRVP FBP TOP VIEW 32 31 30 29 28 27 26 25 SRC 1 24 COMP REF 2 23 FB AGND 3 22 IN PGND 4 21 LX OUT1 5 20 OUT5 NEG1 6 19 NEG5 POS1 7 18 POS5 OUT2 8 17 OUT4 9 10 11 12 13 14 15 16 POS2 BGND POS3 OUT3 SUP POS4 NEG4 MAX1518B NEG2 MAX1518B Pin Configuration THIN QFN 5mm x 5mm 24 ______________________________________________________________________________________ TFT-LCD DC-DC Converter with Operational Amplifiers QFN THIN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX1518B Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)