IRF IRF6604

PD - 94365B
IRF6604
HEXFET®
l
Application Specific MOSFETs
l Ideal for CPU Core DC-DC Converters
l Low Conduction Losses
l Low Switching Losses
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface Mount
Techniques
Power MOSFET
VDSS
RDS(on) max
Qg
30V
11.5mΩ@VGS = 7.0V
13mΩ@VGS = 4.5V
17nC
DirectFET™ ISOMETRIC
Description
The IRF6604 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging
to achieve the lowest on-state resistance charge product in a package that has the footprint of an SO-8 and only 0.7 mm
profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly
equipment and vapor phase, infra-red or convection soldering techniques. The DirectFET package allows dual sided cooling
to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%.
The IRF6604 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power
the latest generation of processors operating at higher frequencies. The IRF6604 has been optimized for parameters that
are critical in synchronous buck converters including Rds(on) and gate charge to minimize losses in the control FET socket.
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
30
V
VGS
±12
ID @ TC = 25°C
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 7.0V
ID @ TA = 25°C
Continuous Drain Current, VGS @ 7.0V
12
ID @ TA = 70°C
9.2
IDM
Continuous Drain Current, VGS @ 7.0V
Pulsed Drain Current
PD @TA = 25°C
Power Dissipation
2.3
49
c
PD @TA = 70°C
g
Power Dissipation g
PD @TC = 25°C
Power Dissipation
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
A
92
1.5
W
42
0.018
-40 to + 150
W/°C
°C
Thermal Resistance
Parameter
RθJA
Junction-to-Ambient
f
g
h
RθJA
Junction-to-Ambient
RθJA
Junction-to-Ambient
RθJC
Junction-to-Case
RθJ-PCB
Junction-to-PCB Mounted
i
Typ.
Max.
–––
55
12.5
–––
20
–––
–––
3.0
1.0
–––
Units
°C/W
Notes  through ‡ are on page 11
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6/11/03
IRF6604
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
V
Conditions
30
–––
–––
VGS = 0V, ID = 250µA
–––
27
–––
9.0
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 7.0V, ID = 12A
11.5
–––
10
–––
e
e
13
VGS = 4.5V, ID = 9.6A
VGS(th)
Gate Threshold Voltage
1.0
–––
3.0
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-4.5
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
30
µA
VDS = 24V, VGS = 0V
–––
–––
100
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 12V
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
38
–––
–––
gfs
Qg
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = -12V
S
VDS = 15V, ID = 9.6A
nC
VGS = 4.5V
Total Gate Charge
–––
17
26
Qgs1
Pre-Vth Gate-to-Source Charge
–––
4.1
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
1.0
–––
Qgd
Gate-to-Drain Charge
–––
6.3
–––
ID = 9.6A
Qgodr
–––
5.6
–––
See Fig. 16
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
7.3
–––
Qoss
Output Charge
–––
9.5
–––
td(on)
Turn-On Delay Time
–––
11
–––
VDD = 15V, VGS = 4.5V
tr
Rise Time
–––
4.3
–––
ID = 9.6A
td(off)
Turn-Off Delay Time
–––
18
–––
tf
Fall Time
–––
25
–––
Ciss
Input Capacitance
–––
2270
–––
Coss
Output Capacitance
–––
420
–––
Crss
Reverse Transfer Capacitance
–––
190
–––
VDS = 15V
nC
ns
VDS = 16V, VGS = 0V
e
Clamped Inductive Load
VGS = 0V
pF
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
Max.
Units
–––
32
mJ
–––
9.6
A
–––
0.23
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
12
ISM
(Body Diode)
Pulsed Source Current
–––
–––
92
showing the
integral reverse
VSD
(Body Diode)
Diode Forward Voltage
–––
0.94
1.2
V
p-n junction diode.
TJ = 25°C, IS = 9.6A, VGS = 0V
trr
Reverse Recovery Time
–––
31
47
ns
Qrr
Reverse Recovery Charge
–––
26
39
nC
ton
Forward Turn-On Time
2
c
MOSFET symbol
A
D
G
S
e
TJ = 25°C, IF = 9.6A
di/dt = 100A/µs
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRF6604
1000
1000
VGS
10V
7.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
VGS
10V
7.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
100
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
2.7V
10
100
2.7V
10
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
1
1
0.1
1
10
0.1
100
1
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100.00
2.0
I D = 12A
10.00
VDS = 15V
20µs PULSE WIDTH
1.00
2.5
3.0
3.5
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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4.0
1.5
(Normalized)
TJ = 25°C
R DS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (Α)
T J = 150°C
1.0
0.5
V GS = 7.0V
0.0
-60
-40
-20
0
20
40
60
TJ , Junction Temperature
80
100
120
140
160
( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF6604
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
Coss = Cds + Cgd
Ciss
1000
Coss
Crss
100
6.0
ID= 9.6A
VGS , Gate-to-Source Voltage (V)
10000
VDS= 24V
VDS= 15V
5.0
4.0
3.0
2.0
1.0
0.0
1
10
100
0
5
VDS, Drain-to-Source Voltage (V)
20
25
1000
ID, Drain-to-Source Current (A)
100
I SD , Reverse Drain Current (A)
15
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
T J= 25 ° C
1
V GS = 0 V
0.0
0.5
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
TJ = 150 ° C
10
1.0
1.5
V SD,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
10
100µsec
1msec
1
0.1
0.1
4
10
Q G Total Gate Charge (nC)
2.0
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF6604
2.0
VGS(th) Gate threshold Voltage (V)
12
ID , Drain Current (A)
9
6
3
1.8
1.6
1.4
ID = 250µA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
150
-75
-50
-25
°
TA, Ambient Temperature
(°C)
0
25
50
75
100 125 150
T J , Temperature ( °C )
Fig 9. Maximum Drain Current Vs.
Ambient Temperature
Fig 10. Threshold Voltage Vs. Temperature
(Z thJA )
100
D = 0.50
0.20
10
Thermal Response
0.10
0.05
P DM
0.02
1
t1
0.01
t2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
2. Peak T
0.1
0.00001
0.0001
0.001
0.01
0.1
t1/ t 2
J = P DM x Z thJA
1
+T A
10
100
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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IRF6604
80
ID
4.3A
7.7A
9.6A
15V
TOP
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
BOTTOM
DRIVER
L
VDS
60
40
20
0
25
50
75
100
125
150
( ° C)
Starting Tj, Junction Temperature
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
Fig 14a. Switching Time Test Circuit
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
10%
IG
ID
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
6
VGS
td(on)
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
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IRF6604
D.U.T
Driver Gate Drive
+
ƒ
+
‚
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
V DD
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRF6604
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
Q

+  oss × Vin × f + (Qrr × Vin × f )
 2

This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )

Qgs 2
Qgd
 

+I ×
× Vin × f  +  I ×
× Vin × f 
ig
ig

 

+ (Qg × Vg × f )
+
 Qoss
× Vin × f 
 2

This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRF6604
DirectFET™ Outline Dimension, MQ Outline
(Medium Size Can, Q-Designation).
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9
IRF6604
DirectFET™ Board Footprint, MQ Outline
(Medium Size Can, Q-Designation).
DirectFET™ Tape & Reel Dimension
(Showing component orientation).
10
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IRF6604
DirectFET™ Part Marking
6604
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.70mH
R G = 25Ω, IAS = 9.6A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ Surface mounted on 1 in. square Cu board.
… Used double sided cooling , mounting pad.
† Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
‡ TC measured with thermal couple mounted to top (Drain) of
part.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.6/03
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