TI1 BQ771605 External delay capacitor Datasheet

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bq7716xy Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries
with External Delay Capacitor
1 Features
3 Description
•
•
•
•
The bq7716xy device family provides an overvoltage
monitor and protector for Li-Ion battery pack systems.
Each cell is monitored independently for an
overvoltage condition. For quicker production-line
testing, the bq7716xy device provides a Customer
Test Mode with greatly reduced delay time.
1
•
•
•
2-, 3-, and 4-Series Cell Overvoltage Protection
External Capacitor-Programmed Delay Timer
Fixed OVP Threshold
High-Accuracy Overvoltage Protection:
±10 mV
Low Power Consumption ICC ≈ 1 µA
(VCELL(ALL) < VPROTECT)
Low Leakage Current Per Cell Input < 100 nA
Small Package Footprint
– 8-pin WSON (3.00 mm × 4.00 mm)
In the bq7716xy device, an external delay timer is
initiated upon detection of an overvoltage condition
on any cell. Upon expiration of the delay timer, the
output is triggered into its active state (either high or
low, depending on the configuration). The external
delay timer feature also includes the ability to detect
an open or shorted delay capacitor on the CD pin,
which will similarly trigger the output driver in an
overvoltage condition.
2 Applications
•
•
•
Power Tools
UPS Battery Backup
Light Electric Vehicles
– eBike
– eScooter
– Pedal Assist Bicycles
Table 1. Device Information Table(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
bq771600
WSON (8)
3.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet and the Device Comparison Table.
4 Simplified Schematic
C VD
VDD
OUT
R VD
V4
CD
V3
VSS
V2
V1
CCD
R IN
CIN
Cell 2
R IN
Cell 1
CIN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
bq771600, bq771601, bq771602
bq771604, bq771605, bq771611, bq771612
SLUSAX0D – DECEMBER 2012 – REVISED JULY 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Export Control Notice............................................
Glossary ................................................................
15
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2014) to Revision D
Page
•
Changed QFN to WSON ....................................................................................................................................................... 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed the bq771605 to Production Data ........................................................................................................................... 3
•
Added table note 2, which was hidden inadvertently ............................................................................................................. 4
•
Moved Pin Details to Feature Description section ................................................................................................................. 8
•
Moved from Application Information section to Design Requirements section ................................................................... 13
Changes from Revision B (June 2014) to Revision C
•
Page
Added the bq771612 device to Production Data.................................................................................................................... 3
Changes from Revision A (September 2013) to Revision B
Page
•
Changed the data sheet format .............................................................................................................................................. 1
•
Added the bq771611 device to Production Data.................................................................................................................... 3
Changes from Original (December 2012) to Revision A
•
2
Page
Added the bq771604 device to Production Data.................................................................................................................... 3
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SLUSAX0D – DECEMBER 2012 – REVISED JULY 2015
Table 2. Device Comparison Table
PART NUMBER
OVP (V)
OV HYSTERESIS (V)
OUTPUT DRIVE
TAPE AND REEL
(LARGE)
TAPE AND REEL (SMALL)
bq771600
4.3
0.3
CMOS Active High
bq771600DPJR
bq771600DPJT
bq771601
4.225
0.05
CMOS Active High
bq771601DPJR
bq771601DPJT
bq771602
4.225
0.05
NCH Active Low, Open Drain
bq771602DPJR
bq771602DPJT
bq771603 (1)
4.325
0.05
NCH Active Low, Open Drain
bq771603DPJR
bq771603DPJT
bq771604
4.2
0.05
CMOS Active High
bq771604DPJR
bq771604DPJT
bq771605
3.85
0.25
NCH Active Low
bq771605DPJR
bq771605DPJT
bq771607 (1)
4.2
0.25
CMOS Active High
bq771607DPJR
bq771607DPJT
bq771608 (1)
4.225
0.25
CMOS Active High
bq771608DPJR
bq771608DPJT
bq771609 (1)
4.25
0.05
CMOS Active High
bq771609DPJR
bq771609DPJT
bq771610 (1)
4.250
0.25
CMOS Active High
bq771610DPJR
bq771610DPJT
bq771611
4.35
0.3
CMOS Active High
bq771611DPJR
bq771611DPJT
bq771612
3.9
0.3
CMOS Active High
bq771612DPJR
bq771612DPJT
bq771613 (1)
4.2
0.05
NCH Active Low
bq771613DPJR
bq771613DPJT
bq771614 (1)
4.225
0.25
NCH Active Low
bq771614DPJR
bq771614DPJT
bq771615 (1)
4.25
0.05
NCH Active Low
bq771615DPJR
bq771615DPJT
0–0.3
CMOS Active High or NCH
Active Low, Open Drain
bq7716xyTBD
bq7716xyTBD
bq7716xy future options (2)
(1)
(2)
3.85–4.65
Product Preview only.
Contact TI.
6 Pin Configuration and Functions
DPJ Package
8-Pin WSON
Top View
VDD
1
8
OUT
V4
2
7
CD
V3
3
6
VSS
V2
4
5
V1
Pin Functions
PIN
(1)
TYPE
DESCRIPTION
NAME
NO.
I/O (1)
CD
7
I/O
External capacitor connection for delay timer
OUT
8
OA
Output drive for overvoltage fault signal
VDD
1
P
Power supply
VSS
6
P
Electrically connected to IC ground and negative terminal of the lowest cell in the stack
V1
5
I
Sense input for positive voltage of the lowest cell in the stack
V2
4
I
Sense input for positive voltage of the second cell from the bottom of the stack
V3
3
I
Sense input for positive voltage of the third cell from the bottom of the stack
V4
2
I
Sense input for positive voltage of the fourth cell from the bottom of the stack
IA = Input Analog, OA = Output Analog, P = Power Connection
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range (2)
Input voltage range
(2)
Output voltage range (2)
MIN
MAX
UNIT
VDD–VSS
–0.3
30
V
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
–0.3
30
V
OUT–VSS
–0.3
30
V
110
°C
Continuous total power dissipation, PTOT
See package
dissipation rating.
Functional temperature
–40
Lead temperature (soldering, 10 s), TSOLDER
300
Storage temperature, Tstg
–65
(1)
(2)
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Absolute maximum ratings for input voltage range, output voltage range, and supply voltage are assured by design and not tested in
production.
7.2 ESD Ratings
VALUE
VESD Rating
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
VDD
(1)
NOM
MAX
UNIT
Supply voltage
3
20
V
V4–V3, V3–V2,
V2–V1, V1–VSS, or
CD–VSS
Input voltage range
0
5
V
TA
Operating ambient temperature range
–40
110
°C
(1)
See Typical Application.
7.4 Thermal Information
bq7716xy
THERMAL METRIC (1)
DPJ (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
56.6
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
56.4
°C/W
RθJB
Junction-to-board thermal resistance
30.6
°C/W
ψJT
Junction-to-top characterization parameter
1.0
°C/W
ψJB
Junction-to-board characterization parameter
37.8
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
11.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLUSAX0D – DECEMBER 2012 – REVISED JULY 2015
7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE PROTECTION THRESHOLD VCx
V(PROTECT)
Overvoltage
Detection
VOV
bq771600
4.300
V
bq771601
4.225
V
bq771602
4.225
V
bq771603 (1)
4.325
V
bq771604
4.200
V
bq771605
3.850
V
bq771607 (1)
4.200
V
(1)
4.225
V
bq771609 (1)
4.250
V
bq771610 (1)
4.250
V
bq771611
4.350
V
bq771612
3.900
V
bq771613 (1)
4.200
V
bq771614 (1)
4.225
V
bq771608
bq771615
VHYS
OV Detection
Hysteresis
VOADRIFT
OV Detection
Accuracy Across
Temperature
V
250
300
400
mV
bq771601
25
50
75
mV
bq771602
25
50
75
mV
bq771603 (1)
25
50
75
mV
bq771604
25
50
75
mV
bq771605
200
250
300
mV
bq771607 (1)
200
250
300
mV
bq771608 (1)
200
250
300
mV
bq771609 (1)
25
50
75
mV
(1)
200
250
300
mV
bq771611
250
300
400
mV
bq771612
250
300
400
mV
(1)
25
50
75
mV
bq771614 (1)
200
250
300
mV
bq771615 (1)
25
50
75
mV
bq771613
OV Detection
Accuracy
4.250
bq771600
bq771610
VOA
(1)
TA = 25°C
–10
10
mV
TA = –40°C
–40
44
mV
TA = 0°C
–20
20
mV
TA = 60°C
–24
24
mV
TA = 110°C
–54
54
mV
2
µA
0.1
µA
SUPPLY AND LEAKAGE CURRENT
ICC
Supply Current
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
(See Figure 10.)
IIN
Input Current at Vx
Pins
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
(See Figure 10.)
(1)
1
–0.1
Future option. Contact TI.
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Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DRIVE OUT, CMOS ACTIVE HIGH VERSIONS ONLY
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
= 14.4 V, IOH = 100 µA
Output Drive
Voltage, Active High
VOUT1
6
If three of four cells are short circuited, only one cell
remains powered and > VOV, VDD = Vx (cell voltage),
IOH = 100 µA
VDD – 0.3
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, IOL = 100 µA measured into OUT pin
IOUTH1
OUT Source Current (V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
(During OV)
= 14.4 V, OUT = 0 V. Measured out of OUT pin
IOUTL1
OUT Sink Current
(No OV)
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, OUT = VDD.
Measured into OUT pin
V
250
0.5
V
400
mV
4.5
mA
14
mA
400
mV
14
mA
100
nA
OUTPUT DRIVE OUT, NCH OPEN DRAIN ACTIVE LOW VERSIONS ONLY
VOUT2
Output Drive
Voltage, Active Low
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
= 14.4 V, IOL = 100 µA measured into OUT pin
IOUTH2
OUT Sink Current
(During OV)
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
= 14.4 V. OUT = VDD.
Measured into OUT pin
IOUTLK
OUT Pin Leakage
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, OUT = VDD. Measured out of OUT pin
250
0.5
DELAY TIMER
CCD = 0.1 µF
(For capacitor sizing, see .)
tCD
OV Delay Time
VCD
CD Fault Detection
External Comparator The CD pin will first be quickly charged to this value
Threshold, Initial
before being discharged back to VSS.
Charge Value
tCHGDELAY
CD Charging Delay
OVP to OUT delay with CD shorted to ground
ICHG
OV Detection
Charging Current
CD pin fast charging current from VSS to VCD to begin
delay countdown
300
µA
IDSG
OV Detection
Discharging Current
CD pin discharging current from VDELAY to VSS
100
nA
6
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1
1.5
2
1.5
20
s
V
170
ms
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SLUSAX0D – DECEMBER 2012 – REVISED JULY 2015
7.6 Typical Characteristics
4.40
0.316
Mean
Min
Max
4.39
4.38
0.315
4.36
VHYS (V)
VOUT (V)
4.37
4.35
4.34
4.33
0.314
0.313
4.32
4.31
4.30
−50
−25
0
25
50
Temperature (°C)
75
100
125
0.312
−50
−25
0
G001
Figure 2. Overvoltage Threshold (OVT) vs. Temperature
25
50
Temperature (°C)
75
100
125
G002
Figure 3. Hysteresis VHYS vs. Temperature
1.8
1.6
1.5
1.6
1.4
1.4
1.2
ICELL (µA)
IDD (µA)
1.3
1.1
1.0
1.2
1.0
0.9
0.8
0.8
0.7
0.6
−50
−25
0
25
50
Temperature (°C)
75
100
125
0.6
−50
Figure 4. IDD Current Consumption vs.
Temperature at VDD = 16 V
0
25
50
Temperature (°C)
75
100
125
G004
Figure 5. ICELL vs. Temperature
at VCELL= 9.2 V
−3.68
8
−3.70
7
−3.72
6
−3.74
−3.76
VOUT (V)
IOUT (mA)
−25
G003
−3.78
−3.80
−3.82
5
4
3
2
−3.84
1
−3.86
−3.88
−50
−25
0
25
50
Temperature (°C)
75
100
Figure 6. Output Current IOUT vs. Temperature
Copyright © 2012–2015, Texas Instruments Incorporated
125
G005
0
0
5
10
15
VDD (V)
20
25
30
G006
Figure 7. VOUT vs. VDD
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8 Detailed Description
8.1 Overview
In the bq7716xy family of devices for overvoltage protection, each cell is monitored independently and an
external delay timer is initiated if an overvoltage condition is detected when any cell voltage is higher than the
protection voltage threshold, VOV. After the delay time expires, the OUT pin is inserted.
For quicker production-line testing, the device provides a Customer Test Mode with greatly reduced delay time.
8.2 Functional Block Diagram
PACK+
R VD
C VD
VDD
VC4
CIN
RIN
VC3
CIN
RIN
VC2
Sensing Circuit
RIN
CIN
RIN
VOV
Enable
Delay
Charging/ Active
Discharging
Circuit
OUT
VC1
CIN
VSS
CD
CCD
PACK–
8.3 Feature Description
In the bq7716xy device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, a timer
circuit is activated. This timer circuit charges the CD pin to a nominal value, then slowly discharges it with a fixed
current back down to VSS. When the CD pin falls below a nominal threshold near VSS, the OUT terminal goes
from inactive to active state. Additionally, a timeout detection circuit checks to ensure that the CD pin
successfully begins charging to above VSS and subsequently drops back down to VSS, and if a timeout error is
detected in either direction, it will similarly trigger the OUT pin to become active. See Figure 8 for reference.
For an NCH Open Drain Active Low configuration, the OUT pin pulls down to VSS when active (OV present), and
is high impedance when inactive (no OV).
8
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Cell Voltage (V)
(V4–V3, V3–V2, V2–V1, V1–VSS)
Feature Description (continued)
VOV
VOV –VHYS
t DELAY
OUT (V)
Figure 8. Timing for Overvoltage Sensing
Figure 9 shows an overview of the behavior of the CD pin during an OV sequence.
Fault condition
present
Fault response
becomes active
VCD
V(CD)
t CHGDELAY
t CD
ICHG
I(CD)
IDSG
VOUT1
V(OUT)
Note: Active High OUT version shown
Figure 9. CD Pin Mechanism
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Feature Description (continued)
8.3.1 Sense Positive Input for Vx
This is an input to sense each single battery cell voltage. A series resistor and a capacitor across the cell for
each input is required for noise filtering and stable voltage monitoring.
8.3.2 Output Drive, OUT
This terminal serves as the fault signal output, and may be ordered in either active HIGH or LOW options.
8.3.3 Supply Input, VDD
This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,
and a capacitor is connected to ground for noise filtering.
8.3.4 External Delay Capacitor, CD
This terminal is connected to an external capacitor that is used for setting the delay timer during an overvoltage
fault event.
The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or
open capacitor during an overvoltage event.
The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the OV
threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor
discharges below a set voltage, the OUT transitions from an inactive to active state.
To calculate the delay, use the following equation:
tCD (s) = K × CCD (µF), where K = 10 to 20 range.
(1)
Example: If CCD= 0.1 µF (typical), then the delay timer range is
tCD (s) = 10 × 0.1 = 1 s (Minimum)
tCD (s) = 20 × 0.1 = 2 s (Maximum)
NOTE
The tolerance on the capacitor used for CCD increases the range of the tCD timer.
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode.
The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1), (V3–V2), and (V4–V3).
The OUT pin is inactive and if configured:
• Active high is low
• Active low is being externally pulled up and is an open drain
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltages exceeds the overvoltage threshold, VOV for
configured OV delay time. The OUT pin is activated after a delay time set by the capacitance in the CD pin. The
OUT pin will either pull high internally, if configured as active high, or will be pulled low internally, if configured as
active low. When all of the cell voltages fall below the (VOV–VHYS), the device returns to NORMAL mode
8.4.3 Customer Test Mode
It is possible to reduce test time for checking the overvoltage function by simply shorting the external CD
capacitor to VSS. In this case, the OV delay would be reduced to the t(CHGDELAY) value, which has a maximum of
170 ms.
10
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SLUSAX0D – DECEMBER 2012 – REVISED JULY 2015
Device Functional Modes (continued)
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part
into Customer Test Mode. Also avoid exceeding Absolute Maximum Voltages for the
individual cell voltages (V4–V3), (V3–V2), (V2–V1), and (V1–VSS). Stressing the pins
beyond the rated limits may cause permanent damage to the device.
Figure 10 shows the timing for the Customer Test Mode.
OV Condition
V(VCELL)
≤ 170 ms
V(OUT)
CD pin held low
V(CD)
Figure 10. Timing for Customer Test Mode
Figure 11 shows the measurement for current consumption for the product for both VDD and Vx.
I CC
IIN
VDD
OUT
V4
CD
IIN
V3
VSS
IIN
V2
V1
Cell4
Cell3
Cell2
IIN
Cell1
Figure 11. Configuration for IC Current Consumption Test
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 12 shows each external component.
CVD
VDD
OUT
RVD
Cell 4
R IN
C IN
V4
CD
CCD
Cell 3
R IN
V3
VSS
V2
V1
C IN
R IN
C IN
Cell 2
Cell1
R IN
C IN
Figure 12. Application Configuration
NOTE
In the case of an Open Drain Active Low configuration, an external pull-up resistor is
required on the OUT terminal.
Changes to the ranges stated in Table 3 will impact the accuracy of the cell
measurements.
NOTE
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this
recommended value changes the accuracy of the cell voltage measurements and VOV
trigger level.
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SLUSAX0D – DECEMBER 2012 – REVISED JULY 2015
9.2 Typical Application
C VD
CVD
VDD
OUT
OUT
VDD
RVD
R VD
V4
CD
V4
CD
V3
VSS
V2
V1
CCD
V3
CCD
VSS
RIN
Cell 3
V1
V2
RIN
R IN
Cell 2
R IN
Cell 1
CIN
CIN
Cell 2
CIN
Cell 1
CIN
RIN
Figure 13. 2-Series Cell Configuration with CapacitorProgrammed Delay
CIN
Figure 14. 3-Series Cell Configuration with CapacitorProgrammed Delay
NOTE
In these application examples of 2 s and 3 s, an external pull-up resistor is required on the
OUT terminal to configure for an Open Drain Active Low operation.
9.2.1 Design Requirements
Changes to the ranges stated in Table 3 will impact the accuracy of the cell measurements.
Table 3. Design Parameters
PARAMETER
EXTERNAL COMPONENT
MIN
NOM
MAX
1000
1100
Ω
0.1
µF
Voltage monitor filter resistance
RIN
900
Voltage monitor filter capacitance
CIN
0.01
100
Supply voltage filter resistance
RVD
Supply voltage filter capacitance
CVD
0.1
CD external delay capacitance
CCD
0.1
OUT Open drain version pull-up
resistance to PACK+
ROUT
100k
UNIT
1K
Ω
µF
1
µF
Ω
9.2.2 Detailed Design Procedure
1. Determine the number of cells in series. The device supports a 2-S to 4-S cell configuration. For 2S and 3S,
the top unused pin(s) should be shorted as shown in Figure 13 and Figure 14.
2. Determine the overvoltage protection delay. Follow the calculation example described in External Delay
Capacitor, CD . Select the correct capacitor to connect to the CD pin.
3. Follow the application schematic to connect the device. If the OUT pin is configured to open drain, an
external pull-up resistor should be used. Refer to the Out Sink Current specification, IOUTH2 to ensure a
proper pull-up resistor value is used, so that the OUT pin sink current is able to pull down the pin during OV
condition.
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9.2.3 Application Curves
0.316
1.6
1.5
1.4
1.3
IDD (µA)
VHYS (V)
0.315
0.314
1.2
1.1
1.0
0.9
0.313
0.8
0.7
0.312
−50
−25
0
25
50
Temperature (°C)
75
100
0.6
−50
125
−25
G002
Figure 15. Hysteresis VHYS vs. Temperature
0
25
50
Temperature (°C)
75
100
125
G003
Figure 16. IDD Current Consumption vs.
Temperature at VDD = 16 V
10 Power Supply Recommendations
The maximum power of this device is 20 V on VDD.
11 Layout
11.1 Layout Guidelines
1. Ensure the RC filters for the Vx pins and VDD pin are placed as close as possible to the target terminal,
reducing the tracing loop area.
2. The capacitor for CD pin should be placed close to the IC terminals.
11.2 Layout Example
Place the RC filters close to the
device terminals
Power Trace Line
Pack +
VDD
OUT
V4
CD
V3
VSS
OUT
Pack -
PWPD
VCELL3
V2
V1
VCELL2
VCELL1
Place close to the CD pin
Figure 17. Layout
14
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bq771604, bq771605, bq771611, bq771612
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SLUSAX0D – DECEMBER 2012 – REVISED JULY 2015
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq771600
Click here
Click here
Click here
Click here
Click here
bq771601
Click here
Click here
Click here
Click here
Click here
bq771602
Click here
Click here
Click here
Click here
Click here
bq771604
Click here
Click here
Click here
Click here
Click here
bq771605
Click here
Click here
Click here
Click here
Click here
bq771611
Click here
Click here
Click here
Click here
Click here
bq771612
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ771600DPJR
ACTIVE
WSON
DPJ
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
771600
BQ771600DPJT
ACTIVE
WSON
DPJ
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
771600
BQ771601DPJR
ACTIVE
WSON
DPJ
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
771601
BQ771601DPJT
ACTIVE
WSON
DPJ
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
771601
BQ771602DPJR
ACTIVE
WSON
DPJ
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
771602
BQ771602DPJT
ACTIVE
WSON
DPJ
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
771602
BQ771604DPJR
ACTIVE
WSON
DPJ
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771604
BQ771604DPJT
ACTIVE
WSON
DPJ
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771604
BQ771605DPJR
ACTIVE
WSON
DPJ
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771605
BQ771605DPJT
ACTIVE
WSON
DPJ
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771605
BQ771611DPJR
ACTIVE
WSON
DPJ
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771611
BQ771611DPJT
ACTIVE
WSON
DPJ
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771611
BQ771612DPJR
ACTIVE
WSON
DPJ
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771612
BQ771612DPJT
ACTIVE
WSON
DPJ
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771612
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2015
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
BQ771600DPJR
WSON
DPJ
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771600DPJT
WSON
DPJ
8
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771601DPJR
WSON
DPJ
8
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771601DPJT
WSON
DPJ
8
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771602DPJR
WSON
DPJ
8
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771602DPJT
WSON
DPJ
8
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771604DPJR
WSON
DPJ
8
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771604DPJT
WSON
DPJ
8
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771605DPJR
WSON
DPJ
8
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771605DPJT
WSON
DPJ
8
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771611DPJR
WSON
DPJ
8
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771611DPJT
WSON
DPJ
8
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771612DPJR
WSON
DPJ
8
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
BQ771612DPJT
WSON
DPJ
8
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ771600DPJR
WSON
DPJ
8
3000
367.0
367.0
35.0
BQ771600DPJT
WSON
DPJ
8
250
210.0
185.0
35.0
BQ771601DPJR
WSON
DPJ
8
3000
367.0
367.0
35.0
BQ771601DPJT
WSON
DPJ
8
250
210.0
185.0
35.0
BQ771602DPJR
WSON
DPJ
8
3000
367.0
367.0
35.0
BQ771602DPJT
WSON
DPJ
8
250
210.0
185.0
35.0
BQ771604DPJR
WSON
DPJ
8
3000
367.0
367.0
35.0
BQ771604DPJT
WSON
DPJ
8
250
210.0
185.0
35.0
BQ771605DPJR
WSON
DPJ
8
3000
367.0
367.0
35.0
BQ771605DPJT
WSON
DPJ
8
250
210.0
185.0
35.0
BQ771611DPJR
WSON
DPJ
8
3000
367.0
367.0
35.0
BQ771611DPJT
WSON
DPJ
8
250
210.0
185.0
35.0
BQ771612DPJR
WSON
DPJ
8
3000
367.0
367.0
35.0
BQ771612DPJT
WSON
DPJ
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
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