BSI BS616LV1622TIG70 Very low power/voltage cmos sram 1m x 16 or 2m x 8 bit switchable Datasheet

BSI
Very Low Power/Voltage CMOS SRAM
1M x 16 or 2M x 8 bit switchable
„ FEATURES
BS616LV1622
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
• Wide Vcc operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 45mA (@55ns) operating current
I -grade: 46mA (@55ns) operating current
C-grade: 36mA (@70ns) operating current
I -grade: 37mA (@70ns) operating current
3.0uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 113mA (@55ns) operating current
I -grade: 115mA (@55ns) operating current
C-grade: 90mA (@70ns) operating current
I -grade: 92mA (@70ns) operating current
15uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
„ DESCRIPTION
The BS616LV1622 is a high performance, very low power CMOS Static
Random Access Memory organized as 1,048,676 words by 16 bits or
2,097,152 bytes by 8 bits selectable by CIO pin and operates in a wide
range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 3.0uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC .
This device provide three control inputs and three states output drivers
for easy memory expansion.
The BS616LV1622 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1622 is available in 48-pin 12mmx20mm TSOP1 package.
„ PRODUCT FAMILY
PRODUCT FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
55ns : 3.0~5.5V
70ns : 2.7~5.5V
POWER DISSIPATION
STANDBY
Operating
(ICCSB1, Max)
PKG TYPE
(ICC, Max)
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
70ns
70ns
BS616LV1622TC
+0 O C to +70 O C
2.4V ~ 5.5V
55 / 70
10uA
110uA
36mA
90mA
TSOP1-48(12mmx20mm)
BS616LV1622TI
-40 O C to +85 O C
2.4V ~ 5.5V
55 / 70
20uA
220uA
37mA
92mA
TSOP1-48(12mmx20mm)
„ BLOCK DIAGRAM
„ PIN CONFIGURATIONS
A4
A3
A2
A1
A0
/CE1
D0
D1
D2
D3
Vcc
CIO
Vss
D4
D5
D6
D7
A19
/WE
A18
A17
A16
A15
A14
1
48
47
46
9
10
13
BS616LV1622TC
BS616LV1622T I
37
16
17
27
24
25
A19
A15
A14
A13
A5
A6
A7
/OE
/UB
/LB
CE2
SAE
D15
D14
D13
D12
Vss
Vcc
D11
D10
D9
D8
A8
A9
A10
A11
A12
A13
A12
Address
A11
A10
A9
A8
A17
A7
A6
Input
Buffer
24
4096
Row
Memory Array
Decoder
4096 x 4096
4096
16(8)
D0
.
.
.
.
.
.
.
.
Data
Input
Buffer
16(8)
Column I/O
Write Driver
Sense Amp
16(8)
16(8)
256(512)
Data
Output
Buffer
D15
Column Decoder
CE1
CE2
WE
OE
UB
LB
CIO
48-pin 12mmx20mm TSOP1 top view
16(18)
Control
Address Input Buffer
A16 A0 A1 A2 A3 A4 A5 A18 (SAE)
Vdd
Vss
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV1622
1
Revision 2.1
Jan.
2004
BSI
BS616LV1622
„ PIN DESCRIPTIONS
Name
Function
A0-A19 Address Input
These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.
SAE Address Input
This address input incorporates with the above 20 address inputs select one of the
2,097,152 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input
This input selects the organization of the SRAM. 1,048,576 x 16-bit words
configuration is selected if CIO is HIGH. 2,097,152 x 8-bit bytes configuration is
selected if CIO is LOW.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
R0201-BS616LV1622
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Revision 2.1
Jan.
2004
BSI
BS616LV1622
„ TRUTH TABLE
MODE
CE1
CE2
H
X
Fully Standby
Output Disable
Read from SRAM
( WORD mode )
Write to SRAM
( WORD mode )
X
L
L
H
L
L
OE
WE
CIO
X
X
X
H
H
L
H
X
H
X
H
H
L
H
LB
UB
SAE
D0~7
D8~15
VCC Current
X
X
X
X
X
High-Z
High-Z
ICCSB, ICCSB1
X
X
X
High-Z
High-Z
ICC
L
H
Dout
High-Z
H
L
High-Z
Dout
L
L
Dout
Dout
L
H
Din
X
H
L
X
Din
L
L
Din
Din
X
X
ICC
ICC
Read from SRAM
( BYTE Mode )
L
H
L
H
L
X
X
A-1
Dout
High-Z
ICC
Write to SRAM
( BYTE Mode )
L
H
X
L
L
X
X
A-1
Din
X
ICC
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
V TERM
T BIAS
PARAMETER
Terminal Voltage
Respect to GND
with
Temperature Under Bias
„ OPERATING RANGE
RATING
UNITS
-0.5 to
Vcc+0.5
V
-40 to +85
O
-60 to +150
O
RANGE
Commercial
C
T STG
Storage Temperature
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
Industrial
C
O
O
0 C to +70 C
O
O
-40 C to +85 C
Vcc
2.4V ~ 5.5V
2.4V ~ 5.5V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS616LV1622
AMBIENT
TEMPERATURE
3
SYMBOL
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V
10
pF
VI/O=0V
12
pF
1. This parameter is guaranteed and not 100% tested.
Revision 2.1
Jan.
2004
BSI
BS616LV1622
„ DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
PARAMETER
NAME
PARAMETER
VIL
Guaranteed Input Low
Voltage(3)
VIH
Guaranteed Input High
Voltage(3)
IIL
Input Leakage Current
ILO
Output Leakage Current
TEST CONDITIONS
MIN. TYP.
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
Vcc = Max, VIN = 0V to Vcc
Vcc = Max, CE1 = VIH , or CE2 = V iL , or
OE = VIH, VI/O = 0V to Vcc
-0.5
-0.5
--
(1)
MAX.
2.0
2.2
----
0.8
0.8
Vcc+0.3
Vcc+0.3
--
--
1
uA
--
--
1
uA
-----
0.4
0.4
---
VOL
Output Low Voltage
Vcc = Max, IOL= 2mA
Vcc=3V
Vcc=5V
VOH
Output High Voltage
Vcc = Min, IOH= -1mA
Vcc=3V
Vcc=5V
--2.4
2.4
Operating Power Supply
Current
CE1 = VIL and CE2 = VIH
, IDQ = 0mA, F = Fmax(2)
70ns
Vcc=3V
--
--
37
70ns
Vcc=5V
--
--
92
Standby Current-TTL
CE1 = VIH or CE2 = VIL
, IDQ = 0mA
Vcc=3V
--
--
1.3
Vcc=5V
--
--
2.5
CE1≧ Vcc-0.2V, or CE2≦ 0.2V, or
LB and UB ≧ Vcc - 0.2V
V IN ≧ Vcc - 0.2V or VIN ≦ 0.2V
Vcc=3V
--
3
20
Standby Current-CMOS
Vcc=5V
--
15
220
(4)
ICC
ICCSB
(5)
ICCSB1
UNITS
V
V
V
V
mA
mA
uA
1. Typical characteristics are at TA = 25oC.
2. Fmax = 1/tRC .
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
5.IccsB1 is 10uA/110uA at Vcc=3.0V/5.0V and TA=70oC.
4. Icc_Max. is 46mA(@3.0V) / 115mA(@5.0V) under 55ns operation.
R0201-BS616LV1622
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Revision 2.1
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2004
BSI
BS616LV1622
„ DATA RETENTION CHARACTERISTICS ( TA = -40oC to +85oC )
MIN.
TYP. (1)
MAX.
UNITS
Vcc for Data Retention
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V or
LB ≧ Vcc - 0.2V and UB ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
1.5
--
--
V
ICCDR
Data Retention Current
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V or
LB ≧ Vcc - 0.2V and UB ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
--
1.5
5
uA
tCDR
Chip Deselect to Data
Retention Time
0
--
--
ns
--
--
ns
SYMBOL
VDR
PARAMETER
(3)
TEST CONDITIONS
See Retention Waveform
tR
Operation Recovery Time
TRC
(2)
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR(Max.) is 2.5uA at TA=70OC.
„ LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
Vcc
VDR ≧ 1.5V
Vcc
CE1
Vcc
tR
t CDR
CE1 ≧ Vcc - 0.2V
VIH
VIH
„ LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
VDR ≧ 1.5V
Vcc
CE2
R0201-BS616LV1622
VIL
Vcc
tR
t CDR
CE2 ≦ 0.2V
5
VIL
Revision 2.1
Jan.
2004
BSI
BS616LV1622
„AC TEST CONDITIONS
„ KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
WAVEFORM
Input and Output
Timing Reference Level
0.5Vcc
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to +85oC )
READ CYCLE
JEDEC
PARAMETER
PARAMETER
NAME
NAME
tAVAX
tAVQV
tELQV
tRC
tAA
t ACS1
tELQV
tBA
CYCLE TIME : 70ns CYCLE TIME : 55ns
DESCRIPTION
Vcc = 2.7~5.5V
Read Cycle Time
Vcc = 3.0~5.5V
UNIT
MIN. TYP. MAX.
MIN. TYP. MAX.
70
--
--
55
--
--
ns
--
--
70
--
--
55
ns
Chip Select Access Time
(CE1)
--
--
70
--
--
55
ns
t ACS2
tBA (1)
Chip Select Access Time
(CE2)
--
--
70
--
--
55
ns
(LB,UB)
--
--
35
--
--
30
ns
tGLQV
tELQX
tBE
tGLQX
tOE
tCLZ
tBE
tOLZ
Output Enable to Output Valid
--
--
35
--
--
30
ns
(CE2,CE1)
10
--
--
10
--
--
ns
5
--
--
5
--
--
ns
Output Enable to Output in Low Z
5
--
--
5
--
--
ns
tEHQZ
tBDO
tCHZ
tBDO
Chip Deselect to Output in High Z (CE2,CE1)
--
--
35
--
--
30
ns
Data Byte Control to Output High Z (LB,UB)
--
--
35
--
--
30
ns
tGHQZ
tOHZ
Output Disable to Output in High Z
--
--
30
--
--
25
ns
tAXOX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
Address Access Time
Data Byte Control Access Time
Chip Select to Output Low Z
Data Byte Control to Output Low Z
(LB,UB)
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-BS616LV1622
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Revision 2.1
Jan.
2004
BSI
BS616LV1622
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
ADDRESS
t AA
t OH
t OH
D OUT
READ CYCLE2 (1,3,4)
CE2
t
ACS2
t
ACS1
CE1
t
t CHZ(5)
(5)
CLZ
D OUT
READ CYCLE3 (1,4)
t RC
ADDRESS
t
AA
OE
t
CE2
t
t
CE1
t
t
t
OE
OH
ACS2
OLZ
t
ACS1
(5)
CLZ
OHZ
(5)
(1,5)
t
CHZ
t
BDO
LB,UB
t
BE
t
BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
R0201-BS616LV1622
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Revision 2.1
Jan.
2004
BSI
BS616LV1622
„ AC ELECTRICAL CHARACTERISTICS ( TA =
WRITE CYCLE
JEDEC
PARAMETER
PARAMETER
NAME
NAME
t AVAX
t E1LWH
t AVWL
t AVWH
t WLWH
t WHAX
t BW
t WLQZ
t DVWH
t WHDX
t GHQZ
t WC
t CW
t AS
t AW
t WP
t WR
t BW(1)
t WHZ
t DW
t DH
t OHZ
t WHOX
t OW
-40oC
to
+85oC
)
CYCLE TIME : 70ns CYCLE TIME : 55ns
DESCRIPTION
Vcc = 3.0~5.5V
Vcc = 2.7~5.5V
MIN. TYP. MAX.
MIN. TYP. MAX.
UNIT
Write Cycle Time
70
--
--
55
--
--
ns
Chip Select to End of Write
70
--
--
55
--
--
ns
Address Setup Time
0
--
--
0
--
--
ns
Address Valid to End of Write
70
--
--
55
--
--
ns
Write Pulse Width
35
--
--
30
--
--
ns
0
--
--
0
--
--
ns
(CE2,CE1,WE)
Write recovery Time
Date Byte Control to End of Write (LB,UB)
30
--
--
25
--
--
ns
Write to Output in High Z
--
--
30
--
--
25
ns
Data to Write Time Overlap
30
--
--
25
--
--
ns
Data Hold from Write Time
0
--
--
0
--
--
ns
Output Disable to Output in High Z
--
--
30
--
--
25
ns
End of Write to Output Active
5
--
--
5
--
--
ns
NOTE :
1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
(3)
t WR
OE
CE2
(5)
(11)
t CW
(5)
CE1
t
BW
(5)
LB,UB
t AW
WE
(3)
t WP
t AS
(2)
(4,10)
t OHZ
D OUT
t DH
t DW
D IN
R0201-BS616LV1622
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Revision 2.1
Jan.
2004
BSI
BS616LV1622
WRITE CYCLE2 (1,6)
t WC
ADDRESS
CE2
(11)
t
(5)
CE1
t
BW
(5)
LB,UB
t
WE
CW
AW
t WR
t WP
(3)
(2)
t AS
(4,10)
t WHZ
D OUT
t
OW
t
DH
(7)
(8)
t DW
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV1622
9
Revision 2.1
Jan.
2004
BSI
BS616LV1622
„ ORDERING INFORMATION
BS616LV1622 X X
Z
YY
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
T : TSOP1-48(12mmx20mm)
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
„ PACKAGE DIMENSIONS
TSOP1-48 (12mm x 20mm)
R0201-BS616LV1622
10
Revision 2.1
Jan.
2004
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