BSI BS616LV8021 Very low power/voltage cmos sram 512k x 16 or 1m x 8 bit switchable Datasheet

BSI
Very Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
BS616LV8021
„ DESCRIPTION
„ FEATURES
The BS616LV8021 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from
a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1uA and maximum access time of 70/100ns in 3.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV8021 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8021 is available in 48-pin BGA type.
• Very low operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
1uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc=3.0V
-10 100ns (Max.) at Vcc=3.0V
•Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
POWER DISSIPATION
STANDBY
Operating
SPEED
(ns)
(ICCSB1 , Max)
(ICC , Max)
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
PKG TYPE
BS616LV8021AC
+0 O C to +70 O C
2.7V ~ 3.6V
70 / 100
16uA
20mA
BGA-48-0608
BS616LV8021AI
-40 O C to +85 O C
2.7V ~ 3.6V
70 / 100
24uA
25mA
BGA-48-0608
„ BLOCK DIAGRAM
„ PIN CONFIGURATIONS
A
1
2
3
4
5
6
LB
OE
A0
A1
A2
CE2
B
D8
UB
A3
A4
CE1
D0
C
D9
D10
A5
A6
D1
D2
D
E
VSS
VCC
D11
D12
A17
VSS
A7
A16
D3
D4
A15
A14
A13
A12
Address
A11
A10
Input
A9
A8
A17
A7
A6
Buffer
16(8)
D0
.
.
.
.
VSS
.
.
.
.
D6
D13
A14
A15
G
D15
CIO
.
A 12
A13
WE
D7
H
A18
A8
A9
A10
A11
SAE.
Memory Array
Decoder
2048 x 4096
Data
Input
Buffer
16(8)
Column I/O
Write Driver
16(8)
16(8)
Sense Amp
256(512)
Data
Output
Buffer
D15
D5
D14
2048
Row
4096
VCC
F
22
Column Decoder
CE1
CE2
WE
OE
UB
LB
CIO
16(18)
Control
Address Input Buffer
A16 A0 A1 A2 A3 A4 A5 A18 (SAE)
Vdd
Vss
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8021
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Revision 2.3
April 2002
BSI
BS616LV8021
„ PIN DESCRIPTIONS
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
SAE Address Input
This address input incorporate with the above 19 address inputs select one of the
1,048,576 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input
This input selects the organization of the SRAM. 524,288 x 16-bit words configuration
is selected if CIO is HIGH. 1,048,576 x 8-bit bytes configuration is selected if CIO is
LOW.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
R0201-BS616LV8021
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Revision 2.3
April 2002
BSI
BS616LV8021
„ TRUTH TABLE
MODE
CE1
CE2
OE
WE
CIO
LB
UB
SAE
D0~7
D8~15
VCC Current
Fully Standby
H
L
X
X
X
X
X
X
High-Z
High-Z
ICCSB, ICCSB1
Output Disable
L
H
H
H
X
X
X
X
High-Z
High-Z
ICC
L
H
Dout
High-Z
H
L
High-Z
Dout
L
L
Dout
Dout
L
H
Din
X
H
L
X
Din
L
L
Din
Din
Read from SRAM
( WORD mode )
Write to SRAM
( WORD mode )
Read from SRAM
( BYTE Mode )
Write to SRAM
( BYTE Mode )
L
L
H
L
H
X
H
H
H
L
X
X
ICC
ICC
L
H
L
H
L
X
X
A-1
Dout
High-Z
ICC
L
H
X
L
L
X
X
A-1
Din
X
ICC
L
L
X
X
X
X
X
X
X
X
Icc
H
H
X
X
X
X
X
X
X
X
Icc
Prohibit Mode
„ OPERATING RANGE
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
PARAMETER
with
RATING
UNITS
-0.5 to
Vcc+0.5
V
VTERM
Terminal Voltage
Respect to GND
TBIAS
Temperature Under Bias
-40 to +125
O
C
TSTG
Storage Temperature
-60 to +150
O
C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
AMBIENT
TEMPERATURE
Vcc
Commercial
0 O C to +70 O C
2.7V ~ 3.6V
Industrial
-40 O C to +85 O C
2.7V ~ 3.6V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS616LV8021
RANGE
3
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V
10
pF
VI/O=0V
12
pF
1. This parameter is guaranteed and not tested.
Revision 2.3
April 2002
BSI
BS616LV8021
„ DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.(1) MAX.
UNITS
VIH
Guaranteed Input Low
Voltage(2)
Guaranteed Input High
Voltage(2)
I IL
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
--
--
1
uA
I OL
Output Leakage Current
Vcc = Max, CE1 = VIH , or CE2 = ViL, or
OE = VIH, VI/O = 0V to Vcc
--
--
1
uA
VOL
Output Low Voltage
Vcc= max, I OL= 2mA
Vcc=3V
--
--
0.4
V
VOH
Output High Voltage
Vcc= Min, IOH = -1mA
Vcc=3V
2.4
--
--
V
I CC
Operating Power Supply
Current
Vcc=max, CE1=VIL and CE2= VIH,
IDQ = 0mA, F = Fmax (3)
Vcc=3V
--
--
20
mA
I CCSB
Standby Current-TTL
Vcc= max, CE1=VIH or CE2 = VIL,
IDQ = 0mA
Vcc=3V
--
--
1
mA
I CCSB1
Standby Current-CMOS
Vcc= max,CE1Њ Vcc-0.2V, or
CE2 Љ 0.2V; VIN Њ Vcc - 0.2V
or VIN Љ 0.2V
Vcc=3V
--
1
16
uA
VIL
Vcc=3V
-0.5
--
0.8
V
Vcc=3V
2.0
--
Vcc+0.2
V
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/ tRC .
R0201-BS616LV8021
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Revision 2.3
April 2002
BSI
BS616LV8021
„ DATA RETENTION CHARACTERISTICS ( TA = 0oC to +70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
VDR
Vcc for Data Retention
CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V;
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
1.5
--
--
V
ICCDR
Data Retention Current
CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
--
0.8
12
uA
tCDR
Chip Deselect to Data
Retention Time
0
--
--
ns
TRC (2)
--
--
ns
See Retention Waveform
tR
Operation Recovery Time
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
„ LOW VCC DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
Data Retention Mode
Vcc
VDR Њ 1.5V
Vcc
CE1
Vcc
tR
t CDR
CE1 Њ Vcc - 0.2V
VIH
„ LOW VCC DATA RETENTION WAVEFORM (2)
VIH
( CE2 Controlled )
Data Retention Mode
Vcc
VDR Њ 1.5V
Vcc
CE2
R0201-BS616LV8021
VIL
Vcc
tR
t CDR
CE2 Љ 0.2V
5
VIL
Revision 2.3
April 2002
BSI
BS616LV8021
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
„ KEY TO SWITCHING WAVEFORMS
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
1269
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
5PF
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
1269
3.3V
3.3V
OUTPUT
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
1404 Ω
1404 Ω
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667 Ω
OUTPUT
,
1.73V
ALL INPUT PULSES
Vcc
GND
10%
→
90% 90%
←
→
10%
← 5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to +70oC, Vcc=3V )
READ CYCLE
JEDEC
PARAMETER
NAME
tAVAX
tAVQV
tE1LQV
tE2LQV
tBA
tGLQV
tELQX
tBE
tGLQX
tEHQZ
tBDO
tGHQZ
tAXQX
PARAMETER
NAME
tRC
tAA
tACS1
tACS2
tBA (1)
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
tOH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
(CE1)
(CE2)
Chip Select Access Time
Data Byte Control Access Time
(LB,UB)
Output Enable to Output Valid
Chip Select to Output Low Z
(CE2,CE1)
Data Byte Control to Output Low Z (LB,UB)
Output Enable to Output in Low Z
Chip Deselect to Output in High Z (CE2,CE1)
Data Byte Control to Output High Z (LB,UB)
Output Disable to Output in High Z
Output Disable to Output Address Change
BS616LV8021-70
BS616LV8021-10
MIN. TYP. MAX.
MIN. TYP. MAX.
70
100
70
70
70
35
35
10
10
10
0
0
0
10
35
35
30
100
100
100
50
50
15
15
15
0
0
0
15
40
40
35
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle .
tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle .
R0201-BS616LV8021
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Revision 2.3
April 2002
BSI
BS616LV8021
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
ADDRESS
t AA
t OH
t OH
D OUT
READ CYCLE2 (1,3,4)
CE2
t
ACS2
t
ACS1
CE1
t
t CHZ(5)
(5)
CLZ
D OUT
READ CYCLE3 (1,4)
t RC
ADDRESS
t
AA
OE
t
CE2
CE1
t
t
t
ACS2
t
OLZ
t
OE
t
ACS1
(5)
CLZ
OHZ
OH
(5)
(1,5)
t
CHZ
t
BDO
LB,UB
t
BE
t
BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS616LV8021
7
Revision 2.3
April 2002
BSI
BS616LV8021
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to +70oC, Vcc=3V )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tCW
tAS
tAW
tWP
tWR
tBW (1)
tWHZ
tDW
tDH
tOHZ
tOW
BS616LV8021-10
BS616LV8021-70
DESCRIPTION
MIN.
TYP.
70
70
0
70
35
0
30
0
30
0
0
5
Write Cycle Time
Chip Select to End of Write
Address Set up Time
Address Valid to End of Write
Write Pulse Width
(CE2, CE1, WE)
Write Recovery Time
Data Byte Control to End of Write (LB,UB)
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
MIN.
MAX.
100
100
0
100
50
0
40
0
40
0
0
10
30
30
TYP.
UNIT
MAX.
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle.
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
(3)
t WR
OE
CE2
(5)
(11)
t CW
(5)
CE1
t
BW
(5)
LB,UB
t AW
WE
(3)
t WP
t AS
(2)
(4,10)
t OHZ
D OUT
t DH
t DW
D IN
R0201-BS616LV8021
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Revision 2.3
April 2002
BSI
BS616LV8021
WRITE CYCLE2 (1,6)
t WC
ADDRESS
CE2
(11)
t
(5)
CE1
t
BW
(5)
LB,UB
t
WE
CW
AW
t WR
t WP
(3)
(2)
t
t AS
DH
(4,10)
t WHZ
D OUT
(7)
(8)
t DW
t
DH
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured± 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV8021
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Revision 2.3
April 2002
BSI
BS616LV8021
BS616LV8021
X X
-- Y Y
SPEED
70: 70ns
10: 100ns
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
A :BGA - 48 PIN(6x8mm)
„ PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
1.4 Max.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
E1
e
D1
VIEW A
48 mini-BGA (6 x 8mm)
R0201-BS616LV8021
10
Revision 2.3
April 2002
BSI
BS616LV8021
REVISION HISTORY
Revision
Description
Date
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify some AC parameters
April,12,2002
R0201-BS616LV8021
11
Note
Revision 2.3
April 2002
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