BSI BS62LV4001TI Low power/voltage cmos sram 512k x 8 bit Datasheet

BSI
Low Power/Voltage CMOS SRAM
512K X 8 bit
„ FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Low power consumption
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.25uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 45mA (Max.) operation current
I -grade: 50mA (Max.) operating current
1.5uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
-10
100ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
BS62LV4001
„ GENERAL DESCRIPTION
The BS62LV4001 is a high performance, low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with maximum access time of 70/ 100ns
in 3.0V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE), and active LOW output enable (OE) and three-state
output drivers.
The BS62LV4001 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4001 is available in DICE form, JEDEC standard 32 pin
SOP, 32 pin TSOPII, 32 pin TSOP and 32 pin Small SOP.
„ PRODUCT FAMILY
„ PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
•
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8 BS62LV4001SC
9 BS62LV4001SI
10 BS62LV4001EC
BS62LV4001EI
11
BS62LV4001PC
12 BS62LV4001PI
13
14
15
16
•
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
BS62LV4001TC
BS62LV4001STC
BS62LV4001TI
BS62LV4001STI
„ FUNCTIONAL BLOCK DIAGRAM
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
22
2048
Row
Memory Array
2048 X 2048
Decoder
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
8
8
Data
Input
Buffer
Data
Output
Buffer
Column I/O
8
8
Write Driver
Sense Amp
256
Column Decoder
16
CE
WE
Control
Address Input Buffer
OE
Vdd
Gnd
A11 A9 A8 A3 A2 A1 A0 A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV4001
1
Revision 2.5
April 2002
BSI
BS62LV4001
„ PIN DESCRIPTIONS
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 8-bit words in the RAM
CE Chip Enable Input
CE is active LOW. Chip enable must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
„ TRUTH TABLE
MODE
WE
CE
OE
I/O OPERATION
Vcc CURRENT
Not selected
X
H
X
High Z
ICCSB, ICCSB1
Output Disabled
H
L
H
High Z
ICC
Read
H
L
L
DOUT
ICC
Write
L
L
X
DIN
ICC
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
PARAMETER
VTERM
Terminal Voltage
Respect to GND
with
TBIAS
Temperature Under Bias
„ OPERATING RANGE
RATING
UNITS
-0.5 to
Vcc+0.5
V
-40 to +125
O
C
TSTG
Storage Temperature
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
-60 to +150
O
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0 O C to +70 O C
2.4~5.5V
Industrial
C
O
-40 C to +85 C
2.4~5.5V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS62LV4001
O
2
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V
6
pF
VI/O=0V
8
pF
1. This parameter is guaranteed and not tested.
Revision 2.5
April 2002
BSI
BS62LV4001
„ DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER
NAME
VIL
VIH
IIL
PARAMETER
MIN. TYP. (1)
TEST CONDITIONS
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
MAX.
UNITS
-0.5
--
0.8
V
2.0
2.2
--
Vcc+0.2
V
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
--
--
1
uA
IOL
Output Leakage Current
Vcc = Max, CE = VIH, or OE = VIH,
VI/O = 0V to Vcc
--
--
1
uA
VOL
Output Low Voltage
Vcc = Max, IOL = 2mA
--
--
0.4
V
VOH
Output High Voltage
Vcc = Min, IOH = -1mA
2.4
--
--
V
ICC
Operating Power Supply
Current
CE = VIL, IDQ = 0mA, F = Fmax
Vcc=3.0V
--
--
20
Vcc=5.0V
--
--
45
ICCSB
Standby Current-TTL
CE = VIH, IDQ = 0mA
Vcc=3.0V
ICCSB1
Standby Current-CMOS
CE Њ Vcc-0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
Vcc=3.0V
----
--0.25
1
2
1.5
Vcc=5.0V
--
1.5
15
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
(3)
Vcc=5.0V
mA
mA
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
„ DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
VDR
Vcc for Data Retention
CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
1.5
--
--
V
ICCDR
Data Retention Current
CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
--
0.1
1
uA
tCDR
Chip Deselect to Data
Retention Time
--
--
ns
--
--
ns
tR
0
See Retention Waveform
Operation Recovery Time
TRC
(2)
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
„ LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
Vcc
VDR ≥ 1.5V
Vcc
CE
R0201-BS62LV4001
VIH
Vcc
tR
t CDR
CE ≥ Vcc - 0.2V
3
VIH
Revision 2.5
April 2002
BSI
BS62LV4001
„ KEY TO SWITCHING WAVEFORMS
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0
5ns
WAVEFORM
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
1269 Ω
3.3V
1269 Ω
3.3V
OUTPUT
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
OUTPUT
,
100PF
INCLUDING
JIG AND
SCOPE
5PF
INCLUDING
JIG AND
SCOPE
1404 Ω
1404 Ω
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667 Ω
OUTPUT
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
1.73V
ALL INPUT PULSES
Vcc
GND
90% 90%
10%
→
←
→
10%
← 5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
PARAMETER
NAME
NAME
t AVAX
t AVQV
t ELQV
t GLQV
t ELQX
t GLQX
t EHQZ
t GHQZ
t RC
t AA
t ACS
t OE
t CLZ
t OLZ
t CHZ
t OHZ
t AXOX
t OH
R0201-BS62LV4001
BS62LV4001-70
MIN. TYP. MAX.
DESCRIPTION
--
BS62LV4001-10
MIN. TYP. MAX.
--
100
--
UNIT
Read Cycle Time
70
Address Access Time
--
ns
--
--
70
--
--
100
ns
Chip Select Access Time
--
--
70
--
--
100
ns
Output Enable to Output Valid
--
--
35
--
--
50
ns
Chip Select to Output Low Z
10
--
--
15
--
--
ns
Output Enable to Output in Low Z
10
--
--
15
--
--
ns
Chip Deselect to Output in High Z
0
--
35
0
--
40
ns
Output Disable to Output in High Z
0
--
30
0
--
35
ns
Output Disable to Output Address Change
10
--
--
15
--
--
ns
4
Revision 2.5
April 2002
BSI
BS62LV4001
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
ADDRESS
t
t
t OH
AA
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
t
(5)
ACS
t CHZ
(5)
CLZ
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
t
AA
OE
t
t
CE
t OH
OE
OLZ
t ACS
t
(5)
t OHZ (5)
t CHZ(1,5)
CLZ
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV4001
5
Revision 2.5
April 2002
BSI
BS62LV4001
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
BS62LV4001-70
MIN. TYP. MAX.
DESCRIPTION
BS62LV4001-10
MIN. TYP. MAX.
UNIT
tAVAX
tWC
Write Cycle Time
70
--
--
100
--
--
ns
t E1LWH
tCW
Chip Select to End of Write
70
--
--
100
--
--
ns
tAVWL
tAS
Address Set up Time
0
--
--
0
--
--
ns
tAVWH
tAW
Address Valid to End of Write
70
--
--
100
--
--
ns
tWLWH
tWP
Write Pulse Width
35
--
--
50
--
--
ns
tWHAX
tWR
Write Recovery Time
0
--
--
0
--
--
ns
tWLOZ
tWHZ
Write to Output in High Z
--
--
30
--
--
40
ns
tDVWH
tDW
Data to Write Time Overlap
30
--
--
40
--
--
ns
tWHDX
tDH
Data Hold from Write Time
0
--
--
0
--
--
ns
tGHOZ
tOHZ
Output Disable to Output in High Z
0
--
30
0
--
40
ns
tWHQX
tOW
End ot Write to Output Active
5
--
--
10
--
--
ns
(CE , WE)
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WC
ADDRESS
(3)
t WR
OE
(11)
t CW
(5)
CE
t AW
WE
t WP
t AS
(2)
(4,10)
t OHZ
D OUT
t DH
t DW
D IN
R0201-BS62LV4001
6
Revision 2.5
April 2002
BSI
BS62LV4001
WRITE CYCLE2 (1,6)
t
WC
t
CW
ADDRESS
(11)
(5)
CE
t AW
t WP
(2)
WE
t
t AS
DH
(4,10)
t WHZ
(7)
D OUT
(8)
t DW
t DH
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
R0201-BS62LV4001
7
Revision 2.5
April 2002
BSI
BS62LV4001
„ ORDERING INFORMATION
BS62LV4001
X X
ˀˀ Y Y
SPEED
70: 70ns
10: 100ns
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
S: SOP
E: TSOP 2
ST: Small TSOP
T: TSOP
P: PDIP
D: DICE
„ PACKAGE DIMENSIONS
WITH PLATING
b
c c1
BASE METAL
b1
SECTION A-A
SOP -32
R0201-BS62LV4001
8
Revision 2.5
April 2002
BSI
BS62LV4001
„ PACKAGE DIMENSIONS (continued)
TSOP2 - 32
TSOP - 32
R0201-BS62LV4001
9
Revision 2.5
April 2002
BSI
BS62LV4001
„ PACKAGE DIMENSIONS (continued)
STSOP - 32
PDIP - 32
R0201-BS62LV4001
10
Revision 2.5
April 2002
BSI
BS62LV4001
REVISION HISTORY
Revision
Description
Date
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify Standby Current (Typ. and Jun. 29, 2001
Max.)
2.4
To add DICE form
March 06, 2002
2.5
Modify some AC parameters.
Modify 5V ICCSB1_Max(I-grade)
from 25uA to 50uA.
April,10,2002
R0201-BS62LV4001
11
Note
Revision 2.5
April 2002
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