BSI BS62LV4007 Very low power/voltage cmos sram 512k x 8 bit Datasheet

BSI
Very Low Power/Voltage CMOS SRAM
512K X 8 bit
BS62LV4007
„ FEATURES
„ DESCRIPTION
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 68mA (@55ns) operating current
I -grade: 70mA (@55ns) operating current
C-grade: 58mA (@70ns) operating current
I -grade: 60mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Three state outputs and TTL compatible
The BS62LV4007 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
2.0uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4007 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.
„ PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV4007TC
BS62LV4007STC
BS62LV4007SC
BS62LV4007EC
BS62LV4007PC
BS62LV4007TI
BS62LV4007STI
BS62LV4007SI
BS62LV4007EI
BS62LV4007PI
OPERATING
TEMPERATURE
O
O
•
BS62LV4007SC
BS62LV4007SI
BS62LV4007EC
BS62LV4007EI
BS62LV4007PC
BS62LV4007PI
•
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV4007TC
BS62LV4007STC
BS62LV4007TI
BS62LV4007STI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
STANDBY
Operating
( I CCSB1 , Max )
55ns :4.5~5.5V
70ns :4.5~5.5V
55ns
Vcc =5.0V
70ns
55 / 70
30uA
68mA
58mA
O
4.5V ~ 5.5V
55 / 70
60uA
70mA
60mA
C to +85 C
PKG
TYPE
( I CC , Max )
Vcc = 5.0V
Vcc =5.0V
4.5V ~ 5.5V
TSOP - 32
STSOP -32
SOP - 32
TSOP2 - 32
PDIP - 32
TSOP - 32
STSOP - 32
SOP - 32
TSOP2 - 32
PDIP - 32
„ BLOCK DIAGRAM
„ PIN CONFIGURATIONS
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
POWER DISSIPATION
SPEED
( ns )
O
+0 C to +70 C
- 40
Vcc
RANGE
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
22
2048
Row
Memory Array
2048 X 2048
Decoder
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
8
8
Data
Input
Buffer
Data
Output
Buffer
Column I/O
8
8
Write Driver
Sense Amp
256
Column Decoder
16
CE
WE
Control
Address Input Buffer
OE
Vdd
GND
A11 A9 A8 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62LV4007
1
Revision 1.1
Jan.
2004
BSI
BS62LV4007
„ PIN DESCRIPTIONS
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 8-bit words in the RAM
CE Chip Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
GND
Ground
„ TRUTH TABLE
MODE
WE
CE
OE
I/O OPERATION
Vcc CURRENT
Not selected
X
H
X
High Z
ICCSB, ICCSB1
Output Disabled
H
L
H
High Z
ICC
Read
H
L
L
DOUT
ICC
Write
L
L
X
DIN
ICC
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
PARAMETER
with
„ OPERATING RANGE
RATING
UNITS
-0.5 to
Vcc+0.5
V
VTERM
Terminal Voltage
Respect to GND
TBIAS
Temperature Under Bias
-40 to +85
O
C
TSTG
Storage Temperature
-60 to +150
O
C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
RANGE
Commercial
Industrial
O
O
0 C to +70 C
O
O
-40 C to +85 C
Vcc
4.5V ~ 5.5V
4.5V ~ 5.5V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS62LV4007
AMBIENT
TEMPERATURE
2
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V
6
pF
VI/O=0V
8
pF
1. This parameter is guaranteed and not 100% tested.
Revision 1.1
Jan.
2004
BSI
BS62LV4007
„ DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
Guaranteed Input Low
Voltage(3)
Guaranteed Input High
Voltage(3)
VIL
VIH
MIN. TYP.
(1)
MAX.
UNITS
Vcc = 5.0 V
-0.5
--
0.8
V
Vcc = 5.0 V
2.2
--
Vcc+0.3
V
IIL
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
--
--
1
uA
ILO
Output Leakage Current
Vcc = Max, CE = VIH, or OE = VIH,
VI/O = 0V to Vcc
--
--
1
uA
VOL
Output Low Voltage
Vcc = Max, IOL = 2.0mA
--
--
0.4
V
--
V
VOH
ICC
(5)
ICCSB
ICCSB1
(4)
Vcc = 5.0 V
Output High Voltage
Vcc = Min, I OH = -1.0mA
Operating Power Supply
Current
CE = VIL, IDQ = 0mA,
F=Fmax (2)
Standby Current-TTL
CE = VIH, IDQ = 0mA
Standby Current-CMOS
CE ≧ Vcc-0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
2.4
--
--
--
Vcc = 5.0 V
--
--
1.0
mA
Vcc = 5.0 V
--
2.0
60
uA
Vcc = 5.0 V
55ns
Vcc = 5.0 V
70
60
70ns
mA
1. Typical characteristics are at TA = 25oC.
2. Fmax = 1/tRC .
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. IccSB1_MAX. is 30uA at Vcc=5.0V and TA=70oC.
5. Icc_MAX. is 68mA(@55ns) / 58mA(@70ns) at Vcc=5.0V and TA=0~70oC.
„ DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
VDR
Vcc for Data Retention
CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
ICCDR
Data Retention Current
CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
tCDR
Chip Deselect to Data
Retention Time
tR
See Retention Waveform
Operation Recovery Time
MIN.
TYP. (1)
MAX.
UNITS
1.5
--
--
V
--
0.3
1.3
uA
0
--
--
ns
TRC (2)
--
--
ns
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR_MAX. is 0.8uA at TA=70OC.
„ LOW VCC DATA RETENTION WAVEFORM
( CE Controlled )
Data Retention Mode
Vcc
VDR ≥ 1.5V
Vcc
CE
R0201-BS62LV4007
VIH
Vcc
tR
t CDR
CE ≥ Vcc - 0.2V
3
VIH
Revision 1.1
Jan.
2004
BSI
BS62LV4007
„ KEY TO SWITCHING WAVEFORMS
„AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
WAVEFORM
INPUTS
OUTPUTS
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
t AVAX
t AVQV
t ELQV
t GLQV
t ELQX
t GLQX
t EHQZ
t GHQZ
tRC
t AA
t ACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
t AXOX
tOH
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
MIN.
TYP.
MAX.
DESCRIPTION
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN.
TYP. MAX.
UNIT
Read Cycle Time
55
--
--
70
--
--
ns
Address Access Time
--
--
55
--
--
70
ns
Chip Select Access Time
--
--
55
--
--
70
ns
Output Enable to Output Valid
--
--
30
--
--
35
ns
Chip Select to Output Low Z
10
--
--
10
--
--
ns
Output Enable to Output in Low Z
10
--
--
10
--
--
ns
Chip Deselect to Output in High Z
--
--
30
--
--
35
ns
Output Disable to Output in High Z
--
--
25
--
--
30
ns
Data Hold from Address Change
10
--
--
10
--
--
ns
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t RC
ADDRESS
t
t
t OH
AA
OH
D OUT
R0201-BS62LV4007
4
Revision 1.1
Jan.
2004
BSI
READ CYCLE2
BS62LV4007
(1,3,4)
CE
t
t
(5)
ACS
t CHZ
(5)
CLZ
D OUT
READ CYCLE3
(1,4)
t RC
ADDRESS
t
AA
OE
t
t
CE
OLZ
t ACS
t
t OH
OE
t OHZ (5)
t CHZ(1,5)
(5)
CLZ
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
R0201-BS62LV4007
5
Revision 1.1
Jan.
2004
BSI
BS62LV4007
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
DESCRIPTION
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
UNIT
t AVAX
t WC
Write Cycle Time
55
--
--
70
--
--
ns
t E1LWH
t CW
Chip Select to End of Write
55
--
--
70
--
--
ns
t AVWL
t AS
Address Set up Time
0
--
--
0
--
--
ns
t AVWH
t AW
Address Valid to End of Write
55
--
--
70
--
--
ns
t WLWH
t WP
Write Pulse Width
30
--
--
35
--
--
ns
t WHAX
t WR
Write Recovery Time
0
--
--
0
--
--
ns
t WLOZ
t WHZ
Write to Output in High Z
--
--
25
--
--
30
ns
t DVWH
t DW
Data to Write Time Overlap
25
--
--
30
--
--
ns
t WHDX
t DH
Data Hold from Write Time
0
--
--
0
--
--
ns
t GHOZ
t OHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
t WHQX
t OW
End ot Write to Output Active
5
--
--
5
--
--
ns
(CE , WE)
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WC
ADDRESS
(3)
t WR
OE
(11)
t CW
(5)
CE
t AW
WE
t WP
t AS
(2)
(4,10)
t OHZ
D OUT
t DH
t DW
D IN
R0201-BS62LV4007
6
Revision 1.1
Jan.
2004
BSI
BS62LV4007
WRITE CYCLE2 (1,6)
t
WC
t
CW
ADDRESS
(11)
(5)
CE
t AW
t WP
(2)
WE
t AS
(4,10)
t
t WHZ
D OUT
OW
(7)
(8)
t DW
t DH
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
R0201-BS62LV4007
7
Revision 1.1
Jan.
2004
BSI
BS62LV4007
„ ORDERING INFORMATION
BS62LV4007 X X
Z
YY
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
S: SOP
E: TSOP 2
ST: Small TSOP
T: TSOP
P: PDIP
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
„ PACKAGE DIMENSIONS
WITH PLATING
b
c c1
BASE METAL
b1
SECTION A-A
SOP -32
R0201-BS62LV4007
8
Revision 1.1
Jan.
2004
BSI
BS62LV4007
TSOP2 - 32
TSOP - 32
R0201-BS62LV4007
9
Revision 1.1
Jan.
2004
BSI
BS62LV4007
„ PACKAGE DIMENSIONS (continued)
STSOP - 32
PDIP - 32
R0201-BS62LV4007
10
Revision 1.1
Jan.
2004
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