Rohm BU2099F-E2 Serial / parallel 4-input driver Datasheet

Serial-in / Parallel-out Driver Series
Serial / Parallel
4-input Drivers
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
No.09051EAT03
●Description
Serial-in-parallel-out driver incorporates a built-in shift register and a latch circuit to control a maximum of 24 LED by a 4-line
interface, linked to a microcontroller.
A single external resistor can set the output current value of the constant current up to a maximum of 50mA. (BD7851FP only)
CMOS open drain output type products can drive the maximum current of 25mA.
●Features
1) LED can be driven directly.
2) Parallel output of a maximum of 24 bit
3) Operational on low voltage (2.7V to 5.5V)
4) Cascade connection is possible (BU2050F and BU2092F,BU2092FV are not acceptable)
●Application
For AV equipment such as, audio stereo sets, videos and TV sets, PCs, control microcontroller mounted equipment.
●Product line-up
Parameter
BU2050F
BU2092F
BU2092FV
BU2099FV
BD7851FP
BU2152FS
Unit
Output current
25
25
25
25
50
25
mA
Output line
8
12
12
12
24
line
Output type
CMOS
CMOS
-
Package
SOP14
16
Constant
current
HSOP25
SSOP-A32
-
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© 2009 ROHM Co., Ltd. All rights reserved.
Open drain
SOP18
SSOP-B20
1/24
SSOP-B20
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
●Thermal derating curve
700
Pd [mW]
600
BU2050F
500
Power dissipation
Power dissipation
Pd [mW]
700
400
BU2099FV
300
200
600
BU2092F
500
400
BU2092FV
300
200
100
100
85℃
0
25
50
75
100
125
150
0
175
Ambient temperature Ta [℃]
25
50
75
100
125
150
175
Ambient temperature Ta [℃]
Power dissipation
Pd [mW]
1600
1400
BD7851FP
1200
1000
BU2152FS
800
600
400
200
0
85℃
25
50
75
100
125
150
175
Ambient temperature Ta [℃]
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
Power Supply Voltage
Power dissipation 1
Power dissipation 2
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
*1 Reduced by 4.5mW/℃
*2 Reduced by 4.5mW/℃
*3 Reduced by 4.0mW/℃
*4 Reduced by 5.5mW/℃
*5 Reduced by 6.5mW/℃
VDD
Pd1
Pd2
VIN
Vo
Topr
Tstg
BU2050F
-0.3 to +7.0
450 *1
VSS-0.3 to VDD+0.5
VSS-0.3 to VDD+0.5
-40 to +85
-55 to +125
Limits
BU2092F
BU2092FV
-0.3 to +7.0
450 (SOP) *2
400 (SSOPB) *3
4
550 (SOP) *
650 (SSOPB) *5
VSS-0.3 to VDD+0.3
VSS to +25.0
-25 to +75
-55 to +125
Unit
V
mW
mW
V
V
℃
℃
over 25℃
over 25℃
over 25℃
for each increase in Ta of 1℃ over 25℃ (When mounted on a board 50mm×50mm×1.6mm Glass-epoxy PCB).
for each increase in Ta of 1℃ over 25℃ (When mounted on a board 70mm×70mm×1.6mm Glass-epoxy PCB).
Parameter
Power Supply Voltage
Power dissipation 1
Power dissipation 2
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Symbol
VDD
Pd1
Pd2
VIN
Vo
Topr
Tstg
BU2099FV
-0.3 to +7.0
400 (SSOPB) *6
650 (SSOPB) *9
VSS-0.3 to VDD+0.3
VSS to +25.0
-40 to +85
-55 to +125
Limits
BD7851FP
0 to +7.0
1450 *7
-0.3 to VCC+0.3
0 to +10
-30 to +85
-55 to +150
BU2152FS
-0.3 to +7.0
800 *8
VSS-0.3 to VDD+0.3
VSS-0.3 to VDD+0.3
-25 to +85
-55 to +125
Unit
V
mW
mW
V
V
℃
℃
*6 Reduced by 4.5mW/℃ over 25℃
*7 Reduced by 11.6mW/℃ over 25℃
*8 Reduced by 8.0mW/℃ over 25℃
*9 Reduced by 6.5mW/℃ for each increase in Ta of 1℃ over 25℃ (When mounted on a board 70mm×70mm×1.6mm Glass-epoxy PCB).
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2/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
●Electrical characteristics
BU2050F (Unless otherwise noted, Ta=25℃, VDD=4.5 to 5.5V)
Parameter
Symbol
Min.
Power Supply Voltage
VDD
4.5
Input high-level Voltage
VIH
0.7VDD
Input low-level Voltage
VIL
VSS
Input Hysteresis
VHYS
VDD-1.5
Output high-level Voltage
VOHD
VDD-1.0
VDD-0.5
VSS
Output low-level Voltage
VOLD
VSS
VSS
Quiescent Current
IDD
-
Typ.
0.5
-
Max.
5.5
VDD
0.3VDD
VDD
VDD
VDD
1.5
0.8
0.4
0.1
BU2092F/BU2092FV (Unless otherwise noted, Ta=25℃, VSS=0V, VDD=5.0V/3.0V)
Parameter
Symbol
Min.
Typ.
Max.
Power Supply Voltage
VDD
2.7
5.5
3.5
/
2.5
Input high-level Voltage
VIH
Input low-level Voltage
VIL
1.5 / 0.4
Unit
V
V
V
V
V
V
mA
Unit
V
V
V
Output low-level Voltage
VOL
-
-
2.0 / 1.0
V
Output high-level disable Current
Output low-level disable Current
IOZH
IOZL
-
-
10.0
-5.0
μA
μA
Quiescent Current
IDD
-
-
5.0 / 3.0
μA
Max.
5.5
1.5 / 0.9
Unit
V
V
V
-
V
BU2099FV (Unless otherwise noted, Ta=25℃, VSS=0V, VDD=5.0V/3.0V)
Parameter
Symbol
Min.
Typ.
Power Supply Voltage
VDD
2.7
Input high-level Voltage
VIH
3.5 / 2.1
Input low-level Voltage
VIL
VDD-0.5
Output high-level Voltage (SO)
VOH
/ VDD-0.3
-
-
1.0
-
-
1.5
2.0
IOH=-25mA
IOH=-15mA
IOH=-10mA
IOL=25mA
IOL=15mA
IOL=10mA
VIH=VDD, VIL=VSS
Condition
VDD=5V/3V
VDD=5V/3V
VDD=5V/3V,
IOL=20mA/5mA
VO=25.0V
VO=0V
VIN=VSS or VDD
(VDD=5V/3V)
OUTPUT:OPEN
Condition
VDD=5V/3V
VDD=5V/3V
VDD=5V/3V,
IOH=-400μA/-100μA
VDD=5V/3V,
IOL1=10mA/5mA
VDD=5V, IOL1=15mA
VDD=5V, IOL1=20mA
VDD=5V/3V,
IOL2=1.5mA/0.5mA
Output low-level Voltage 1 (Qx)
VOL1
Output low-level Voltage 2 (SO)
VOL2
-
-
0.4 / 0.3
V
IOZH
-
-
10
μA
VO=25.0V
IOZL
-
-
-5.0
μA
VO=0V
IPD
VCLR
1.1
-
150 / 60
2.4
μA
V
OE= VDD, VDD=5V/3V
Low Voltage Reset
Quiescent Current
IDD
-
-
200
μA
Output high-level disable Current
(Qx)
Output low-level disable Current
(Qx)
IPULLDOWN (OE)
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3/24
V
Condition
VIN=VSS or VDD,
VDD=5V
OUTPUT:OPEN
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
●Electrical characteristics
BD7851FP (Unless otherwise noted, Ta=25℃, VCC=5.0V)
Parameter
Symbol
Min.
Power Supply Voltage
VDD
4.5
0.8×VCC
Input high-level Voltage
VIH
Input low-level Voltage
Output high-level Voltage
Output low-level Voltage
Quiescent Current
Reference Current Output Current
(including the equation between
each bit)
Equation between each bit of
Reference Current Output Current
Change rate of reference current
output current for output voltage
Output Leak Current
VCC-0.5
-
Typ.
-
Max.
5.5
0.2×VCC
0.5
Unit
V
V
V
V
V
-
0.7
1.0
mA
-
1.8
3.0
mA
-
4.0
6.5
mA
-
30
40
mA
Iolc1
48
55
62
mA
IOH=-1mA
IOL=1mA
R=13kΩ
OUT1~OUT16:OFF
R=1.3kΩ
OUT1~OUT16:OFF
R=13kΩ
OUT1~OUT16:ON
R=1.3kΩ
OUT1~OUT16:ON
VOUT=2.0V, R=1.3kΩ
Iolc2
5.0
5.9
6.8
mA
VOUT=2.0V, R=13kΩ
Δiolc
-
±1
±6
%
IΔVCC
-
±1
±6
%/V
IOH
-
0.01
0.8
μA
Max.
5.5
0.6
1.5
1.0
0.8
5
1
1
Unit
V
V
V
VIL
VOH
VOL
ICC
BU2152FS (Unless otherwise noted, Ta=25℃, VDD=2.7 to 5.5V)
Parameter
Symbol
Min.
Typ.
Power Supply Voltage
VDD
2.7
2.0
Input high-level Voltage
VIH
Input low-level Voltage
VIL
VDD-1.5
Output high-level Voltage
VOH
VDD-1.0
VDD-0.5
Output low-level Voltage
VOL
Quiescent Current
IDDST
Input high-level Current
IIH
Input low-level Current
IIL
-
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4/24
V
V
μA
μA
μA
Condition
VOUTn=2.0V, R=1.3kΩ
(1bit : ON)
VOUT=2.0 to 3.0V,
R=1.3kΩ
VOUT=10V
Condition
VDD=5V
VDD=5V
IOH=-25mA
IOH=-15mA
IOH=-10mA
IOL=25mA
IOL=15mA
IOL=10mA
VIL=VSS, VIH=VDD
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
●Block diagram
BU2050F
STB
Controller
CLR
8bit
Shift
CLOCK
Register
L
a
t
c
h
Write
Buffer
P1~P8
DATA
BU2092F/BU2092FV
LCK
Controller
CLOCK
DATA
12bit
Shift
Register
L
a
t
c
h
Write
Buffer
Q0~Q11
OE
BU2099FV
LCK
CLOCK
LPF
Controller
DATA
12bit
Shift
Register
L
a
t
c
h
Write
Buffer
Q0~Q11
OE
BD7851FP
S_IN
16bit
Shift
CLOCK
Register
L
a
t
c
h
Write
Buffer
OUT1~OUT16
SOUT
LATCH
ENABLE
R_Iref
Current Adjustment
BU2152FS
STB
CLB
Controller
24bit
Shift
CLOCK
Register
DATA
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© 2009 ROHM Co., Ltd. All rights reserved.
L
a
t
c
h
Write
Buffer
P1~P24
SO
5/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
●Operating description
(1) Data clear
When the reset terminal (CLR, CLB) is set to “L”, the content of all latch circuits are set to “H”, and all parallel outputs are
initialised.
(For model with reset terminal only)
(2) Data transfer
Serial data is sequentially input to the shift register during the rise of the clock time (strobe signal is not active). When
the strobe signal is active, the content of the shift register are transferred to the latch circuit.
(3) Cascade connection
Serial input data is output from the serial output through the shift register, regardless of the strobe signal.
(except
for
BU2050F,
BU2092F/BU2092FV)
●Application circuit
C1
(*)
VDD
P1 P2
Pn-2 Pn-1 Pn
VDD
Serial data input
Clock input
MPU
VSS
Strobe input
Latch input
VSS
Serial data output
P1 P2
Pn-2 Pn-1 Pn
VDD
Serial data input
Clock input
VSS
Strobe input
Latch input
Serial data output
(*C1 must be placed as close to the terminal as possible.)
Fig. 1
BU2092F/BU2092FV
DATA, CLOCK, LCK, OE
BU2092F/BU2092FV
Q0~Q11
●Interfaces
BU2050F
DATA, CLOCK, STB, CLR
BU2050F
P1~P8
VDD
VDD
VDD
VDD
OUT
INPUT
OUTPUT
IN
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
BU2099FV
DATA, CLOCK, LCK, OE
VDD
VDD
GND(VSS)
GND(VSS)
GND(VSS)
BU2099FV
Q0~Q11
BU2099FV
SO
VDD
BU2152FS
CLOCK, DATA, STB, CLB
VDD
VDD
VDD
VDD
GND(VSS)
GND(VSS)
OUT
IN
OUT
GND(VSS)
(only OE pin)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
BU2152FS
P1~P28
VDD
VDD
VSS
VSS
GND(VSS)
BU2152FS
SO
VDD
VSS
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© 2009 ROHM Co., Ltd. All rights reserved.
GND(VSS)
VDD
VDD
GND(VSS) GND(VSS)
6/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BU2050F】
●Pin descriptions
Pin No.
Pin Name
1
P3
2
P4
3
P5
4
VSS
5
P6
6
P7
Function
Parallel Data Output
GND
Parallel Data Output
7
P8
8
DATA
Serial Data Input
9
CLK
10
STB
11
CLR
Clock Signal Input
Strobe Signal Input
In case of “L”, the data of shift register outputs.
In case of “H”, all parallel outputs and data of latch circuit do not change.
Reset Signal Input
In case of “L”, the data of latch circuit reset, and all parallel output (P1~P8) can be L.
Normally CLR=H
12
P1
13
P2
14
VDD
Parallel Data output
Power Supply
●Timing chart
CLK
DATA
DATA8
DATA7
DATA6
DATA2
DATA1
CLR
STB
Pn
Previous DATA
DATA
“L”
Fig. 2
1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into the
DATA pin.
th
2. Pn parallel output data of the shift register is set after the 8 clock by the STB.
3. Since the STB is level latch, data is retained in the “L” section and renewed in the “H” section of the STB.
[Function explanation]
・
A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is “L”, the latch
circuit is reset non-synchronously without the other input condition, and all parallel output can be “L”.
・
A serial data inputted from DATA terminal is read in shift register with synchronized rising of clock.
In case of STB is “L” (CLR is ”H”), transmit the data which read in the shift register to latch circuit, and
outputs from the parallel data output terminal (P1~P8).
In case of STB is “H”, all parallel outputs and the data of latch do not change.
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7/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
●Switching characteristics (Unless otherwise specified, VDD=4.5 to 5.5V, Ta=25℃)
Limit
Parameter
Symbol
Unit
Min.
Typ.
Max.
Condition
Set up time (DATA-CLK)
tSD
20
-
-
ns
-
Hold time (DATA-CLK)
tHD
20
-
-
ns
-
Set up time ( STB  CLK)
tSSTB
30
-
-
ns
-
Hold time ( STB  CLK)
tHSTB
30
-
-
ns
-
Propagation ( CLR  P1~P8)
tPDPCK
-
-
100
ns
P1~P8 terminal load 20pF or less
Propagation ( STB  P1~P8)
tPDPSTB
-
-
80
ns
P1~P8 terminal load 20pF or less
Propagation ( CLR  P1~P8)
tPDPCLR
-
-
80
ns
P1~P8 terminal load 20pF or less
fMAX
5
-
-
MHz
-
Maximum clock frequency
●Switching Time Test Waveform
fMAX
1
2
8
9
10
11
12
CLK
tSD
DATA
tHD
STB
tHSTB
tSSTB
CLR
P8
P1
tPDPSTB
Fig. 3
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8/24
tPDPCLR
tPDPCK
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BU2092F/BU2092FV】
●Pin descriptions
Pin No.
Pin Name
I/O
Function
1
2
3
4
VSS
DATA
CLOCK
LCK
I
I
I
GND
Serial Data Input
Shift clock of DATA (Rising Edge Trigger)
Latch clock of DATA (Rising Edge Trigger)
5~11,
14~18
Q0~Q11
O
Parallel Data Output (Nch Open Drain FET)
Latch Data
L
H
12, 13
17
18
N.C.
OE
VDD
Output FET
I
-
ON
OFF
Non connected
Output Enable (“H” level : output FET is OFF)
Power Supply
●Timing chart
CLOCK
DATA
DATA11
DATA10
DATA9
DATA1
DATA0
LCK
OE
“H”
Qx
Previous DATA
DATA11~0
Note) Diagram shows a status where a pull-up resistor is connected to output.
Fig. 4
1.
2.
3.
4.
After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into
the DATA terminal.
th
Qx parallel output data of the shift register is set after the 12 clock by the LCK.
Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
Data retained in the internal latch circuit is output when the OE is in the “L” section.
[Truth Table]
Input
CLOCK
×
×
×
×
DATA
×
×
LCK
×
×
OE
H
L
L
×
×
H
×
×
×
×
×
×
×
×
×
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Function
Output (Q0~Q11) Disable
Output (Q0~Q11) Enable
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
The data of shift register has no change.
The data of shift register is transferred to the storage register.
The data of storage register has no change.
9/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
●Switching characteristics (Unless otherwise specified, VDD=5V, VSS=0V, Ta=25℃)
Parameter
Symbol
Minimum Clock Pulse Width
tw
Minimum Latch Pulse Width
tw
(LCK)
(LCK)
Setup Time
(LCK→CLOCK)
Setup Time
(DATA→CLOCK)
Hold Time
(CLOCK→DATA)
Propagation
(LCK→OUTPUT QX)
Propagation
( OE →OUTPUT QX)
ts
tsu
tH
tPLZ
(LCK)
tPZL
(LCK)
tPLZ
tPZL
Limit
Unit
VDD(V)
Condition
Min.
Typ.
Max.
1000
-
-
ns
3
500
-
-
ns
5
1000
-
-
ns
3
500
-
-
ns
5
400
-
-
ns
3
200
-
-
ns
5
400
-
-
ns
3
200
-
-
ns
5
400
-
-
ns
3
200
-
-
ns
5
-
90
-
ns
3
RL=5kΩ
-
55
-
ns
5
CL=10pF
-
115
-
ns
3
RL=5kΩ
-
50
-
ns
5
CL=10pF
-
70
-
ns
3
RL=5kΩ
-
45
-
ns
5
CL=10pF
-
80
-
ns
3
RL=5kΩ
-
35
-
ns
5
CL=10pF
-
-
-
-
-
●Switching Time Test Circuit
±25V
VDD
Pulse
Gen.
RL
Q0
CL
CLOCK
Pulse
Gen.
LCK
Pulse
Gen.
DATA
GND (Vss)
±25V
RL
OE
Q11
CL
Pulse
Gen.
GND (Vss)
GND (Vss)
Fig. 5
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10/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BU2092F/BU2092FV】
●Switching Time Test Waveforms
tW
90%
CLOCK
10%
tSU
90%
tW
90%
90%
VDD
90%
10%
10%
GND (VSS)
tH
VDD
90%
tS
DATA
GND (VSS)
tW(CLK)
90%
50%
LCK
VDD
90%
50%
10%
tPLZ(LCK)
GND (VSS)
tPZL(LCK)
VDD
50%
OE
50%
GND (VSS)
tPZL
tPLZ
VDD
Qx
50%
10%
10%
50%
GND (VSS)
Fig. 6
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11/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BU2099FV】
●Pin descriptions
Pin No.
Pin Name
I/O
Function
1
2
3
4
5
VSS
N.C.
DATA
CLOCK
LCK
I
I
I
GND
Non connected
Serial Data Input
Shift clock of Shift register (Rising Edge Trigger)
Latch clock of Storage register (Rising Edge Trigger)
6~17
Q0~Q11
(Qx)
O
Parallel Data Output (Nch Open Drain FET)
Latch Data
L
H
Output FET
ON
OFF
18
19
20
SO
OE
VDD
O
I
-
Serial Data Output
Output Enable Control Input
Power Supply
*OE pin is pulled down to Vss.
●Timing chart
CLOCK
DATA
DATA12
DATA11
DATA10
DATA2
DATA1
LCK
OE
Qx
SO
Previous DATA
“H”
Previous
DATA 11
DATA
Previous
DATA 11
DATA12
DATA11
Fig. 7
1.
2.
3.
4.
5.
After the power is turned on and the voltage is stabilized, LCK should be activates, after clocking 12 data bits into
the DATA terminal.
Qx parallel output data of the shift register is set after the 12th clock by the LCK.
Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
Data retained in the internal latch circuit is output when the OE is in the “L” section.
The final stage data of the shift register is output to the SO by synchronizing with the rise time of the CLOCK.
[Truth Table]
Input
CLOCK
×
×
×
×
DATA
×
×
LCK
×
×
OE
H
L
L
×
×
H
×
×
×
×
×
×
×
×
×
Function
All the output data output “H” with pull-up.
The Q0~Q11 output can be enable and output the data of storage register.
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
The data of shift register has no change.
SO outputs the final stage data of shift register with synchronized falling
edge of CLOCK, not controlled by OE.
The data of shift register is transferred to the storage register.
The data of storage register has no change.
*The Q0~Q11 output have a Nch open drain Tr. The Tr is ON when data from shift register is “L”, and Tr is OFF when data is “H”.
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© 2009 ROHM Co., Ltd. All rights reserved.
12/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BU2099FV】
●Switching characteristics
(Unless otherwise specified, VDD=5V, VSS=0V, Ta=25℃)
Limit
Parameter
Symbol
Unit
Min.
Typ.
Max.
1000
ns
Minimum Clock Pulse Width
tW
(CLOCK)
500
ns
1000
ns
Minimum Latch Pulse Width
tW
(LCK)
(LCK)
500
ns
400
ns
Setup Time
tS
(LCK→CLOCK)
200
ns
400
ns
Setup Time
tsu
(DATA→CLOCK)
200
ns
400
ns
Hole Time
tH
(CLOCK→DATA)
200
ns
500
ns
Propagation
tPLH
(SO)
tPHL
250
ns
360
ns
tPLZ
(LCK)
Propagation
170
ns
(LCK→QX) *
260
ns
tPZL
(LCK)
175
ns
115
ns
tPLZ
Propagation
85
ns
( QE →QX) *
175
ns
tPZL
65
ns
30
ns
Noise Pulse Suppression
tI
Time (LCK) *
20
ns
VDD(V)
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
-
Condition
RL=5kΩ
CL=10pF
RL=5kΩ
CL=10pF
RL=5kΩ
CL=10pF
RL=5kΩ
CL=10pF
-
*Reference value
●Input Voltage Test Circuit
RL =10kΩ
GND
(Vss)
P.G.
VIH
VIL
GND
Fig. 8
●Switching Time Test Circuit
+25V
VDD
RL =5kΩ
CL =10pF
GND
(Vss)
GND
(Vss)
+25V
P.G.
RL =5kΩ
CL =10pF
GND
(Vss)
Fig. 9
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© 2009 ROHM Co., Ltd. All rights reserved.
13/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BU2099FV】
●Output Voltage Test Circuit
VDD
±25V
12
SW4
1
SW3
SW2
2
1
3
2
SW1
1
GND
(Vss)
IOL1
P.G.
GND
(Vss)
GND
(Vss)
GND
(Vss)
IOH
GND
(Vss)
GND
(Vss)
IOL2
GND
(Vss)
Test condition
VOL1
:Set all data “L”. SW1=”ON”, SW2=”3”, SW3=”1”~”12”.
VOL2
:Set output data “L” to SO and SW4 is positioned to “2”, then voltage is measured at IOL2.
VOH
:Set output data “H” to SO and SW4 is positioned to “1”, then voltage is measured at IOH.
Fig. 10
●Switching Time Test Waveforms
tW
90%
tW
90%
90%
CLOCK
VDD
90%
50%
50%
10%
50%
10%
10%
GND (VSS)
tH
tSU
90%
VDD
90%
tS
DATA
GND (VSS)
tW (CLK)
90%
50%
LCK
VDD
90%
50%
tS 2
10%
GND (VSS)
tPLZ
tPLZ(LCK)
VDD
50%
50%
OE
tPZL(LCK)
tPZL
50%
50%
GND (VSS)
VEXT
Qx
10%
10%
tPLH
tPHL
GND (VSS)
VDD
50%
SO
50%
GND (VSS)
Fig. 11
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© 2009 ROHM Co., Ltd. All rights reserved.
14/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BD7851FP】
●Pin descriptions
Pin No.
Pin Name
Function
1
2
3
4
GND
R_Iref
LATCH
S_IN
OUT16
~OUT6
P_GND
OUT5
~OUT1
SOUT
CLOCK
ENABLE
VCC
Ground
Reference Current Output Current setting
Latch Signal Input
Serial Data Input
5~15
16
17~21
22
23
24
25
Reference Current Output
Ground for Driver
Reference Current Output
Serial Data Output
Clock Input
ENABLE
VCC
●Timing chart
CLOCK
S_IN
DATA16
DATA15
DATA14
DATA2
DATA1
LATCH
ENABLE
OUTn
SOUT
Previous DATA
Previous
DATA15
DATA
Previous
DATA2
Previous
DATA14
Previous
DATA1
DATA16
DATA15
DATA14
Fig. 12
1.
2.
3.
4.
5.
After the power is turned on and the voltage is stabilized, LATCH should be activated, after clocking 16 data bits
into the S_IN terminal.
OUTn parallel output data of the shift register is set after the 16th clock by the LATCH.
The final stage data of the shift register is outputted to the SOUT by synchronizing with the rise time of the
CLOCK.
Since the LATCH is a label latch, data is retained in the “L” section and renewed in the “H” section of the LATCH.
Data retained in the internal latch circuit is outputted when the ENABLE is in the “L” section. When the ENABLE
is in the “H” section, data is fixed in the “H” section.
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© 2009 ROHM Co., Ltd. All rights reserved.
15/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BD7851FP】
●Timing characteristics
(Unless otherwise specified, VCC=5V, Ta=25℃)
Limit
Parameter
Symbol
Min.
Typ.
Max.
Frequency CLOCK
fclk
10
Pulse Width CLOCK
twh
20
50
Pulse Width LATCH
twh
40
50
Pulse Width ENABLE
tw
30
Rise Time / Fall Time
tr / tf
30
100
30
50
Setup Time
tSU
30
50
30
50
Hold Time
th
30
50
300
Rise Time
tr
50
300
Fall Time
tf
50
-
tpLH
400
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
650
ns
Propagation
tpHL
-
300
400
Condition
CLOCK
LATCH
ENABLE
CLOCK
S_IN-CLOCK
LATCH-CLOCK
S_IN-CLOCK
LATCH-CLOCK
OUTn
SOUT
OUTn
SOUT
CLK-SOUT, LATCH
ENABLE-OUTn
CLK-SOUT, LATCH
ENABLE-OUTn
●Reference Current of Output Current
250
[Condition]
Vcc=5.0V, Vo=5.0V, Ta=25℃
IOUT [mA]
200
The reference current of output current is determined by the
external resistor.
(between 2pin and GND )
150
100
50
0
0.1
1
10
100
R_Iref [kΩ]
*This is a data for the standard sample, not guaranteed the characteristic.
Fig. 13
●R_Iref-VOUT
1.6
[Condition]
Vcc=5.0V, Ta=27℃, all bit : ON
1.4
1.2
VOUT [V]
1.0
0.8
0.6
0.4
0.2
0.0
1
10
100
R_Iref [kΩ]
*Notes the increase of consumption current Icc, in case sets the voltage of VOUT lower. See the graph above.
Fig. 14
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© 2009 ROHM Co., Ltd. All rights reserved.
16/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
【BD7851FP】
●Test Circuit 1
Vcc
R
LATCH
S_IN
Vcc 25
1 GND
2 R_Iref
ENABLE 24
3 LATCH
CLOCK 23
SOUT 22
5 OUT16
OUT1 21
6 OUT15
OUT2 20
7 OUT14
BD7851FP
4 S_IN
8 OUT13
OUT3 19
9 OUT12
OUT4 18
10 OUT11
OUT5 17
11 OUT10
P_GND 16
12 OUT9
OUT6 15
13 OUT8
OUT7 14
ENABLE
CLOCK
SOUT
VE
P_GND
Fig. 15
●Test Circuit 2
Vcc
R
LATCH
S_IN
Vcc 25
1 GND
2 R_Iref
ENABLE 24
3 LATCH
CLOCK 23
SOUT 22
5 OUT16
OUT1 21
6 OUT15
OUT2 20
7 OUT14
BD7851FP
4 S_IN
8 OUT13
OUT3 19
9 OUT12
OUT4 18
10 OUT11
OUT5 17
11 OUT10
P_GND 16
12 OUT9
OUT6 15
13 OUT8
OUT7 14
ENABLE
CLOCK
SOUT
VE
P_GND
*R=51Ω (note : R_Iref=1.3kΩ) , C=15pF
Fig. 16
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© 2009 ROHM Co., Ltd. All rights reserved.
17/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BD7851FP】
●Switching Time Test Waveforms
tWh
tr
tf
0.8×VCC 0.8×VCC
CLOCK
0.8×VCC
0.2×VCC
0.2×VCC
tSU
th
0.8×VCC
0.8×VCC
S_IN
twh
0.8×VCC
LATCH
0.2×VCC
tSU
tpHL
th
90%
OUTn
tpHL
90%
10%
90%
10%
tf
10%
tr
tpHL・tpLH
0.8×VCC
ENABLE
tw
0.2×VCC
0.8×VCC
SOUT
0.2×VCC
tpHL・tpLH
tf・tr
Fig. 17
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© 2009 ROHM Co., Ltd. All rights reserved.
18/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BU2152FS】
●Pin descriptions
Pin
Pin Name
No.
1
2
3
4
5~28
29
30
31
32
VSS
CLK
VSS
DATA
P1~P24
SO
STB
CLB
VDD
I/O
Function
I
I
O
O
I
I
-
Ground
Clock Input
Ground
Serial Data Input
Parallel Data Output
Cascade Output
Strobe Signal Input active “L”
Clear Signal Input active “L”
Power Supply
●Timing chart
CLK
DATA
DATA24
DATA23
DATA22
DATA2
DATA1
STB
Pn
Previous DATA
Previous
DATA24
SO
DATA
Previous
DATA23
Previous
DATA2
Previous
DATA1
DATA24
DATA23
DATA22
Fig. 18
1.
After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 24 data bits into
the DATA terminal.
Pn parallel output data of the shift register is set after the 24th clock by the LCK.
Since the STB is a label latch, data is retained in the “H” section and renewed in the “L” section of the STB.
The final stage data of the shift register is outputted to the SO by synchronizing with the rise time of the CLOCK.
2.
3.
4.
[Truth Table]
CLK
Input
STB
CLB
×
×
L
H
H
L
H
L
H
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© 2009 ROHM Co., Ltd. All rights reserved.
Function
All the data of the latch circuit are set to “H” (data of shift register does not
change), all the parallel outputs are “H”.
Serial data of DATA pin are latched to the shift register.
At this time, the data of the latch circuit does not change.
The data of the shift register are transferred to the latch circuit, and the data of
the latch circuit are outputted from the parallel output pin.
The data of the shift register shifts 1bit, and the data of the latch circuit and
parallel output also change.
19/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BU2152FS】
●Switching characteristics
(Unless otherwise specified, VDD=2.7 to 5.5V, VSS=0V, Ta=25℃)
Parameter
Symbol
Maximum Clock Frequency
Limit
Unit
Condition
Min.
Typ.
Max.
fMAX
5
-
-
MHz
Setup Time 1
tSU1
20
-
-
ns
DATA-CLK
Hold Time 1
tHD1
20
-
-
ns
CLK-DATA
Setup Time 2
tSU2
30
-
-
ns
STB-CLK
Hold Time 2
tHD2
30
-
-
ns
CLK-STB
Setup Time 3
tSU3
30
-
-
ns
CLB-CLK
Hold Time 3
tHD3
30
-
-
ns
CLK-CLB
Setup Time 4
tSU4
30
-
-
ns
STB-CLB
Hold Time 4
tHD4
30
-
-
ns
CLB-STB
Output Delay Time 1*
tPD1
-
-
100
ns
CLK-P1~P24
Output Delay Time 2*
tPD2
-
-
80
ns
STB-P1~P24
Output Delay Time 3*
tPD3.
-
-
80
ns
CLB-P1~P24
*50pF of load is attached.
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© 2009 ROHM Co., Ltd. All rights reserved.
20/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
●Switching characteristic conditions
○Setup/Hold Time (DATA-CLOCK, STB-CLOCK, CLB-CLOCK)
tr
tr
90%
90%
CLOCK
DATA
50%
50%
10%
10%
tSU1
tHD1
STB
50%
50%
tSU2
tHD2
CLB
50%
50%
tSU3
tHD3
○Setup/Hold Time (STB-CLB)
CLB
50%
STB
tSU4
tHD4
Fig. 19 Switching characteristic conditions 1
○Output Delay Time (CLOCK-P1~P24)
CLOCK
50%
tPD1
P1~P24
○Output Delay Time (STB-P1~P24)
STB
50%
tPD2
P1~P24
○ Output Delay Time (CLB-P1~P24)
CLB
50%
tPD3
50%
Fig. 20 Switching characteristic conditions 2
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© 2009 ROHM Co., Ltd. All rights reserved.
21/24
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
●Notes for use
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to
ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit,
not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
8. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure.
Use similar precaution when transporting or storing the IC.
9. Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused
by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern
of any external components, either.
10. Unused input terminals
Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation.
Insertion of a resistor (100kΩ approx.) is also recommended.
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© 2009 ROHM Co., Ltd. All rights reserved.
22/24
2009.06 - Rev.A
Technical Note
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
●Ordering part number
B
U
2
Part No.
0
9
2
F
Part No.
2050
2092
2099
7851
2152
V
-
E
Package
F : SOP14
: SOP18
FV : SSOP-B20
FP : HSOP25
FS : SSOP-A32
2
Packaging and forming specification
E2: Embossed tape and reel
SOP14
<Tape and Reel information>
8.7 ± 0.2
(MAX 9.05 include BURR)
8
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
0.3MIN
4.4±0.2
6.2±0.3
14
1
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
7
1.5±0.1
0.15 ± 0.1
0.11
1.27
0.4 ± 0.1
0.1
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SOP18
<Tape and Reel information>
11.2 ± 0.2
(MAX 11.55 include BURR)
10
0.3MIN
5.4±0.2
7.8±0.3
18
1
Tape
Embossed carrier tape
Quantity
2000pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
9
0.11
1.8±0.1
0.15 ± 0.1
0.1
0.4 ± 0.1
1.27
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SSOP-B20
<Tape and Reel information>
6.5 ± 0.2
11
0.3Min.
4.4 ± 0.2
6.4 ± 0.3
20
1
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
10
0.1± 0.1
1.15 ± 0.1
0.15 ± 0.1
0.1
0.65
0.22 ± 0.1
1pin
Reel
(Unit : mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
23/24
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.06 - Rev.A
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
HSOP25
<Tape and Reel information>
13.6 ± 0.2
(MAX 13.95 include BURR)
2.75 ± 0.1
2000pcs
Direction
of feed
0.3Min.
7.8 ± 0.3
1
13
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
0.25 ± 0.1
1.95 ± 0.1
1.9 ± 0.1
Embossed carrier tape
Quantity
14
5.4 ± 0.2
25
Tape
0.11
S
0.1 S
0.8
0.36 ± 0.1
12.0 ± 0.2
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SSOP-A32
<Tape and Reel information>
13.6 ± 0.2
(MAX 13.95 include BURR)
17
Embossed carrier tape
Quantity
2000pcs
Direction
of feed
0.3MIN
5.4±0.2
7.8±0.3
32
Tape
1
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
16
0.11
1.8±0.1
0.15 ± 0.1
0.36 ± 0.1
0.1
0.8
1pin
Reel
(Unit : mm)
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
24/24
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.06 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
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